ADS7817
AD
ADS
781
7
OPSA7817
658
SBAS066A – MAY 2001
12-Bit Differential Input Micro Power Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
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The ADS7817 is a 12-bit, 200kHz sampling Analog-toDigital (A/D) converter that features a high impedance fully
differential analog input. The reference voltage can be varied from 100mV to 2.5V, with a corresponding inputreferred resolution between 49µV and 1.22mV.
The differential input, low power, automatic power down,
and small size make the ADS7817 ideal for direct connection to transducers in battery operated systems, remote data
acquisition, or multi-channel applications. The ADS7817 is
available in a plastic mini-DIP-8, an SO-8, or an MSOP-8
package.
BIPOLAR INPUT RANGE
TRUE DIFFERENTIAL INPUT
200kHz SAMPLING RATE
MICRO POWER: 2.3mW at 200kHz
POWER DOWN: 3µA Max
AVAILABLE IN MSOP-8 PACKAGE
SERIAL INTERFACE
AC COMMON-MODE REJECTION
APPLICATIONS
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TRANSDUCER INTERFACE
BATTERY OPERATED SYSTEMS
REMOTE DATA ACQUISITION
ISOLATED DATA ACQUISITION
AC MOTOR CONTROL
Control
SAR
VREF
DOUT
+In
CDAC
Serial
Interface
–In
S/H Amp
Comparator
DCLOCK
CS/SHDN
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
+VCC ..................................................................................................... +6V
Analog Input ........................................................... –0.3V to (+VCC + 0.3V)
Logic Input ............................................................. –0.3V to (+VCC + 0.3V)
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature ..................................................................... +125°C
External Reference Voltage .............................................................. +5.5V
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
NOTE: (1) Stresses above these ratings may permanently damage the device.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PIN CONFIGURATION
VREF
1
+In
2
8
+VCC
7
DCLOCK
ADS7817
–In
3
6
DOUT
GND
4
5
CS/SHDN
PDIP-8,
SOIC-8,
MSOP-8
PIN DESCRIPTIONS
PIN
NAME
1
VREF
DESCRIPTION
2
+In
Non Inverting Input.
3
–In
Inverting Input.
Reference Input.
4
GND
5
CS/SHDN
Ground.
6
DOUT
7
DCLOCK
8
+VCC
Chip Select when LOW, Shutdown Mode when HIGH.
The serial output data word is comprised of 12 bits of data. In operation the data is valid on the falling edge of DCLOCK. The
second clock pulse after the falling edge of CS enables the serial output. After one null bit the data is valid for the next 12 edges.
Data Clock synchronizes the serial data transfer and determines conversion speed.
Power Supply.
PACKAGE/ORDERING INFORMATION
PRODUCT
ADS7817P
ADS7817U
ADS7817U
ADS7817E
ADS7817E
ADS7817E
ADS7817PB
ADS7817UB
ADS7817UB
ADS7817EB
ADS7817EB
ADS7817EB
ADS7817PC
ADS7817UC
ADS7817UC
ADS7817EC
ADS7817EC
ADS7817EC
MAXIMUM
INTEGRAL
LINEARITY
ERROR
(LSB)
MAXIMUM
DIFFERENTIAL
LINEARITY
ERROR
(LSB)
±2
±2
PACKAGE
PACKAGE
DRAWING
NUMBER(1)
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE
MARKING(2)
±2
±2
DIP-8
SO-8
006
182
–40°C to +85°C
–40°C to +85°C
ADS7817P
ADS7817U
"
"
"
"
"
±2
±2
MSOP-8
337
–40°C to +85°C
"
"
"
"
"
"
"
"
"
"
±2
±2
±1
±1
Plastic DIP-8
SO-8
006
182
–40°C to +85°C
–40°C to +85°C
"
"
"
"
"
±2
±1
MSOP
337
–40°C to +85°C
"
"
"
"
"
"
"
"
"
"
±1
±1
±0.75
±0.75
DIP-8
SO-8
006
182
–40°C to +85°C
–40°C to +85°C
"
"
"
"
"
±1
±0.75
MSOP-8
337
–40°C to +85°C
"
"
"
"
"
"
"
"
"
"
ORDERING
NUMBER(3)
ADS7817P
ADS7817U
"
ADS7817U/2K5
A17
ADS7817E
"
ADS7817E/250
"
ADS7817E/2K5
ADS7817PB
ADS7817PB
ADS7817UB
ADS7817UB
"
ADS7817UB/2K5
A17
ADS7817EB
"
ADS7817EB/250
"
ADS7817EB/2K5
ADS7817PC
ADS7817PC
ADS7817UC
ADS7817UC
"
ADS7817UC/2K5
A17
ADS7817EC
"
ADS7817EC/250
"
ADS7817EC/2K5
TRANSPORT
MEDIA
Rails
"
Tape and Reel
Rails
Tape and Reel
"
Rails
"
Tape and Reel
Rails
Tape and Reel
"
Rails
"
Tape and Reel
Rails
Tape and Reel
"
NOTE: (1) For detail drawing and dimension table, please see end of data sheet or Package Drawing File on Web. (2) Performance Grade information is marked
on the reel. (3) Models with a slash(/) are available only in Tape and reel in quantities indicated (e.g. /250 indicates 250 units per reel, /2K5 indicates 2500 devices
per reel). Ordering 2500 pieces of ”ADS7817E/2K5“ will get a single 2500-piece Tape and Reel.
2
ADS7817
SBAS066A
ELECTRICAL CHARACTERISTICS
At –40°C to +85°C, +VCC = +5V, VREF = +2.5V, fSAMPLE = 200kHz, fCLK = 16 • fSAMPLE, –In = +2.5V, unless otherwise specified.
ADS7817
PARAMETER
CONDITIONS
MIN
+In – (–In)
+In
–In
–VREF
–0.3
–0.3
ANALOG INPUT
Full-Scale Input Span
Absolute Input Voltage
Capacitance
Leakage Current
REFERENCE INPUT
Voltage Range
Resistance
Current Drain
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels:
VIH
VIL
VOH
VOL
Data Format
+VREF
VCC +0.3
4
✻
✻
✻
TYP
±2
±2
±6
±4
±0.8
±0.7
✻
✻
✻
✻
✻
0.1
3
–0.3
3.5
✻
✻
✻
–40
✻
✻
✻
✻
✻
✻
✻
✻
+85
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
Clk Cycles
Clk Cycles
kHz
V
GΩ
GΩ
µA
µA
µA
✻
✻
✻
✻
Bits
Bits
LSB(1)
LSB
LSB
LSB
µVrms
dB
dB
dB
dB
dB
dB
✻
✻
✻
✻
✻
✻
✻
✻
3
±1
±1
✻
✻
✻
✻
5.25
800
V
V
V
pF
µA
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
0.4
Binary Two’s Complement
460
40
330
✻
✻
✻
✻
✻
100
20
3
+VCC +0.3
0.8
4.75
±0.5
±0.4
✻
✻
✻
✻
✻
✻
CMOS
IIH = +5µA
IIL = +5µA
IOH = –250µA
IOL = 250µA
±2
±1
✻
✻
✻
✻
✻
✻
2.5
5
5
20
1.3
0.001
CS = VCC
CS = GND, fSAMPLE = 0Hz
At Code FF8h
fSAMPLE = 12.5kHz
CS = VCC
UNITS
✻
✻
–83
–81
71
86
MAX
✻
✻
✻
200
1kHz
5kHz
1kHz
1kHz
✻
✻
✻
TYP
✻
12
at
at
at
at
✻
✻
✻
✻
1.5
5.0Vp-p
5.0Vp-p
5.0Vp-p
5.0Vp-p
MIN
12
±1
±1
±1
±0.5
63
80
82
VIN =
VIN =
VIN =
VIN =
ADS7817C
MAX
✻
✻
12
POWER SUPPLY REQUIREMENTS
VCC
Specified Performance
Quiescent Current
fSAMPLE = 12.5kHz(2, 3)
fSAMPLE = 12.5kHz(3)
Power Down
CS =VCC, fSAMPLE = 0Hz
TEMPERATURE RANGE
Specified Performance
MIN
11
SAMPLING DYNAMICS
Conversion Time
Acquisition Time
Throughput Rate
SINAD
Spurious Free Dynamic Range
ADS7817B
MAX
15
±1
SYSTEM PERFORMANCE
Resolution
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
Noise
Common-Mode Rejection
Power Supply Rejection
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion
TYP
✻
✻
✻
✻
V
V
V
V
✻
V
µA
µA
µA
µA
✻
°C
✻ Specifications same as ADS7817.
NOTE: (1) LSB means Least Significant Bit, with VREF equal to +2.5V, one LSB is 1.22mV. (2) fCLK = 3.2MHz, CS = VCC for 241 clock cycles out of every 256.
(3) See the Power Dissipation section for more information regarding lower sample rates.
ADS7817
SBAS066A
3
TIMING CHARACTERISTICS
At TA = +25°C, VCC = +5V, VREF = +2.5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE, –In = +2.5V, unless otherwise specified.
CHANGE IN OFFSET vs TEMPERATURE
CHANGE IN OFFSET vs REFERENCE VOLTAGE
1.2
5
0.8
4
Delta from 25°C (LSB)
Change in Offset (LSB)
4.5
3.5
3
2.5
2
1.5
1
0.4
0.0
–0.4
–0.8
0.5
–1.2
0
1.0
1.25
1.5
1.75
2.0
Reference Voltage (V)
2.25
–50
2.5
75
100
0.1
Delta from 25°C (LSB)
Change in Gain (LSB)
25
50
Temperature (°C)
0.15
3.5
3
2.5
2
1.5
1
0.05
0
–0.05
–0.1
0.5
0
1.0
1.25
1.5
1.75
2.0
Reference Voltage (V)
2.25
2.5
–0.15
–50
11.5
15
Peak-to-Peak Noise (LSB)
18
11.0
10.5
10.0
9.5
9.0
1
Reference Voltage
0
25
50
75
100
PEAK-TO-PEAK NOISE vs REFERENCE VOLTAGE
12.0
0.1
–25
Temperature (°C)
EFFECTIVE NUMBER OF BITS
vs REFERENCE VOLTAGE
Effective Number of Bits
0
CHANGE IN GAIN vs TEMPERATURE
CHANGE IN GAIN vs REFERENCE VOLTAGE
4
4
–25
10
12
9
6
3
0
0.1
1
10
Reference Voltage
ADS7817
SBAS066A
TIMING CHARACTERISTICS (Cont.)
At TA = +25°C, VCC = +5V, VREF = +2.5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE, –In = +2.5V, unless otherwise specified.
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 9.9kHz, –0.5dB)
POWER SUPPLY REJECTION vs RIPPLE FREQUENCY
0
0
–20
–20
–30
Amplitude (dB)
Power Supply Rejection (dB)
–10
–40
–50
–60
–40
–60
–80
–70
–100
–80
–90
–120
10
100
1000
Ripple Frequency (kHz)
10000
0
25
100
95
73
72
–95
90
SNR
–90
SFDR
71
SFDR (dB)
SNR and SINAD (dB)
75
SPURIOUS FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION
vs INPUT FREQUENCY
SIGNAL-TO-NOISE RATIO AND
SIGNAL-TO-(NOISE+DISTORTION)
vs INPUT FREQUENCY
70
SINAD
85
–85
80
–80
75
69
–75
THD
70
68
–70
65
67
1
10
–65
1
100
10
100
Input Frequency (kHz)
Input Frequency (kHz)
SIGNAL-TO-(NOISE+DISTORTION)
vs INPUT LEVEL
CHANGE IN INTEGRAL LINEARITY and DIFFERENTIAL
LINEARITY vs SAMPLE RATE
1.5
Delta from fSAMPLE = 200kHz (LSB)
80
70
60
SINAD (dB)
50
Frequency (kHz)
THD (dB)
1
50
40
30
20
1.0
Change in Integral
Linearity (LSB)
0.5
0
Change in Differential
Linearity (LSB)
–0.5
10
–60
–50
–40
–30
Input Level (dB)
ADS7817
SBAS066A
–20
–10
0
0
80
160
240
320
400
Sample Rate (kHz)
5
TIMING CHARACTERISTICS (Cont.)
At TA = +25°C, VCC = +5V, VREF = +2.5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE, –In = +2.5V, unless otherwise specified.
DIFFERENTIAL LINEARITY ERROR vs CODE
1.00
0.75
0.75
0.50
0.50
0.25
0.25
DLE (LSB)
ILE (LSB)
INTEGRAL LINEARITY ERROR vs CODE
1.00
0.00
–0.25
0.00
–0.25
–0.50
–0.50
–0.75
–0.75
–1.00
–1.00
800
000
800
7FF
000
CHANGE IN INTEGRAL LINEARITY AND DIFFERENTIAL
LINEARITY vs REFERENCE VOLTAGE
INPUT LEAKAGE CURRENT vs TEMPERATURE
10
0.05
Leakage Current (nA)
Delta from +2.5V Reference (LSB)
0.10
Change in Differential
Linearity (LSB)
0.00
–0.05
–0.10
Change in Integral
Linearity (LSB)
–0.15
–0.20
1
0.1
0.01
1
1.25
1.5
1.75
2.0
Reference Voltage (V)
2.25
–50
2.5
0
25
50
75
100
75
100
POWER DOWN SUPPLY CURRENT
vs TEMPERATURE
600
3
550
2.5
Supply Current (µA)
Supply Current (µA)
–25
Temperature (°C)
SUPPLY CURRENT vs TEMPERATURE
500
450
400
350
2
1.5
1
0.5
300
0
–50
–25
0
25
50
Temperature (°C)
6
7FF
Hex BTC Code
Hex BTC Code
75
100
–50
–25
0
25
50
Temperature (°C)
ADS7817
SBAS066A
TIMING CHARACTERISTICS (Cont.)
At TA = +25°C, VCC = +5V, VREF = +2.5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE, –In = +2.5V, unless otherwise specified.
REFERENCE CURRENT vs TEMPERATURE
(Code = FF8h)
REFERENCE CURRENT vs SAMPLE RATE
(Code = FF8h)
20
30
Reference Current (µA)
Reference Current (µA)
25
15
10
5
20
15
10
5
0
0
0
40
80
120
Sample Rate (kHz)
ADS7817
SBAS066A
160
200
–50
–25
0
25
50
75
100
Temperature (°C)
7
THEORY OF OPERATION
2 • VREF
peak-to-peak
The ADS7817 is a classic successive approximation register
(SAR) analog-to-digital (A/D) converter. The architecture is
based on capacitive redistribution which inherently includes
a sample/hold function. The converter is fabricated on a 0.6µ
CMOS process. The architecture and process allow the
ADS7817 to acquire and convert an analog signal at up to
200,000 conversions per second while consuming very little
power.
The external clock can vary between 10kHz (625Hz throughput) and 3.2MHz (200kHz throughput). The duty cycle of
the clock is essentially unimportant as long as the minimum
high and low times are at least 150ns. The minimum clock
frequency is set by the leakage on the capacitors internal to
the ADS7817.
The analog input is provided to two input pins: +In and –In.
When a conversion is initiated, the differential input on these
pins is sampled on the internal capacitor array. While a
conversion is in progress, both inputs are disconnected from
any internal function.
The digital result of the conversion is clocked out by the
DCLOCK input and is provided serially, most significant bit
first, on the DOUT pin. The digital data that is provided on the
DOUT pin is for the conversion currently in progress—there
is no pipeline delay. It is possible to continue to clock the
ADS7817 after the conversion is complete and to obtain the
serial data least significant bit first. See the Digital Interface
section for more information.
Common
Voltage
Single-Ended Input
VREF
peak-to-peak
ADS7817
Common
Voltage
VREF
peak-to-peak
Differential Input
FIGURE 1. Methods of Driving the ADS7817: SingleEnded or Differential.
5
VCC = 5V
4.0
4
Common Voltage Range (V)
The ADS7817 requires an external reference, an external
clock, and a single +5V power source. The external reference can be any voltage between 100mV and 2.5V. The
value of the reference voltage directly sets the range of the
analog input. The reference input current depends on the
conversion rate of the ADS7817.
ADS7817
Single-Ended Input
3
2.8
2.2
2
1
0
–0.3
–1
0.0
0.5
1.0
1.5
2.0
2.5
VREF (V)
FIGURE 2. Single-Ended Input: Common Voltage Range vs
VREF.
ANALOG INPUT
When the input is differential, the amplitude of the input is the
difference between the +In and –In input, or: +In – (–In). A
voltage or signal is common to both of these inputs. The peakto-peak amplitude of each input is VREF about this common
voltage. However, since the inputs are 180° out of phase, the
peak-to-peak amplitude of the difference voltage is 2 • VREF.
The value of VREF also determines the range of the voltage
that may be common to both inputs (see Figure 3).
5
VCC = 5V
4.0
4
Common Voltage Range (V)
The analog input is bipolar and fully differential. There are
two general methods of driving the analog input of the
ADS7817: single-ended or differential (see Figure 1). When
the input is single-ended, the –In input is held at a fixed
voltage. The +In input swings around the same voltage and
the peak-to-peak amplitude is 2 • VREF. The value of VREF
determines the range over which the common voltage may
vary (see Figure 2).
3
Differential Input
2.75
2
1
1.95
0
–0.3
–1
0.0
0.5
1.0
1.5
2.0
2.5
VREF (V)
FIGURE 3. Differential Input: Common Voltage Range vs
VREF.
8
ADS7817
SBAS066A
In each case, care should be taken to ensure that the output
impedance of the sources driving the +In and –In inputs are
matched. If this is not observed, the two inputs could have
different settling times. This may result in offset error, gain
error, and linearity error which change with both temperature
and input voltage. If the impedance cannot be matched, the
errors can be lessened by giving the ADS7817 more acquisition time.
The input current on the analog inputs depends on a number
of factors: sample rate, input voltage, and source impedance.
Essentially, the current into the ADS7817 charges the internal capacitor array during the sample period. After this
capacitance has been fully charged, there is no further input
current. The source of the analog input voltage must be able
to charge the input capacitance (15pF) to a 12-bit settling
level within 1.5 clock cycles. When the converter goes into
the hold mode or while it is in the power down mode, the
input impedance is greater than 1GΩ.
Care must be taken regarding the absolute analog input
voltage. The +In input should always remain within the
range of GND –300mV to VCC +300mV. The –In input
should always remain within the range of GND –300mV to
4V. Outside of these ranges, the converter’s linearity may
not meet specifications.
With lower reference voltages, extra care should be taken to
provide a clean layout including adequate bypassing, a clean
power supply, a low-noise reference, and a low-noise input
signal. Because the LSB size is lower, the converter will also
be more sensitive to external sources of error such as nearby
digital signals and electromagnetic interference.
The current that must be provided by the external reference
will depend on the conversion result. The current is lowest
at negative full-scale (800h) and is typically 15µA at a
200kHz conversion rate (25°C). For the same conditions, the
current will increase as the analog input approaches positive
full scale, reaching 25µA at an output result of 7FFh. The
current does not increase linearly, but depends, to some
degree, on the bit pattern of the digital output.
The reference current diminishes directly with both conversion rate and reference voltage. As the current from the
reference is drawn on each bit decision, clocking the converter more quickly during a given conversion period will
not reduce the overall current drain from the reference. The
reference current changes only slightly with temperature.
See the curves, “Reference Current vs Sample Rate” and
“Reference Current vs Temperature” in the Typical Performance Curves section for more information.
DIGITAL INTERFACE
REFERENCE INPUT
The external reference sets the analog input range. The
ADS7817 will operate with a reference in the range of 100mV
to 2.5V. There are several important implications of this.
As the reference voltage is reduced, the analog voltage
weight of each digital output code is reduced. This is often
referred to as the LSB (least significant bit) size and is equal
to two times the reference voltage divided by 4096. This
means that any offset or gain error inherent in the A/D
converter will appear to increase, in terms of LSB size, as
the reference voltage is reduced. The typical performance
curves of “Change in Offset vs Reference Voltage” and
“Change in Gain vs Reference Voltage” provide more information.
The noise inherent in the converter will also appear to
increase with lower LSB size. With a 2.5V reference, the
internal noise of the converter typically contributes only
0.52 LSB peak-to-peak of potential error to the output code.
When the external reference is 100mV, the potential error
contribution from the internal noise will be 25 times larger—
13 LSBs. The errors due to the internal noise are gaussian in
nature and can be reduced by averaging consecutive conversion results.
For more information regarding noise, consult the typical
performance curves “Effective Number of Bits vs Reference
Voltage” and “Peak-to-Peak Noise vs Reference Voltage.”
Note that the effective number of bits (ENOB) figure is
calculated based on the converter’s signal-to-(noise + distortion) with a 1kHz, 0dB input signal. SINAD is related to
ENOB as follows: SINAD = 6.02 • ENOB + 1.76.
ADS7817
SBAS066A
SERIAL INTERFACE
The ADS7817 communicates with microprocessors and other
digital systems via a synchronous 3-wire serial interface as
shown in Figure 4 and Table I. The DCLOCK signal
synchronizes the data transfer with each bit being transmitted on the falling edge of DCLOCK. Most receiving systems
will capture the bitstream on the rising edge of DCLOCK.
However, if the minimum hold time for DOUT is acceptable,
the system can use the falling edge of DCLOCK to capture
each bit.
DESCRIPTION
MIN
tSMPL
SYMBOL
Analog Input Sample TIme
1.5
TYP
MAX
UNITS
2.0
Clk Cycles
tCONV
Conversion Time
tCYC
Throughput Rate
200
kHz
tCSD
CS Falling to
DCLOCK LOW
0
ns
tSUCS
CS Falling to
DCLOCK Rising
30
ns
thDO
DCLOCK Falling to
Current DOUT Not Valid
15
ns
tdDO
DCLOCK Falling to Next
DOUT Valid
85
tdis
CS Rising to DOUT Tri-State
ten
DCLOCK Falling to DOUT
Enabled
tf
tr
12
Clk Cycles
150
ns
25
50
ns
50
100
ns
DOUT Fall Time
70
100
ns
DOUT Rise Time
60
100
ns
TABLE I. Timing Specifications –40°C to +85°C.
9
tCYC
CS/SHDN
POWER
DOWN
tSUCS
DCLOCK
tCSD
DOUT
HI-Z
NULL
BIT
tSMPL
NULL
BIT
HI-Z
B11 B10 B9
(MSB)
B8
B7
B6
B5
B4
B3
B2
B1 B0(1)
tCONV
B11 B10
B9
B8
tDATA
Note: (1) After completing the data transfer, if further clocks are applied with CS
LOW, the A/D will output LSB-First data then followed with zeroes indefinitely.
tCYC
CS/SHDN
tSUCS
POWER DOWN
DCLOCK
tCSD
DOUT
HI-Z
NULL
BIT
tSMPL
HI-Z
B11 B10 B9
(MSB)
B8
B7
B6
B5
B4
B3
B2
B1
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9 B10 B11
(2)
tCONV
tDATA
Note: (2) After completing the data transfer, if further clocks are applied with CS
LOW, the A/D will output zeroes indefinitely.
tDATA: During this time, the bias current and the comparator power down and the reference input
becomes a high impedance node, leaving the CLK running to clock out LSB-First data or zeroes.
FIGURE 4. ADS7817 Basic Timing Diagrams.
A falling CS signal initiates the conversion and data transfer.
The first 1.5 to 2.0 clock periods of the conversion cycle are
used to sample the input signal. After the second falling
DCLOCK edge, DOUT is enabled and will output a LOW
value for one clock period. For the next 12 DCLOCK
periods, DOUT will output the conversion result, most significant bit first. After the least significant bit (B0) has been
output, subsequent clocks will repeat the output data but in
a least significant bit first format.
After the most significant bit (B11) has been repeated, DOUT
will tri-state. Subsequent clocks will have no effect on the
converter. A new conversion is initiated only when CS has
been taken HIGH and returned LOW.
DATA FORMAT
The output data from the ADS7817 is in Binary Two’s
Complement format as shown in Table II. This table represents the ideal output code for the given input voltage and
does not include the effects of offset, gain error, or noise.
DESCRIPTION
Full Scale Input Span
ANALOG VALUE
2 • VREF
DIGITAL OUTPUT:
BINARY TWO’S COMPLEMENT
Least Significant
Bit (LSB)
2 • VREF/4096
BINARY CODE
HEX CODE
+Full Scale
VREF –1 LSB
0111 1111 1111
7FF
0V
0000 0000 0000
000
0V – 1 LSB
1111 1111 1111
FFF
–VREF
1000 0000 0000
800
Midscale
Midscale – 1 LSB
–Full Scale
POWER DISSIPATION
The architecture of the converter, the semiconductor fabrication process, and a careful design allow the ADS7817 to
convert at up to a 200kHz rate while requiring very little
power. Still, for the absolute lowest power dissipation, there
are several things to keep in mind.
The power dissipation of the ADS7817 scales directly with
conversion rate. The first step to achieving the lowest power
dissipation is to find the lowest conversion rate that will
satisfy the requirements of the system.
In addition, the ADS7817 is in power down mode under two
conditions: when the conversion is complete and whenever
CS is HIGH (see Figure 1). Ideally, each conversion should
occur as quickly as possible, preferably, at a 3.2MHz clock
rate. This way, the converter spends the longest possible
time in the power down mode. This is very important as the
converter not only uses power on each DCLOCK transition
(as is typical for digital CMOS components) but also uses
some current for the analog circuitry, such as the comparator. The analog section dissipates power continuously, until
the power down mode is entered.
Figure 6 shows the current consumption of the ADS7817
versus sample rate. For this graph, the converter is clocked
at 3.2MHz regardless of the sample rate—CS is HIGH for
the remaining sample period. Figure 7 also shows current
consumption versus sample rate. However, in this case, the
DCLOCK period is 1/16th of the sample period—CS is
HIGH for one DCLOCK cycle out of every 16.
TABLE II. Ideal Input Voltages and Output Codes.
10
ADS7817
SBAS066A
1.4V
3kΩ
VOH
DOUT
DOUT
VOL
Test Point
tr
100pF
CLOAD
tf
Voltage Waveforms for DOUT Rise and Fall Times tr, and tf
Load Circuit for tdDO, tr, and tf
Test Point
DCLOCK
VIL
VCC
tdDO
VOH
DOUT
tdis Waveform 2, ten
3kΩ
DOUT
tdis Waveform 1
100pF
CLOAD
VOL
thDO
Load Circuit for tdis and tden
Voltage Waveforms for DOUT Delay Times, tdDO
VIH
CS/SHDN
DOUT
Waveform 1(1)
CS/SHDN
90%
DCLOCK
10%
DOUT
1
2
tdis
DOUT
Waveform 2(2)
VOL
B11
ten
Voltage Waveforms for tdis
NOTES: (1) Waveform 1 is for an output with internal conditions such that
the output is HIGH unless disabled by the output control. (2) Waveform 2
is for an output with internal conditions such that the output is LOW unless
disabled by the output control.
Voltage Waveforms for ten
FIGURE 5. Timing Diagrams and Test Circuits for the Parameters in Table I.
1000
Supply Current (µA)
Supply Current (µA)
1000
100
10
TA = 25°C
VCC = +5V
VREF = +2.5V
fCLK = 3.2MHz
1
100
10
TA = 25°C
VCC = +5V
VREF = +2.5V
fCLK = 16 • fSAMPLE
1
1
10
100
1000
Sample Rate (kHz)
FIGURE 6. Maintaining fCLK at the Highest Possible Rate
Allows Supply Current to Drop Directly with
Sample Rate.
ADS7817
SBAS066A
1
10
100
1000
Sample Rate (kHz)
FIGURE 7. Scaling fCLK Reduces Supply Current Only
Slightly with Sample Rate.
11
There is an important distinction between the power down
mode that is entered after a conversion is complete and the
full power down mode which is enabled when CS is HIGH.
While both power down the analog section, the digital section
is powered down only when CS is HIGH. Thus, if CS is left
LOW at the end of a conversion and the converter is continually clocked, the power consumption will not be as low as
when CS is HIGH. See Figure 8 for more information.
By lowering the reference voltage, the ADS7817 requires
less current to completely charge its internal capacitors on
both the analog input and the reference input. This reduction
in power dissipation should be weighed carefully against the
resulting increase in noise, offset, and gain error as outlined
in the Reference section.
60
TA = 25°C
VCC = +5V
VREF = +2.5V
fCLK = 16 • fSAMPLE
Supply Current (µA)
50
40
CS LOW
(GND)
30
20
CS = HIGH (VCC)
10
0
1
10
100
1000
Sample Rate (kHz)
FIGURE 8. Shutdown Current is Considerably Lower with
CS HIGH than when CS is LOW.
SHORT CYCLING
Another way of saving power is to utilize the CS signal to
short cycle the conversion. Because the ADS7817 places the
latest data bit on the DOUT line as it is generated, the
converter can easily be short cycled. This term means that
the conversion can be terminated at any time. For example,
if only 8-bits of the conversion result are needed, then the
conversion can be terminated (by pulling CS HIGH) after
the 8th bit has been clocked out.
This technique can be used to lower the power dissipation in
those applications where an analog signal is being monitored
until some condition becomes true. For example, if the
signal is outside a predetermined range, the full 12-bit
conversion result may not be needed. If so, the conversion
can be terminated after the first n-bits, where n might be as
low as 3 or 4. This results in lower power dissipation in both
the converter and the rest of the system, as they spend more
time in the power down mode.
12
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS7817 circuitry. This is particularly
true if the reference voltage is low and/or the conversion rate
is high. At 200kHz conversion rate, the ADS7817 makes a bit
decision every 312ns. That is, for each subsequent bit decision, the digital output must be updated with the results of the
last bit decision, the capacitor array appropriately switched
and charged, and the input to the comparator settled to a
12-bit level all within one clock cycle.
The basic SAR architecture is sensitive to spikes on the
power supply, reference, and ground connections that occur
just prior to latching the comparator output. Thus, during
any single conversion for an n-bit SAR converter, there are
n “windows” in which large external transient voltages can
easily affect the conversion result. Such spikes might originate from switching power supplies, digital logic, and high
power devices, to name a few. This particular source of error
can be very difficult to track down if the glitch is almost
synchronous to the converter’s DCLOCK signal—as the
phase difference between the two changes with time and
temperature, causing sporadic misoperation.
With this in mind, power to the ADS7817 should be clean
and well bypassed. A 0.1µF ceramic bypass capacitor should
be placed as close to the ADS7817 package as possible. In
addition, a 1 to 10µF capacitor and a 10Ω series resistor may
be used to lowpass filter a noisy supply.
The reference should be similarly bypassed with a 0.1µF
capacitor. Again, a series resistor and large capacitor can be
used to lowpass filter the reference voltage. If the reference
voltage originates from an op amp, be careful that the opamp can drive the bypass capacitor without oscillation (the
series resistor can help in this case). Keep in mind that while
the ADS7817 draws very little current from the reference on
average, there are higher instantaneous current demands
placed on the external reference circuitry.
Also, keep in mind that the ADS7817 offers no inherent
rejection of noise or voltage variation in regards to the
reference input. This is of particular concern when the
reference voltage is derived from the power supply. Any
noise and ripple from the supply that is not rejected by the
external reference circuitry will appear directly in the digital
results. While high frequency noise can be filtered out as
described in the previous paragraph, voltage variation due to
line frequency (50Hz or 60Hz) can be difficult to remove.
The GND pin on the ADS7817 should be placed on a clean
ground point. In many cases, this will be the “analog”
ground. Avoid connecting the GND pin too close to the
grounding point for a microprocessor, microcontroller, or
digital signal processor. If needed, run a ground trace directly from the converter to the power supply connection
point. The ideal layout will include an analog ground plane
for the converter and associated analog circuitry.
ADS7817
SBAS066A
APPLICATION CIRCUITS
Figures 9, 10 and 11 show some typical applications circuits
for the ADS7817. Figure 9 shows a low cost, low power
circuit for basic data acquisition. Total power dissipation in
the ADS7817 and reference circuitry is under 5mW over
temperature, power supply variations, and at a 200kHz sample
rate.
Figure 11 is a similar application that isolates the digital
outputs of the three ADS7817s instead of the analog signal
from the motor. Here, the reference voltage for the ADS7817
is 150mV, and the analog input of each ADS7817 is connected directly to the current sense resistor. By removing the
ISO130 from the signal path, a greater signal-to-noise ratio is
achieved in the sensing system. However, nine optical isolators are needed to isolate the A/D converters.
Figure 10 is a motor control application using three ISO130s
to isolate the motor from the sensing system (three ADS7817s
and a DSP56004). The ISO130 provides 10kV/µs (minimum)
isolation-mode rejection, 85kHz large signal bandwidth, and
a fixed gain of 8. The ADS7817’s reference voltage is 1.2V
and is derived from a REF1004-1.2. This gives the converter
a full-scale input range of ±1.2V. Because of the gain of 8 in
the ISO130, the current sense resistor should give a worstcase output voltage of less than ±150mV.
+5V
5Ω to 10Ω
+ 1µF to
10µF
24.9kΩ
22Ω
REF1004-2.5
+
ADS7817
VREF
4.7µF
VCC
0.1µF
+In
CS
–In
DOUT
GND
+ 1µF to
10µF
Microcontroller
DCLOCK
FIGURE 9. Low Cost, Low Power Data Acquisition System.
ADS7817
SBAS066A
13
+5V
R1
1kΩ
+VISO3
78L05
REF1004-1.2
Motorola
DSPS6004
C10
5µF
C1
C2
0.1µF GND3 0.1µF
+
C11
0.1µF
+5V
WST
WSR
R2
200Ω
to 3rd Motor
Leg Driver
DOUT
C3
0.01µF
ISO130
ADS7817
CLK
SDI 0
CS/SHDN
R3
200Ω
System
GND
System
GND
+5V
GND3
+VISO2
R4
1kΩ
78L05
SCKR
SCK/SCL
REF1004-1.2
C12
5µF
C4
C5
0.1µF GND2 0.1µF
+
C13
0.1µF
+5V
R5
200Ω
to 2nd Motor
Leg Driver
CS/SHDN
System
GND
System
GND
from
PWM
•••
+5V
GND2
+VISO1
R7
1kΩ
78L05
REF1004-1.2
C14
5µF
C8
C7
0.1µF GND1 0.1µF
+
C15
0.1µF
+5V
R8
200Ω
0.01µF
–
System
GND
RSENSE
HV–
(Several
Hundred
Volts)
ADS7817
R9
200Ω
R10
+
CLK
C9
0.01µF
ISO130
AC Motor
•••
SDI 1
CLK
ADS7817
R6
200Ω
First Motor
Leg Driver
HV+
(Several
Hundred
Volts)
DOUT
C6
0.01µF
ISO130
•••
from
PWM
CS/SHDN
DOUT
SCKT
SDO 0
MOSI/HA 0
SD02
System
GND
SS/HA2
System
GND
GND1
FIGURE 10. Motor Control Using the ISO130, ADS7817, and DSPS6004.
14
ADS7817
SBAS066A
+VISO1
R1
+5V
+VCC
Motorola
DSP56004
R2
768Ω
+ C
1
4.7µF
R3
301Ω
REF1004-1.2
WST
+150mV
VREF
+ C
2
4.7µF
R4
43.2Ω
C3
0.1µF
To 3rd Motor
Leg
SDO0
SDO1
SDO2
SCKT
SCKR
SDI0
To 2nd Motor
Leg
SDI1
WSR
SCK/SCL
MISO/SDA
VREF +VCC
from
PWM
HREQ
R5
200Ω
AC Motor
MOSI/HA0
SS/HA2
C4
0.01µF
RSENSE
ADS7817
CS
DOUT
CLK
R6
200Ω
from
PWM
Opto-Couplers(1)
1st Motor Leg
NOTE: (1) Suggested Opto-couplers are HCPL-2611 or
HCPL-7611. Inverters or buffers will be needed to drive
these devices. See the appropriate Hewlett-Packard data
sheet for more information.
FIGURE 11. Motor Control Using an Isolated ADS7817.
ADS7817
SBAS066A
15
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS7817E/250
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
A17
ADS7817E/250G4
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
A17
ADS7817E/2K5
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
A17
ADS7817E/2K5G4
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
A17
ADS7817EB/250
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
A17
ADS7817EB/2K5
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
A17
ADS7817EB/2K5G4
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
A17
ADS7817EC/250
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
A17
ADS7817EC/250G4
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
A17
ADS7817EC/2K5
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
A17
ADS7817P
OBSOLETE
PDIP
P
8
TBD
Call TI
Call TI
-40 to 85
ADS7817PB
OBSOLETE
PDIP
P
8
TBD
Call TI
Call TI
-40 to 85
ADS7817PC
OBSOLETE
PDIP
P
8
TBD
Call TI
Call TI
-40 to 85
ADS7817U
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS
7817U
ADS7817U/2K5
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS
7817U
ADS7817U/2K5G4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS
7817U
ADS7817UB
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS
7817U
B
ADS7817UBG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS
7817U
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
B
ADS7817UC
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS
7817U
C
ADS7817UC/2K5
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS
7817U
C
ADS7817UG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS
7817U
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Feb-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS7817E/250
VSSOP
DGK
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
ADS7817E/2K5
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
ADS7817EB/250
VSSOP
DGK
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
ADS7817EB/2K5
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
ADS7817EC/250
VSSOP
DGK
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
ADS7817EC/2K5
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
ADS7817U/2K5
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ADS7817UC/2K5
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Feb-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS7817E/250
VSSOP
DGK
8
250
210.0
185.0
35.0
ADS7817E/2K5
VSSOP
DGK
8
2500
367.0
367.0
38.0
ADS7817EB/250
VSSOP
DGK
8
250
210.0
185.0
35.0
ADS7817EB/2K5
VSSOP
DGK
8
2500
367.0
367.0
38.0
ADS7817EC/250
VSSOP
DGK
8
250
210.0
185.0
35.0
ADS7817EC/2K5
VSSOP
DGK
8
2500
367.0
367.0
38.0
ADS7817U/2K5
SOIC
D
8
2500
367.0
367.0
38.0
ADS7817UC/2K5
SOIC
D
8
2500
367.0
367.0
38.0
Pack Materials-Page 2
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