ADS7821U

® ADS 782 1 ADS7821 782 1 ADS 16-Bit 10µs Sampling CMOS ANALOG-to-DIGITAL CONVERTER FEATURES q 100kHz min SAMPLING RATE q 0 to +5V INPUT RANGE q 86dB min SINAD WITH 20kHz INPUT q DNL: 16-bits “No Missing Codes” q SINGLE +5V SUPPLY OPERATION q PIN-COMPATIBLE WITH 12-BIT ADS7820 q USES INTERNAL OR EXTERNAL REFERENCE q FULL PARALLEL DATA OUTPUT q 100mW max POWER DISSIPATION q 28-PIN 0.3" PLASTIC DIP AND SOIC DESCRIPTION The ADS7821 is a complete 16-bit sampling A/D using state-of-the-art CMOS structures. It contains a complete 16-bit, capacitor-based, SAR A/D with S/H, reference, clock, interface for microprocessor use, and three-state output drivers. The ADS7821 is specified at a 100kHz sampling rate, and guaranteed over the full temperature range. Lasertrimmed scaling resistors provide a 0 to +5V input range, with power dissipation under 100mW. The 28-pin ADS7821 is available in a plastic 0.3" DIP and in an SOIC, both fully specified for operation over the –25°C to +85°C range. Clock Successive Approximation Register and Control Logic R/C CS BYTE BUSY CDAC 5kΩ 0 to +5V Input 6.66kΩ 20kΩ Comparator CAP Buffer 4kΩ REF Internal +2.5V Ref Output Latches and Three State Drivers Three State Parallel Data Bus International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1996 Burr-Brown Corporation PDS-1323A 1 ADS7821 Printed in U.S.A. June, 1996 SPECIFICATIONS ELECTRICAL TA = –25°C to +85°C, fS = 100kHz, VDIG = VANA = VD = +5V, using external reference, unless otherwise specified. ADS7821P, U PARAMETER RESOLUTION ANALOG INPUT Voltage Range Impedance Capacitance THROUGHPUT SPEED Conversion Cycle Throughput Rate DC ACCURACY Integral Linearity Error No Missing Codes Transition Noise(2) Full Scale Error(3,4) Full Scale Error Drift Full Scale Error(3,4) Full Scale Error Drift Offset Error Offset Error Drift Power Supply Sensitivity (VDIG = VANA = VD) AC ACCURACY Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise+Distortion) Signal-to-Noise Full-Power Bandwidth(6) SAMPLING DYNAMICS Aperture Delay Transient Response Overvoltage Recovery(7) REFERENCE Internal Reference Voltage Internal Reference Source Current (Must use external buffer) Internal Reference Drift External Reference Voltage Range for Specified Linearity External Reference Current Drain DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Data Coding VOL VOH Leakage Current Output Capacitance DIGITAL TIMING Bus Access Time Bus Relinquish Time Acquire and Convert 100 ±4 15 0.9 ±2 Internal Reference Internal Reference ±7 ±2 +4.75V < VD < +5.25V ±0.5 D ±0.5 ±8 ±12 ±5 D ±8 ±0.25 ±4 16 D ±0.25 CONDITIONS MIN TYP MAX 16 D D D 10 D ±3 D MIN ADS7821PB, UB TYP MAX D UNITS Bits 0 to +5 10 35 V kΩ pF µs kHz LSB(1) Bits LSB % ppm/°C % ppm/°C mV ppm/°C LSB fIN = 20kHz fIN = 20kHz fIN = 20kHz fIN = –60dB Input fIN = 20kHz 90 –90 83 28 83 250 40 94 –94 86 30 86 D D 2 150 D 2.52 D D D D D D D dB(5) dB dB dB dB kHz ns µs ns V µA ppm/°C V µA FS Step 2.48 2.5 1 8 2.5 2.3 Ext. 2.5000V Ref 2.7 100 D D D –0.3 +2.0 +0.8 VD +0.3V ±10 ±10 D D D D D D V V µA µA ISINK = 1.6mA ISOURCE = 500µA High-Z State, VOUT = 0V to VDIG High-Z State +4 Parallel 16 bits Straight Binary +0.4 D ±5 15 D D D D D V V µA pF 83 83 ns ns The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® ADS7821 2 SPECIFICATIONS (CONT) ELECTRICAL TA = –25°C to +85°C, f S = 100kHz, VDIG = VANA = VD = +5V, using external reference, unless otherwise specified. ADS7821P, U PARAMETER POWER SUPPLIES Specified Performance VDIG VANA IDIG IANA Power Dissipation TEMPERATURE RANGE Specified Performance Derated Performance Storage Thermal Resistance (θJA) Plastic DIP SOIC CONDITIONS MIN TYP MAX MIN ADS7821PB, UB TYP MAX UNITS Must be ≤ VANA +4.75 +4.75 +5 +5 0.3 16 +5.25 +5.25 D D D D D D D D fS = 100kHz –25 –55 –65 75 75 100 +85 +125 +150 D D D D D D D D D V V mA mA mW °C °C °C °C/W °C/W NOTES: (1) LSB means Least Significant Bit. For the 16-bit, 0 to +5V input ADS721, one LSB is 76µV. (2) Typical rms noise at worst case transitions and temperatures. (3) Adjustable to zero with external potentiometer as shown in Figure 6a. (4) Full scale error is the worst case of Full Scale untrimmed deviation from ideal last code transition divided by the transition voltage and includes the effect of offset error. (5) All specifications in dB are referred to a full-scale input. (6) FullPower Bandwidth defined as Full-Scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60dB, or 10 bits of accuracy. (7) Recovers to specified performance after 2 x FS input overvoltage. ABSOLUTE MAXIMUM RATINGS Analog Inputs: VIN ...................................................... –0.7V to VANA +0.3V REF ................................... AGND2 –0.3V to +VANA +0.3V CAP .......................................... Indefinite Short to AGND2, Momentary Short to VANA Ground Voltage Differences: DGND, AGND1, AGND2 ................... ±0.3V VANA ....................................................................................................... 7V VDIG to VANA ..................................................................................... +0.3V VDIG ....................................................................................................... 7V Digital Inputs ............................................................ –0.3V to +VDIG +0.3V Maximum Junction Temperature ................................................... +165°C Internal Power Dissipation ............................................................. 825mW Lead Temperature (soldering, 10s) ................................................ +300°C ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. BurrBrown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. PACKAGE INFORMATION PRODUCT ADS7821P ADS7821PB ADS7821U ADS7821UB PACKAGE Plastic DIP Plastic DIP SOIC SOIC PACKAGE DRAWING NUMBER(1) 246 246 217 217 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ORDERING INFORMATION MINIMUM SIGNAL-TO(NOISE + DISTORTION) RATIO (dB) 83 86 83 86 PRODUCT ADS7821P ADS7821PB ADS7821U ADS7821UB MAXIMUM LINEARITY ERROR (LSB) ±4 ±3 ±4 ±3 SPECIFICATION TEMPERATURE RANGE –25° C –25° C –25° C –25° C to to to to +85°C +85°C +85°C +85°C PACKAGE Plastic DIP Plastic DIP SOIC SOIC ® 3 ADS7821 PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NAME VIN AGND1 REF CAP AGND2 D15 (MSB) D14 D13 D12 D11 D10 D9 D8 DGND D7 D6 D5 D4 D3 D2 D1 D0 (LSB) BYTE R/C CS BUSY VANA VDIG DIGITAL I/O DESCRIPTION Analog Input. Analog Ground. Used internally as ground reference point. Reference Input/Output. 2.2µF tantalum capacitor to ground. Reference Buffer Capacitor. 2.2µF tantalum capacitor to ground. Analog Ground. O O O O O O O O Data Bit 15. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW. Data Bit 14. Hi-Z state when CS is HIGH, or when R/C is LOW. Data Bit 13. Hi-Z state when CS is HIGH, or when R/C is LOW. Data Bit 12. Hi-Z state when CS is HIGH, or when R/C is LOW. Data Bit 11. Hi-Z state when CS is HIGH, or when R/C is LOW. Data Bit 10. Hi-Z state when CS is HIGH, or when R/C is LOW. Data Bit 9. Hi-Z state when CS is HIGH, or when R/C is LOW. Data Bit 8. Hi-Z state when CS is HIGH, or when R/C is LOW. Digital Ground. O O O O O O O O I I I O Data Bit 7. Hi-Z state when CS is HIGH, or when R/C is LOW. Data Bit 6. Hi-Z state when CS is HIGH, or when R/C is LOW. Data Bit 5. Hi-Z state when CS is HIGH, or when R/C is LOW. Data Bit 4. Hi-Z state when CS is HIGH, or when R/C is LOW. Data Bit 3. Hi-Z state when CS is HIGH, or when R/C is LOW. Data Bit 2. Hi-Z state when CS is HIGH, or when R/C is LOW. Data Bit 1. Hi-Z state when CS is HIGH, or when R/C is LOW. Data Bit 0. Lease Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW. Swaps Pins 6 through 13 with Pins 15 through 22 when HIGH. See Figures 2 and 5. With CS LOW and BUSY HIGH, a Falling Edge on R/C Initiates a New Conversion. With CS LOW, a rising edge on R/C enables the parallel output. Internally OR’d with R/C. If R/C LOW, a falling edge on CS initiates a new conversion. At the start of a conversion, BUSY goes LOW and stays LOW until the conversion is completed and the digital outputs have been updated. Analog Supply Input. Nominally +5V. Decouple to ground with 0.1µF ceramic and 10µF tantalum capacitors. Digital Supply Input. Nominally +5V. Connect directly to pin 27. Must be ≤ VANA. TABLE I. Pin Assignments. PIN CONFIGURATION VIN AGND1 REF CAP AGND2 D15 (MSB) D14 D13 D12 1 2 3 4 5 6 7 ADS7821 8 9 28 VDIG 27 VANA 26 BUSY 25 CS 24 R/C 23 BYTE 22 D0 (LSB) 21 D1 20 D2 19 D3 18 D4 17 D5 16 D6 15 D7 D11 10 D10 11 D9 12 D8 13 DGND 14 ® ADS7821 4 TYPICAL PERFORMANCE CURVES TA = –25°C to +85°C, f S = 100kHz, VDIG = V ANA = +5V, using external reference, unless otherwise specified. CONVERSION TIME vs TEMPERATURE 8.00 7.90 INTERNAL REFERENCE VOLTAGE vs TEMPERATURE 2.52 2.515 Conversion Time (µs) 7.80 7.70 7.60 7.50 7.40 7.30 7.20 –25 0 25 Temp (°C) 50 75 Internal Reference (V) 2.51 2.505 2.5 2.495 2.49 2.485 2.48 –25 0 25 Temp (°C) 50 75 Min/Max DNL Errors –0.740 at 36431 1.070 at 32767 16-Bit LSBs 16-Bit LSBs +2.0 +1.0 Min/Max INL Errors –0.900 at 12447 1.910 at 32767 +1.0 +0.5 –0.5 –1.0 –1.0 –2.0 0 8192 16384 24576 32768 40960 49152 57344 65536 0 8192 16384 24576 32768 40960 49152 57344 65536 ® 5 ADS7821 BASIC OPERATION Figure 1 shows a basic circuit to operate the ADS7821 with a full parallel data output. Taking R/C (pin 24) LOW for a minimum of 40ns (5µs max) will initiate a conversion. BUSY (pin 26) will go LOW and stay LOW until the conversion is completed and the output registers are updated. Data will be output in Straight Binary with the MSB on pin 6. BUSY going HIGH can be used to latch the data. All convert commands will be ignored while BUSY is LOW. The ADS7821 will begin tracking the input signal at the end of the conversion. Allowing 10µs between convert commands assures accurate acquisition of a new signal. CS and R/C are internally OR’d and level triggered. There is not a requirement which input goes LOW first when initiating a conversion. If, however, it is critical that CS or R/C initiates conversion ‘n’, be sure the less critical input is LOW at least 10ns prior to the initiating input. To reduce the number of control pins, CS can be tied LOW using R/C to control the read and convert modes. However, the output will become active whenever R/C goes HIGH. Refer to the Reading Data section. CS 1 ↓ 0 R/C X 0 ↓ 1 1 1 ↑ 0 BUSY X 1 1 ↑ 1 0 0 ↑ OPERATION None. Databus is in Hi-Z state. Initiates conversion “n”. Databus remains in Hi-Z state. Initiates conversion “n”. Databus enters Hi-Z state. Conversion “n” completed. Valid data from conversion “n” on the databus. Enables databus with valid data from conversion “n”. Enables databus with valid data from conversion “n-1”(1). Conversion n in progress. Enables databus with valid data from conversion “n-1”(1). Conversion “n” in progress. New conversion initiated without acquisition of a new signal. Data will be invalid. CS and/or R/C must be HIGH when BUSY goes HIGH. New convert commands ignored. Conversion “n” in progress. STARTING A CONVERSION 0 The combination of CS (pin 25) and R/C (pin 24) LOW for a minimum of 40ns immediately puts the sample/hold of the ADS7821 in the hold state and starts conversion ‘n’. BUSY (pin 26) will go LOW and stay LOW until conversion ‘n’ is completed and the internal output register has been updated. All new convert commands during BUSY LOW will be ignored. CS and/or R/C must go HIGH before BUSY goes HIGH or a new conversion will be initiated without sufficient time to acquire a new signal. The ADS7821 will begin tracking the input signal at the end of the conversion. Allowing 10µs between convert commands assures accurate acquisition of a new signal. Refer to Table II for a summary of CS, R/C, and BUSY states and Figures 3 through 5 for timing diagrams. ↓ ↓ 0 0 X X 0 NOTE: (1) See Figures 3 and 4 for constraints on data valid from conversion “n-1”. Table II. Control Line Functions for “Read” and “Convert”. 1 2 + + 2.2µF 3 4 5 D15 (MSB) D14 D13 D12 D11 D10 D9 D8 6 7 ADS7821 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 D0 (LSB) D1 D2 D3 D4 D5 D6 D7 40ns min 5µs max Convert Pulse + 0.1µF + +5V 10µF 2.2µF FIGURE 1. Basic Operation. ® ADS7821 6 READING DATA The ADS7821 outputs full or byte-reading parallel data in Straight Binary data output format. The parallel output will be active when R/C (pin 24) is HIGH and CS (pin 25) is LOW. Any other combination of CS and R/C will tri-state the parallel output. Valid conversion data can be read in a full parallel, 16-bit word or two 8-bit bytes on pins 6-13 and pins 15-22. BYTE (pin 23) can be toggled to read both bytes within one conversion cycle. Refer to Table III for ideal output codes and Figure 2 for bit locations relative to the state of BYTE. DIGITAL OUTPUT STRAIGHT BINARY DESCRIPTION Full Scale Range Least Significant Bit (LSB) Full Scale Midscale One LSB below Midscale Zero Scale ANALOG INPUT 0 to +5V 76µV 4.999924V 2.5V 2.499924V 0V 1111 1111 1111 1111 1000 0000 0000 0000 0111 1111 1111 1111 0000 0000 0000 0000 FFFF 8000 7FFF BINARY CODE HEX CODE PARALLEL OUTPUT (During a Conversion) After conversion ‘n’ has been initiated, valid data from conversion ‘n-1’ can be read and will be valid up to 5µs after the start of conversion ‘n’. Do not attempt to read data from 5µs after the start of conversion ‘n’ until BUSY (pin 26) goes HIGH; this may result in reading invalid data. Refer to Table IV and Figures 3 through 5 for timing specifications. Note! For the best possible performance, data should not be read during a conversion. The switching noise of the asynchronous data transfer can cause digital feedthrough degrading the converter’s performance. The number of control lines can be reduced by tying CS LOW while using R/C to initiate conversions and activate the output mode of the converter. See Figure 3. SYMBOL t1 t2 t3 t4 DESCRIPTION Convert Pulse Width Data Valid Delay after Start of Conversion BUSY Delay from Start of Conversion BUSY LOW BUSY Delay after End of Conversion Aperture Delay Conversion Time Acquisition Time Bus Relinquish Time BUSY Delay after Data Valid Previous Data Valid after Start of Conversion Throughput Time R/C to CS Setup Time Time Between Conversions Bus Access Time and BYTE Delay 10 10 10 83 10 50 35 200 5 9 10 220 40 7.6 8 2 83 MIN TYP MAX UNITS 40 5000 8 65 8 ns µs ns µs ns ns µs µs ns ns µs µs ns µs ns 0000 t5 t6 t7 t8 t9 t10 t11 t7 + t6 t12 t13 t14 Table III. Ideal Input Voltages and Output Codes. PARALLEL OUTPUT (After a Conversion) After conversion ‘n’ is completed and the output registers have been updated, BUSY (pin 26) will go HIGH. Valid data from conversion ‘n’ will be available on D15-D0 (pin 6-13 and 15-22). BUSY going HIGH can be used to latch the data. Refer to Table IV and Figures 3 through 5 for timing specifications. TABLE IV. Conversion Timing. BYTE LOW Bit 15 (MSB) Bit 14 Bit 13 Bit 12 6 7 ADS7821 8 9 21 Bit 1 20 Bit 2 19 Bit 3 18 Bit 4 17 Bit 5 16 Bit 6 15 Bit 7 Bit 5 Bit 4 8 9 23 22 Bit 0 (LSB) Bit 7 Bit 6 6 7 BYTE HIGH +5V 23 22 Bit 8 ADS7821 21 Bit 9 20 Bit 10 19 Bit 11 18 Bit 12 17 Bit 13 16 Bit 14 15 Bit 15 (MSB) Bit 11 10 Bit 10 11 Bit 9 12 Bit 8 13 14 Bit 3 10 Bit 2 11 Bit 1 12 Bit 0 (LSB) 13 14 FIGURE 2. Bit Locations Relative to State of BYTE (pin 23). ® 7 ADS7821 t1 R/C t13 t2 BUSY t3 t6 MODE Acquire Convert t7 Acquire t8 t5 Convert t4 DATA BUS Previous Data Valid t9 Hi-Z Previous Data Valid t11 Not Valid Data Valid t10 Hi-Z Data Valid FIGURE 3. Conversion Timing with Outputs Enabled after Conversion (CS Tied LOW.) t12 R/C t1 CS t12 t12 t12 t3 BUSY t4 t6 MODE Acquire Convert t7 Acquire DATA BUS Hi-Z State Data Valid t14 t9 Hi-Z State FIGURE 4. Using CS to Control Conversion and Read Timing. t12 R/C t12 CS BYTE Pins 6 - 13 Hi-Z High Byte t14 Low Byte t14 High Byte t9 Hi-Z Pins 15 - 22 Hi-Z Low Byte Hi-Z FIGURE 5. Using CS and BYTE to Control Data Bus. ® ADS7821 8 INPUT RANGE The ADS7821 offers a standard 0V to 5V input range. Figure 6 shows the required circuit connections for the ADS7821 with and without the gain adjustment hardware. Adjustments for offset and gain are described in the calibration section of this data sheet. CALIBRATION The ADS7821 can be trimmed in hardware or software. There is no external offset adjustment. If offset adjustment is required, an op amp featuring an offset trim pin should be used to drive the ADS7821. The offset should be trimmed before the gain since the offset directly affects the gain. To achieve optimum performance, several iterations may be required. GAIN ADJUSTMENT To calibrate the gain of the ADS7821, a 576kΩ resistor can be tied between the REF pin and a 50kΩ potentiometer as shown in Figure 6a. The calibration range is ±15mV for the gain. REF REF (pin 3) is an input for an external reference or the output for the internal 2.5V reference. A 2.2µF capacitor should be connected as close to the REF pin as possible. The capacitor and the output resistance of REF create a low pass filter to bandlimit noise on the reference. Using a smaller value capacitor will introduce more noise to the reference degrading the SNR and SINAD. The REF pin should not be used to directly drive external loads. The range for the external reference is 2.3V to 2.7V and determines the actual LSB size. Increasing the reference voltage will increase the full scale range and the LSB size of the converter which can improve the SNR. CAP CAP (pin 4) is the output of the internal reference buffer. A 2.2µF capacitor should be placed as close to the CAP pin as possible to provide optimum switching currents for the CDAC throughout the conversion cycle and compensation for the output of the internal buffer. Using a capacitor any smaller than 1µF can cause the output buffer to oscillate and may not have sufficient charge for the CDAC. Capacitor values larger than 2.2µF will have little affect on improving performance. The output of the buffer is capable of driving up to 2mA of current to a static load. Static loads requiring more than 2mA of current from the CAP pin will begin to degrade the linearity of the ADS7821. Use of an external buffer is recommended for loads requiring more than 2mA. Do not attempt to directly drive any dynamic load with the output voltage on CAP. This will cause performance degradation of the converter. REFERENCE The ADS7821 can operate with its internal 2.5V reference or an external reference. By applying an external reference to pin 3, the internal reference can be bypassed. The reference voltage at REF is buffered internally with the output on CAP (pin 4). a) With Hardware Gain Trim b) Without Hardware Gain Trim 0 to +5V 1 VIN 0 to +5V 1 VIN 2 +5V 2.2µF + AGND1 2.2µF + 2 AGND1 3 REF 3 REF 576kΩ 50kΩ 4 Gain 2.2µF + 5 2.2µF CAP + 4 CAP AGND2 5 AGND2 NOTE: Use 1% metal film resistors. FIGURE 6. Circuit Diagram With and Without External Gain Trim. ® 9 ADS7821 LAYOUT POWER For optimum performance, tie the analog and digital power pins to the same +5V power supply and tie the analog and digital grounds together. As noted in the electrical specifications, the ADS7821 uses 98% of its power for the analog circuitry. The ADS7821 should be considered as an analog component. The +5V power for the A/D should be separate from the +5V used for the system’s digital logic. Connecting VDIG (pin 28) directly to a digital supply can reduce converter performance due to switching noise from the digital logic. For best performance, the +5V supply can be produced from whatever analog supply is used for the rest of the analog signal conditioning. If +12V or +15V supplies are present, a simple +5V regulator can be used. Although it is not suggested, if the digital supply must be used to power the converter, be sure to properly filter the supply. Either using a filtered digital supply or a regulated analog supply, both VDIG and VANA should be tied to the same +5V source. GROUNDING Three ground pins are present on the ADS7821. DGND is the digital supply ground. AGND2 is the analog supply ground. AGND1 is the ground which all analog signals internal to the A/D are referenced. AGND1 is more susceptible to current induced voltage drops and must have the path of least resistance back to the power supply. All the ground pins of the A/D should be tied to the analog ground plane, separated from the system’s digital logic ground, to achieve optimum performance. Both analog and digital ground planes should be tied to the “system” ground as near to the power supplies as possible. This helps to prevent dynamic digital ground currents from modulating the analog ground through a common impedance to power ground. SIGNAL CONDITIONING The FET switches used for the sample hold on many CMOS A/D converters release a significant amount of charge injection which can cause the driving op amp to oscillate. The FET switch on the ADS7821, compared to the FET switches on other CMOS A/D converters, releases 5%-10% of the charge. There is also a resistive front end which attenuates any charge which is released. Any op amp sufficient for the signal in an application should be sufficient to drive the ADS7821. INTERMEDIATE LATCHES The ADS7821 does have tri-state outputs for the parallel port, but intermediate latches should be used if the bus will be active during conversions. If the bus is not active during conversion, the tri-state outputs can be used to isolate the A/D from other peripherals on the same bus. Tri-state outputs can also be used when the A/D is the only peripheral on the data bus. Intermediate latches are beneficial on any monolithic A/D converter. The ADS7821 has an internal LSB size of 38µV. Transients from fast switching signals on the parallel port, even when the A/D is tri-stated, can be coupled through the substrate to the analog circuitry causing degradation of converter performance. ® ADS7821 10