ADS7824

® ADS 782 4 ADS7824 782 4 ADS www.burr-brown.com/databook/ADS7824.html 4 Channel, 12-Bit Sampling CMOS A/D Converter FEATURES q 25µs max SAMPLING AND CONVERSION q SINGLE +5V SUPPLY OPERATION q PIN-COMPATIBLE WITH 16-BIT ADS7825 q PARALLEL AND SERIAL DATA OUTPUT q 28-PIN 0.3" PLASTIC DIP AND SOIC q ±0.5 LSB max INL AND DNL q 50mW max POWER DISSIPATION q 50µW POWER DOWN MODE q ±10V INPUT RANGE, FOUR CHANNEL MULTIPLEXER q CONTINUOUS CONVERSION MODE DESCRIPTION The ADS7824 can acquire and convert 12 bits to within ±0.5 LSB in 25µs max while consuming only 50mW max. Laser-trimmed scaling resistors provide the standard industrial ±10V input range and channelto-channel matching of ±0.1%. The ADS7824 is a low-power 12-bit sampling A/D with a four channel input multiplexer, S/H, clock, reference, and a parallel/serial microprocessor interface. It can be configured in a continuous conversion mode to sequentially digitize all four channels. The 28-pin ADS7824 is available in a plastic 0.3" DIP and in a SOIC, both fully specified for operation over the industrial –40°C to +85°C range. Continuous Conversion 40kΩ AIN0 Clock 20kΩ 40kΩ AIN1 20kΩ 40kΩ AIN2 20kΩ 40kΩ AIN3 20kΩ 8kΩ CAP 6kΩ REF 8kΩ 8kΩ 8kΩ CDAC CONTC Channel A0 A1 R/C CS PWRD Successive Approximation Register and Control Logic BUSY Serial Comparator Data Out or Parallel Data Out Buffer Internal +2.5V Ref 8 D7-D0 BYTE SDATA DATACLK International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1996 Burr-Brown Corporation PDS-1303B 1 Printed in U.S.A. ADS7824October, 1997 SPECIFICATIONS ELECTRICAL At TA = –40°C to +85°C, f S = 40kHz, VS1 = VS2 = VS = +5V ±5%, using external reference, CONTC = 0V, unless otherwise specified. ADS7824P, U PARAMETER RESOLUTION ANALOG INPUT Voltage Range Impedance Capacitance THROUGHPUT SPEED Conversion Time Acquisition Time Multiplexer Settling Time Complete Cycle (Acquire and Convert) Complete Cycle (Acquire and Convert) Throughput Rate DC ACCURACY Integral Linearity Error Differential Linearity Error No Missing Codes Transition Noise(3) Full Scale Error(4) Full Scale Error Drift Full Scale Error(4) Full Scale Error Drift Bipolar Zero Error Bipolar Zero Error Drift Channel-to-Channel Mismatch Power Supply Sensitivity AC ACCURACY Spurious-Free Dynamic Range(5) Total Harmonic Distortion Signal-to-(Noise+Distortion) Signal-to-Noise Channel Separation(6) –3dB Bandwidth Useable Bandwidth(7) SAMPLING DYNAMICS Aperture Delay Transient Response(8) Overvoltage Recovery(9) REFERENCE Internal Reference Voltage Internal Reference Source Current (Must use external buffer) External Reference Voltage Range for Specified Linearity External Reference Current Drain DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Data Coding VOL VOH Leakage Current Output Capacitance ±10V 45.7 35 CONDITIONS MIN TYP MAX 12 T T T T T T 25 40 40 ±0.15 ±0.15 Guaranteed 0.1 Internal Reference Internal Reference ±7 ±2 ±2 +4.75 < VS < +5.25 fIN = fIN = fIN = fIN = fIN = 1kHz 1kHz 1kHz 1kHz 1kHz 80 70 70 90 90 –90 73 73 100 2 90 ±1 ±1 T T T T T ±5 T ±10 T ±0.1 ±0.5 T –80 72 72 T T T T T T T T T T T T T T T T ±0.1 T T ±0.5 ±0.5 T T MIN ADS7824PB, UB TYP MAX T(1) UNITS Bits Channel On or Off V kΩ pF µs µs µs µs µs kHz LSB (2) LSB LSB % ppm/°C % ppm/°C mV ppm/°C % LSB Includes Acquisition CONTC = +5V 20 5 5 ±0.5 ±0.5 ±0.25 ±0.25 T dB dB dB dB dB MHz kHz FS Step 40 5 1 ns µs µs V µA V µA 2.48 2.5 1 2.5 2.52 2.3 VREF = +2.5V 2.7 100 T T T –0.3 +2.4 +0.8 VS +0.3V ±10 ±10 T T T T T T T T T V V µA µA ISINK = 1.6mA ISOURCE = 500µA High-Z State, VOUT = 0V to VS High-Z State Parallel in two bytes; Serial Binary Two's Complement +0.4 +4 ±5 15 T T T V V µA pF The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® ADS7824 2 SPECIFICATIONS (CONT) ELECTRICAL At TA = –40°C to +85°C, fS = 40kHz, VS1 = VS2 = V S = +5V ±5%, using external reference, CONTC = 0V, unless otherwise specified. ADS7824P, U PARAMETER DIGITAL TIMING Bus Access Time Bus Relinquish Time Data Clock Internal Clock (Output only when transmitting data) External Clock POWER SUPPLIES VS1 = VS2 = VS Power Dissipation TEMPERATURE RANGE Specified Performance Storage Thermal Resistance (θJA) Plastic DIP SOIC CONDITIONS PAR/SER = +5V PAR/SER = +5V PAR/SER = 0V EXT/INT LOW EXT/INT HIGH MIN TYP MAX 83 83 0.5 0.1 +4.75 fS = 40kHz PWRD HIGH –40 –65 75 75 +5 50 +85 +150 T T T T 1.5 10 +5.25 50 T T T T T T T MIN ADS7824PB, UB TYP MAX T T T T T T UNITS ns ns MHz MHz V mW µW °C °C °C/W °C/W NOTES: (1) An asterik (T) specifies same value as grade to the left. (2) LSB means Least Significant Bit. For the 12-bit, ±10V input ADS7824, one LSB is 4.88mV. (3) Typical rms noise at worst case transitions and temperatures. (4) Full scale error is the worst case of –Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. (5) All specifications in dB are referred to a full-scale ±10V input. (6) A full scale sinewave input on one channel will be attenuated by this amount on the other channels. (7) Useable Bandwidth defined as Full-Scale input frequency at which Signal-to-(Noise+Distortion) degrades to 60dB, or 10 bits of accuracy. (8) The ADS7824 will accurately acquire any input step if given a full acquisition period after the step. (9) Recovers to specified performance after 2 x FS input overvoltage, and normal acquisitions can begin. PACKAGE/ORDERING INFORMATION PACKAGE DRAWING NUMBER(1) 246 246 217 217 TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C MAXIMUM INTEGRAL LINEARITY ERROR (LSB) ±1 ±0.5 ±1 ±0.5 MINIMUM SIGNALTO-(NOISE + DISTORTION) RATIO (dB) 70 72 70 72 PRODUCT ADS7824P ADS7824PB ADS7824U ADS7824UB PACKAGE Plastic Dip Plastic Dip SOIC SOIC NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ABSOLUTE MAXIMUM RATINGS Analog Inputs: AIN0, AIN1, AIN2, AIN3 .............................................. ±15V REF ................................... (AGND2 –0.3V) to (VS + 0.3V) CAP ........................................ Indefinite Short to AGND2, Momentary Short to VS VS1 and VS2 to AGND2 ........................................................................... 7V VS1 to VS2 .......................................................................................... ±0.3V Difference between AGND1, AGND2 and DGND ............................. ±0.3V Digital Inputs and Outputs .......................................... –0.3V to (VS + 0.3V) Maximum Junction Temperature ..................................................... 150°C Internal Power Dissipation ............................................................. 825mW Lead Temperature (soldering, 10s) ................................................ +300°C Maximum Input Current to Any Pin ................................................. 100mA PIN CONFIGURATION Top View DIP/SOIC AGND1 AIN0 AIN1 AIN2 AIN3 CAP REF AGND2 TRI-STATE TRI-STATE TRI-STATE EXT/INT SYNC D7 1 2 3 4 5 6 7 8 9 ADS7824 28 VS1 27 VS2 26 PWRD 25 CONTC 24 BUSY 23 CS 22 R/C 21 BYTE 20 PAR/SER 19 A0 18 A1 17 D0 16 D1 15 D2 TAG SDATA DATACLK ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 3 D6 10 D5 11 D4 12 D3 13 DGND 14 ® ADS7824 PIN ASSIGNMENTS PIN # 1 2 3 4 5 6 7 8 9 10 11 12 NAME AGND1 AIN0 AIN 1 AIN 2 AIN 3 CAP REF AGND2 D7 D6 D5 D4 O O O I/O I/O DESCRIPTION Analog Ground. Used internally as ground reference point. Analog Input Channel 0. Full-scale input range is ±10V. Analog Input Channel 1. Full-scale input range is ±10V. Analog Input Channel 2. Full-scale input range is ±10V. Analog Input Channel 3. Full-scale input range is ±10V. Internal Reference Output Buffer. 2.2µF Tantalum to ground. Reference Input/Output. Outputs +2.5V nominal. If used externally, must be buffered to maintain ADS7825 accuracy. Can also be driven by external system reference. In both cases, bypass to ground with a 2.2µF Tantalum capacitor. Analog Ground. Parallel Data Bit 7 if PAR/SER HIGH; Tri-state if PAR/SER LOW. See Table I. Parallel Data Bit 6 if PAR/SER HIGH; Tri-state if PAR/SER LOW. See Table I. Parallel Data Bit 5 if PAR/SER HIGH; Tri-state if PAR/SER LOW. See Table I. Parallel Data Bit 4 if PAR/SER HIGH; if PAR/SER LOW, a LOW level input here will transmit serial data on SDATA from the previous conversion using the internal serial clock; a HIGH input here will transmit serial data using an external serial clock input on DATACLK (D2). See Table I. Parallel Data Bit 3 if PAR/SER HIGH; SYNC output if PAR/SER LOW. See Table I. Digital Ground. I/O O I/O I/O I/O I I Parallel Data Bit 2 if PAR/SER HIGH; if PAR/SER LOW, this will output the internal serial clock if EXT/INT (D4) is LOW; will be an input for an external serial clock if EXT/INT (D4) is HIGH. See Table I. Parallel Data Bit 1 if PAR/SER HIGH; SDATA serial data output if PAR/SER LOW. See Table I. Parallel Data Bit 0 if PAR/SER HIGH; TAG data input if PAR/SER LOW. See Table I. Channel Address. Input if CONTC LOW, output if CONTC HIGH. See Table I. Channel Address. Input if CONTC LOW, output if CONTC HIGH. See Table I. Select Parallel or Serial Output. If HIGH, parallel data will be output on D0 thru D7. If LOW, serial data will be output on SDATA. See Table I and Figure 1. Byte Select. Only used with parallel data, when PAR/SER HIGH. Determines which byte is available on D0 thru D7. Changing BYTE with CS LOW and R/C HIGH will cause the data bus to change accordingly. LOW selects the 8 MSBs; HIGH selects the 4 LSBs, see Figures 2 and 3. Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and starts a conversion. With CS LOW, a rising edge on R/C enables the output data bits if PAR/SER HIGH, or starts transmission of serial data if PAR/SER LOW and EXT/INT HIGH. Chip Select. Internally OR'd with R/C. With CONTC LOW and R/C LOW, a falling edge on CS will initiate a conversion. With R/C HIGH, a falling edge on CS will enable the output data bits if PAR/SER HIGH, or starts transmission of serial data if PAR/SER LOW and EXT/INT HIGH. Busy Output. Falls when conversion is started; remains LOW until the conversion is completed and the data is latched into the output register. In parallel output mode, output data will be valid when BUSY rises, so that the rising edge can be used to latch the data. Continuous Conversion Input. If LOW, conversions will occur normally when initiated using CS and R/C; if HIGH, acquisition and conversions will take place continually, cycling through all four input channels, as long as CS, R/C and PWRD are LOW. See Table I. For serial mode only. Power Down Input. If HIGH, conversions are inhibited and power consumption is significantly reduced. Results from the previous conversion are maintained in the output register. In the continuous conversion mode, the multiplexer address channel is reset to channel 0 Supply Input. Nominally +5V. Connect directly to pin 28. Decouple to ground with 0.1µF ceramic and 10µF Tantalum capacitors. Supply Input. Nominally +5V. Connect directly to pin 27. 13 14 15 16 17 18 19 20 21 D3 DGND D2 D1 D0 A1 A0 PAR/SER BYTE O 22 R/C I 23 CS I 24 BUSY O 25 CONTC I 26 PWRD I 27 28 VS2 VS1 ® ADS7824 4 TYPICAL PERFORMANCE CURVES At TA = +25°C, fS = 40kHz, VS1 = VS2 = +5V, using internal reference, unless otherwise noted. FREQUENCY SPECTRUM (8192 Point FFT; fIN = 1.02kHz, –0.5dB) 0 –10.0 –20.0 –30.0 –40.0 –50.0 –60.0 –70.0 –80.0 –90.0 –100.0 –110.0 0 5 10 Frequency (kHz) 15 20 0 –10.0 –20.0 –30.0 –40.0 –50.0 –60.0 –70.0 –80.0 –90.0 –100.0 –110.0 0 ADJACENT CHANNEL CROSSTALK, WORST PAIR (8192 Point FFT; AIN3 = 1.02kHz, –0.1dB; AIN2 = AGND) Amplitude (dB) Amplitude (dB) 5 10 Frequency (kHz) 15 20 ADJACENT CHANNEL CROSSTALK, WORST PAIR (8192 Point FFT; AIN3 = 10.1kHz, –0.1dB; AIN2 = AGND) 0 –20.0 12-Bit LSBs –10.0 –30.0 –40.0 –50.0 –60.0 –70.0 –90.0 –100.0 –110.0 0 5 10 Frequency (kHz) 15 20 –80.0 Amplitude (dB) 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 0 All Codes INL 512 1024 1536 2048 2560 3072 3584 4095 Decimal Code 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 0 12-Bit LSBs All Codes DNL 512 1024 1536 2048 2560 3072 3584 4095 Decimal Code ENDPOINT ERRORS 2 mV From Ideal POWER SUPPLY RIPPLE SENSITIVITY INL/DNL DEGRADATION PER LSB OF P-P RIPPLE 1 BPZ Error 1 0 –1 –2 0.2 Linearity Degradation (LSB/LSB) 10–1 INL 10–3 Percent From Ideal 10–2 +FS Error 0 –0.2 10–4 Percent From Ideal 0.2 DNL 10–5 101 102 103 104 105 106 107 Power Supply Ripple Frequency (Hz) –FS Error 0 –0.2 –50 –25 0 25 Temperature (°C) 50 75 100 ® 5 ADS7824 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25 °C, fS = 40kHz, VS1 = VS2 = +5V, using internal reference, unless otherwise noted. INTERNAL REFERENCE VOLTAGE vs TEMPERATURE 2.520 2.515 CONVERSION TIME vs TEMPERATURE 15.7 15.6 Conversion Time (µs) Internal Reference (V) 2.510 2.505 2.500 2.495 2.490 2.485 2.480 –50 –25 0 25 50 75 100 15.5 15.4 15.3 15.2 15.1 15.0 14.9 14.8 –50 –25 0 25 50 75 100 Temperature (°C) Temperature (°C) ® ADS7824 6 BASIC OPERATION PARALLEL OUTPUT Figure 1a shows a basic circuit to operate the ADS7824 with parallel output (Channel 0 selected). Taking R/C (pin 22) LOW for 40ns (12µs max) will initiate a conversion. BUSY (pin 24) will go LOW and stay LOW until the conversion is completed and the output register is updated. If BYTE (pin 21) is LOW, the 8 most significant bits will be valid when pin 24 rises; if BYTE is HIGH, the 4 least significant bits will be valid when BUSY rises. Data will be output in Binary Two’s Complement format. BUSY going HIGH can be used to latch the data. After the first byte has been read, BYTE can be toggled allowing the remaining byte to be read. All convert commands will be ignored while BUSY is LOW. The ADS7824 will begin tracking the input signal at the end of the conversion. Allowing 25µs between convert commands assures accurate acquisition of a new signal. Parallel Output 1 ±10V 2 3 4 5 + 2.2µF SERIAL OUTPUT Figure 1b shows a basic circuit to operate the ADS7824 with serial output (Channel 0 selected). Taking R/C (pin 22) LOW for 40ns (12µs max) will initiate a conversion and output valid data from the previous conversion on SDATA (pin 16) synchronized to 12 clock pulses output on DATACLK (pin 15). BUSY (pin 24) will go LOW and stay LOW until the conversion is completed and the serial data has been transmitted. Data will be output in Binary Two’s Complement format, MSB first, and will be valid on both the rising and falling edges of the data clock. BUSY going HIGH can be used to latch the data. All convert commands will be ignored while BUSY is LOW. The ADS7824 will begin tracking the input signal at the end of the conversion. Allowing 25µs between convert commands assures accurate acquisition of a new signal. 28 27 26 25 BUSY 24 23 R/C 22 ADS7824 BYTE 21 20 19 18 17 16 15 +5V(1) 40ns min Convert Pulse 0.1µF 10µF + + +5V 6 + 2.2µF 7 8 9 10 11 12 13 14 Serial Output Pin 21 LOW Pin 21 HIGH D11 D10 D9 D8 D7 D6 D5 D4 1 D3 D2 D1 D0 LOW NOTE: (1) PAR/SER = 5V LOW LOW LOW 28 27 26 25 24 23 22 ADS7824 21 20 19 18 17 16 15 SDATA DATACLK(1) (3) ±10V 2 3 4 5 + 6 + 2.2µF 0.1µF 10µF + + +5V BUSY Convert Pulse R/C 40ns min 2.2µF 7 8 NC(2) 9 NC(2) 10 NC(2) 11 EXT/INT SYNC 12 13 14 NOTES: (1) DATACLK (pin 15) is an output when EXT/INT (pin 12) is LOW and an input when EXT/INT is HIGH. (2) NC = no connection. (3) PAR/SER = 0V. FIGURE 1. Basic Connection Diagram, (a) Parallel Output, (b) Serial Output. ® 7 ADS7824 STARTING A CONVERSION The combination of CS (pin 23) and R/C (pin 22) LOW for a minimum of 40ns places the sample/hold of the ADS7824 in the hold state and starts conversion ‘n’. BUSY (pin 24) will go LOW and stay LOW until conversion ‘n’ is completed and the internal output register has been updated. All new convert commands during BUSY LOW will be ignored. CS and/or R/C must go HIGH before BUSY goes HIGH or a new conversion will be initiated without sufficient time to acquire a new signal. The ADS7824 will begin tracking the input signal at the end of the conversion. Allowing 25µs between convert commands assures accurate acquisition of a new signal. Refer to Tables Ia and Ib for a summary of CS, R/C, and BUSY states and Figures 2 through 6 and Table II for timing information. CS and R/C are internally OR’d and level triggered. There is not a requirement which input goes LOW first when INPUTS CS 1 X 0 0 0 R/C X 0 1 1 1 BYTE X X 0 1 X CONTC X X X X X PWRD X X X X X BUSY X X X X ↑ D7 Hi-Z Hi-Z D11 (MSB) D3 ↑↓ D6 Hi-Z Hi-Z D10 D2 ↑↓ D5 Hi-Z Hi-Z D9 D1 ↑↓ OUTPUTS D4 Hi-Z Hi-Z D8 D0 (LSB) ↑↓ D3 Hi-Z Hi-Z D7 LOW ↑↓ D2 Hi-Z Hi-Z D6 LOW ↑↓ D1 Hi-Z Hi-Z D5 LOW ↑↓ D0 Hi-Z Hi-Z D4 LOW ↑↓ COMMENTS initiating a conversion. If, however, it is critical that CS or R/C initiates conversion ‘n’, be sure the less critical input is LOW at least 10ns prior to the initiating input. If EXT/INT (pin 12) is LOW when initiating conversion ‘n’, serial data from conversion ‘n – 1’ will be output on SDATA (pin 16) following the start of conversion ‘n’. See Internal Data Clock in the Reading Data section. To reduce the number of control pins, CS can be tied LOW using R/C to control the read and convert modes. This will have no effect when using the internal data clock in the serial output mode. However, the parallel output and the serial output (only when using an external data clock) will be affected whenever R/C goes HIGH. Refer to the Reading Data section and Figures 2, 3, 5, and 6. Results from last completed conversion. Results from last completed conversion. Data will change at the end of a conversion. TABLE Ia. Read Control for Parallel Data (PAR/SER = 5V.) CS Input 1 X 0 R/C Input X 0 ↓ CONTC PWRD Input X X 0 Input X X X BUSY Output 1 1 1 D7, D6, D5 D4 LOW EXT/INT Output Hi-Z Hi-Z Hi-Z Input LOW LOW LOW D3 SYNC Output LOW LOW LOW D2 DATACLK I/O Output Output Output D1 SDATA Output Hi-Z Hi-Z Output D0 TAG Input X X X COMMENTS ↓ 0 0 X 1 Hi-Z LOW LOW Output Output X 0 1 0 X X Hi-Z HIGH LOW Input Output Input 0 1 0 X ↑ Hi-Z HIGH LOW Input Output Input 0 ↑ 0 X 1 Hi-Z HIGH LOW Input Output X ↓ 1 0 X 1 Hi-Z HIGH LOW Input Output X 0 0 1 0 ↓ Hi-Z LOW LOW Output Output X ↓ 0 ↓ 0 1 ↑ 0 ↓ X X 1 1 X X X X X X X X Hi-Z Hi-Z Hi-Z Hi-Z HIGH HIGH LOW LOW Output Output LOW LOW Input Input Output Output Output Output Output Output X X X X Starts transmission of data from previous conversion on SDATA synchronized to 12 pulses output on DATACLK. Starts transmission of data from previous conversion on SDATA synchronized to 12 pulses output on DATACLK. The level output on SDATA will be the level input on TAG 12 DATACLK input cycles earlier. At the end of the conversion, when BUSY rises, data from the conversion will be shifted into the output registers. If DATACLK is HIGH, valid data will be lost. Initiates transmission of a HIGH pulse on SYNC followed by data from last completed conversion on SDATA synchronized to the input on DATACLK. Initiates transmission of a HIGH pulse on SYNC followed by data from last completed conversion on SDATA synchronized to the input on DATACLK. Starts transmission of data from previous conversion on SDATA synchronized to 12 pulses output on DATACLK SDATA becomes active. Inputs on DATACLK shift out data. SDATA becomes active. Inputs on DATACLK shift out data. Restarts continuous conversion mode (n – 1 data transmitted when BUSY is LOW). Restarts continuous conversion mode (n – 1 data transmitted when BUSY is LOW). TABLE Ib. Read Control for Serial Data (PAR/SER = 0V.) ® ADS7824 8 t1 R/C t3 BUSY t6 t7 MODE Acquire t12 Convert t11 t10 Parallel Data Bus Previous High Byte Valid t9 BYTE Hi-Z Previous High Byte Valid t12 Previous Low Byte Valid t2 t12 t12 Not Valid High Byte Valid Low Byte Valid t8 Acquire t4 t5 t6 t3 t1 Convert t12 Hi-Z t9 High Byte Valid t12 FIGURE 2. Conversion Timing with Parallel Output (CS LOW). t21 R/C t1 CS t3 BUSY t21 t21 t21 t21 t21 t4 t21 BYTE t21 t21 t21 DATA BUS Hi-Z State High Byte t12 Hi-Z State t9 Low Byte t12 t9 Hi-Z State FIGURE 3. Using CS to Control Conversion and Read Timing with Parallel Outputs. CS or R/C(1) t14 t13 1 2 t16 t15 SDATA Hi-Z t25 BUSY MSB Valid Bit 10 Valid Bit 9 Valid 3 t7 + t8 DATACLK 11 12 1 2 Bit 1 Valid LSB Valid Hi-Z MSB Valid Bit 10 Valid (Results from previous conversion.) t26 NOTE: (1) If controlling with CS, tie R/C LOW. If controlling with R/C, tie CS LOW. FIGURE 4. Serial Data Timing Using Internal Data Clock (TAG LOW). ® 9 ADS7824 ® ADS7824 t17 t18 0 1 2 3 4 13 14 t19 t20 t22 t21 t23 t17 t24 EXTERNAL DATACLK t1 CS t21 R/C t3 10 Bit 11 (MSB) t27 Bit 10 BUSY SYNC SDATA Bit 1 Bit 0 (LSB) Tag 0 t28 TAG Tag 0 Tag 1 Tag 2 Tag 11 Tag 12 Tag 13 FIGURE 5. Conversion and Read Timing with External Clock (EXT/INT HIGH). Read After Conversion. t17 t18 t19 EXTERNAL DATACLK t22 CS t21 t20 R/C t1 t11 BUSY t3 t23 11 t17 Bit 11 (MSB) t27 t24 SYNC SDATA Bit 0 (LSB) Tag 0 t28 TAG Tag 0 Tag 1 Tag 12 Tag 13 ADS7824 FIGURE 6. Conversion and Read Timing with External Clock (EXT/INT HIGH). Read During Conversion (Previous Conversion Results). ® READING DATA PARALLEL OUTPUT To use the parallel output, tie PAR/SER (pin 20) HIGH. The parallel output will be active when R/C (pin 22) is HIGH and CS (pin 23) is LOW. Any other combination of CS and R/C will tri-state the parallel output. Valid conversion data can be read in two 8-bit bytes on D7-D0 (pins 9-13 and 15-17). When BYTE (pin 21) is LOW, the 8 most significant bits will be valid with the MSB on D7. When BYTE is HIGH, the 4 least significant bits will be valid with the LSB on D4. BYTE can be toggled to read both bytes within one conversion cycle. Upon initial power up, the parallel output will contain indeterminate data. PARALLEL OUTPUT (After a Conversion) After conversion ‘n’ is completed and the output registers have been updated, BUSY (pin 24) will go HIGH. Valid data from conversion ‘n’ will be available on D7-D0 (pins 9-13 and 15-17). BUSY going HIGH can be used to latch the data. Refer to Table II and Figures 2 and 3 for timing constraints. PARALLEL OUTPUT (During a Conversion) After conversion ‘n’ has been initiated, valid data from conversion ‘n – 1’ can be read and will be valid up to 12µs SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t7 + t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 DESCRIPTION Convert Pulse Width Start of Conversion to New Data Valid Start of Conversion to BUSY LOW BUSY LOW End of Conversion to BUSY HIGH Aperture Delay Conversion Time Acquisition Time Throughput Time Bus Relinquish Time Data Valid to BUSY HIGH Start of Conversion to Previous Data Not Valid Bus Access Time and BYTE Delay Start of Conversion to DATACLK Delay DATACLK Period Data Valid to DATACLK HIGH DATACLK LOW to Data Not Valid External DATACLK Period External DATACLK HIGH External DATACLK LOW after the start of conversion ‘n’. Do not attempt to read data beyond 12µs after the start of conversion ‘n’ until BUSY (pin 24) goes HIGH; this may result in reading invalid data. Refer to Table II and Figures 2 and 3 for timing constraints. SERIAL OUTPUT When PAR/SER (pin 20) is LOW, data can be clocked out serially with the internal data clock or an external data clock. When EXT/INT (pin 12) is LOW, DATACLK (pin 15) is an output and is always active regardless of the state of CS (pin 23) and R/C (pin 22). The SDATA output is active when BUSY (pin 24) is LOW. Otherwise, it is in a tri-state condition. When EXT/INT is HIGH, DATACLK is an input. The SDATA output is active when CS is LOW and R/C is HIGH. Otherwise, it is in a tri-state condition. Regardless of the state of EXT/INT, SYNC (pin 13) is an output and always active, while TAG (pin 17) is always an input. INTERNAL DATA CLOCK (During A Conversion) To use the internal data clock, tie EXT/INT (pin 12) LOW. The combination of R/C (pin 22) and CS (pin 23) LOW will initiate conversion ‘n’ and activate the internal data clock (typically 900kHz clock rate). The ADS7824 will output 12 bits of valid data, MSB first, from conversion ‘n – 1’ on SDATA (pin 16), synchronized to 12 clock pulses output on DATACLK (pin 15). The data will be valid on both the MIN 0.04 15 15 90 40 15 3 10 20 12 60 15 83 1.4 1.1 20 400 100 50 40 25 10 25 15 25 35 55 83 83 83 83 20 500 75 600 21 5 25 83 TYP MAX 12 21 85 21 UNITS µs µs ns µs ns ns µs µs µs ns ns µs ns µs µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CS LOW and R/C HIGH to External DATACLK HIGH (Enable Clock) R/C to CS Setup Time CS HIGH or R/C LOW to External DATACLK HIGH (Disable Clock) DATACLK HIGH to SYNC HIGH DATACLK HIGH to Valid Data Start of Conversion to SDATA Active End of Conversion to SDATA Tri-State CS LOW and R/C HIGH to SDATA Active CS HIGH or R/C LOW to SDATA Tri-State BUSY HIGH to Address Valid Address Valid to BUSY LOW TABLE II. Conversion, Data, and Address Timing. TA = –40°C to +85°C. ® ADS7824 12 rising and falling edges of the internal data clock. The rising edge of BUSY (pin 24) can be used to latch the data. After the 12th clock pulse, DATACLK will remain LOW until the next conversion is initiated, while SDATA will go to whatever logic level was input on TAG (pin 17) during the first clock pulse. The SDATA output will tri-state when BUSY returns HIGH. Refer to Table II and Figure 4 for timing information. EXTERNAL DATA CLOCK To use an external clock, tie EXT/INT (pin 12) HIGH. The external clock is not a conversion clock; it can only be used as a data clock. To enable the output mode of the ADS7824, CS (pin 23) must be LOW and R/C (pin 22) must be HIGH. DATACLK must be HIGH for 20% to 70% of the total data clock period; the clock rate can be between DC and 10MHz. Serial data from conversion ‘n’ can be output on SDATA (pin 16) after conversion ‘n’ is completed or during conversion ‘n + 1’. An obvious way to simplify control of the converter is to tie CS LOW while using R/C to initiate conversions. While this is perfectly acceptable, there is a possible problem when using an external data clock. At an indeterminate point from 12µs after the start of conversion ‘n’ until BUSY rises, the internal logic will shift the results of conversion ‘n’ into the output register. If CS is LOW, R/C is HIGH and the external clock is HIGH at this point, data will be lost. So, with CS LOW, either R/C and/or DATACLK must be LOW during this period to avoid losing valid data. EXTERNAL DATA CLOCK (After a Conversion) After conversion ‘n’ is completed and the output registers have been updated, BUSY (pin 24) will go HIGH. With CS LOW (pin 23) and R/C HIGH (pin 22), valid data from conversion ‘n’ will be output on SDATA (pin 16) synchronized to the external data clock input on DATACLK (pin 15). Between 15 and 35ns following the rising edge of the first external data clock, the SYNC output pin will go HIGH for one full data clock period (100ns minimum). The MSB will be valid between 25 and 55ns after the rising edge of the second data clock. The LSB will be valid on the 13th falling edge and the 14th rising edge of the data clock. TAG (pin 17) will input a bit of data for every external clock pulse. The first bit input on TAG will be valid on SDATA on the CONTC 0 0 0 0 0 1 1 1 1 1 CS X X 0 ↓ X X X 0 ↓ X R/C X X ↓ 0 X X X ↓ 0 X BUSY X 0 1 1 X X 0 1 1 X PWRD X 0 0 0 1 X 0 0 0 1 14th falling edge and the 15th rising edge of DATACLK; the second input bit will be valid on the 15th falling edge and the 16th rising edge, etc. With a continuous data clock, TAG data will be output on DATA until the internal output registers are updated with the results from the next conversion. Refer to Table II and Figure 5 for timing information. EXTERNAL DATA CLOCK (During a Conversion) After conversion ‘n’ has been initiated, valid data from conversion ‘n – 1’ can be read and will be valid up to 12µs after the start of conversion ‘n’. Do not attempt to clock out data from 12µs after the start of conversion ‘n’ until BUSY (pin 24) rises; this will result in data loss. NOTE: For the best possible performance when using an external data clock, data should not be clocked out during a conversion. The switching noise of the asynchronous data clock can cause digital feedthrough degrading the converter’s performance. Refer to Table II and Figure 6 for timing information. TAG FEATURE TAG (pin 17) inputs serial data synchronized to the external or internal data clock. When using an external data clock, the serial bit stream input on TAG will follow the LSB output on SDATA (pin 16) until the internal output register is updated with new conversion results. See Table II and Figures 5 and 6. The logic level input on TAG for the first rising edge of the internal data clock will be valid on SDATA after all 12 bits of valid data have been output. MULTIPLEXER TIMING The four channel input multiplexer may be addressed manually or placed in a continuous conversion mode where all four channels are sequentially addressed. CONTINUOUS CONVERSION MODE (CONTC= 5V) To place the ADS7824 in the continuous conversion mode, CONTC (pin 25) must be tied HIGH. In this mode, acquisition and conversions will take place continually, cycling through all four channels as long as CS, R/C and PWRD are LOW (See Table III). Whichever address was last loaded A0 and A1 OPERATION Inputs Inputs Inputs Inputs Inputs Outputs Outputs Outputs Outputs Outputs Initiating conversion n latches in the levels input on A0 and A1 to select the channel for conversion 'n + 1'. Conversion in process. New convert commands ignored. Initiates conversion on channel selected at start of previous conversion. Initiates conversion on channel selected at start of previous conversion. All analog functions powered down. Conversions in process or initiated will yield meaningless data. The end of conversion n (when BUSY rises) increments the internal channel latches and outputs the channel address for conversion 'n + 1' on A0 and A1. Conversion in process. Restarts continuous conversion process on next input channel. Restarts continuous conversion process on next input channel. All analog functions powered down. Conversions in process or initiated will yield meaningless data. Resets selected input channel for next conversion to AIN0. TABLE III. Conversion Control. ® 13 ADS7824 into the A0 and A1 registers (pins 19 and 18, respectively) prior to CONTC being raised HIGH, becomes the first address in the sequential continuous conversion mode (e.g., if Channel 1 was the last address selected then Channel 2 will follow, then Channel 3, and so on). The A0 and A1 address inputs become outputs when the device is in this mode. When BUSY rises at the end of a conversion, A0 and A1 will output the address of the channel that will be converted when BUSY goes LOW at the beginning of the next conversion. Data will be valid for the previous channel after BUSY rises. The address lines are updated when BUSY rises. See Table IVa and Figure 7 for channel selection timing in continuous conversion mode. PWRD (pin 26) can be used to reset the multiplexer address to zero. With the ADS7824 configured for no conversion, PWRD can be taken HIGH for a minimum of 200ns. When PWRD returns LOW, the multiplexer address will be reset to zero. When the continuous conversion mode is enabled, the first conversion will be done on Channel 0. Subsequent conversions will proceed through each higher channel, cycling back to zero after Channel 3. If PWRD is held HIGH for a significant period of time, the REF (pin 7) bypass capacitor may discharge (if the internal reference is being utilized) and the CAP (pin 6) bypass capacitor will discharge (for both internal and external references). The continuous conversion mode should not be enabled until the bypass capacitor(s) have recharged and stabilized (1ms for 2.2µF capacitors recommended). In addition, the continuous conversion mode should not be enabled even with a short pulse on PWRD until the minimum acquisition time has been met. MANUAL CHANNEL SELECTION (CONTC= 0V) The channels of the ADS7824 can be selected manually by using the A0 and A1 address pins (pins 19 and 18, respectively). See Table IVb for the multiplexer truth table and Figure 8 for channel selection timing. ADS7824 TIMING AND CONTROL A1 0 0 1 1 A0 0 1 0 1 DATA AVAILABLE FROM CHANNEL AIN3 AIN0 AIN1 AIN2 CHANNEL TO BE OR BEING CONVERTED AIN0 AIN1 AIN2 AIN3 DESCRIPTION OF OPERATION Channel being acquired or converted is output on these address lines. Data is valid for the previous channel. These lines are updated when BUSY rises. TABLE IVa. A0 and A1 Outputs (CONTC HIGH). A1 0 0 1 1 A0 0 1 0 1 CHANNEL SELECTED WHEN BUSY GOES HIGH AIN0 AIN1 AIN2 AIN3 DESCRIPTION OF OPERATION Channel to be converted during conversion 'n + 1' is latched when conversion 'n' is initiated (BUSY goes LOW). The selected input starts being acquired as soon as conversion 'n' is done (BUSY goes HIGH). TABLE IVb. A0 and A1 Inputs (CONTC LOW). Conversion Currently in Progress: BUSY n–2 n–1 n n+1 n+2 n+3 n+4 Channel Address for Conversion: A0, A1 (Output) n–2 n–1 n n+1 n+2 t29 Results from Conversion: D7-D0 n–3 n–2 n–1 n n+1 n+2 n+3 n+4 n+3 n+4 n+5 FIGURE 7. Channel Addressing in Continuous Conversion Mode (CONTC HIGH, CS and R/C LOW). R/C Conversion Currently in Progress: BUSY n–2 n–1 n n+1 n+2 n+3 n+4 Channel Address for Conversion: A0, A1 (Input) n–1 n n+1 n+2 t30 Results from Conversion: D7-D0 n–3 n–2 n–1 n n+1 n+2 n+3 n+4 n+3 n+4 n+5 FIGURE 8. Channel Addressing in Normal Conversion Mode (CONTC and CS LOW). ® ADS7824 14 CALIBRATION The ADS7824 has no internal provision for correcting the individual bipolar zero error or full-scale error for each individual channel. Instead, the bipolar zero error of each channel is guaranteed to be below a level which is quite small for a converter with a ±10V input range (slightly more than ±2 LSBs). In addition, the channel errors should match each other to within 1 LSB. For the full-scale error, the circuit of Figure 9 can be used. This will allow the reference to be adjusted such that the full-scale error for any single channel can be set to zero. Again, the close matching of the channels will ensure that the full-scale errors on the other channels will be small. CDAC. Capacitor values larger than 2.2(F will have little affect on improving performance. The output of the buffer is capable of driving up to 1mA of current to a DC load. Using an external buffer will allow the internal reference to be used for larger DC loads and AC loads. Do not attempt to directly drive an AC load with the output voltage on CAP. This will cause performance degradation of the converter. PWRD PWRD (pin 26) HIGH will power down all of the analog circuitry including the reference. Data from the previous conversion will be maintained in the internal registers and can still be read. With PWRD HIGH, a convert command yields meaningless data. When PWRD is returned LOW, adequate time must be provided in order for the capacitors on REF (pin 7) and CAP (pin 6) to recharge. For 2.2µF capacitors, a minimum recharge/settling time of 1ms is recommended before the conversion results should be considered valid. AIN2 AIN3 +5V P1 50kΩ CAP R1 1MΩ + 2.2µF REF 2.2µF + AGND2 LAYOUT POWER The ADS7824 uses 90% of its power for the analog circuitry, and the converter should be considered an analog component. For optimum performance, tie both power pins to the same +5V power supply and tie the analog and digital grounds together. The +5V power for the converter should be separate from the +5V used for the system’s digital logic. Connecting VS1 and VS2 (pins 28 and 27) directly to a digital supply can reduce converter performance due to switching noise from the digital logic. For best performance, the +5V supply can be produced from whatever analog supply is used for the rest of the analog signal conditioning. If +12V or +15V supplies are present, a simple +5V regulator can be used. Although it is not suggested, if the digital supply must be used to power the converter, be sure to properly filter the supply. Either using a filtered digital supply or a regulated analog supply, both VS1 and VS2 should be tied to the same +5V source. GROUNDING Three ground pins are present on the ADS7824. DGND is the digital supply ground. AGND2 is the analog supply ground. AGND1 is the ground which all analog signals internal to the A/D are referenced. AGND1 is more susceptible to current induced voltage drops and must have the path of least resistance back to the power supply. All the ground pins of the A/D should be tied to an analog ground plane, separated from the system’s digital logic ground, to achieve optimum performance. Both analog and digital ground planes should be tied to the ‘system’ ground as near to the power supplies as possible. This helps to prevent dynamic digital ground currents from modulating the analog ground through a common impedance to power ground. ® FIGURE 9. Full Scale Trim. REFERENCE The ADS7824 can operate with its internal 2.5V reference or an external reference. By applying an external reference to pin 7, the internal reference can be bypassed. REF REF (pin 7) is an input for an external reference or the output for the internal 2.5V reference. A 2.2µF capacitor should be connected as close to the REF pin as possible. This capacitor and the output resistance of REF create a low pass filter to bandlimit noise on the reference. Using a smaller value capacitor will introduce more noise to the reference degrading the SNR and SINAD. The REF pin should not be used to drive external AC or DC loads. The range for the external reference is 2.3V to 2.7V and determines the actual LSB size. Increasing the reference voltage will increase the full scale range and the LSB size of the converter which can improve the SNR. CAP CAP (pin 6) is the output of the internal reference buffer. A 2.2µF capacitor should be placed as close to the CAP pin as possible to provide optimum switching currents for the CDAC throughout the conversion cycle. This capacitor also provides compensation for the output of the buffer. Using a capacitor any smaller than 1µF can cause the output buffer to oscillate and may not have sufficient charge for the 15 ADS7824 CROSSTALK With a full-scale 1kHz input signal, worst case crosstalk on the ADS7824 is better than –95dB. This should be adequate for even the most demanding applications. However, if crosstalk is a concern, the following items should be kept in mind: The worst case crosstalk is generally from Channel 3 to 2. In addition, crosstalk from Channel 3 to any other channel is worse than from those channels to Channel 3. The reason for this is that channel three is nearer to the reference on the ADS7824. This allows two coupling modes: channel-tochannel and Channel 3 to the reference. In general, when crosstalk is a concern, avoid placing signals with higher frequency components on Channel 3. If a particular channel should be as immune as possible from crosstalk, Channel 0 would be the best channel for the signal and Channel 1 should have the signal with the lowest frequency content. If two signals are to have as little crosstalk as possible, they should be placed on Channel 0 and Channel 2 with lower frequency, less-sensitive inputs on the other channels. SIGNAL CONDITIONING The FET switches used for the sample hold on many CMOS A/D converters release a significant amount of charge injection which can cause the driving op amp to oscillate. The amount of charge injection due to the sampling FET switch on the ADS7824 is approximately 5-10% of the amount on similar ADCs with the charge redistribution DAC (CDAC) architecture. There is also a resistive front end which attenuates any charge which is released. The end result is a minimal requirement for the drive capability on the signal conditioning preceding the A/D. Any op amp sufficient for the signal in an application will be sufficient to drive the ADS7824. The resistive front end of the ADS7824 also provides a guaranteed ±15V overvoltage protection. In most cases, this eliminates the need for external over voltage protection circuitry. INTERMEDIATE LATCHES The ADS7824 does have tri-state outputs for the parallel port, but intermediate latches should be used if the bus will be active during conversions. If the bus is not active during conversions, the tri-state outputs can be used to isolate the A/D from other peripherals on the same bus. Intermediate latches are beneficial on any monolithic A/D converter. The ADS7824 has an internal LSB size of 610µV. Transients from fast switching signals on the parallel port, even when the A/D is tri-stated, can be coupled through the substrate to the analog circuitry causing degradation of converter performance. The effect of this phenomenon will be more obvious when using the pin-compatible ADS7825 or any of the other 16-bit converters in the ADS Family. This is due to the smaller LSB size of 38µV. For an ADS7824 with proper layout, grounding, and bypassing; the effect should only be a few tenths of an LSB at the most. In those cases where this is not true, it is possible for the conversion results to exhibit random errors of many LSBs. Poor grounding, poor bypassing, and high-speed digital signals will increase the magnitude of the errors. ® ADS7824 16