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ADS7828-Q1
SBAS456B – DECEMBER 2008 – REVISED JANUARY 2016
ADS7828-Q1 12-Bit 8-Channel Sampling Analog-to-Digital Converter
With I2C Interface
1 Features
3 Description
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The ADS7828 is a single-supply low-power 12-bit
data acquisition device that features a serial I2C
interface and an 8-channel multiplexer. The analogto-digital converter (ADC) features a sample-and-hold
amplifier and internal asynchronous clock. The
combination of an I2C serial 2-wire interface and
micropower consumption makes the ADS7828 ideal
for applications requiring the ADC to be close to the
input source in remote locations and for applications
requiring isolation. The ADS7828 is available in a
TSSOP-16 package.
1
Qualified for Automotive Applications
8-Channel Multiplexer
50-kHz Sampling Rate
No Missing Codes
2.7 V to 5 V Operation
Internal 2.5-V Reference
I2C Interface Supports Standard, Fast, and HighSpeed Modes
2 Applications
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Device Information(1)
Automotive Head Units
Heads-Up Display (HUD)
Automotive Battery Management Systems
Automotive On-Board Chargers
Voltage-Supply Monitoring
Isolated Data Acquisition
Transducer Interfaces
Battery-Operated Systems
Remote Data Acquisition
NOx Sensors
Ssot and Particulate Matter (PM) Sensors
Oxygen (O2, Lambda, A/F) Sensors
Ammonia (NH3) Sensors
Other Emissions and Gas Sensors
PART NUMBER
ADS7828-Q1
PACKAGE
TSSOP (16)
BODY SIZE (NOM)
6.40 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
2.7 V to 3.6 V
5W
+ 1 µF to
10 µF
ADS7828
0.1 µF
REFIN/
REFOUT
2 kW
VDD
2 kW
+ 1 µF to
10 µF
CH0
SDA
CH1
SCL
CH2
A0
CH3
A1
CH4
GND
Microcontroller
CH5
CH6
CH7
COM
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS7828-Q1
SBAS456B – DECEMBER 2008 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
7
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Electrical Characteristics for ADS7828E................... 5
Electrical Characteristics for ADS7828EB ................ 6
Electrical Characteristics for ADS7828E................... 8
Electrical Characteristics for ADS7828EB ................ 9
Switching Characteristics ........................................ 10
Typical Characteristics .......................................... 13
Detailed Description ............................................ 15
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 15
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 17
8
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Applications ............................................... 25
9 Power Supply Recommendations...................... 27
10 Layout................................................................... 27
10.1 Layout Guidelines ................................................. 27
10.2 Layout Example .................................................... 27
11 Device and Documentation Support ................. 28
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
12 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (October 2009) to Revision B
•
2
Page
Added Device Information table, Thermal Information table, Detailed Description section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
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SBAS456B – DECEMBER 2008 – REVISED JANUARY 2016
5 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
CH0
1
16
+VDD
CH1
2
15
SDA
CH2
3
14
SCL
CH3
4
13
A1
CH4
5
12
A0
CH5
6
11
COM
CH6
7
10
REFIN/REFOUT
CH7
8
9
GND
Pin Functions
PIN
NO.
DESCRIPTION
NAME
1
CH0
Differential channel 0: positive input or single-ended channel 0 input
2
CH1
Differential channel 0: negative input or single-ended channel 1 input
3
CH2
Differential channel 1: positive input or single-ended channel 2 input
4
CH3
Differential channel 1: negative input or single-ended channel 3 input
5
CH4
Differential channel 2: positive input or single-ended channel 4 input
6
CH5
Differential channel 2: negative input or single-ended channel 5 input
7
CH6
Differential channel 3: positive input or single-ended channel 6 input
8
CH7
Differential channel 3: negative input or single-ended channel 7 input
9
GND
Analog ground
10
REFIN / REFOUT
11
COM
12
A0
Slave address bit 0
13
A1
Slave address bit 1
14
SCL
Serial clock
15
SDA
Serial data
16
+VDD
Power supply, 3.3 V (nominal)
Internal 2.5-V reference / external reference input
Common to analog input channel
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ADS7828-Q1
SBAS456B – DECEMBER 2008 – REVISED JANUARY 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range, unless otherwise noted. (1) (2)
MIN
MAX
UNIT
VDD
Supply voltage
–0.3
6
V
VIN
Digital input voltage
–0.3
θJA
Thermal impedance, junction to free air (3) (4)
TA
Operating free-air temperature
Tlead
Lead temperature during soldering
TJ
Operating virtual-junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
(4)
0.3
V
108.4
°C/W
85
°C
Vapor phase (60 seconds)
215
°C
Infrared (15 seconds)
220
°C
150
°C
150
°C
–40
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to the GND terminal.
The package thermal impedance is calculated in accordance with JESD 51-7.
Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can impact reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Human-body model (HBM), per AEC Q100-002
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per AEC Q100-011
V
±1000
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VDD
Supply Voltage
VIN
Analog Input Voltage
2.7-V nominal
NOM
2.7
MAX
3.6
5-V nominal
4.75
Positive Input
–0.2
+VDD + 0.2
Negative Input
–0.2
0.2
0
VREF
Full-scale differential (Positive input – Negative
input)
5
5.25
UNIT
V
V
VIN(REF)
Voltage Reference Input voltage
0.05
+VDD
V
VIH
High-level digital input voltage
0.7 × +VDD
+VDD + 0.5
V
VIL
Low-level digital input voltage
–0.3
0.3 × +VDD
V
TA
Operating free-air temperature
–40
85
°C
4
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SBAS456B – DECEMBER 2008 – REVISED JANUARY 2016
6.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)
ADS7828-Q1
THERMAL METRIC
(1)
PW (TSSOP)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
102.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
37.2
°C/W
RθJB
Junction-to-board thermal resistance
47.1
°C/W
ψJT
Junction-to-top characterization parameter
2.9
°C/W
ψJB
Junction-to-board characterization parameter
46.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics for ADS7828E
+VDD = 2.7 V, VREF = 2.5 V, SCL clock frequency = 3.4 MHz (high-speed mode), over operating free-air temperature range,
unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analog Input
Ileak
Leakage current
CI
±1
µA
25
pF
Overall Performance
No missing codes
12
bits
Integral linearity error
±1
Differential linearity error
±1
Offset error
Offset error match
Gain error
Gain error match
Vn
Noise
PSRR
Power-supply ripple rejection
RMS
LSB (1)
±2
LSB
±1
±3
LSB
±0.2
±1
LSB
±1
±4
LSB
±0.2
±1
LSB
33
µV
82
dB
Sampling Dynamics
High-speed mode: SCL = 3.4 MHz
Throughput frequency
50
Fast mode: SCL = 400 kHz
8
Standard mode: SCL = 100 kHz
2
Conversion time
kHz
6
µs
AC Accuracy
THD
Total harmonic distortion (2)
VIN = 25 VPP at 10 kHz
–82
dB
Signal-to-noise ratio
VIN = 25 VPP at 10 kHz
72
dB
Signal-to-(noise + distortion) ratio
VIN = 25 VPP at 10 kHz
71
dB
Spurious-free dynamic range
VIN = 25 VPP at 10 kHz
86
dB
120
dB
Channel-to-channel isolation
Voltage Reference Output
VO
Output voltage
2.475
Internal reference drift
zo
Output impedance
IQ
Quiescent current
(1)
(2)
2.5
15
2.525
V
ppm/°C
Ω
Internal reference on
110
Internal reference off
1
GΩ
850
µA
LSB means Least Significant Bit; with VREF equal to 2.5 V, one LSB is 610 µV.
THD is measured to the ninth harmonic.
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Electrical Characteristics for ADS7828E (continued)
+VDD = 2.7 V, VREF = 2.5 V, SCL clock frequency = 3.4 MHz (high-speed mode), over operating free-air temperature range,
unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Voltage Reference Input
rI
Input resistance
Current drain
1
GΩ
20
µA
Digital Input and Output
VOL
Low-level output voltage
Minimum 3-mA sink current
0.4
V
IIH
High-level input current
VIH = +VDD + 0.5 V
10
µA
IIL
Low-level input current
VIL = –0.3 V
–10
µA
Power Supply
IQ
Quiescent current
High-speed mode: SCL = 3.4 MHz
225
Fast mode: SCL = 400 kHz
100
Standard mode: SCL = 100 kHz
PO
Power dissipation
Power-down current with wrong
address selected
Full power-down current
µA
60
High-speed mode: SCL = 3.4 MHz
675
Fast mode: SCL = 400 kHz
300
Standard mode: SCL = 100 kHz
180
High-speed mode: SCL = 3.4 MHz
70
Fast mode: SCL = 400 kHz
25
Standard mode: SCL = 100 kHz
IPD
320
1000
µW
µA
6
SCL pulled high, SDA pulled high
400
3000
nA
6.6 Electrical Characteristics for ADS7828EB
+VDD = 2.7 V, VREF = 2.5 V, SCL clock frequency = 3.4 MHz (high-speed mode), over operating free-air temperature range,
unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analog Input
Ileak
Leakage current
CI
±1
µA
25
pF
Overall Performance
No missing codes
12
Integral linearity error
Differential linearity error
Offset error
Offset error match
Gain error
Gain error match
Vn
Noise
PSRR
Power-supply ripple rejection
RMS
bits
±0.5
±1
LSB (1)
±0.5
–1 to 2
LSB
±0.75
±2
LSB
±0.2
±1
LSB
±0.75
±3
LSB
±0.2
±1
LSB
33
µV
82
dB
Sampling Dynamics
High-speed mode: SCL = 3.4 MHz
Throughput frequency
Fast mode: SCL = 400 kHz
8
Standard mode: SCL = 100 kHz
2
Conversion time
(1)
6
50
6
kHz
µs
LSB means Least Significant Bit; with VREF equal to 2.5 V, one LSB is 610 µV.
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SBAS456B – DECEMBER 2008 – REVISED JANUARY 2016
Electrical Characteristics for ADS7828EB (continued)
+VDD = 2.7 V, VREF = 2.5 V, SCL clock frequency = 3.4 MHz (high-speed mode), over operating free-air temperature range,
unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC Accuracy
THD
Total harmonic distortion (2)
VIN = 25 VPP at 10 kHz
–82
dB
Signal-to-noise ratio
VIN = 25 VPP at 10 kHz
72
dB
Signal-to-(noise + distortion) ratio
VIN = 25 VPP at 10 kHz
71
dB
Spurious-free dynamic range
VIN = 25 VPP at 10 kHz
86
dB
120
dB
Channel-to-channel isolation
Voltage Reference Output
VO
Output voltage
2.475
Internal reference drift
zo
Output impedance
IQ
Quiescent current
2.5
2.525
15
V
ppm/°C
Ω
Internal reference on
110
Internal reference off
1
GΩ
850
µA
1
GΩ
20
µA
Voltage Reference Input
rI
Input resistance
Current drain
Digital Input and Output
VOL
Low-level output voltage
Minimum 3-mA sink current
0.4
V
IIH
High-level input current
VIH = +VDD + 0.5 V
10
µA
IIL
Low-level input current
VIL = –0.3 V
–10
µA
Power Supply
IQ
Quiescent current
High-speed mode: SCL = 3.4 MHz
225
Fast mode: SCL = 400 kHz
100
Standard mode: SCL = 100 kHz
PO
Power dissipation
Power-down current with wrong
address selected
(2)
Full power-down current
675
Fast mode: SCL = 400 kHz
300
Standard mode: SCL = 100 kHz
180
High-speed mode: SCL = 3.4 MHz
70
Fast mode: SCL = 400 kHz
25
SCL pulled high, SDA pulled high
µA
60
High-speed mode: SCL = 3.4 MHz
Standard mode: SCL = 100 kHz
IPD
320
1000
µW
µA
6
400
3000
nA
THD is measured to the ninth harmonic.
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6.7 Electrical Characteristics for ADS7828E
+VDD = 5 V, VREF = External 5 V, SCL clock frequency = 3.4 MHz (high-speed mode), over operating free-air temperature
range, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analog Input
Ileak
Leakage current
CI
±1
µA
25
pF
Overall Performance
No missing codes
12
bits
Integral linearity error
±1
Differential linearity error
±1
Offset error
±1
Offset error match
Gain error
±1
Gain error match
Vn
Noise
PSRR
Power-supply ripple rejection
RMS
±2
LSB (1)
LSB
±3
LSB
±1.5
LSB
±3
LSB
±1
LSB
33
µV
82
dB
Sampling Dynamics
High-speed mode: SCL = 3.4 MHz
Throughput frequency
50
Fast mode: SCL = 400 kHz
8
Standard mode: SCL = 100 kHz
2
Conversion time
kHz
6
µs
AC Accuracy
THD
Total harmonic distortion (2)
VIN = 25 VPP at 10 kHz
–82
dB
Signal-to-noise ratio
VIN = 25 VPP at 10 kHz
72
dB
Signal-to-(noise + distortion) ratio
VIN = 25 VPP at 10 kHz
71
dB
Spurious-free dynamic range
VIN = 25 VPP at 10 kHz
86
dB
120
dB
Channel-to-channel isolation
Voltage Reference Output
VO
Output voltage
2.475
Internal reference drift
zo
Output impedance
IQ
Quiescent current
Internal reference on
Internal reference off
2.5
2.525
V
15
ppm/°C
110
Ω
1
GΩ
1300
µA
1
GΩ
20
µA
Voltage Reference Input
rI
Input resistance
Current drain
Digital Input and Output
VOL
Low-level output voltage
Minimum 3-mA sink current
IIH
High-level input current
VIH = +VDD + 0.5 V
IIL
Low-level input current
VIL = –0.3 V
(1)
(2)
8
–10
0.4
V
10
µA
µA
LSB means Least Significant Bit; with VREF equal to 5 V, one LSB is 1.22 mV.
THD is measured to the ninth harmonic.
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Electrical Characteristics for ADS7828E (continued)
+VDD = 5 V, VREF = External 5 V, SCL clock frequency = 3.4 MHz (high-speed mode), over operating free-air temperature
range, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
High-speed mode: SCL = 3.4 MHz
750
100
Fast mode: SCL = 400 kHz
300
Standard mode: SCL = 100 kHz
150
High-speed mode: SCL = 3.4 MHz
3.75
UNIT
Power Supply
IQ
Quiescent current
PO
Power dissipation
Power-down current with wrong
address selected
Fast mode: SCL = 400 kHz
Full power-down current
5
1.5
Standard mode: SCL = 100 kHz
0.75
High-speed mode: SCL = 3.4 MHz
400
Fast mode: SCL = 400 kHz
150
Standard mode: SCL = 100 kHz
IPD
µA
µW
µA
35
SCL pulled high, SDA pulled high
400
3000
nA
6.8 Electrical Characteristics for ADS7828EB
+VDD = 5 V, VREF = External 5 V, SCL clock frequency = 3.4 MHz (high-speed mode), over operating free-air temperature
range, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analog Input
Ileak
Leakage current
CI
±1
µA
25
pF
Overall Performance
No missing codes
12
Integral linearity error
Differential linearity error
Offset error
bits
±1
±0.5
–1 to 2
LSB
±0.75
±2
LSB
±1
LSB
±2
LSB
±1
LSB
Offset error match
Gain error
±0.75
Gain error match
Vn
Noise
PSRR
Power-supply ripple rejection
RMS
LSB (1)
±0.5
33
µV
82
dB
Sampling Dynamics
High-speed mode: SCL = 3.4 MHz
Throughput frequency
50
Fast mode: SCL = 400 kHz
8
Standard mode: SCL = 100 kHz
Conversion time
kHz
2
6
µs
AC Accuracy
THD
Total harmonic distortion (2)
VIN = 25 VPP at 10 kHz
–82
dB
Signal-to-noise ratio
VIN = 25 VPP at 10 kHz
72
dB
Signal-to-(noise + distortion) ratio
VIN = 25 VPP at 10 kHz
71
dB
Spurious-free dynamic range
VIN = 25 VPP at 10 kHz
86
dB
120
dB
Channel-to-channel isolation
(1)
(2)
LSB means Least Significant Bit; with VREF equal to 5 V, one LSB is 1.22 mV.
THD is measured to the ninth harmonic.
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Electrical Characteristics for ADS7828EB (continued)
+VDD = 5 V, VREF = External 5 V, SCL clock frequency = 3.4 MHz (high-speed mode), over operating free-air temperature
range, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2.475
2.5
2.525
UNIT
Voltage Reference Output
VO
Output voltage
Internal reference drift
zo
Output impedance
IQ
Quiescent current
Internal reference on
Internal reference off
V
15
ppm/°C
110
Ω
1
GΩ
1300
µA
1
GΩ
20
µA
Voltage Reference Input
rI
Input resistance
Current drain
Digital Input and Output
VOL
Low-level output voltage
Minimum 3-mA sink current
IIH
High-level input current
VIH = +VDD + 0.5 V
IIL
Low-level input current
VIL = –0.3 V
0.4
V
10
µA
–10
µA
Power Supply
IQ
Quiescent current
PO
Power dissipation
Power-down current with wrong
address selected
High-speed mode: SCL = 3.4 MHz
750
Fast mode: SCL = 400 kHz
300
Standard mode: SCL = 100 kHz
150
High-speed mode: SCL = 3.4 MHz
3.75
Fast mode: SCL = 400 kHz
Full power-down current
µA
5
1.5
Standard mode: SCL = 100 kHz
0.75
High-speed mode: SCL = 3.4 MHz
400
Fast mode: SCL = 400 kHz
150
Standard mode: SCL = 100 kHz
IPD
1000
µW
µA
35
SCL pulled high, SDA pulled high
400
3000
nA
6.9 Switching Characteristics
+VDD = 2.7 V, over operating free-air temperature range, unless otherwise noted. (1) (2) See Figure 1.
PARAMETER
fSCL
SCL clock frequency
TEST CONDITIONS
Bus free time between Stop and
Start conditions
tHD;
Hold time (repeated) Start condition
Fast mode
400
Cb = 100 pF max
3.4
Cb = 400 pF max
1.7
Standard mode
4.7
Fast mode
1.3
Standard mode
tlow
STA
Low period of the SCL clock
10
4
Fast mode
600
High-speed mode
160
Standard mode
4.7
Fast mode
1.3
High-speed mode (3)
(1)
(2)
(3)
MAX
100
High-speed mode
tBUF
MIN
Standard mode
Cb = 100 pF max
160
Cb = 400 pF max
320
UNIT
kHz
MHz
μs
μs
ns
μs
ns
All values referred to VIH(MIN) and VIL(MAX) levels.
Not production tested, except for the perameter tHD; DAT, data hold time, high-speed mode, Cb = 100 pF max.
For bus line loads (CB) between 100 pF and 400 pF, the timing parameters must be linearly interpolated.
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Switching Characteristics (continued)
+VDD = 2.7 V, over operating free-air temperature range, unless otherwise noted.(1)(2) See Figure 1.
PARAMETER
TEST CONDITIONS
Standard mode
thigh
High period of the SCL clock
tSU; DAT
Setup time for a repeated Start
condition
Data setup time
DAT
Data hold time
Cb = 100 pF max
60
Cb = 400 pF max
120
Standard mode
4.7
Fast mode
600
High-speed mode
160
Standard mode
250
Fast mode
100
3.45
0.9
Cb = 100 pF max
0
82
Cb = 400 pF max
0
162
(4)
20 + 0.1Cb
300
Cb = 100 pF max
10
40
Cb = 400 pF max
20
300
Cb = 100 pF max
10
80
Cb = 400 pF max
20
160
20 + 0.1Cb
300
Cb = 100 pF max
10
40
Cb = 400 pF max
20
Fast mode
(3)
20 + 0.1Cb
300
10
80
Cb = 400 pF max
20
160
Cb
ns
300
20 + 0.1Cb
300
Cb = 100 pF max
10
80
Cb = 400 pF max
20
160
Standard mode
Setup time for Stop condition
80
Cb = 100 pF max
Fast mode
High-speed mode (3)
tSU; STO
ns
1000
Standard mode
Fall time of SDA signal
ns
300
Standard mode
tfDA
ns
80
20 + 0.1Cb
Fast mode
High-speed mode
ns
1000
High-speed mode (3)
Rise time of SDA signal
μs
1000
Fast mode
Standard mode
trDA
ns
0
Rise time of SCL signal after a
Fast mode
repeated Start condition and after an
acknowledge bit
High-speed mode (3)
Fall time of SCL signal
ns
0
Standard mode
tfCL
μs
Fast mode
High-speed mode (3)
trCL1
ns
Standard mode
Standard mode
Rise time of SCL signal
μs
10
High-speed mode (3)
trCL
UNIT
600
High-speed mode
tHD;
MAX
4
Fast mode
High-speed mode (3)
tSU; STA
MIN
μs
4
Fast mode
600
High-speed mode
160
Capacitive load for SDA or SCL
ns
ns
400
Fast mode
50
High-speed mode
10
pF
tSP
Pulse width of spike suppressed
VnH
Noise margin at the high level for
each connected device (including
hysteresis)
0.2 × VDD
V
VnL
Noise margin at the low level for
each connected device (including
hysteresis)
0.1 × VDD
V
(4)
ns
A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH
signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.
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SDA
tBUF
tHD;STA
tLOW
tr
tSP
tf
SCL
tSU;DAT
tHD;STA
tHD;DAT
Stop
tHIGH
tSU;STO
tSU;DAT
Repeated
Start
Start
Figure 1. I2C Timing
12
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6.10 Typical Characteristics
0.00
2.00
1.50
ILE (LSB)
Amplitude (dB)
1.00
–40.00
–80.00
0.50
0.00
–0.50
–1.00
–1.50
–120.0
–2.00
0
10
20
25
0
1024
2048
Output Code
Frequency (kHz)
2.00
2.00
1.50
1.50
1.00
1.00
0.50
0.50
0.00
–0.50
0.00
–0.50
–1.00
–1.00
–1.50
–1.50
–2.00
–2.00
0
1024
2048
Output Code
3072
0
4095
Figure 4. Differential Linearity Error vs Code
(2.5-V Internal Reference)
1024
2048
Output Code
3072
4095
Figure 5. Integral Linearity Error vs Code
(2.5-V External Reference)
1.5
2.00
1.50
Delta from 25°C (LSB)
1.0
1.00
DLE (LSB)
4095
Figure 3. Integral Linearity Error vs Code
(2.5-V Internal Reference)
ILE (LSB)
DLE (LSB)
Figure 2. Frequency Spectrum
(4096 Point FFT: fIN = 1 kHz, 0 dB)
3072
0.50
0.00
–0.50
–1.00
0.5
0.0
–0.5
–1.0
–1.50
–1.5
–2.00
0
1024
2048
Output Code
3072
4095
–50
–25
0
25
50
75
100
Temperature ( °C)
Figure 6. Differential Linearity Error vs Code
(2.5-V External Reference)
Figure 7. Change in Offset vs Temperature
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1.5
2.51875
1.0
2.51250
Internal Reference (V)
Delta from 25°C (LSB)
Typical Characteristics (continued)
0.5
0.0
–0.5
2.50625
2.50000
2.49375
2.48750
–1.0
2.48125
–1.5
–50
–25
0
25
50
75
–50
100
–25
0
Temperature (° C)
400
600
350
Supply Current (µA)
Supply Current (nA)
750
450
300
150
0
75
100
300
250
200
150
–150
100
–50
–25
0
25
50
75
100
125
–50
–25
0
Temperature ( °C)
25
50
75
100
Temperature (°C)
Figure 10. Power-Down Supply Current vs Temperature
Figure 11. Supply Current vs Temperature
100
300
250
No Cap
(42 µs)
12-Bit Settling
80
Internal VREF (%)
Supply Current (µA)
50
Figure 9. Internal Reference vs Temperature
Figure 8. Change in Gain vs Temperature
200
150
100
1-µF Cap
(1240 µs)
12-Bit Settling
60
40
20
50
0
0
10
100
1k
10k
0
200
400
600
800
1000
1200
1400
Turn-On Time (µs)
I2C Bus Rate (kHz)
Figure 12. Supply Current vs I2C Bus Rate
14
25
Temperature (° C)
Figure 13. Internal VREF vs Turn-On Time
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7 Detailed Description
7.1 Overview
The ADS7828 is a classic Successive Approximation Register (SAR) ADC. The architecture is based on
capacitive redistribution which inherently includes a sample-and-hold function. The converter is fabricated on a
0.6μ CMOS process.
The ADS7828 core is controlled by an internally generated free-running clock. When the ADS7828 is not
performing conversions or being addressed, it keeps the ADC core powered off, and the internal clock does not
operate.
7.2 Functional Block Diagram
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
SAR
8-Channel
Multiplexer
S/H Amp
Comparator
SDA
SCL
CDAC
Serial
Interface
A0
A1
2.5-V VREF
REFIN/REFOUT
Buffer
7.3 Feature Description
7.3.1 Analog Input
When the converter enters the hold mode, the voltage on the selected CHx pin is captured on the internal
capacitor array. The input current on the analog inputs depends on the conversion rate of the device. During the
sample period, the source must charge the internal sampling capacitor (typically 25 pF). After the capacitor has
been fully charged, there is no further input current. The amount of charge transfer from the analog source to the
converter is a function of conversion rate.
7.3.2 Reference
The ADS7828 can operate with an internal 2.5-V reference or an external reference. If a 5-V supply is used, an
external 5-V reference is required in order to provide full dynamic range for a 0 V to +VDD analog input. This
external reference can be as low as 50 mV. When using a 2.7-V supply, the internal 2.5-V reference will provide
full dynamic range for a 0 V to +VDD analog input.
As the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. This is
often referred to as the LSB (least significant bit) size and is equal to the reference voltage divided by 4096. This
means that any offset or gain error inherent in the ADC will appear to increase, in terms of LSB size, as the
reference voltage is reduced.
The noise inherent in the converter will also appear to increase with lower LSB size. With a 2.5-V reference, the
internal noise of the converter typically contributes only 0.32 LSB peak-to-peak of potential error to the output
code. When the external reference is 50 mV, the potential error contribution from the internal noise is 50 times
larger—16 LSBs. The errors due to the internal noise are Gaussian in nature and can be reduced by averaging
consecutive conversion results.
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Feature Description (continued)
7.3.3 Digital Interface
The ADS7828 supports the I2C serial bus and data transmission protocol, in all three defined modes: standard,
fast, and high-speed. A device that sends data onto the bus is defined as a transmitter, and a device receiving
data as a receiver. The device that controls the message is called a master. The devices that are controlled by
the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL),
controls the bus access, and generates the Start and Stop conditions. The ADS7828 operates as a slave on the
I2C bus. Connections to the bus are made via the open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (see Figure 14):
• Data transfer may be initiated only when the bus is not busy.
• During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data
line while the clock line is high will be interpreted as control signals.
SDA
MSB
Slave Address
R/W
Direction
Bit
Acknowledgement
Signal from
Receiver
Acknowledgement
Signal from
Receiver
1
SCL
2
6
7
8
9
1
ACK
Start
Condition
2
3-8
8
9
ACK
Repeated If More Bytes Are Transferred
Stop Condition
or Repeated
Start Condition
Figure 14. Basic Operation
Accordingly, the following bus conditions have been defined:
• Bus Not Busy
Both data and clock lines remain high.
• Start Data Transfer
A change in the state of the data line, from high to low, while the clock is high, defines a Start condition.
• Stop Data Transfer
A change in the state of the data line, from low to high, while the clock line is high, defines the Stop condition.
• Data Valid
The state of the data line represents valid data, when, after a Start condition, the data line is stable for the
duration of the high period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of data
bytes transferred between Start and Stop conditions is not limited and is determined by the master device.
The information is transferred byte-wise and each receiver acknowledges with a ninth-bit.
Within the I2C bus specifications a standard mode (100-kHz clock rate), a fast mode (400-kHz clock rate), and
a highspeed mode (3.4-MHz clock rate) are defined. The ADS7828 works in all three modes.
• Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each
byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of the acknowledge clock pulse. Of course, setup and
hold times must be taken into account. A master must signal an end of data to the slave by not generating an
acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the
data line high to enable the master to generate the Stop condition.
16
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Feature Description (continued)
Figure 14 shows how data transfer is accomplished on the I2C bus. Depending upon the state of the R/W bit, two
types of data transfer are possible:
• Data transfer from a master transmitter to a slave receiver.
The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave
returns an acknowledge bit after the slave address and each received byte.
• Data transfer from a slave transmitter to a master receiver.
The first byte, the slave address, is transmitted by the master. The slave then returns an acknowledge bit.
Next, a number of data bytes are transmitted by the slave to the master. The master returns an acknowledge
bit after all received bytes other than the last byte. At the end of the last received byte, a not-acknowledge is
returned.
The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended
with a Stop condition or a repeated Start condition. Since a repeated Start condition is also the beginning of the
next serial transfer, the bus will not be released.
7.4 Device Functional Modes
The ADS7828 may operate in the following two modes:
• Slave Receiver Mode
Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is
transmitted. Start and Stop conditions are recognized as the beginning and end of a serial transfer. Address
recognition is performed by hardware after reception of the slave address and direction bit.
• Slave Transmitter Mode
The first byte (the slave address) is received and handled as in the slave receiver mode. However, in this
mode the direction bit will indicate that the transfer direction is reversed. Serial data is transmitted on SDA by
the ADS7828 while the serial clock is input on SCL. Start and Stop conditions are recognized as the
beginning and end of a serial transfer.
7.4.1 Address Byte
The address byte is the first byte received following the Start condition from the master device (see Figure 15).
The first five bits (MSBs) of the slave address are factory pre-set to 10010. The next two bits of the address byte
are the device select bits, A1 and A0. Input pins (A1-A0) on the ADS7828 determine these two bits of the device
address for a particular ADS7828. A maximum of four devices with the same pre-set code can therefore be
connected on the same bus at one time.
Figure 15. Address Byte
MSB
1
6
0
5
0
4
1
3
0
2
A1
1
A0
LSB
R/W
The A1 and A0 address inputs can be connected to VDD or digital ground. The device address is set by the state
of these pins upon power-up.
The last bit of the address byte (R/W) defines the operation to be performed. When set to a 1, a read operation is
selected; when set to a 0, a write operation is selected. Following the Start condition, the ADS7828 monitors the
SDA bus, checking the device type identifier being transmitted. Upon receiving the 10010 code, the appropriate
device select bits, and the R/W bit, the slave device outputs an acknowledge signal on the SDA line.
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7.4.2 Command Byte
The operating mode is determined by a command byte (see Figure 16).
Figure 16. Command Byte
MSB
SD
6
C2
5
C1
4
C0
3
PD1
2
PD0
1
X
LSB
X
SD: Single-ended or differential inputs
0 = Differential inputs
1 = Single-ended inputs
C2 to C0: Channel selections (see Table 1)
PD1, PD0: Power-down selection (see Table 2)
X: Unused
Table 1. Channel Selection Control Addressed by Command Byte
COMMAND BYTE INPUTS
CHANNEL SELECTIONS
SD
C2
C1
C0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
0
0
0
0
+IN
–IN
—
—
—
—
—
—
—
0
0
0
1
—
—
+IN
–IN
—
—
—
—
—
0
0
1
0
—
—
—
—
+IN
–IN
—
—
—
0
0
1
1
—
—
—
—
—
—
+IN
–IN
—
0
1
0
0
–IN
+IN
—
—
—
—
—
—
—
0
1
0
1
—
—
–IN
+IN
—
—
—
—
—
0
1
1
0
—
—
—
—
–IN
+IN
—
—
—
0
1
1
1
—
—
—
—
—
—
–IN
+IN
—
1
0
0
0
+IN
—
—
—
—
—
—
—
–IN
1
0
0
1
—
—
+IN
—
—
—
—
—
–IN
1
0
1
0
—
—
—
—
+IN
—
—
—
–IN
1
0
1
1
—
—
—
—
—
—
+IN
—
–IN
1
1
0
0
—
+IN
—
—
—
—
—
—
–IN
1
1
0
1
—
—
—
+IN
—
—
—
—
–IN
1
1
1
0
—
—
—
—
—
+IN
—
—
–IN
1
1
1
1
—
—
—
—
—
—
—
+IN
–IN
Table 2. Power-Down Selection
PD1
PD0
0
0
Power down between ADC conversions
DESCRIPTION
0
1
Internal reference off and ADC on
1
0
Internal reference on and ADC off
1
1
Internal reference on and ADC on
7.4.3 Initiating Conversion
Provided the master has write-addressed it, the ADS7828 turns on the ADC section and begins conversions
when it receives bit 4 of the command byte shown in Figure 16. If the command byte is correct, the ADS7828
returns an ACK condition.
18
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7.4.4 Reading Data
Data can be read from the ADS7828 by read addressing the part (LSB of address byte set to 1) and receiving
the transmitted bytes. Converted data can be read from the ADS7828 only after a conversion has been initiated
as described in the preceding section.
Each 12-bit data word is returned in two bytes (see Figure 17), where D11 is the MSB of the data word, and D0
is the LSB. Byte 0 is sent first, followed by byte 1.
Figure 17. Reading Data
MSB
0
D7
Byte 0
Byte 1
6
0
D6
5
0
D5
4
0
D4
3
D11
D3
2
D10
D2
1
D9
D1
LSB
D8
D0
7.4.5 Reading in Fast or Standard (F/S) Mode
Figure 18 shows the interaction between the master and the slave ADS7828 in fast or standard (F/S) mode. At
the end of reading conversion data, the ADS7828 can be issued a repeated Start condition by the master to
secure bus operation for subsequent conversions of the ADC. This would be the most efficient way to perform
continuous conversions.
ADC Power-Down Mode
S
1
0
0
1
0
A1 A0
W
ADC Sampling Mode
A
SD C2
C1
0
0
1
0
A1
A0
A
ADC Power-Down Mode
(depending on power-down selection bits)
ADC Converting Mode
1
X
Command Byte
Write-Addressing Byte
Sr
C0 PD1 PD0 X
R
A
0
0
0
0
D11 D10 D9
D8
A
D7
D6...D1
D0
N
P
See Note (1)
Read-Addressing Byte
From Master to Slave
From Slave to Master
2 x (8 bits + ack/nack)
A = Acknowledge (SDA low)
N = Not acknowledge (SDA high)
S = Start condition
P = Stop condition
Sr = Repeated Start condition
W = 0 (write)
R = 1 (read)
NOTE: (1) To secure bus operation and loop back to the stage of write-addressing for next conversion, use Repeated Start.
Figure 18. Typical Read Sequence in F/S Mode
7.4.6 Reading in High-Speed (HS) Mode
High Speed (HS) mode is fast enough that codes can be read out one at a time. In HS mode, there is not
enough time for a single conversion to complete between the reception of a repeated Start condition and the
read-addressing byte, so the ADS7828 stretches the clock after the read-addressing byte has been fully
received, holding it low until the conversion is complete.
See Figure 19 for a typical read sequence for HS mode. Included in the read sequence is the shift from F/S to
HS modes. It may be desirable to remain in HS mode after reading a conversion; to do this, issue a repeated
Start instead of a Stop at the end of the read sequence, since a Stop causes the part to return to F/S mode.
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F/S Mode
S
0
0
0
0
1
X
X
X
N
HS Mode Master Code
HS Mode Enabled
ADC Power-Down Mode
Sr
1
0
0
1
0
A1 A0
W
A
ADC Sampling Mode
SD
C2 C1
Write-Addressing Byte
C0 PD1 PD0 X
X
A
Command Byte
HS Mode Enabled
ADC Converting Mode
Sr
1
0
0
1
0
A1 A0
R
SCLH(2) is stretched low waiting for data conversion
A
Read-Addressing Byte
HS Mode Enabled
Return to F/S Mode(1)
ADC Power-Down Mode
(depending on power-down selection bits)
0
0
0
0
D11 D10 D9
D8
A
D7
D6...D1
D0
N
P
2 x (8 Bits + ack/not-ack)
A = Acknowledge (SDA low)
N = Not acknowledge (SDA high)
S = StartCondition
P = Stop Condition
Sr = Repeated Start condition
From Master to Slave
From Slave to Master
W = 0 (write)
R = 1 (read)
NOTES: (1) To remain in HS mode, use Repeated Start instead of Stop.
(2) SCLH is SCL in HS mode.
Figure 19. Typical Read Sequence in HS Mode
7.4.7 Reading With Reference On or Off
The internal reference defaults to off when the ADS7828 power is on. To turn the internal reference on or off, see
Table 2. If the reference (internal or external) is constantly turned on and off, a proper amount of settling time
must be added before a normal conversion cycle can be started. The exact amount of settling time needed
varies depending on the configuration.
See Figure 20 for an example of the proper internal reference turn-on sequence before issuing the typical read
sequences required for the F/S mode when an internal reference is used.
20
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Internal Reference Turn-On Sequence
S
1
0
0
1
0
A1 A0
W
A
X
X
Write-Addressing Byte
X
X
1
X
X
X
A
P
Internal Reference
Turn-On
Settling Time
Wait until the required
settling time is reached
Command Byte
Typical Read
Sequence(1)
in F/S Mode
Settled Internal Reference
ADC Power-Down Mode
S
1
0
0
1
0
A1 A0
W
A
ADC Sampling Mode
SD C2
Write-Addressing Byte
C1
C0
1
PD0 X
X
A
Command Byte
Settled Internal Reference
ADC Power-Down Mode
(depending on power-down selection bits)
ADC Converting Mode
Sr
1
0
0
1
0
A0
A1
R
A
0
0
0
0
Read-Addressing Byte
From Master to Slave
From Slave to Master
D11 D10 D9
D8
A
D7
2 x (8 bits + ack/nack)
A = Acknowledge (SDA low)
N = Not acknowledge (SDA high)
S = Start condition
P = Stop condition
Sr = Repeated Start condition
D6...D1
D0
N
P
See
Note (2)
W = 0 (write)
R = 1 (read)
NOTES: (1) Typical read sequences can be reused after the internal reference is settled.
(2) To secure bus operation and loop back to the stage of write-addressing for next conversion, use Repeated Start.
Figure 20. Internal Reference Turn-On Sequence and Typical Read Sequence (F/S Mode Shown)
When using an internal reference, there are three things that must be done:
1. To use the internal reference, the PD1 bit of Command Byte must always be set to logic 1 for each sample
conversion that is issued by the sequence, as shown in Figure 18.
2. To achieve 12-bit accuracy conversion when using the internal reference, the internal reference settling time
must be considered, as shown in the Internal VREF vs Turn-On Time Typical Characteristic plot. If the PD1
bit has been set to logic 0 while using the ADS7828, then the settling time must be reconsidered after PD1 is
set to logic 1. In other words, whenever the internal reference is turned on after it has been turned off, the
settling time must be long enough to get 12-bit accuracy conversion.
3. When the internal reference is off, it is not turned on until both the first Command Byte with PD1 = 1 is sent
and then a Stop condition or repeated Start condition is issued. (The actual turn-on time occurs once the
Stop or repeated Start condition is issued.) Any Command Byte with PD1 = 1 issued after the internal
reference is turned on serves only to keep the internal reference on. Otherwise, the internal reference would
be turned off by any Command Byte with PD1 = 0.
The example in Figure 20 can be generalized for an HS mode conversion cycle by changing the timing of the
conversion cycle. If using an external reference, PD1 must be set to 0, and the external reference must be
settled. The typical sequence in Figure 18 or Figure 19 can then be used.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The following sections give example circuits and suggestions for using the ADS7828-Q1 device in various
situations.
8.1.1 Basic Connections
For many applications, connecting the ADS7828-Q1 device is simple. Figure 21 shows a basic connection
diagram for the ADS7828-Q1 device.
The fully differential voltage input of the ADS7828-Q1 device is ideal for connection to differential sources with
moderately low source impedance, such as thermocouples and thermistors. Although the ADS7828-Q1 device
can read bipolar differential signals, they cannot accept negative voltages on either input. It may be helpful to
think of the ADS7828-Q1 positive voltage input as noninverting, and of the negative input as inverting.
When the ADS7828-Q1 device converts data, it draws current in short spikes. The 0.1-μF bypass capacitor
supplies the momentary bursts of extra current needed from the supply.
The ADS7828-Q1 device interfaces directly to standard mode, fast mode, and high-speed mode I2C controllers.
Any microcontroller I2C peripheral, including master-only and non-multiple-master I2C peripherals, can operate
with the ADS7828-Q1 device. The ADS7828-Q1 device does not perform clock-stretching (that is, it never pulls
the clock line low), so it is not necessary to provide for this function unless other clock-stretching devices are on
the same I2C bus.
Pullup resistors are required on both the SDA and SCL lines because I2C bus drivers are open-drain. The size of
these resistors depends on the bus operating speed and capacitance of the bus lines. Higher-value resistors
consume less power, but increase the transition times on the bus, limiting the bus speed. Lower-value resistors
allow higher speed at the expense of higher power consumption. Long bus lines have higher capacitance and
require smaller pullup resistors to compensate. The resistors should not be too small; if they are, the bus drivers
may not be able to pull the bus lines low.
ADS7828-Q1 14
VDD
SCL
VDD
Pullup Resistors
1 kΩ to 10 kΩ (typical)
Microcontroller or
Microprocessor
2
1
CH0
SDA 15
2
CH1
VDD 16
9
GND
CH6
7
4
CH3
CH5
6
0.1 µF (typical)
CH4
with I C Port
5
SCL
SDA
Inputs Selected
from Configuration
Register
Figure 21. Typical Connections of the ADS7828-Q1
22
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8.1.1.1 Connecting Multiple Devices
Connecting multiple ADS7828-Q1 devices to a single bus is simple. Using the address pin, the ADS7828-Q1
device can be set to one of four different I2C addresses. Figure 22 shows an example using three ADS7828-Q1
devices. Up to four ADS7828-Q1 devices (using different address pin configurations) can be connected to a
single bus.
Only one set of pullup resistors is require per bus. The pullup resistor values can be lowered slightly to
compensate for the additional bus capacitance presented by multiple devices and increased line length.
GND
ADS7828-Q1 14
SCL
GND
9
13 A1
CH7
8
3
CH2
CH6
7
4
CH3
CH5
6
12 A0
Pullup Resistors
1 kΩ to 10 kΩ (typical)
VDD
Microcontroller or
Microprocessor
CH4
2
5
with I C Port
SCL
SDA
ADS7828-Q1 14
SCL
12 A0
SDA 15
13 A1
CH7
8
3
CH2
CH6
7
4
CH3
CH5
6
CH4
5
ADS7828-Q1 14
SCL
12 A0
SDA 15
13 A1
CH7
8
3
CH2
CH6
7
4
CH3
CH5
6
CH4
5
ADS7828-Q1 14
SCL
SDA 15
12 A0
VDD
13 A1
CH7
8
3
CH2
CH6
7
4
CH3
CH5
6
CH4
5
The ADS7828-Q1 power and input connections are omitted for clarity. The ADDR pin selects the I2C address.
Figure 22. Connecting Multiple ADS7828-Q1 Devices
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8.1.1.2 Using GPIO Ports for Communication
Most microcontrollers have programmable input-output (I/O) pins that can be set in software to act as inputs or
outputs. If an I2C controller is not available, the ADS7828-Q1 device can be connected to GPIO pins and the I2C
bus protocol simulated, or bit-banged, in software. Figure 23 shows an example of this configuration for a single
ADS7828-Q1 device.
Bit-banging the I2C with GPIO pins occurs by setting the GPIO line to 0 and toggling it between input and output
modes to apply the proper bus states. To drive the line low, the pin is set to output 0; to let the line go high, the
pin is set to input. When the pin is set to input, the state of the pin can be read; if another device is pulling the
line low, this configuration reads as a 0 in the port input register.
Note that no pullup resistor is shown on the SCL line. In this simple case, the resistor is not needed; the
microcontroller can simply leave the line on output, and set it to 1 or 0 as appropriate. This action is possible
because the ADS7828-Q1 never drives the clock line low. This technique can also be used with multiple devices,
and has the advantage of lower current consumption as a result of the absence of a resistive pullup.
If there are any devices on the bus that may drive the clock lines low, this method should not be used; the SCL
line should be high-Z or 0 and a pullup resistor provided as usual.
Some microcontrollers have selectable strong pullup circuits built into the GPIO ports. In some cases, these
circuits can be switched on and used in place of an external pullup resistor. Weak pullups are also provided on
some microcontrollers, but usually these are too weak for I2C communication. If there is any doubt about the
matter, test the circuit before committing it to production.
ADS7828-Q1 14
VDD
Microcontroller or
Microprocessor
with GPIO Ports
GPIO_1
SCL
1
CH0
SDA 15
2
CH1
CH7
8
3
CH2
CH6
7
4
CH3
CH5
6
CH4
5
GPIO_0
ADS7828-Q1 power and input connections omitted for clarity.
Figure 23. Using GPIO with a Single ADS7828-Q1
8.1.1.3 Single-Ended Inputs
Although the ADS7828-Q1 device has four differential inputs, the device can easily measure eight single-ended
signals. Figure 24 shows a single-ended connection scheme. The ADS7828-Q1 device is configured for singleended measurement by configuring the MUX to measure each channel with respect to ground. Data are then
read out of one input based on the selection on the configuration register. The single-ended signal can range
from 0 V to the supply voltage. The ADS7828-Q1 device loses no linearity anywhere within the input range.
Negative voltages cannot be applied to this circuit because the ADS7828-Q1 device can only accept positive
voltages.
The ADS7828-Q1 input range is bipolar differential with respect to the reference. The single-ended circuit shown
in Figure 24 covers only half the ADS7828-Q1 input scale because it does not produce differentially negative
inputs; therefore, one bit of resolution is lost.
24
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VDD
Output Codes
0-32767
ADS7828-Q1 14
SCL
1
CH0
SDA 15
2
CH1
VDD 16
9
GND
CH6
7
4
CH3
CH5
6
0.1 µF (typical)
CH4
5
Inputs Selected
from Configuration
Register
Digital and address pin connections omitted for clarity.
Figure 24. Measuring Single-Ended Inputs
8.2 Typical Applications
8.2.1 ADS7828-Q1 With Current Shunt Monitor
5V
Shunt Resistor
Load
5V
0.1 µF
3.3 V
INA214-Q1
REF
VIN–
IN+
2
I C
ADS7828 -Q1
+
VIN+
OUT
IN–
Figure 25. ADS7828-Q1 With Current Shunt Monitor
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Typical Applications (continued)
8.2.1.1 Design Requirements
For this design example, the ADS7828-Q1 device is paired with a current shunt monitor. Bi-directional current
monitoring is required when there is both charging and discharging. The requirements for this example are as
follows:
• Voltage across current shunt varies –15 mV to 15 mV
• 5-V supply
• 3.3-V rail available as reference
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Part Selection
The INA214-Q1 device was selected because of the low offset and zero drift of the device. The ADS7828-Q1
device has a low noise floor, so it can support more of the gain. For this reason, the lowest gain option was
selected from the INA21x-Q1 family. The INA214-Q1 device has a gain of 50.
8.2.1.2.2 Full-Scale Differential Range
First, determine the full-scale differential range into the ADS7828-Q1 device.
Vfs = VINdiff ´ GINA214
(1)
Vfs = ±15mV ´ 100
(2)
Vfs = ±1.5V
(3)
8.2.1.2.3 Circuit Implementation
Because the ADS7828-Q1 device has a differential input, connect the reference voltage of the INA214-Q1 device
to the negative input terminal of the ADS7828-Q1 device. Because bi-directional current sensing is required in
this application, VREF must be chosen so that:
VREF >
Vfs
2
(4)
V
VREF < Vsup ply - fs
2
where
•
Vfs = 3 V
(5)
A 3.3-V reference is used for this example. Because the ADS7828-Q1 device is a differential input ADC, a
resistive divider can be used to generate the reference voltage because impedance effects on the INA214-Q1
device is canceled out by the ADS7828-Q1 device.
8.2.1.3 Application Curve
4500
4000
ADC Output Code
3500
3000
2500
2000
1500
1000
500
0
-0.02
-0.01
0
0.01
Differential Input Voltage to INA213-Q1 (V)
0.02
D001
Figure 26. ADC Code vs Voltage Across Current-Shunt Resistor in Bi-Directional Current Sensing
Application
26
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9 Power Supply Recommendations
The device requires only one power supply, VDD, which can have an input voltage between 2.7 V and 5.0 V.
The value of VDD affects the input voltage range and the digital logic high and low levels. A decoupling capacitor
should be placed close to the VDD pin. TI recommends a value of at least 0.1 µF.
10 Layout
10.1 Layout Guidelines
For optimum performance, care should be taken with the physical layout of the ADS7828 circuitry. The basic
SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections,
and digital inputs that occur just prior to latching the output of the analog comparator. Therefore, during any
single conversion for an "n-bit" SAR converter, there are n "windows" in which large external transient voltages
can easily affect the conversion result. Such glitches might originate from switching power supplies, nearby
digital logic, and high-power devices.
With this in mind, power to the ADS7828 should be clean and well-bypassed. A 0.1-μF ceramic bypass capacitor
should be placed as close to the device as possible. A 1-μF to 10-μF capacitor may also be needed if the
impedance of the connection between +VDD and the power supply is high.
The ADS7828 architecture offers no inherent rejection of noise or voltage variation in regards to using an
external reference input. This is of particular concern when the reference input is tied to the power supply. Any
noise and ripple from the supply will appear directly in the digital results. While high-frequency noise can be
filtered out, voltage variation due to line frequency (50 Hz or 60 Hz) can be difficult to remove.
The GND pin should be connected to a clean ground point. In many cases, this will be the "analog" ground.
Avoid connections that are too near the grounding point of a microcontroller or digital signal processor. The ideal
layout will include an analog ground plane dedicated to the converter and associated analog circuitry.
10.2 Layout Example
Place power supply
capacitor as close as
possible to VDD pin
CH0
+VDD
CH1
SDA
CH2
SCL
CH3
A1
ADS7828-Q1
CH4
A0
CH5
COM
CH6
REF
CH7
GND
= Via to ground plane
Figure 27. Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• ADS7823—20 EVM, SLAU124
• Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to the Input,
SBAA173
• Determining Minimum Acquisition Times for SAR ADCs When a DC Voltage is Applied to the Input, SBAA178
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ADS7828EIPWRQ1
ACTIVE
TSSOP
PW
16
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS
7828EI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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