ADS7830IPWT

ADS7830 ADS 7830 ® SBAS302 – DECEMBER 2003 8-Bit, 8-Channel Sampling ANALOG-TO-DIGITAL CONVERTER with I2C™ Interface FEATURES q q q q q q q 70kHz SAMPLING RATE ±0.5LSB INL/DNL 8 BITS NO MISSING CODES 4 DIFFERENTIAL/8 SINGLE-ENDED INPUTS 2.7V TO 5V OPERATION BUILT-IN 2.5V REFERENCE/BUFFER SUPPORTS ALL THREE I2C MODES: Standard, Fast, and High-Speed q LOW POWER: 180µW (Standard Mode) 300µW (High-Speed Mode) 675µW (Fast Mode) q DIRECT PIN COMPATIBLE WITH ADS7828 q TSSOP-16 PACKAGE APPLICATIONS q q q q q VOLTAGE-SUPPLY MONITORING ISOLATED DATA ACQUISITION TRANSDUCER INTERFACE BATTERY-OPERATED SYSTEMS REMOTE DATA ACQUISITION DESCRIPTION The ADS7830 is a single-supply, low-power, 8-bit data acquisition device that features a serial I2C interface and an 8-channel multiplexer. The Analog-to-Digital (A/D) converter features a sample-and-hold amplifier and internal, asynchronous clock. The combination of an I2C serial, 2-wire interface and micropower consumption makes the ADS7830 ideal for applications requiring the A/D converter to be close to the input source in remote locations and for applications requiring isolation. The ADS7830 is available in a TSSOP-16 package. CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM S/H Amp Comparator CDAC Serial Interface SDA SCL A0 A1 8-Channel MUX SAR 2.5V VREF REFIN/REFOUT Buffer Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003, Texas Instruments Incorporated www.ti.com ABSOLUTE MAXIMUM RATINGS(1) +VDD to GND ........................................................................ –0.3V to +6V Digital Input Voltage to GND ................................. –0.3V to +VDD + 0.3V Operating Temperature Range ...................................... –40°C to +105°C Storage Temperature Range ......................................... –65°C to +150°C Junction Temperature (TJ max) .................................................... +150°C TSSOP Package Power Dissipation .................................................... (TJ max – TA)/θJA θJA Thermal Impedance ........................................................ 240°C/W Lead Temperature, Soldering Vapor Phase (60s) ............................................................ +215°C Infrared (15s) ..................................................................... +220°C NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION(1) MAXIMUM INTEGRAL LINEARITY ERROR (LSB) ±0.5 SPECIFIED TEMPERATURE RANGE –40°C to +85°C PRODUCT ADS7830I PACKAGE-LEAD TSSOP-16 PACKAGE DESIGNATOR PW ORDERING NUMBER ADS7830IPWT ADS7830IPWR TRANSPORT MEDIA, QUANTITY Tape and Reel, 250 Tape and Reel, 2500 " " " " " NOTE: (1) For the most current package and ordering information, refer to our web site at www.ti.com. PIN CONFIGURATION Top View TSSOP PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 NAME CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 GND COM A0 A1 SCL SDA +VDD DESCRIPTION Analog Input Channel 0 Analog Input Channel 1 Analog Input Channel 2 Analog Input Channel 3 Analog Input Channel 4 Analog Input Channel 5 Analog Input Channel 6 Analog Input Channel 7 Analog Ground Common to Analog Input Channel Slave Address Bit 0 Slave Address Bit 1 Serial Clock Serial Data Power Supply, 3.3V Nominal CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 1 2 3 4 ADS7830 5 6 7 8 16 15 14 13 12 11 10 9 +VDD SDA SCL A1 A0 COM REFIN / REFOUT GND 10 REFIN / REFOUT Internal +2.5V Reference, External Reference Input 2 www.ti.com ADS7830 SBAS302 ELECTRICAL CHARACTERISTICS: +2.7V At TA = –40°C to +85°C, +VDD = +2.7V, VREF = +2.5V, SCL Clock Frequency = 3.4MHz (High-Speed Mode), unless otherwise noted. ADS7830E PARAMETER ANALOG INPUT Full-Scale Input Scan Absolute Input Range Capacitance Leakage Current SYSTEM PERFORMANCE No Missing Codes Integral Linearity Error Differential Linearity Error Offset Error Offset Error Match Gain Error Gain Error Match Noise Power-Supply Rejection SAMPLING DYNAMICS Throughput Frequency High-Speed Mode: SCL = 3.4MHz Fast Mode: SCL = 400kHz Standard Mode, SCL = 100kHz 5 VIN = VIN = VIN = VIN = 2.5VPP 2.5VPP 2.5VPP 2.5VPP at at at at 1kHz 1kHz 1kHz 1kHz –72 50 49 68 90 2.475 Internal Reference ON Internal Reference OFF Internal Reference ON, SCL and SDA pulled HIGH 0.05 High-Speed Mode: SCL= 3.4MHz 1 20 CMOS +VDD • 0.7 –0.3 Minimum 3mA Sink Current VIH = +VDD +0.5 VIL = -0.3 +VDD + 0.5 +VDD • 0.3 0.4 10 Straight Binary 10010 Specified Performance High-Speed Mode: SCL = 3.4MHz Fast Mode: SCL = 400kHz Standard Mode, SCL = 100kHz High-Speed Mode: SCL = 3.4MHz Fast Mode: SCL = 400kHz Standard Mode, SCL = 100kHz High-Speed Mode: SCL = 3.4MHz Fast Mode: SCL = 400kHz Standard Mode, SCL = 100kHz SCL Pulled HIGH, SDA Pulled HIGH 2.7 225 100 60 675 300 180 70 25 6 400 –40 3.6 320 Binary V µA µA µA µW µW µW µA µA µA nA °C V V V µA µA 2.5 15 110 1 850 2.525 8 ±0.1 ±0.1 +0.5 ±0.05 ±0.1 ±0.05 100 72 ±0.5 ±0.5 +1 ±0.25 ±0.5 ±0.25 CONDITIONS Positive Input - Negative Input Positive Input Negative Input MIN 0 –0.2 –0.2 25 ±1 TYP MAX VREF +VDD + 0.2 +0.2 UNITS V V V pF µA Bits LSB (1) LSB LSB LSB LSB LSB µVRMS dB kSPS(2) kSPS kSPS µs dB (3) dB dB dB dB V ppm/°C Ω GΩ µA V GΩ µA 70 10 2.5 Conversion Time AC ACCURACY Total Harmonic Distortion Signal-to-Ratio Signal-to-(Noise+Distortion) Ratio Spurious-Free Dynamic Range Isolation Channel-to-Channel VOLTAGE REFERENCE OUTPUT Range Internal Reference Drift Output Impedance Quiescent Current VOLTAGE REFERENCE INPUT Range Resistance Current Drain DIGITAL INPUT/OUTPUT Logic Family Logic Levels: VIH VIL VOL Input Leakage: IIH IIL Data Format ADS7830 HARDWARE ADDRESS POWER-SUPPLY REQUIREMENTS Power-Supply Voltage, +VDD Quiescent Current VDD -10 Power Dissipation 1000 Power-Down Mode w/Wrong Address Selected Full Power-Down TEMPERATURE RANGE Specified Performance 3000 85 NOTES: (1) LSB means least significant bit. When VREF = 2.5V, 1LSB is 9.8mV. (2) kSPS means kilo samples-per-second. (3) THD measured out to the 9th-harmonic. ADS7830 SBAS302 3 www.ti.com ELECTRICAL CHARACTERISTICS: +5V At TA = –40°C to +85°C, +VDD = +5.0V, VREF = External +5.0V, SCL Clock Frequency = 3.4MHz (High-Speed Mode), unless otherwise noted. ADS7830E PARAMETER ANALOG INPUT Full-Scale Input Scan Absolute Input Range Capacitance Leakage Current SYSTEM PERFORMANCE No Missing Codes Integral Linearity Error Differential Linearity Error Offset Error Offset Error Match Gain Error Gain Error Match Noise Power-Supply Rejection SAMPLING DYNAMICS Throughput Frequency High-Speed Mode: SCL = 3.4MHz Fast Mode: SCL = 400kHz Standard Mode, SCL = 100kHz 5 VIN = VIN = VIN = VIN = 5VPP 5VPP 5VPP 5VPP at at at at 1kHz 1kHz 1kHz 1kHz –72 50 49 68 90 2.475 Internal Reference ON Internal Reference OFF Int. Ref. ON, SCL and SDA pulled HIGH 0.05 High-Speed Mode: SCL = 3.4MHz 1 20 CMOS +VDD • 0.7 –0.3 Minimum 3mA Sink Current VIH = +VDD +0.5 VIL = -0.3 +VDD + 0.5 +VDD • 0.3 0.4 10 Straight Binary 10010 Specified Performance High-Speed Mode: SCL = 3.4MHz Fast Mode: SCL = 400kHz Standard Mode, SCL = 100kHz High-Speed Mode: SCL = 3.4MHz Fast Mode: SCL = 400kHz Standard Mode, SCL = 100kHz High-Speed Mode: SCL = 3.4MHz Fast Mode: SCL = 400kHz Standard Mode, SCL = 100kHz SCL Pulled HIGH, SDA Pulled HIGH 4.75 5 750 300 150 3.75 1.5 0.75 400 150 35 400 5.25 1000 Binary V µA µA µA mW mW mW µA µA µA nA °C V V V µA µA 2.5 15 110 1 1300 2.525 8 ±0.1 ±0.1 +0.5 ±0.05 ±0.1 ±0.05 100 72 ±0.5 ±0.5 +1 ±0.25 ±0.5 ±0.25 Positive Input - Negative Input Positive Input Negative Input 0 –0.2 –0.2 25 ±1 VREF +VDD + 0.2 +0.2 V V V pF µA Bits LSB (1) LSB LSB LSB LSB LSB µVRMS dB kSPS(2) kSPS kSPS µs dB (3) dB dB dB dB V ppm/°C Ω GΩ µA V GΩ µA CONDITIONS MIN TYP MAX UNITS 70 10 2.5 Conversion Time AC ACCURACY Total Harmonic Distortion Signal-to-Ratio Signal-to-(Noise+Distortion) Ratio Spurious-Free Dynamic Range Isolation Channel-to-Channel VOLTAGE REFERENCE OUTPUT Range Internal Reference Drift Output Impedance Quiescent Current VOLTAGE REFERENCE INPUT Range Resistance Current Drain DIGITAL INPUT/OUTPUT Logic Family Logic Levels: VIH VIL VOL Input Leakage: IIH IIL Data Format ADS7830 HARDWARE ADDRESS POWER-SUPPLY REQUIREMENTS Power-Supply Voltage, +VDD Quiescent Current VDD -10 Power Dissipation 5 Power-Down Mode w/Wrong Address Selected Full Power-Down TEMPERATURE RANGE Specified Performance 3000 85 –40 NOTES: (1) LSB means Least Significant Bit. When VREF = 5.0V, 1LSB is 19.5mV. (2) kSPS means kilo samples-per-second. (3) THD measured out to the 9th-harmonic. 4 www.ti.com ADS7830 SBAS302 TIMING DIAGRAM SDA tBUF tLOW tR tF tHD; STA tSP SCL tHD; STA tSU; STA tHD; DAT STOP START tSU; STO tHIGH tSU; DAT REPEATED START TIMING CHARACTERISTICS(1) At TA = –40°C to +85°C, +VDD = +2.7V, unless otherwise noted. PARAMETER SCL Clock Frequency SYMBOL fSCL CONDITIONS Standard Mode Fast Mode High-Speed Mode, CB = 100pF max High-Speed Mode, CB = 400pF max Standard Mode Fast Mode Standard Mode Fast Mode High-Speed Mode Standard Mode Fast Mode High-Speed Mode, CB = 100pF max(2) High-Speed Mode, CB = 400pF max(2) Standard Mode Fast Mode High-Speed Mode, CB = 100pF max(2) High-Speed Mode, CB = 400pF max(2) Standard Mode Fast Mode High-Speed Mode Standard Mode Fast Mode High-Speed Mode Standard Mode Fast Mode High-Speed Mode, CB = 100pF max(2) High-Speed Mode, CB = 400pF max(2) Standard Mode Fast Mode High-Speed Mode, CB = 100pF max(2) High-Speed Mode, CB = 400pF max(2) Standard Mode Fast Mode High-Speed Mode, CB = 100pF max(2) High-Speed Mode, CB = 400pF max(2) Standard Mode Fast Mode High-Speed Mode, CB = 100pF max(2) High-Speed Mode, CB = 400pF max(2) 4.7 1.3 4.0 600 160 4.7 1.3 160 320 4.0 600 60 120 4.7 600 160 250 100 10 0 0 0(3) 0(3) 20 + 0.1CB 10 20 20 + 0.1CB 10 20 20 + 0.1CB 10 20 3.45 0.9 70 150 1000 300 40 80 1000 300 80 160 300 300 40 80 MIN MAX 100 400 3.4 1.7 UNITS kHz kHz MHz MHz µs µs µs ns ns µs µs ns ns µs ns ns ns µs ns ns ns ns ns µs µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns Bus Free Time Between a STOP and START Condition Hold Time (Repeated) START Condition LOW Period of the SCL Clock tBUF tHD;STA tLOW HIGH Period of the SCL Clock tHIGH Setup Time for a Repeated START Condition Data Setup Time tSU;STA tSU;DAT Data Hold Time tHD;DAT Rise Time of SCL Signal tRCL Rise Time of SCL Signal After a Repeated START Condition and After an Acknowledge Bit Fall Time of SCL Signal tRCL1 tFCL ADS7830 SBAS302 5 www.ti.com TIMING CHARACTERISTICS(1) (Cont.) At TA = –40°C to +85°C, +VDD = +2.7V, unless otherwise noted. PARAMETER Rise Time of SDA Signal SYMBOL tRDA CONDITIONS Standard Mode Fast Mode High-Speed Mode, CB = 100pF max(2) High-Speed Mode, CB = 400pF max(2) Standard Mode Fast Mode High-Speed Mode, CB = 100pF max(2) High-Speed Mode, CB = 400pF max(2) Standard Mode Fast Mode High-Speed Mode MIN 20 + 0.1CB 10 20 20 + 0.1CB 10 20 4.0 600 160 400 Fast Mode High-Speed Mode Standard Mode Fast Mode High-Speed Mode Standard Mode Fast Mode High-Speed Mode 0.2VDD 50 10 MAX 1000 300 80 160 300 300 80 160 UNITS ns ns ns ns ns ns ns ns µs ns ns pF ns ns V Fall Time of SDA Signal tFDA Setup Time for STOP Condition tSU;STO Capacitive Load for SDA and SCL Line Pulse Width of Spike Suppressed Noise Margin at the HIGH Level for Each Connected Device (Including Hysteresis) Noise Margin at the LOW Level for Each Connected Device (Including Hysteresis) CB tSP VNH VNL 0.1VDD V NOTES: (1) All values referred to VIHMIN and VILMAX levels. (2) For bus line loads CB between 100pF and 400pF the timing parameters must be linearly interpolated. (3) A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time. 6 www.ti.com ADS7830 SBAS302 TYPICAL CHARACTERISTICS TA = +25°C, VDD = +2.7V, VREF = External +2.5V, fSAMPLE = 50kHz, unless otherwise noted. FFT vs FREQUENCY 0 −20 0.5 0.4 0.3 0.2 ILE (LSB) INTEGRAL LINEARITY ERROR vs CODE (2.5V Internal Reference) Amplitude (dB) −40 −60 −80 −100 0 10 Frequency (kHz) 20 25 0.1 0 −0.1 −0.2 −0.3 −0.4 −0.5 0 64 128 Output Code 192 255 DIFFERENTIAL LINEARITY ERROR vs CODE (2.5V Internal Reference) 0.5 0.4 0.3 0.2 ILE (LSB) ILE (LSB) INTEGRAL LINEARITY ERROR vs CODE (2.5V External Reference) 0.5 0.4 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 −0.5 0.1 0 −0.1 −0.2 −0.3 −0.4 −0.5 0 64 128 Output Code 192 255 0 64 128 Output Code 192 255 DIFFERENTIAL LINEARITY ERROR vs CODE (2.5V External Reference) 0.5 0.4 Delta from 25°C (LSB) CHANGE IN OFFSET vs TEMPERATURE 0.10 0.3 0.2 ILE (LSB) 0.05 0.1 0 −0.1 −0.2 −0.3 −0.4 −0.5 0 64 128 Output Code 192 255 0 −0.05 −0.10 −50 −25 0 25 Temperature (°C) 50 75 100 ADS7830 SBAS302 7 www.ti.com TYPICAL CHARACTERISTICS (Cont.) TA = +25°C, VDD = +2.7V, VREF = External +2.5V, fSAMPLE = 50kHz, unless otherwise noted. CHANGE IN GAIN vs TEMPERATURE 0.10 2.51875 2.51250 INTERNAL REFERENCE vs TEMPERATURE Delta from 25°C (LSB) Internal Reference (V) −50 −25 0 25 Temperature (°C) 50 75 100 0.05 2.50625 2.50000 2.49375 2.48750 0 −0.05 −0.10 2.48125 –50 –25 0 25 Temperature (°C) 50 75 100 POWER-DOWN SUPPLY CURRENT vs TEMPERATURE 750 600 400 350 Supply Current (µA) 300 250 200 150 100 –50 –25 0 25 50 75 100 125 –50 SUPPLY CURRENT vs TEMPERATURE Supply Current (nA) 450 300 150 0 –150 Temperature (°C) –25 0 25 Temperature (°C) 50 75 100 SUPPLY CURRENT vs I2C BUS RATE 300 250 Supply Current (µA) 200 150 100 50 0 10 100 I2C 1k Bus Rate (KHz) 10k 8 www.ti.com ADS7830 SBAS302 THEORY OF OPERATION The ADS7830 is a classic Successive Approximation Register (SAR) A/D converter. The architecture is based on capacitive redistribution which inherently includes a sampleand-hold function. The converter is fabricated on a 0.6µ CMOS process. The ADS7830 core is controlled by an internally generated free-running clock. When the ADS7830 is not performing conversions or being addressed, it keeps the A/D converter core powered off, and the internal clock does not operate. The simplified diagram of input and output for the ADS7830 is shown in Figure 1. range for a 0V to +VDD analog input. This external reference can be as low as 50mV. As the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. This is often referred to as the LSB (least significant bit) size and is equal to the reference voltage divided by 256. This means that any offset or gain error inherent in the A/D converter will appear to increase, in terms of LSB size, as the reference voltage is reduced. The noise inherent in the converter will also appear to increase with lower LSB size. With a 2.5V reference, the internal noise of the converter typically contributes only 0.02LSB peak-topeak of potential error to the output code. When the external reference is 50mV, the potential error contribution from the internal noise will be 50 times larger—1LSB. The errors due to the internal noise are Gaussian in nature and can be reduced by averaging consecutive conversion results. ANALOG INPUT When the converter enters the hold mode, the voltage on the selected CHx pin is captured on the internal capacitor array. The input current on the analog inputs depends on the conversion rate of the device. During the sample period, the source must charge the internal sampling capacitor (typically 25pF). After the capacitor has been fully charged, there is no further input current. The amount of charge transfer from the analog source to the converter is a function of conversion rate. DIGITAL INTERFACE The ADS7830 supports the I2C serial bus and data transmission protocol, in all three defined modes: standard, fast, and high-speed. A device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the message is called a “master.” The devices that are controlled by the master are “slaves.” The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The ADS7830 operates as a slave on the I2C bus. Connections to the bus are made via the open-drain I/O lines SDA and SCL. REFERENCE The ADS7830 can operate with its internal 2.5V reference or an external reference. When using a +2.7V supply, the internal 2.5V reference will provide full dynamic range for a 0V to +VDD analog input. If a +5V supply is used, an external 5V reference is required in order to provide full dynamic +2.7V to +3.6V 5Ω + 1µF to 10µF 0.1µF REFIN/ REFOUT VDD 2kΩ + 1µF to 10µF 2kΩ CH0 CH1 CH2 ADS7828 CH3 CH4 CH5 CH6 CH7 COM SDA SCL A0 A1 GND Microcontroller FIGURE 1. Simplified I/O of the ADS7830. ADS7830 SBAS302 9 www.ti.com The following bus protocol has been defined (as shown in Figure 2): • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus Not Busy: Both data and clock lines remain HIGH. Start Data Transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop Data Transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data Valid: The state of the data line represents valid data, when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth-bit. Within the I2C bus specifications a standard mode (100kHz clock rate), a fast mode (400kHz clock rate), and a highspeed mode (3.4MHz clock rate) are defined. The ADS7830 works in all three modes. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. Figure 2 details how data transfer is accomplished on the I2C bus. Depending upon the state of the R/W bit, two types of data transfer are possible: 1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after the slave address and each received byte. 2. Data transfer from a slave transmitter to a master receiver. The first byte, the slave address, is transmitted by the master. The slave then returns an acknowledge bit. Next, a number of data bytes are transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not-acknowledge is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus will not be released. The ADS7830 may operate in the following two modes: • Slave Receiver Mode: Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. • Slave Transmitter Mode: The first byte (the slave address) is received and handled as in the slave receiver mode. However, in this mode the direction bit will indicate that the transfer direction is reversed. Serial data is transmitted on SDA by the ADS7830 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. SDA MSB Slave Address R/W Direction Bit Acknowledgement Signal from Receiver SCL 1 2 6 7 8 9 ACK START Condition 1 2 3-8 8 9 ACK Repeated If More Bytes Are Transferred STOP Condition or Repeated START Condition Acknowledgement Signal from Receiver FIGURE 2. Basic Operation of the ADS7830. 10 www.ti.com ADS7830 SBAS302 Address Byte MSB 1 6 0 5 0 4 1 3 0 2 A1 1 A0 LSB R/W Command Byte MSB SD 6 C2 5 C1 4 C0 3 PD1 2 PD0 1 X LSB X The address byte is the first byte received following the START condition from the master device. The first five bits (MSBs) of the slave address are factory pre-set to 10010. The next two bits of the address byte are the device select bits, A1 and A0. Input pins (A1-A0) on the ADS7830 determine these two bits of the device address for a particular ADS7830. A maximum of four devices with the same pre-set code can therefore be connected on the same bus at one time. The A1-A0 Address Inputs can be connected to VDD or digital ground. The device address is set by the state of these pins upon power-up of the ADS7830. The last bit of the address byte (R/W) defines the operation to be performed. When set to a “1” a read operation is selected; when set to a “0” a write operation is selected. Following the START condition the ADS7830 monitors the SDA bus, checking the device type identifier being transmitted. Upon receiving the 10010 code, the appropriate device select bits, and the R/W bit, the slave device outputs an acknowledge signal on the SDA line. The ADS7830’s operating mode is determined by a command byte which is illustrated above. SD: Single-Ended/Differential Inputs 0: Differential Inputs 1: Single-Ended Inputs C2 - C0: Channel Selections PD1 - 0: Power-Down Selection X: Unused See Table I for Truth Table. POWER-DOWN SELECTION PD1 0 0 1 1 PD0 0 1 0 1 DESCRIPTION Power Down Between A/D Converter Conversions Internal Reference OFF and A/D Converter ON Internal Reference ON and A/D Converter OFF Internal Reference ON and A/D Converter ON INITIATING CONVERSION Provided the master has write-addressed it, the ADS7830 turns on the A/D converter’s section and begins conversions when it receives BIT 4 of the command byte shown in the Command Byte. If the command byte is correct, the ADS7830 will return an ACK condition. CHANNEL SELECTION CONTROL SD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 C0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CH0 +IN — — — –IN — — — +IN — — — — — — — CH1 –IN — — — +IN — — — — — — — +IN — — — CH2 — +IN — — — –IN — — — +IN — — — — — — CH3 — –IN — — — +IN — — — — — — — +IN — — CH4 — — +IN — — — –IN — — — +IN — — — — — CH5 — — –IN — — — +IN — — — — — — — +IN — CH6 — — — +IN — — — –IN — — — +IN — — — — CH7 — — — –IN — — — +IN — — — — — — — +IN COM — — — — — — — — –IN –IN –IN –IN –IN –IN –IN –IN TABLE I. Channel Selection Control Addressed by Command BYTE. ADS7830 SBAS302 11 www.ti.com READING DATA Data can be read from the ADS7830 by read-addressing the part (LSB of address byte set to 1) and receiving the transmitted byte. Converted data can only be read from the ADS7830 once a conversion has been initiated as described in the preceding section. Each 8-bit data word is returned in one byte, as shown below, where D7 is the MSB of the data word, and D0 is the LSB. MSB DATA D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 LSB D0 modes. It may be desirable to remain in HS mode after reading a conversion; to do this, issue a repeated START instead of a STOP at the end of the read sequence, since a STOP causes the part to return to F/S mode. LAYOUT For optimum performance, care should be taken with the physical layout of the ADS7830 circuitry. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. Therefore, during any single conversion for an “n-bit” SAR converter, there are n “windows” in which large external transient voltages can easily affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, and high-power devices. With this in mind, power to the ADS7830 should be clean and well-bypassed. A 0.1µF ceramic bypass capacitor should be placed as close to the device as possible. A 1µF to 10µF capacitor may also be needed if the impedance of the connection between +VDD and the power supply is high. The ADS7830 architecture offers no inherent rejection of noise or voltage variation in regards to using an external reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply will appear directly in the digital results. While high-frequency noise can be filtered out, voltage variation due to line frequency (50Hz or 60Hz) can be difficult to remove. The GND pin should be connected to a clean ground point. In many cases, this will be the “analog” ground. Avoid connections that are too near the grounding point of a microcontroller or digital signal processor. The ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry. READING IN F/S MODE Figure 3 describes the interaction between the master and the slave ADS7830 in Fast or Standard (F/S) mode. At the end of reading conversion data the ADS7830 can be issued a repeated START condition by the master to secure bus operation for subsequent conversions of the A/D converter. This would be the most efficient way to perform continuous conversions. READING IN HS MODE High Speed (HS) mode is fast enough that codes can be read out one at a time. In HS mode, there is not enough time for a single conversion to complete between the reception of a repeated START condition and the read-addressing byte, so the ADS7830 stretches the clock after the read-addressing byte has been fully received, holding it LOW until the conversion is complete. See Figure 4 for a typical read sequence for HS mode. Included in the read sequence is the shift from F/S to HS ADC Power-Down Mode S 1 0 0 1 0 A1 A0 W A SD C2 C1 ADC Sampling Mode C0 PD1 PD0 X X A Write-Addressing Byte Command Byte ADC Converting Mode Sr 1 0 0 1 0 A1 A0 R A D7 ADC Power-Down Mode (depending on power-down selection bits) D6 D5 D4 D3 D2 D1 D0 N P See Note (1) Read-Addressing Byte 1 x (8 Bits + not-ack) From Master to Slave From Slave to Master A = acknowledge (SDA LOW) N = not acknowledge (SDA HIGH) S = START Condition P = STOP Condition Sr = repeated START condition W = '0' (WRITE) R = '1' (READ) NOTE: (1) To secure bus operation and loop back to the stage of write-addressing for next conversion, use repeated START. FIGURE 3. Typical Read Sequence in F/S Mode. 12 www.ti.com ADS7830 SBAS302 F/S Mode S 0 0 0 0 1 X X X N HS Mode Master Code HS Mode Enabled ADC Power-Down Mode Sr 1 0 0 1 0 A1 A0 W A SD C2 C1 ADC Sampling Mode C0 PD1 PD0 X X A Write-Addressing Byte Command Byte HS Mode Enabled ADC Converting Mode Sr 1 0 0 1 0 A1 A0 R A SCLH(2) is stretched LOW waiting for data conversion Read-Addressing Byte Return to F/S Mode(1) HS Mode Enabled ADC Power-Down Mode (depending on power-down selection bits) D7 D6 D5 D4 D3 D2 D1 D0 N P 1 x (8 Bits + not-ack) A = acknowledge (SDA LOW) N = not acknowledge (SDA HIGH) S = START Condition P = STOP Condition Sr = repeated START condition From Master to Slave W = '0' (WRITE) R = '1' (READ) From Slave to Master NOTES: (1) To remain in HS mode, use repeated START instead of STOP. (2) SCLH is SCL in HS mode. FIGURE 4. Typical Read Sequence in HS Mode. ADS7830 SBAS302 13 www.ti.com PACKAGE OPTION ADDENDUM www.ti.com 31-Dec-2003 PACKAGING INFORMATION ORDERABLE DEVICE ADS7830IPWR ADS7830IPWT STATUS(1) ACTIVE ACTIVE PACKAGE TYPE TSSOP TSSOP PACKAGE DRAWING PW PW PINS 16 16 PACKAGE QTY 2500 250 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) 14 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,65 14 8 0,30 0,19 0,10 M 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0°– 8° 0,75 0,50 Seating Plane 1,20 MAX 0,15 0,05 0,10 PINS ** DIM A MAX 8 14 16 20 24 28 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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