ADS7832BP

® ADS 783 2 ADS7832 ADS 7832 Autocalibrating, 4-Channel, 12-Bit ANALOG-TO-DIGITAL CONVERTER FEATURES q PIN COMPATIBLE TO ADC7802 AND ADS7803 q SINGLE SUPPLY: +5V OR +3.3V q LOW POWER: 14mW plus Power Down q SIGNAL-TO-(NOISE + DISTORTION) RATIO OVER TEMPERATURE: 69dB min with fIN = 1kHz 66dB min with fIN = 50kHz q FAST CONVERSION TIME: 8.5µs Including Acquisition (117kHz Sampling Rate) q FOUR-CHANNEL INPUT MULTIPLEXER q AUTOCAL: No offset or Gain Adjust Required DESCRIPTION The ADS7832 is a monolithic CMOS 12-bit analogto-digital converter with internal sample/hold and fourchannel multiplexer. It is designed and tested for full dynamic performance with input signals to 50kHz. The 5V single-supply requirements and standard CS, RD, and WR control signals make the part easy to use in microprocessor applications. Conversion results are available in two bytes through an 8-bit three-state output bus. The ADS7832 is available in a 28-pin plastic DIP and 28-lead PLCC, fully specified for operation over the industrial –40°C to +85°C temperature range. A0 A1 Address Latch and Decoder Calibration Microcontroller and Memory Clock Control Logic CS RD WR SFR AIN0 AIN1 AIN2 AIN3 Analog Multiplexer Capacitor Array Sampling ADC Three-State Input/Output BUSY 8-Bit Data Bus VREF+ VREF– International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1996 Burr-Brown Corporation PDS-1332B Printed in U.S.A. April, 1998 SPECIFICATIONS ADS7832 Electrical Specifications with 3.3V Supply VA = VD = VREF+ = 3.3V ±10%; VREF– = AGND = DGND = 0V; CLK = 1MHz external, TA = –40°C to +85°C, after calibration at any temperature, unless otherwise specified. ADS7832BP/ADS7832BN PARAMETER RESOLUTION ANALOG INPUT Voltage Input Range Input Capacitance On State Bias Current Off State Bias Current On Resistance Multiplexer Off Resistance Multiplexer Channel Separation REFERENCE INPUT For Specified Performance: VREF+ VREF– For Derated Performance(2): VREF+ VREF– Input Reference Current THROUGHPUT SPEED Conversion Time With External Clock (Including Multiplexer Settling Time and Acquisition Time) With Internal Clock Using Recommended Clock Components Slew Rate Multiplexer Settling Time to 1/2 LSB Multiplexer Access Time SAMPLING DYNAMICS Full Power Bandwidth Aperture Jitter Aperture Delay DC ACCURACY Integral Nonlinearity, All Channels SFR D2 LOW SFR D2 HIGH, Internal Clock or Sampling Command Synchronous to External Clock SFR D2 HIGH, Sampling Command Asynchronous to External Clock ±0.5 ±0.6 ±0.75 Guaranteed All Channels Between Calibration Cycles All Channels SFR D2 LOW SFR D2 HIGH, Internal Clock or Sampling Command Synchronous to External Clock SFR D2 HIGH, Sampling Command Asynchronous to External Clock Between Calibration Cycles SFR D2 LOW SFR D2 HIGH, Internal Clock or Sampling Command Synchronous to External Clock SFR D2 HIGH, Sampling Command Asynchronous to External Clock SFR D2 LOW SFR D2 HIGH, Internal Clock or Sampling Command Synchronous to External Clock SFR D2 HIGH, Sampling Command Asynchronous to External Clock VD = VA = +3.3V ±10% (without recalibration) ±0.2 ±0.5 LSB ppm/°C LSB LSB LSB ±0.75 LSB(4) LSB LSB LSB VA = VD = VREF+ = 3.0V 0 40 TA = +25°C TA = –40°C to +85°C 400 10 0.5 VA 0 (VREF+) – (VREF–) ≥ 2.5V 2.5 0 100 VA 0.5 200 100 10 100 VREF+ V pF nA nA nA Ω MΩ LSB V V V V µA CONDITIONS MIN TYP MAX 12 UNITS Bits FIN = 1kHz, VREF+ = 3.0V CLK = 1MHz CLK = 500kHz TA = +25°C TA = –40°C to +85°C 17 34 30 30 2 0.5 20 2 5 5 µs µs µs µs V/µs µs ns MHz ps µs ns –3dB SRF D2 LOW(3) SFR D2 HIGH Differential Nonlinearity No Missing Codes Gain Error Gain Error Drift Offset Error ±1 ±4 ±0.75 Offset Error Drift ±0.2 ±0.5 ±1 ±0.25 ±0.5 ±1 ±0.125 ppm/°C ppm/°C ppm/°C LSB LSB LSB LSB Channel-to-Channel Mismatch Power Supply Sensitivity AC ACCURACY Signal-to-(Noise + Distortion) Ratio Total Harmonic Distortion Signal-to-Noise Ratio Spurious Free Dynamic Range fIN = 1kHz fIN = 50kHz fIN = 50kHz fIN = 50kHz fIN = 1kHz fIN = 50kHz 69 66 71 69 –75 70 85 82 dB(1) dB dB dB dB dB ® ADS7832 2 SPECIFICATIONS (CONT) ADS7832 Electrical Specifications with 3.3V Supply VA = VD = VREF+ = 3.3V ±10%; VREF– = AGND = DGND = 0V; CLK = 1MHz external, TA = –40°C to +85°C, after calibration at any temperature, unless otherwise specified. ADS7832BP/ADS7832BN PARAMETER DIGITAL INPUTS Voltage Levels: VIL VIH Current Levels: IIL IIL IIH IIH IIH IIH DIGITAL OUTPUTS Data Format Data Coding VOL VOH Leakage Current Output Capacitance CALIBRATION TIMING Calibration Cycle Calibration Cycle DIGITAL TIMING Bus Access Time Bus Relinquish Time POWER SUPPLIES Supply Voltage for Specified Performance: VA VD Supply Current: IA ID Power Dissipation TEMPERATURE RANGE Specification Storage Tested at 3.0V Tested at 3.0V 3 3 3.3 3.3 2.5 300 7.5 50 CONDITIONS MIN TYP MAX UNITS –0.3 0.7 • VD CAL (Internal Pull-Up) All Other Inputs SFR (Internal Pull-Down) CLK All Other Inputs Power Down Mode (SFR D3 HIGH) 10 +0.8 VD +0.3V ±10 90 1.5 ±10 ±100 V V µA µA µA mA µA nA ISINK = 1.6mA ISOURCE = 200µA High-Z State, VOUT = 0V to VD High-Z State Power On or Power Failure During Normal Operation Parallel 12 Bits in Two Bytes Straight Binary 0.2 • VD 0.8 • VD ±1 4 37393 4625 83 83 V V µA pF Clock Cycles Clock Cycles ns ns V V mA µA mW µW °C °C 3 500 Power Up Mode or During Conversion Power Down Mode, No Clock Running –40 –65 +85 +150 T These specifications need to be added based on performance of final silicon. NOTES: (1) All specifications in dB are referred to a full-scale input range. (2) Over this range, total error will typically not exceed ±1LSB. (3) In this mode, the ADS7832 acquires the input signal for five clock cycles after a start command, before the input is held and conversion begins. (4) LSB means Least Significant Bit. For a 0V to 5V input range, one LSB is 1.22mV. For a 0V to 2.5V input range, one LSB is 610µV. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 ADS7832 SPECIFICATIONS ADS7832 Electrical Specifications with 5V Supply VA = VD = 5V ±10%; VREF+ = 5.0V; VREF– = AGND = DGND = 0V; CLK = 1MHz external 50% ±2% Duty Cycle, TA = –40°C to +85°C, after calibration at any temperature, unless otherwise specified. ADS7832BP/ADS7832BN PARAMETER RESOLUTION ANALOG INPUT Voltage Input Range Input Capacitance On State Bias Current Off State Bias Current On Resistance Multiplexer Off Resistance Multiplexer Channel Separation REFERENCE INPUT For Specified Performance: VREF+ VREF– For Derated Performance(2): VREF+ VREF– Input Reference Current THROUGHPUT SPEED Conversion Time With External Clock (Including Multiplexer Settling Time and Acquisition Time) With Internal Clock Using Recommended Clock Components Slew Rate Multiplexer Settling Time to 1/2 LSB Multiplexer Access Time SAMPLING DYNAMICS Full Power Bandwidth Aperture Jitter Aperture Delay DC ACCURACY Integral Nonlinearity, All Channels SFR D2 LOW SFR D2 HIGH, Internal Clock or Sampling Command Synchronous to External Clock SFR D2 HIGH, Sampling Command Asynchronous to External Clock ±0.5 ±0.6 ±0.75 Guaranteed All Channels Between Calibration Cycles All Channels SFR D2 LOW SFR D2 HIGH, Internal Clock or Sampling Command Synchronous to External Clock SFR D2 HIGH, Sampling Command Asynchronous to External Clock Between Calibration Cycles SFR D2 LOW SFR D2 HIGH, Internal Clock or Sampling Command Synchronous to External Clock SFR D2 HIGH, Sampling Command Asynchronous to External Clock SFR D2 LOW SFR D2 HIGH, Internal Clock or Sampling Command Synchronous to External Clock SFR D2 HIGH, Sampling Command Asynchronous to External Clock VD = VA = +5V ±10% (without recalibration) ±0.2 ±0.50 LSB ppm/°C LSB LSB LSB ±0.75 LSB(4) LSB LSB LSB VD = VA = VREF+ = 5V TA = +25°C TA = –40°C to +85°C 400 10 0.5 0 40 100 10 100 CONDITIONS MIN TYP MAX 12 5 UNITS Bits V pF nA nA nA Ω MΩ LSB FIN = 1kHz, VD = VA = VREF+ = 5V VREF = VA = 5V VA 0 (VREF+) – (VREF–) ≥ 2.5V 2.5 0 100 CLK = 2MHz CLK = 1MHz CLK = 500kHz TA = +25°C TA = –40°C to +85°C 2 0.5 20 –3dB SRF D2 LOW(3) SFR D2 HIGH 4 10 2.5 5 VA 1 200 8.5 17 34 30 30 V V V V µA µs µs µs µs µs mV/µs µs ns MHz ps µs ns Differential Nonlinearity No Missing Codes Gain Error Gain Error Drift Offset Error ±1 ±4 ±0.75 Offset Error Drift ±0.2 ±0.5 ±1 ±0.25 ±0.5 ±1.0 ±0.125 ppm/°C ppm/°C ppm/°C LSB LSB LSB LSB Channel-to-Channel Mismatch Power Supply Sensitivity ® ADS7832 4 SPECIFICATIONS (CONT) ADS7832 Electrical Specifications with 5V Supply VA = VD = 5V ±10%; VREF+ = 5V; VREF– = AGND = DGND = 0V; CLK = 1MHz external 50% ±2% Duty Cycle, TA = –40°C to +85°C, after calibration at any temperature, unless otherwise specified. ADS7832BP/ADS7832BN PARAMETER AC ACCURACY Signal-to-(Noise + Distortion) Ratio Total Harmonic Distortion Signal-to-Noise Ratio Spurious Free Dynamic Range DIGITAL INPUTS Voltage Levels: VIL VIH VIL VIH Current Levels: IIL IIL IIH IIH IIH IIH DIGITAL OUTPUTS Data Format Data Coding VOL VOH Leakage Current Output Capacitance CALIBRATION TIMING Calibration Cycle Calibration Cycle DIGITAL TIMING Bus Access Time Bus Relinquish Time POWER SUPPLIES Supply Voltage for Specified Performance: VA VD Supply Current: IA ID Power Dissipation TEMPERATURE RANGE Specification Storage Tested at 5.5V Tested at 5.5V Tested at 5.5V Tested at 5.5V Power Up Mode or During Conversion Power Down Mode, No Clock Running –40 –65 5 5 2.5 300 14 50 fIN = 1kHz fIN = 50kHz fIN = 50kHz fIN = 50kHz fIN = 1kHz fIN = 50kHz CLK CLK All Others All Others CAL (Internal Pull-Up) All Other Inputs SFR (Internal Pull-Down) CLK All Other Inputs Power Down Mode (SFR D3 HIGH) Parallel 12 Bits in Two Bytes Straight Binary ISINK = 1.6mA ISOURCE = 200µA High-Z State High-Z State Power On or Power Failure During Normal Operation 69 66 71 69 –75 70 85 82 0.8 VD +0.3V 0.8 VD +0.3V 10 ±10 90 1.5 ±10 ±100 dB(1) dB dB dB dB dB V V V V µA µA µA mA µA nA CONDITIONS MIN TYP MAX UNITS –0.3 3.5 –0.3 2.4 0.4 4 ±1 4 37393 4625 83 83 5.5 5.5 5.5 500 V V µA pF Clock Cycles Clock Cycles ns ns V V mA µA mW µW °C °C 85 150 TThese specifications need to be added based on performance of final silicon. NOTES: (1) All specifications in dB are referred to a full-scale input range. (2) Over this range, total error will typically not exceed ±1LSB. (3) In this mode, the ADS7832 acquires the input signal for five clock cycles after a start command, before the input is held and conversion begins. (4) LSB means Least Significant Bit. For a 0V to 5V input range, one LSB is 1.22mV. For a 0V to 2.5V input range, one LSB is 610µV. ® 5 ADS7832 PIN CONFIGURATIONS Top View SFR AIN0 AIN1 AIN2 AIN3 VREF+ VREF– DGND VD 1 2 3 4 5 6 7 8 9 28 VA 27 AGND VA 26 CAL (SHC) 25 A1 24 A0 25 A1 DIP Top View LCC 4 3 2 1 28 27 26 23 CLK 22 BUSY 21 HBE 20 WR 19 CS 18 RD 17 D0 16 D1 15 D2 AIN3 VREF+ VREF– DGND VD 5 24 A0 6 23 CLK 7 22 BUSY 8 21 HBE 9 20 WR 19 CS D7 10 D6 11 D5 12 D4 13 D3 14 D7 10 D6 11 12 13 14 15 16 17 18 D5 D4 D3 D2 D1 D0 PACKAGE /ORDERING INFORMATION MINIMUM SIGNAL-TO-(NOISE + DISTORTION) RATIO, dB 69 69 INTEGRAL NONLINEARITY MAXIMUM LSB ±3/4 ±3/4 SPECIFICATION TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C PACKAGE DRAWING NUMBER(1) 251 215 PRODUCT ADS7832BN ADS7832BP PACKAGE 28-Pin LCC 28-Pin Plastic DIP NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ABSOLUTE MAXIMUM RATINGS VA to Analog Ground ............................................................................. 7V VD to Digital Ground .............................................................................. 7V VA to VD ............................................................................................ ±0.3V Analog Ground to Digital Ground ..................................................... ±0.3V Control Inputs to Digital Ground ................................ –0.3V to VD + 0.3V Analog Input Voltage to Analog Ground .................... –0.3V to VA + 0.3V Maximum Junction Temperature ..................................................... 150°C Internal Power Dissipation ............................................................. 875mW Lead Temperature (soldering, 10s) ............................................... +260°C (soldering, 3s) ................................................ +360°C Thermal Resistance, θJA ............................................................ 75°C/W Maximum Input Current to Any Pin ............................................... ±50mA ESD: Human Body Model .................................................................. 1kV ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ® ADS7832 6 RD CAL (SHC) AGND AIN2 AIN1 AIN0 SFR PIN ASSIGNMENTS PIN # 1 2 to 5 6 7 8 9 10 to 17 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 to 25 NAME SFR AIN0 to AIN3 VREF+ VREF– DGND VD D0 to D7 D7 D6 D5 D4 D3 D2 D1 D0 RD CS WR HBE BUSY CLK A0 to A1 DESCRIPTION Special Function Register. When connected to a microprocessor address pin, allows access to special functions through D0 to D7. If not used, connect to DGND. This pin has an internal pull-down. Analog inputs. Channel 0 to channel 3. Positive voltage reference input. Must be ≤ (VA + 0.3V). Negative voltage reference input. Digital ground. DGND = 0V. Logic supply voltage. Must be ≤ (VA + 0.3V) and applied after VA. Data Bus Input/Output Pins. Normally used to read output data. When SFR is LOW, these function as follows: Data Bit 7 if HBE is LOW; if HBE is HIGH, acts as converter status pin and is HIGH during conversion or calibration, goes LOW after the conversion is completed. (Acts as an inverted BUSY). Data Bit 6 if HBE is LOW; LOW if HBE is HIGH. Data Bit 5 if HBE is LOW; LOW if HBE is HIGH. Data Bit 4 if HBE is LOW; LOW if HBE is HIGH. Data Bit 3 if HBE is LOW; Data Bit 11 (MSB) if HBE is HIGH. Data Bit 2 if HBE is LOW; Data Bit 10 if HBE is HIGH. Data Bit 1 if HBE is LOW; Data Bit 9 if HBE is HIGH. Data Bit 0 (LSB) if HBE is LOW; Data Bit 8 if HBE is HIGH. Read Input. Active LOW; used to read the data outputs in combination with CS and HBE. Chip Select Input. Active LOW. Write Input. Active LOW; used to start a new conversion and to select an analog channel via address inputs A0 and A1 in combination with CS. The minimum WR pulse LOW width is 100ns. High Byte Enable. Used to select high or low data output byte in combination with CS and RD, or to select SFR. BUSY is LOW during conversion or calibration. BUSY goes HIGH after the conversion is completed. Clock Input. For internal or external clock operation. For external clock operation, connect to a 74HC-compatible clock source. For internal clock operation, connect per the clock operation description. Address Inputs. Used to select one of four analog input channels in combination with CS and WR. The address inputs are latched on the rising edge of WR or CS. A1 LOW LOW HIGH HIGH 26 CAL (SHC) A0 LOW HIGH LOW HIGH Selected Channel AIN0 AIN1 AIN2 AIN3 Calibration Input. A calibration cycle is initiated when CAL is LOW. The minimum pulse width of CAL is 100ns. If not used, connect to VD. In this case calibration is only initiated at power on, or with SFR. If D2 of the SFR is programmed HIGH, pin 26 will be an input to control the sample-to-hold timing. A rising edge on pin 26 will switch from sample-mode to hold-mode and initiate a conversion. This pin has an internal pull-up. Analog Ground. AGND = 0V. Analog Supply. Must be ≥ (VD – 0.3V) and ((VREF +) – 0.3V) 27 28 AGND VA ® 7 ADS7832 THEORY OF OPERATION ADS7832 uses the advantages of advanced CMOS technology (logic density, stable capacitors, precision analog switches, and low power consumption) to provide a precise 12-bit analog-to-digital converter with on-chip sampling and four-channel analog-input multiplexer. The input stage consists of an analog multiplexer with an address latch to select from four input channels. The converter stage consists of an advanced successive approximation architecture using charge redistribution on a capacitor network to digitize the input signal. A temperature-stabilized differential auto-zeroing circuit is used to minimize offset errors in the comparator. Linearity errors in the binary weighted main capacitor network are corrected using a capacitor trim network and correction factors stored in on-chip memory. The correction terms are calculated by an on-chip microcontroller during a calibration cycle, initiated either by power-up or by applying an external calibration signal at any time. During conversion, the correct trim capacitors are switched into the main capacitor array as needed to correct the conversion accuracy. With all of the capacitors in both the main array and the trim array on the same chip, excellent stability is achieved, both over temperature and over time. For flexibility, timing circuits include both an internal clock generator and an input for an external clock to synchronize with external systems. Standard control signals and threestate input/output registers simplify interfacing ADS7832 to most micro-controllers, microprocessors or digital storage systems. The on-chip sampling provides excellent dynamic performance for input signals to 50kHz, and has a full-power –3dB bandwidth of 4MHz. Full control over sample-to-hold timing is available for applications where this is critical. Finally, this performance is matched with the low-power advantages of CMOS structures to allow a typical power consumption of 10mW, with a 50µW power down option. +5V NC 1 2 0 –5V Input 3 4 5 +5V + 10µF 10nF 6 7 8 9 BUSY LOW LOW LOW Data Bit 7 Data Bit 6 Data Bit 5 Data Bit 4 10 11 12 13 14 VREF+ VREF– DGND VD D7 D6 D5 D4 D3 CLK BUSY HBE WR CS RD D0 D1 D2 23 22 21 20 19 18 17 16 15 Read Command Data Bit 0 Data Bit 8 (LSB) Data Bit 1 Data Bit 9 Data Bit 2 Data Bit 10 HBE Input HBE Input LOW HIGH BUSY High Byte Enable Command Convert Command SFR AIN0 AIN1 AIN2 AIN3 VA AGND CAL A1 A0 28 27 26 NC 25 24 100kΩ 10nF + 10µF Data Bit 11 Data Bit 3 (MSB) HBE Input HBE Input HIGH LOW FIGURE 1. Basic Operation. approximation conversion takes place during clock cycles 6 through 17. Figures 2 and 3 show the full conversion sequence and the timing to initiate a conversion. A conversion can also be initiated by a rising edge on pin 26, if a HIGH has been written to D2 of the Special Function Register, as discussed below. CALIBRATION A calibration cycle is initiated automatically upon power-up (or after a power failure). Calibration can also be initiated by the user at any time by the rising edge of a minimum 100nswide LOW pulse on the CAL pin (pin 26), or by setting D1 HIGH in the Special Function Register (see SFR section). A calibration command will initiate a calibration cycle, regardless of whether a conversion is in process. During a calibration cycle, convert commands are ignored. Calibration takes 4608 clock cycles, and a normal conversion (17 clock cycles) is added automatically. Thus, at the end of a calibration cycle, there is valid conversion data in the output registers. For maximum accuracy, the supplies and reference need to be stable during the calibration procedure. To ensure that supply voltages have settled and are stable, an internal timer provides a waiting period of 37,393 clock cycles between power-up/power-failure and the start of the calibration cycle. READING DATA Data from the ADS7832 is read in two 8-bit bytes, with the Low byte containing the 8 LSBs of data, and the High byte containing the 4 MSBs of data. The outputs are coded in OPERATION BASIC OPERATION Figure 1 shows the simple circuit required to operate ADS7832 in the Transparent Mode, converting a single input channel. A convert command on pin 20 (WR) starts a conversion. Pin 22 (BUSY) will output a LOW during the conversion process (including sample acquisition and conversion), and rises only after the conversion is completed. The two bytes of output data can then be read using pin 18 (RD) and pin 21 (HBE). STARTING A CONVERSION A conversion is initiated on the rising edge of the WR input, with valid signals on A0, A1 and CS. The selected input channel is sampled for five clock cycles. The successive ® ADS7832 8 straight binary (with 0V = 000 hex, 5V = FFF hex), and the data is presented in a right-justified format (with the LSB as the most right bit in the 16-bit word). Two read operations are required to transfer the High byte and Low byte, and the bytes are presented according to the input level on the High Byte Enable pin (HBE). The bytes can be read in either order, depending on the status of the HBE input. If HBE changes while CS and RD are LOW, the output data will change to correspond to the HBE input. Figure 4 shows the timing for reading first the Low byte and then the High byte. 1 CLK 2 3 4 5 6 7 16 17 18 WR Multiplexer Settling, Offset Auto Zeroing and Sampling Acquisition BUSY Successive Approximation Conversion FIGURE 2. Converter Timing. CS t1 t2 t3 WR or CAL t4 BUSY t5 SFR t6 A0, A1 VIH VIL FIGURE 3. Write Cycle Timing (for initiating conversion or calibration). BUSY t7 CS t8 RD t9 t10 t8 t10 SFR t11 HBE t13 D0 - D7 Hi-Z State t14 Low Byte Data Hi-Z t13 t14 High Byte Data t12 t11 t12 FIGURE 4. Read Cycle Timing. ® 9 ADS7832 ADS7832 provides two modes for reading the conversion results. At power-up, the converter is set in the Transparent Mode. TRANSPARENT MODE This is the default mode for ADS7832. In this mode, the conversion decisions from the successive approximation register are latched into the output register as they are made. Thus, the High byte (the 4 MSBs) can be read after the end of the ninth clock cycle (five clock cycles for the mux settling, sample acquisition and auto-zeroing of the comparator, followed by the four clock cycles for the 4MSB decisions.) The complete 12-bit data is available after BUSY has gone HIGH, or the internal status flag goes LOW (D7 when HBE is HIGH). LATCHED OUTPUT MODE This mode is activated by writing a HIGH to D0 in the Special Function Register with CS and WR LOW and SFR and HBE HIGH. (See the discussion of the Special Function Register below.) In this mode, the data from a conversion is latched into the output buffers only after a conversion is complete, and remains there until the next conversion is completed. The conversion result is valid during the next conversion. This allows the data to be read even after a new conversion is started, for faster system throughput. TIMING CONSIDERATIONS Table I and Figures 3 through 9 show the digital timing of ADS7832 under the various operating modes. All of the critical parameters are guaranteed over the full –40°C to +85°C operating range for ease of system design. SPECIAL FUNCTION REGISTER (SFR) An internal register is available, either to determine additional data concerning the ADS7832, or to write additional instructions to the converter. Table II shows the data in the Special Function Register that will be transferred to the output bus by driving HBE HIGH (with SFR HIGH) and initiating a read cycle (driving RD and CS LOW with WR HIGH.) The Power Fail flag in the SFR is set when the power supply falls below about 2.7V. The flag also means that a new calibration has been started, PIN D0 FUNCTION Mode Status DESCRIPTION If LOW, Transparent Mode enabled for data latches. If HIGH, latched Output Mode enabled. If HIGH, calibration cycle in progress. If LOW, pin 26 used as input to initiate calibration cycle. If HIGH, pin 26 used as input to control sample-to-hold timing. If HIGH, in Power Down Mode (Power Down Mode is the default condition). Reserved for factory use. POWER FAIL Flag If HIGH, a power supply failure has occurred (supply fell below 2.7V). Always write as LOW. If HIGH, an overflow occurred during calibration. If HIGH, conversion or calibration in progress. D1 D2 CAL Flag Pin 26 Status D3 D4 D5 Power Down Status D6 D7 CAL ERROR Flag BUSY Flag NOTE: These data are transferred to the bus when a read cycle is initiated with SFR and HBE HIGH. Reading the SFR with SFR HIGH and HBE LOW is reserved for factory use at this time, and will yield unpredictable data. TABLE II. Reading the Special Function Register. SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 PARAMETER(1) CS to WR Setup Time(2) WR or CAL Pulse Width CS to WR Hold Time(2) WR to BUSY Propagation Delay A0, A1, HBE, SFR Valid to WR Setup Time A0, A1, HBE, SFR Valid to WR Hold Time BUSY to CS Setup Time CS to RD Setup Time(2) RD Pulse Width CS to RD Hold Time(2) HBE, SFR to RD Setup Time HBE, SFR to RD Hold Time RD to Valid Data (Bus Access Time)(3) RD to Hi-Z Delay (Bus Release Time)(3) RD to Hi-Z Delay For SFR(3) Data Valid to WR Setup Time Data Valid to WR Hold Time Acquisition Time. Pin 26 LOW with D2 in SFR HIGH Sample-to-Hold Aperture Delay. (D2 in SFR HIGH) Delay from rising edge on pin 26 to start of conversion. (D2 in SFR HIGH) 20 100 20 2.5 5 1.5 MIN 0 100 0 20 0 20 0 0 100 0 50 0 80 90 150 180 60 0 0 0 0 0 50 0 150 TYP 0 MAX 0 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ns CLK cycles NOTES: (1) All input control signals are specified with tRISE = tFALL = 20ns (10% to 90% of 5V) and timed from a voltage level of 1.6V. Data is timed from VIH, VIL, VOH or VOL. (2) The internal RD pulse is performed by a NOR wiring of CS and RD. The internal WR pulse is performed by a NOR wiring of CS and WR. (3) Figures 8 and 9 show the measurement circuits and pulse diagrams for testing transitions to and from Hi-Z states. TABLE I. Timing Specifications (CLK = 2MHz external, TA = –40°C to +85°C). ® ADS7832 10 and any data written to the SFR has been lost. Thus, the ADS7832 will again be in the Transparent Mode. Writing a LOW to D5 in the SFR resets the Power Fail flag. The Cal Error flag in the SFR is set when an overflow occurs during calibration, which may happen in very noisy systems. It is reset by starting a calibration, and remains low after a calibration without an overflow is completed. Table III shows how instructions can be transferred to the Special Function Register by driving HBE HIGH (with SFR HIGH) and initiating a write cycle (driving WR and CS LOW with RD HIGH.) Note that writing to the SFR also initiates a new conversion. POWER DOWN MODE Writing a HIGH to D3 in the SFR puts the ADS7832 in the Power Down Mode. Power consumption is reduced to 50µW and D3 remains HIGH. The internal clock and analog circuitry are turned off, although the output registers and SFR can still be accessed normally. To exit Power Down Mode, either write a LOW to D3 in the SFR, or initiate a calibration by sending a LOW to the CAL pin or writing a HIGH to D1. Note that if the power supply falls below 3V and then recovers, a calibration is automatically initiated, and the SFR will be reset. D3 will be HIGH, and the ADS7832 will be in the Power Down Mode. During Power Down Mode, a pulse on CS and WR will initiate a single conversion, then the ADS7832 will revert to power down. Also, writing to D1 and D3 in the SFR will initiate a calibration, do a single conversion and revert to the Power Down Mode, in 4,625 clock cycles. Accurate conversion results will be available in the output registers. The activation delay from power down to normal operation is included in the sampling time. No extra time is required, either when coming out of the Power Down Mode or when making a single conversion in the Power Down Mode. SAMPLE/HOLD CONTROL MODE With D2 in the SFR HIGH, a rising edge input on pin 26 will switch the ADS7832 from sample-mode to hold-mode with a 5ns aperture delay. This also initiates a conversion, which will start within 1.5 CLK cycles. This mode allows full control over the sample-to-hold timing, which is especially useful where external events trigger sampling timing. OPERATION Enables Transparent Mode for Data Latches Enables Latched Output Mode for Data Latches Initiates Calibration Cycle Activates Sample/Hold Control Mode Activates Power Down Mode(2) Resets Power Fail Flag CS/WR LOW LOW LOW LOW LOW LOW SFR/HBE HIGH HIGH HIGH HIGH HIGH HIGH CS t1 WR t5 HBE SFR VIH D0 - D7 Valid Data t16 VIL t17 t6 t2 t3 FIGURE 5. Writing to the SFR. CS t8 RD t11 HBE t11 SFR t13 D0 - D7 VIH SFR Data t14 t12 t12 t10 FIGURE 6. Reading the FSR. In the Sample/Hold Control Mode, pin 26 must be held LOW a minimum of 2.5µs between conversions to allow accurate acquisition of input signals. Also, offset error will increase in this mode, since auto-zeroing of the comparator is not synchronized to the sampling. Minimum offset is achieved by synchronizing the sampling signal to CLK, whether internal or external. Ideally, the sampling signal rising edge should be delayed 20ns from the falling edge of CLK. This will keep offset error to about 1LSB. In the Sample/Hold Control Mode, a LOW pulse on WR (with CS LOW) will not initiate a conversion, but the rising edge will latch the multiplexer channel according to the inputs on A0 and A1. When changing channels, this must be done at least 2.5µs before pin 26 goes HIGH (to start a conversion.) D0 LOW HIGH(1) X X X X D1 X X HIGH X X X D2 X X X HIGH(1) X X D3 X X X X HIGH(1) X D5 X X X X X LOW D4/D6/D7 LOW LOW LOW LOW LOW LOW NOTES: (1) Writing a LOW here reactivates the standard mode of operation. (2) In Power Down Mode, a pulse on CS and WR will initiate a single conversion, then the ADS7832 will revert to power down. (3) X means it can be either HIGH or LOW without affecting this action. Writing HIGH to D4 or D6, or writing with SFR HIGH and HBE LOW, may result in unpredictable behavior. These modes are reserved for factory use at this time. TABLE III. Writing to the Special Function Register. ® 11 ADS7832 CONTROL LINES Table IV shows the functions of the various control lines on the ADS7832. The use of standard CS, RD and WR control signals simplifies use with most microprocessors. At the same time, flexibility is assured by availability of status information and control functions, both through the SFR and directly on pins. full power bandwidth of the system. For higher source impedances, a buffer like the one in Figure 10b should be used. INPUT PROTECTION The input signal range must not exceed ±VREF or VA by more than 0.3V. The analog inputs are internally clamped to VA. To prevent damage to the ADS7832, the current that can flow into the inputs must be limited to 20mA. One approach is to use an external resistor in series with the input filter resistor. For example, a 1kΩ input resistor allows an overvoltage to 20V without damage. REFERENCE INPUTS A 10µF tantalum capacitor is recommended between VREF+ and VREF – to insure low source impedance. These capacitors should be located as close as possible to the ADS7832 to reduce dynamic errors, since the reference provides packets of current as the successive approximation steps are carried out. VREF+ must not exceed VA. Although the accuracy is specified with VREF+ = 5V and VREF– = 0V, the converter can function with VREF+ as low as 4.5V and VREF– as high as 1V. INSTALLATION INPUT IMPEDANCE ADS7832 has a very high input impedance (input bias current over temperature is 100nA max), and a low 50pF input capacitance. To ensure a conversion accurate to 12 bits, the analog source must be able to charge the 50pF and settle within the first five clock cycles after a conversion is initiated. During this time, the input is also very sensitive to noise at the analog input, since it could be injected into the capacitor array. In many applications, a simple passive low-pass filter as shown in Figure 10a can be used to improve signal quality. In this case, the source impedance needs to be less than 5kΩ to keep the induced offset errors below 1/2LSB, and to meet the acquisition time of five clock cycles. The values in Figure 10a meet these requirements, and will maintain the CS X X 1 0 0 0 0 0 0 0 RD X X X 1 0 0 1 0 1 0 WR X X X 0↑ 1 1 1 0 1 0 1 SFR X X X 0 0 0 1 1 1 1 HBE X X X X 0 1 1 1 0 0 CAL 0↑ 1 X 1 1 1 1 1 1 1 1 BUSY X 0 X 1 X X 1 X X X OPERATION Initiates calibration cycle. (See SFR section for alternate use as Sample/ Hold Control Mode input.) Conversion or calibration in process. Inhibits new conversion from starting. None. Outputs in Hi-Z State. Initiates conversion. Low byte conversion results output on data bus. High byte conversion results output on data bus. Write to SFR and rising edge on WR initiates conversion. Contents of SFR output on data bus. Reserved for factory use. Reserved for factory use. (Unpredictable data on data bus.) TABLE IV. Control Line Functions. 1 CLK t18 SHC (Pin 26) t20 BUSY t19 Sample Hold 2 11 12 Convert Sample FIGURE 7. Timing for Initiating Conversion in Sample/Hold Control Mode (D2 in SFR HIGH). ® ADS7832 12 5V 3kΩ ADS7832 Output CL (a) Load Circuit ADS7832 Output Test Point 3kΩ CL Test Point (a) Load Circuit tFALL VD Output Enable VD tFALL 90% 50% 10% Output Enable 90% 50% 10% Gnd Gnd VD VOL 10% t15 t14 (b) From LOW to Hi-Z, CL = 10pF VOH Gnd 90% t15 t14 (b) From HIGH to Hi-Z, CL = 10pF Output Enable VD 10% tRISE 90% 50% Output Enable VD 10% tRISE 90% 50% Gnd Gnd t13 t13 VD 0.8V VOL VOH 2.4V Gnd (c) From Hi-Z to HIGH, CL = 100pF (c) From Hi-Z to LOW, CL = 100pF FIGURE 8. Measuring Active LOW to/from Hi-Z State. As long as there is at least a 4.5V difference between VREF+ and VREF–, the absolute value of errors does not change significantly, so that accuracy will typically be within ±1LSB The power supply to the reference source needs to be considered during system design to prevent VREF+ from exceeding (or overshooting) VA, particularly at power-on. Also, after power-on, if the reference is not stable within 33,056 clock cycles, an additional calibration cycle may be needed. POWER SUPPLIES The digital and analog power supply lines to the ADS7832 should be bypassed with 10µF tantalum capacitors as close to the part as possible. Although ADS7832 has excellent power supply rejection, even for higher frequencies, linear regulated power supplies are recommended. Care should be taken to insure that VD does not come up before VA, or permanent damage to the part may occur. Figure 11 shows a good supply approach, powering both VA and VD from a clean linear supply, with the 10Ω resistor between VA and VD insuring that VD comes up after VA. FIGURE 9. Measuring Active HIGH to/from Hi-Z State. This is also a good method to further isolate the ADS7832 from digital supplies in a system with significant switching currents that could degrade the accuracy of conversions. GROUNDING To maximize accuracy of the ADS7832, the analog and digital grounds are not connected internally. These points should have very low impedance to avoid digital noise feeding back into the analog ground. The VREF– pin is used as the reference point for input signals, so it should be connected directly to AGND to reduce potential noise problems. EXTERNAL CLOCK OPERATION The circuitry required to drive the ADS7832 clock from an external source is shown in Figure 12a. The external clock must provide a 0.8V max for LOW and a 3.5V min for HIGH, with rise and fall times that do not exceed 200ns. The duty cycle of the external clock can vary as long as the LOW time and HIGH time are each at least 200ns wide. Synchronizing the conversion clock to an external system clock is ® 13 ADS7832 Analog Input 50Ω To ADS7832 5nF VREF– (Normally 0V) (a) Passive Low Pass Filter INTERNAL CLOCK OPERATION Figure 12b shows how to use the internal clock generating circuitry. The clock frequency depends only on the value of the resistor, as shown in “Internal Clock Frequency vs RCLOCK” in the Typical Performance Curves section. The clock generator can operate between 100kHz and 2MHz. With R = 100kΩ, the clock frequency will nominally be 800kHz. The internal clock oscillators may vary by up to 20% from device to device, and will vary with temperature, as shown in the typical performance curves. Therefore, use of an external clock source is preferred in applications where control of the conversion timing is critical, or where multiple converters need to be synchronized. Analog Input R C OPA627 To ADS7832 VREF– (Normally 0V) (b) Active Low Pass Filter 74HC-Compatible Clock Source CLK To ADS7832 Pin 23 FIGURE 10. Input Signal Conditioning. (a) External Clock Operation R +5V See Figure 15 for typical R Values vs Frequency To ADS7832 Pin 23 (b) Internal Clock Operation +5V 1 2 3 5V REF 4 5 10µF + 10nF 6 7 8 + 10nF 9 10 11 12 13 14 SFR AIN0 AIN1 AIN2 AIN3 VREF+ VREF– DGND VD D7 D6 D5 D4 D3 VA AGND CAL A1 A0 CLK BUSY HBE WR CS RD D0 D1 D2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 10nF + 10µF FIGURE 12. Internal Clock Operation. APPLICATIONS BIPOLAR INPUT RANGES Figure 13 shows a circuit to accurately and simply convert a bipolar ±5V input signal into a unipolar 0 to 5V signal for conversion by the ADS7832, using a precision, low-cost complete difference amplifier, INA105. Figure 14 shows a circuit to convert a bipolar ±10V input signal into a unipolar 0 to 5V signal for conversion by the ADS7832. The precision of this circuit will depend on the matching and tracking of the three resistors used. To trim this circuit for full 12-bit precision, R2 and R3 need to be adjustable over appropriate ranges. To trim, first have the ADS7832 converting continually and apply +9.9927V (+10V – 1.5LSB) at the input. Adjust R3 until the ADS7832 output toggles between the codes FFE hex and FFF hex. This makes R3 extremely close to R1. Then, apply –9.9976V (–10V + 0.5LSB) at the input, and adjust R2 until the ADS7832 output toggles between 000 hex and 001 hex. At each trim point, the current through the third resistor will be almost zero, so that one trim iteration will be enough in most cases. More iterations may be required if the op amp selected has large offset voltage or bias currents, or if the +5V reference is not precise. This circuit can also be used to adjust gain and offset errors due to the components preceding the ADS7832, to match the performance of the self-calibration provided by the converter. 10µF 10Ω FIGURE 11. Power Supply and Reference Decoupling. recommended in microprocessor applications to prevent beat-frequency problems. Note that the electrical specification tables are based on using an external 2MHz clock. Typically, the specified accuracy is maintained for clock frequencies between 0.5 and 2.4MHz. ® ADS7832 14 INTERNAL CLOCK FREQUENCY vs RCLK 10.000 INA105 25kΩ 25kΩ 2 5 Internal Clock Frequency (MHz) 1.000 ±5V Input 1 25kΩ 6 0 to 5V to ADS7832 25kΩ 3 +5V (VREF+) 0.100 10 RCLK (kΩ) 100 FIGURE 13. ±5V Input Range. FIGURE 15. Internal Clock Frequency vs RCLK Resistor Value. ±5V (VREF+) R1 10kΩ R2 5kΩ R3 10kΩ 0 to 5V to ADS7832 OPA627 ±10V Input FIGURE 14. ±10V Input Range. ® 15 ADS7832