ADS7835E

® ADS7835 For most current data sheet and other product information, visit www.burr-brown.com 12-Bit, High-Speed, Low Power Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES q 500kHz THROUGHPUT RATE q 2.5V INTERNAL REFERENCE q LOW POWER: 17.5mW q SINGLE SUPPLY +5V OPERATION q SERIAL INTERFACE q GUARANTEED NO MISSING CODES q MSOP-8 q ±VREF INPUT RANGE DESCRIPTION The ADS7835 is a 12-bit, sampling analog-to-digital converter (A/D) complete with sample-and-hold (S/H), internal 2.5V reference, and synchronous serial interface. Typical power dissipation is 17.5mW at a 500kHz throughput rate. The device can be placed into a power-down mode which reduces dissipation to just 2.5mW. The input range is –V REF to +VREF, and the internal reference can be overdriven by an external voltage. Low power, small size, and high speed make the ADS7835 ideal for battery-operated systems such as wireless communication devices, portable multichannel data loggers, and spectrum analyzers. The serial interface also provides low cost isolation for remote data acquisition. The ADS7835 is available in an MSOP-8 package and is guaranteed over the –40°C to +85° C temperature range. APPLICATIONS q BATTERY-OPERATED SYSTEMS q DIGITAL SIGNAL PROCESSING q HIGH-SPEED DATA ACQUISITION q WIRELESS COMMUNICATION SYSTEMS CLK SAR CONV ±2.5V Input 2kΩ CDAC 2kΩ Serial Interface Comparator DATA S/H Amp Buffer Internal +2.5V Ref VREF 10kΩ ±30% International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1998 Burr-Brown Corporation PDS-1478B 1 Printed in U.S.A.May, 2000 ADS7835 SPECIFICATIONS At TA = –40°C to +85°C, +VCC = +5V, fSAMPLE = 500kHz, fCLK = 16 • fSAMPLE, and internal +2.5V reference, unless otherwise specified. ADS7835E PARAMETER RESOLUTION ANALOG INPUT(1) Input Voltage Range Input Capacitance Input Resistance SYSTEM PERFORMANCE No Missing Codes Integral Linearity Differential Linearity Bipolar Offset Error Positive Fulll-Scale Error(3) Negative Full-Scale Error(3) Noise Power Supply Rejection Ratio SAMPLING DYNAMICS Conversion Time Acquisition Time Throughput Rate Aperture Delay Aperture Jitter Step Response DYNAMIC CHARACTERISTICS Signal-to-Noise Ratio Total Harmonic Distortion(4) Signal-to-(Noise+Distortion) Spurious Free Dynamic Range REFERENCE OUTPUT Voltage Source Current(5) Line Regulation REFERENCE INPUT Range Resistance(6) DIGITAL INPUT/OUTPUT Logic Family Logic Levels: VIH VIL VOH VOL Data Format POWER SUPPLY REQUIREMENT +VCC Quiescent Current Power Dissipation Power-Down TEMPERATURE RANGE Specified Performance T Specifications same as ADS7835E. NOTES: (1) Ideal input span, does not include gain or offset error. (2) LSB means Least Significant Bit, with VREF equal to +2.5V, one LSB is 1.22mV. (3) Measured relative to an ideal positive full scale of 2.499V for positive full-scale error. Measured relative to an ideal negative full scale of –2.499V for negative full-scale error. (4) Calculated on the first nine harmonics of the input frequency. (5) If the internal reference is required to source current to an external load, the reference voltage will change due to the internal 10kΩ resistor. (6) Can vary ±30%. –40 VIN VIN VIN VIN = = = = 5Vp-p 5Vp-p 5Vp-p 5Vp-p at at at at 10kHz 10kHz 10kHz 10kHz ±2.5V with the 2.5V Internal Reference During Conversion (CONV = LOW) 12 ±1 ±0.8 ±2 ±12 ±12 200 0.3 1.625 0.350 500 5 30 375 72 –78 70 78 2.50 0.2 2.3 To Internal Reference Voltage 10 CMOS IIH ≤ +5µA IIL ≤ +5µA IOH = –500µA IOL = 500µA 3.0 –0.3 3.5 +VCC + 0.3 0.8 T T T T T T T T T T T V mA mA mW mW °C 2.9 T T T T T T V V V V T T T T –82 72 82 T T T T T T ±2 ± 10 ±20 ± 35 ±20 ± 35 –VREF 25 2 T ± 0.5 ± 0.5 ±1 ±7 ±7 T T ±1 ±1 ±5 ±12 ± 25 ±12 ± 25 CONDITIONS MIN TYP 12 +VREF T T T MAX MIN ADS7835EB TYP T T MAX UNITS Bits V pF kΩ Bits LSB(2) LSB LSB LSB LSB LSB LSB µVrms LSB µs µs kHz ns ps ns dB dB dB dB V µA mV V kΩ At –40°C At –40°C 25°C to +85°C 25°C to +85°C Worst-Case ∆, +VCC = 5V ±5% –72 70 75 2.525 50 2.48 –75 68 72 2.475 IOUT = 0 Static Load 4.75V ≤ VCC ≤ 5.25V 2.52 T 0.4 Binary Two’s Complement 4.75 3.5 0.5 17.5 2.5 5.25 Specified Performance fSAMPLE = 500kHz Power-Down 30 T +85 T The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® ADS7835 2 ABSOLUTE MAXIMUM RATINGS(1) +VCC to GND ............................................................................ –0.3V to 6V Analog Inputs to GND ............................................................. –5.3 to +5.3 Digital Inputs to GND ............................................... –0.3V to (VCC + 0.3V) Power Dissipation .......................................................................... 325mW Maximum Junction Temperature ................................................... +150°C Operating Temperature Range ......................................... –40°C to +85°C Storage Temperature Range .......................................... –65°C to +150°C Lead Temperature (soldering, 10s) ............................................... +300°C NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. PIN CONFIGURATION Top View VREF AIN GND GND 1 2 ADS7835 3 4 MSOP-8 8 7 6 5 +VCC CLK DATA CONV PIN ASSIGNMENTS PIN 1 2 3 4 5 6 NAME VREF AIN GND GND CONV DATA DESCRIPTION Reference Output. Decouple to ground with a 0.1µF ceramic capacitor and a 2.2µF tantalum capacitor. ±2.5V Input Ground Ground Convert Input. Controls the sample/hold mode, start of conversion, start of serial data transfer, type of serial transfer, and powerdown mode. See the Digital Interface section for more information. Serial Data Output. The 12-bit conversion result is serially transmitted most significant bit first with each bit valid on the rising edge of CLK. By properly controlling the CONV input, it is possibly to have the data transmitted least significant bit first. See the Digital Interface section for more information. Clock Input. Synchronizes the serial data transfer and determines conversion speed. Power Supply. Decouple to ground with a 0.1µF ceramic capacitor and a 10µF tantalum capacitor. 7 8 CLK +VCC PACKAGE/ORDERING INFORMATION MAXIMUM INTEGRAL LINEARITY ERROR (LSB) ±2 ±1 ±2 ±1 MAXIMUM DIFFERENTIAL LINEARITY ERROR (LSB) N/S(4) ±1 PRODUCT ADS7835E PACKAGE MSOP-8 PACKAGE DRAWING NUMBER(1) 337 SPECIFICATION TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C –40°C to +85°C PACKAGE MARKING(2) B35 ORDERING NUMBER(3) ADS7835E/250 ADS7835E/2K5 ADS7835EB/250 ADS7835EB/2K5 ADS7835P ADS7835PB TRANSPORT MEDIA Tape and Reel Tape and Reel Tape and Reel Tape and Reel Rails Rails " ADS7835EB " " " " " MSOP-8 " 337 " " " B35 " ADS7835P ADS7835PB " Plastic DIP-8 " 006 " ADS7835P ADS7835PB N/S(4) ±1 " " " NOTE: (1) For detail drawing and dimension table, please see end of data sheet or Package Drawing File on Web. (2) Performance Grade information is marked on the reel. (3) Models with a slash(/) are available only in Tape and reel in quantities indicated (e.g. /250 indicates 250 units per reel, /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of ”ADS7835E/2K5“ will get a single 2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to the www.burr-brown.com web site under Applications and Tape and Reel Orientation and Dimensions. (4) N/S = Not Specified, typical only. However, 12-Bits no missing codes is guaranteed over temperature. ® 3 ADS7835 TYPICAL PERFORMANCE CURVES At TA = +25°C, +VCC = +5V, fSAMPLE = 500kHz, fCLK = 16 • fSAMPLE, and internal +2.5V reference, unless otherwise specified. CHANGE IN FULL-SCALE ERRORS vs TEMPERATURE 1.0 0.0 CHANGE IN BIPOLAR OFFSET ERROR vs TEMPERATURE 0.6 Negative Full-Scale Error 0.4 Delta from +25°C (LSB) Delta from +25°C (LSB) 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 –1.0 –2.0 Positive Full-Scale Error –3.0 –4.0 –5.0 –40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100 Temperature (°C) Temperature (°C) POWER-DOWN SUPPLY CURRENT vs TEMPERATURE 470 Power-Down Supply Current (µA) 3.8 3.7 SUPPLY CURRENT vs TEMPERATURE 460 Supply Current (mA) 450 440 430 420 410 400 390 –40 –20 0 20 40 60 80 100 Temperature (°C) 3.6 3.5 3.4 3.3 3.2 3.1 3.0 –40 fSAMPLE = 125kHz fSAMPLE = 500kHz –20 0 20 40 60 80 100 Temperature (°C) SUPPLY CURRENT vs SAMPLE RATE 4.0 CHANGE IN INTEGRAL and DIFFERENTIAL LINEARITY vs SAMPLE RATE 0.5 Supply Current (mA) 3.8 3.7 3.6 3.5 3.4 3.3 3.2 3.1 3.0 100 200 300 400 500 600 700 Delta from fSAMPLE = 500kHz (LSB) 3.9 0.4 0.3 0.2 0.1 0.0 –0.1 –0.2 –0.3 –0.4 –0.5 0 100 200 300 400 500 600 700 Change in Differential Linearity (LSB) Change in Integral Linearity (LSB) Sample Rate (kHz) Sample Rate (kHz) ® ADS7835 4 TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, +VCC = +5V, fSAMPLE = 500kHz, fCLK = 16 • fSAMPLE, and internal +2.5V reference, unless otherwise specified. CHANGE END-POINT ERRORS vs EXTERNAL REFERENCE VOLTAGE 4.0 0.90 0.85 Negative Full-Scale Error 3.0 2.0 1.0 0.0 –1.0 –2.0 –3.0 –4.0 –5.0 2.2 2.4 2.6 2.8 3.0 External Reference Voltage (V) Positive Full-Scale Error and Bipolar Offset Error PEAK-TO-PEAK NOISE vs EXTERNAL REFERENCE VOLTAGE Delta from VREF = 2.5V (LSB) Peak-to-Peak Noise (LSB) 0.80 0.75 0/70 0.65 0.60 0.55 0.50 2 2.1 2.2 2.3 2.4 2.5 External Reference Voltage (V) POWER SUPPLY REJECTION RATIO vs POWER SUPPLY RIPPLE FREQUENCY 30 0 –20 FREQUENCY SPECTRUM (4096 Point FFT; fIN = 977Hz, –0.2dB) Power Supply Rejection Ratio (mV/V) 25 20 15 10 5 0 1 10 100 1k 10k 100k 1M Power Supply Ripple Frequency (Hz) Amplitude (dB) –40 –60 –80 –100 –120 0 50 100 150 200 250 Frequency (kHz) FREQUENCY SPECTRUM (4096 Point FFT; fIN = 9.77kHz, –0.2dB) 0 –20 0 –20 FREQUENCY SPECTRUM (4096 Point FFT; fIN = 99.7kHz, –0.2dB) Amplitude (dB) –60 –80 –100 –120 0 50 100 150 200 250 Frequency (kHz) Amplitude (dB) –40 –40 –60 –80 –100 –120 0 50 100 150 200 250 Frequency (kHz) ® 5 ADS7835 TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, +VCC = +5V, fSAMPLE = 500kHz, fCLK = 16 • fSAMPLE, and internal +2.5V reference, unless otherwise specified. SIGNAL-TO-NOISE and SIGNAL-TO-(NOISE + DISTORTION) vs INPUT FREQUENCY 75 SNR 73 90 SPURIOUS FREE DYNAMIC RANGE and TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY SNR and SINAD (dB) 85 SFDR and THD (dB) 71 69 67 65 63 1 10 100 1000 Input Frequency (kHz) SINAD SFDR 80 THDT 75 70 T First nine harmonics of the input frequency 10 100 1000 65 1 Input Frequency (kHz) CHANGE IN SIGNAL-TO-NOISE and SIGNAL-TO-(NOISE+DISTORTION) vs TEMPERATURE SNR and SINAD Deltas from +25°C (dB) 0.4 0.3 0.2 0.1 0.0 –0.1 –0.2 –0.3 –0.4 –0.5 –40 –20 0 20 40 60 80 100 Temperature (°C) SINAD SNR fIN = 10kHz, –0.2dB SFDR and THD Deltas from +25°C (dB) CHANGE IN SPURIOUS FREE DYNAMIC RANGE and TOTAL HARMONIC DISTORTION vs TEMPERATURE 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 –40 SFDR ∗First nine harmonics of the input frequency –20 0 20 40 Temperature (°C) 60 80 100 THD∗ fIN = 10kHz, –0.2dB 0.5 CHANGE IN BIPOLAR OFFSET ERROR vs SAMPLE RATE 1.0 0.8 Delta from 500kHz (mA) 0.6 0.4 0.2 0.0 –0.2 0 100 200 300 400 500 600 700 Sample Rate (kHz) ® ADS7835 6 THEORY OF OPERATION The ADS7835 is a high speed Successive Approximation Register (SAR) analog-to-digital converter (A/D) with an internal 2.5V bandgap reference. The architecture is based on capacitive redistribution which inherently includes a S/H function. The converter is fabricated on a 0.6µ CMOS process. See Figure 1 for the basic operating circuit for the ADS7835. The ADS7835 requires an external clock to run the conversion process. This clock can vary between 200kHz (12.5kHz throughput) and 8MHz (500kHz throughput). The duty cycle of the clock is unimportant as long as the minimum HIGH and LOW times are at least 50ns and the clock period is at least 125ns. The minimum clock frequency is set by the leakage on the capacitors internal to the ADS7835. The analog input to the ADS7835 is single-ended. The ADS7835 provides a true bipolar input where the input will swing below ground. When using the internal 2.5V reference the input range is ±2.5V (within ±20mV for the low grade and ±12mV for the high grade). When using an external reference the input range is –VREF to +VREF. The ADS7835 will accept an external reference with a range of 2.3V to 2.9V. The digital result of the conversion is provided in a serial manner, synchronous to the CLK input. The provided result is Most Significant Bit (MSB) first and represents the result of the conversion currently in progress—there is no pipeline delay. By properly controlling the CONV and CLK inputs, it is possible to obtain the digital result Least Significant Bit (LSB) first. ANALOG INPUT The analog input (pin 2) of the ADS7835 is connected to a 2kΩ x 2kΩ voltage divider. This divider allows the ADS7835 to accept bipolar inputs while operating from a single 5V supply. The divider is connected to the output buffer of the internal +2.5V supply. When the input is at +full-scale (+2.5V), the voltage at the input to the CDAC (Capacitive Digital-to-Analog Converter) is also +2.5V resulting in negligible input current. When the input is at –full-scale (–2.5V), the voltage at the input of the CDAC is 0V resulting in 1.25mA of current being sourced out of the input pin. It is recommended that a buffer be placed between the analog input signal and the input of the ADS7835. The input impedance of the ADS7835 depends on whether the device is in the sample or hold mode. When sampling, the input has a 4kΩ input impedance to the reference. The source of the analog input voltage must be able to charge the input impedance (typically 25pF || 1kΩ) to a 12-bit settling level within the same period. This can be as little as 350ns in some operating modes. When the converter is in the hold mode, the input impedance switches to approximately 2kΩ to ground. Care must be taken regarding the input voltage on the AIN pin. The input signal should remain within –5.3V and +5.3V (with a 5V supply) to avoid damaging the converter. REFERENCE The reference voltage on the VREF pin directly sets the fullscale range of the analog input. The ADS7835 can operate with a reference in the range of 2.3V to 2.9V, for a full-scale range of ±2.3V to ±2.9V. The voltage at the VREF pin is internally buffered and this buffer drives the CDAC portion of the converter. This is important because the buffer greatly reduces the dynamic load placed on the reference source. However, the voltage at VREF will still contain some noise and glitches from the SAR conversion process. These can be reduced by carefully bypassing the VREF pin to ground as outlined in the sections that follow. INTERNAL REFERENCE The ADS7835 contains an on-board 2.5V reference, resulting in a –2.5V to +2.5V input range on the analog input. The Specification table gives the various specifications for the internal reference. This reference can be used to supply a small amount of source current to an external load, but the load should be static. Due to the internal 10kΩ resistor, a dynamic load will cause variations in the reference voltage, and will dramatically affect the conversion result. Note that even a static load will reduce the internal reference voltage seen at the buffer input. The amount of reduction depends on the load and the actual value of the internal “10kΩ” resistor. The value of this resistor can vary by ±30%. The VREF pin should be bypassed with a 0.1µF capacitor placed as close as possible to the ADS7835 package. In addition, a 2.2µF tantalum capacitor should be used in parallel with the ceramic capacitor. Placement of this capacitor, while not critical to performance, should be placed as close to the package as possible. +5V + + 2.2µF 0.1µF 1 ±2.5V Analog Input 2 3 4 ADS7835 VREF AIN GND GND +VCC CLK DATA CONV 8 7 6 5 0.1µF 10µF Serial Clock Serial Data Convert Start from Microcontroller or DSP FIGURE 1. Basic Operation of the ADS7835. ® 7 ADS7835 the CLK may be kept LOW or HIGH. EXTERNAL REFERENCE The internal reference is connected to the VREF pin and to the internal buffer via a 10kΩ series resistor. Thus, the reference voltage can easily be overdriven by an external reference voltage. The voltage range for the external voltage is 2.3V to 2.9V, corresponding to an analog input range of 2.3V to 2.9V in both cases. While the external reference will not source significant current into the VREF pin, it does have to drive the 10kΩ series resistor that is terminated into the 2.5V internal reference (the exact value of the resistor will vary up to ±30% from part to part). In addition, the VREF pin should still be bypassed to ground with at least a 0.1µF ceramic capacitor (placed as close to the ADS7835 as possible). The reference will have to be stable with this capacitive load. Depending on the particular reference and A/D conversion speed, additional bypass capacitance may be required, such as the 2.2µF tantalum capacitor shown in Figure 1. Reasons for choosing an external reference over the internal reference vary, but there are two main reasons. One is to achieve a given input range. The other is to provide greater stability over temperature. (The internal reference is typically 20ppm/°C which translates into a full-scale drift of roughly one output code for every 12°C. This does not take into account other sources of full-scale drift.) If greater stability over temperature is needed, then an external reference with lower temperature drift will be required. DIGITAL INTERFACE Figure 2 shows the serial data timing and Figure 3 shows the basic conversion timing for the ADS7835. The specific timing numbers are listed in Table I. There are several important items in Figure 3 which give the converter additional capabilities over typical 8-pin converters. First, the transition from sample mode to hold mode is synchronous to the falling edge of CONV and is not dependent on CLK. Second, the CLK input is not required to be continuous during the sample mode. After the conversion is complete, The asynchronous nature of CONV to CLK raises some interesting possibilities, but also some design considerations. Figure 3 shows that CONV has timing restraints in relation to CLK (tCKCH and tCKCS). However, if these times are violated (which could happen if CONV is completely asynchronous to CLK), the converter will perform a conversion correctly, but the exact timing of the conversion is indeterminate. Since the setup and hold time between CONV and CLK has been violated in this example, the start of conversion could vary by one clock cycle. (Note that the start of conversion can be detected by using a pull-up resistor on DATA. When DATA drops out of high impedance and goes LOW, the conversion has started and that SYMBOL tACQ tCONV tCKP tCKL tCKH tCKDH tCKDS tCVL tCVH tCKCH tCKCS tCKDE tCKDD tCKSP tCKPD tCVHD tCVSP tCVPU tCVDD tCVPD tDRP DESCRIPTION Acquisition Time Conversion Time Clock Period Clock LOW Clock HIGH Clock Falling to Current Data Bit No Longer Valid Clock Falling to Next Data Valid CONV LOW CONV HIGH CONV Hold after Clock Falls(1) CONV Setup to Clock Falling(1) Clock Falling to DATA Enabled Clock Falling to DATA High Impedance Clock Falling to Sample Mode Clock Falling to Power-Down Mode CONV Falling to Hold Mode (Aperture Delay) CONV Rising to Sample Mode CONV Rising to Full Power-up CONV Changing State to DATA High Impedance CONV Changing State to Power-Down Mode CONV Falling to Start of CLK (for hold droop < 0.1 LSB) 40 40 10 10 20 70 5 50 5 5 50 70 50 5 100 50 100 MIN 350 1.625 125 50 50 5 15 30 50 5000 TYP MAX UNITS ns µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs Note: (1) This timing is not required under some situations. See text for more information. TABLE I. Timing Specifications (TA = –40°C to +85°C, CLOAD = 30pF). tCKP tCKH CLK tCKDS DATA tCKL tCKDH FIGURE 2. Serial Data and Clock Timing. ® ADS7835 8 clock cycle is the first of the conversion.) In addition, if CONV is completely asynchronous to CLK and CLK is continuous, there is the possibility that CLK will transition just prior to CONV going LOW. If this occurs faster than the 10ns indicated by tCKCH, there is a chance that some digital feedthrough may be coupled onto the hold capacitor. This could cause a small offset error for that particular conversion. Thus, there are two basic ways to operate the ADS7835. CONV can be synchronous to CLK and CLK can be continuous. This would be the typical situation when interfacing the converter to a digital signal processor. The second method involves having CONV asynchronous to CLK and gating the operation of CLK (a non-continuous clock). This method would be more typical of an SPI-like interface on a microcontroller. This method would also allow CONV to be generated by a trigger circuit and to initiate (after some delay) the start of CLK. These two methods are covered under the DSP Interfacing and SPI Interfacing sections of this data sheet. POWER-DOWN TIMING The conversion timing shown in Figure 3 does not result in the ADS7835 going into the power-down mode. If the conversion rate of the device is high (approaching 500kHz), there is very little power that can be saved by using the power-down mode. However, since the power-down mode incurs no conversion penalty (the very first conversion is valid) at lower sample rates, significant power can be saved by allowing the device to go into power-down mode be- tween conversions. Figure 4 shows the typical method for placing the A/D into the power-down mode. If CONV is kept LOW during the conversion and is LOW at the start of the 13th clock cycle, the device enters the power-down mode. It remains in this mode until the rising edge of CONV. Note that CONV must be HIGH for at least tACQ in order to sample the signal properly as well as to power-up the internal nodes. There are two different methods for clocking the ADS7835. The first involves scaling the CLK input in relation to the conversion rate. For example, an 8MHz input clock and the timing shown in Figure 3 results in a 500kHz conversion rate. Likewise, a 1.6MHz clock would result in a 100kHz conversion rate. The second method involves keeping the clock input as close to the maximum clock rate as possible and starting conversions as needed. This timing is similar to that shown in Figure 4. As an example, a 50kHz conversion rate would require 160 clock periods per conversion instead of the 16 clock periods used at 500kHz. The main distinction between the two is the amount of time that the ADS7835 remains in power-down. In the first mode, the converter only remains in power-down for a small number of clock periods (depending on how many clock periods there are per each conversion). As the conversion rate scales, the converter always spends the same percentage of time in power-down. Since less power is drawn by the digital logic, there is a small decrease in power consumption, but it is very slight. This effect can be seen in the tCVL CONV tCKCS tCKCH CLK 14 (1) tCVCK 15 16 1 2 3 4 11 12 13 14 15 16 1 tCKDE DATA D11 (MSB) D10 D9 D2 D1 D0 (LSB) tCKDD tACQ tCVHD SAMPLE/HOLD MODE SAMPLE (2) tCKSP HOLD SAMPLE HOLD tCONV INTERNAL CONVERSION STATE IDLE CONVERSION IN PROGRESS IDLE(3) NOTES: (1) Clock periods 14 and 15 are shown for clarity, but are not required for proper operation of the ADS7835, provided that the minimum tACQ time is met. The CLK input may remain HIGH or LOW during this period. (2) The transition from sample mode to hold mode occurs on the falling edge of CONV. This transition is not dependent on CLK. (3) The device remains fully powered when operated as shown. If the sample time is longer than 3 clock periods, power consumption can be reduced by allowing the device to enter a power-down mode. See the Power-Down Timing section for more information. FIGURE 3. Basic Conversion Timing. 9 ® ADS7835 CONV CLK 1 2 3 12 13 DATA D11 (MSB) D10 D1 D0 (LSB) tCVSP tACQ SAMPLE (3) SAMPLE/HOLD SAMPLE MODE HOLD HOLD INTERNAL CONVERSION STATE IDLE CONVERSION IN PROGRESS tCKPD IDLE tCVPU LOW POWER (1) (2) POWER MODE FULL POWER FULL POWER NOTES: (1) The low power mode (“power-down”) is entered when CONV remains LOW during the conversion and is still LOW at the start of the 13th clock cycle. (2) The low power mode is exited when CONV goes HIGH. (3) When in power-down, the transition from hold mode to sample mode is initiated by CONV going HIGH. FIGURE 4. Power-Down Timing. tCVH CONV tCKCH CLK 1 2 3 12 13 14 tCKCS DATA D11 (MSB) D10 D1 D0 (LSB) (1) 23 24 tCVDD D1 D10 D11 (MSB) LOW... (2) SAMPLE/HOLD SAMPLE MODE HOLD INTERNAL CONVERSION STATE IDLE CONVERSION IN PROGRESS tCVPD IDLE POWER MODE FULL POWER (3) LOW POWER NOTES: (1) The serial data can be transmitted LSB-first by pulling CONV LOW during the 13th clock cycle. (2) After the MSB has been transmitted, the DATA output pin will remain LOW until CONV goes HIGH. (3) When CONV is taken LOW to initiate the LSB first transfer, the converter enters the power-down mode. FIGURE 5. Serial Data “LSB-First” Timing. typical performance curve “Supply Current vs Sample Rate.” In contrast, the second method (clocking at a fixed rate) means that each conversion takes X clock cycles. As the time between conversions get longer, the converter remains ® in power-down an increasing percentage of time. This reduces total power consumption by a considerable amount. For example, a 50kHz conversion rate results in roughly 1/10 of the power (minus the reference) that is used at a ADS7835 10 500kHz conversion rate. HIGH. SHORT-CYCLE TIMING fSAMPLE 500kHz 250kHz 100kHz POWER WITH CLK = 16 • fSAMPLE 17.5mW 16.5mW 15.5mW POWER WITH CLK = 8MHz 17.5mW 13.5mW 10.5mW TABLE II. Power Consumption versus CLK Input. Table II offers a look at the two different modes of operation and the difference in power consumption. LSB-FIRST DATA TIMING Figure 5 shows a method to transmit the digital result in a LSB format. This mode is entered when CONV is pulled HIGH during the conversion (before the end of the 12th clock) and then pulled LOW during the 13th clock (when D0, the LSB, is being transmitted). The next 11 clocks then repeat the serial data, but in an LSB-first format. The converter enters the power-down mode during the 13th clock and resumes normal operation when CONV goes The conversion currently in progress can be “short-cycled” with the technique shown in Figure 6. This term means that the conversion will terminate immediately, before all 12 bits have been decided. This can be a very useful feature when a resolution of 12 bits is not needed. An example would be when the converter is being used to monitor an input voltage until some condition is met. At that time, the full resolution of the converter would then be used. Short-cycling the conversion can result in a faster conversion rate or lower power dissipation. There are several very important items shown in Figure 6. The conversion currently in progress is terminated when CONV is taken HIGH during the conversion and then taken LOW prior to tCKCH before the start of the 13th clock cycle. Note that if CONV goes LOW during the 13th clock cycle, the LSB-first mode will be entered (Figure 5). Additionally, when CONV goes LOW, the DATA output immediately transitions to high impedance. If the output bit that is present during that clock period is needed, CONV must not go LOW until the bit has been properly latched into the receiving (1) tCVL CONV tCVH CLK 1 2 3 4 5 6 7 tCVDD DATA D11 (MSB) D10 D9 D8 D7 D6 SAMPLE/HOLD MODE SAMPLE HOLD INTERNAL CONVERSION STATE IDLE CONVERSION IN PROGRESS tCVPD IDLE POWER MODE FULL POWER LOW POWER NOTE: (1) The conversion currently in progress can be stopped by pulling CONV LOW during the conversion. This must occur at least tCKCS prior to the start of the 13th clock cycle. The DATA output pin will tri-state and the device will enter the power-down mode when CONV is pulled LOW. FIGURE 6. Short-Cycle Timing. ® 11 ADS7835 logic. DATA FORMAT The ADS7835 output data is in Binary Two’s Complement format as shown in Table III. This table shows the ideal output code for the given input voltage and does not include DESCRIPTION Full-Scale Input Range Least Significant Bit (LSB)(2) +Full Scale Mid-Scale Mid-Scale –1LSB –Full Scale ANALOG INPUT –VREF to +VREF(1) (–VREF to +VREF)/4096 2.49878V 0V –0.00122V –2.49878V DIGITAL OUTPUT BINARY TWO’S COMPLEMENT BINARY HEX CODE CODE 0111 0000 1111 1000 1111 0000 1111 0000 1111 0000 1111 0000 7FF 000 FFF 800 Figure 7 shows a timing diagram that might be used with a typical digital signal processor such as a TI DSP. For the Buffered Serial Port (BSP) on the TMS320C54X family, CONV would tied to BFSX, CLK would be tied to BCLKX, and DATA would be tied to BDR. SPI/QSPI INTERFACING Figure 8 shows the timing diagram for a typical Serial Peripheral Interface (SPI) or Queued Serial Peripheral Interface (QSPI). Such interfaces are found on a number of microcontrollers from various manufacturers. CONV would be tied to a general purpose I/O pin (SPI) or to a PCX pin (QSPI), CLK would be tied to the serial clock, and DATA would be tied to the serial input data pin such as MISO (Master In Slave Out). Note the time tDRP shown in Figure 8. This represents the maximum amount of time between CONV going LOW and the start of the conversion clock. Since CONV going LOW places the S/H in the hold mode and because the hold capacitor loses charge over time, there is a requirement that time tDRP be met as well as the maximum clock period NOTES: (1) –2.5V to +2.5V when the internal reference is used. (2) 1.22mV with a 2.5V reference. TABLE III. Ideal Input Voltages and Output Codes. the effects of offset, gain, or noise. DSP INTERFACING CONV CLK 15 16 1 2 3 12 13 14 15 16 1 2 3 4 DATA D11 (MSB) D10 D1 D0 (LSB) D11 (MSB) D10 D9 FIGURE 7. Typical DSP Interface Timing. tDRP CONV tACQ CLK 1 2 3 4 13 14 15 16 1 2 3 DATA D11 (MSB) D10 D1 D0 (LSB) D11 (MSB) FIGURE 8. Typical SPI/QSPI Interface Timing. ® ADS7835 12 (tCKP). larger capacitor and a 5Ω or 10Ω series resistor may be used to lowpass filter a noisy supply. The ADS7835 draws very little current from an external reference on average as the reference voltage is internally buffered. However, glitches from the conversion process appear at the VREF input and the reference source must be able to handle this. Whether the reference is internal or external, the VREF pin should be bypassed with a 0.1µF capacitor. An additional larger capacitor may also be used, if desired. If the reference voltage is external and originates from an op amp, make sure that it can drive the bypass capacitor or capacitors without oscillation. The GND pin should be connected to a clean ground point. In many cases, this will be the “analog” ground. Avoid connections which are too near the grounding point of a microcontroller or digital signal processor. If needed, run a ground trace directly from the converter to the power supply entry point. The ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry. LAYOUT For optimum performance, care should be taken with the physical layout of the ADS7835 circuitry. This is particularly true if the CLK input is approaching the maximum input rate. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. Thus, during any single conversion for an n-bit SAR converter, there are n “windows” in which large external transient voltages can easily affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, and high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. The error can change if the external event changes in time with respect to the CLK input. With this in mind, power to the ADS7835 should be clean and well bypassed. A 0.1µF ceramic bypass capacitor should be placed as close to the device as possible. In addition, a 1µF to 10µF capacitor is recommended. If needed, an even ® 13 ADS7835