ADS7841E

® ADS 784 1 ADS7841 ADS 784 1 12-Bit, 4-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES q SINGLE SUPPLY: 2.7V to 5V q 4-CHANNEL SINGLE-ENDED OR 2-CHANNEL DIFFERENTIAL INPUT q UP TO 200kHz CONVERSION RATE q ±1 LSB MAX INL AND DNL q GUARANTEED NO MISSING CODES q 72dB SINAD q SERIAL INTERFACE q 16-PIN PDIP OR 16-LEAD SSOP PACKAGE q ALTERNATE SOURCE FOR MAX1247 DESCRIPTION The ADS7841 is a 4-channel, 12-bit sampling analogto-digital converter (ADC) with a synchronous serial interface. The resolution is programmable to either 8 or 12 bits. Typical power dissipation is 2mW at a 200kHz throughput rate and a +5V supply. The reference voltage (VREF) can be varied between 100mV and VCC, providing a corresponding input voltage range of 0V to VREF. The device includes a shutdown mode which reduces power dissipation to under 15µW. The ADS7841 is guaranteed down to 2.7V operation. Low power, high speed, and on-board multiplexer make the ADS7841 ideal for battery operated systems such as personal digital assistants, portable multichannel data loggers, and measurement equipment. The serial interface also provides low-cost isolation for remote data acquisition. The ADS7841 is available in a 16-pin PDIP or a 16-lead SSOP package and is guaranteed over the –40°C to +85°C temperature range. APPLICATIONS q DATA ACQUISITION q TEST AND MEASUREMENT q INDUSTRIAL PROCESS CONTROL q PERSONAL DIGITAL ASSISTANTS q BATTERY-POWERED SYSTEMS SAR DCLK CS CH0 CH1 CH2 CH3 COM VREF Four Channel Multiplexer CDAC Comparator Serial Interface and Control SHDN DIN DOUT MODE BUSY International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1998 Burr-Brown Corporation PDS-1420B Printed in U.S.A. June, 1998 SPECIFICATION: +5V At TA = –40°C to +85°C, +VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE = 3.2MHz, unless otherwise noted. ADS7841E, P PARAMETER ANALOG INPUT Full-Scale Input Span Absolute Input Range Capacitance Leakage Current SYSTEM PERFORMANCE Resolution No Missing Codes Integral Linearity Error Differential Linearity Error Offset Error Offset Error Match Gain Error Gain Error Match Noise Power Supply Rejection SAMPLING DYNAMICS Conversion Time Acquisition Time Throughput Rate Multiplexer Settling Time Aperture Delay Aperture Jitter DYNAMIC CHARACTERISTICS Total Harmonic Distortion(2) Signal-to-(Noise + Distortion) Spurious Free Dynamic Range Channel-to-Channel Isolation REFERENCE INPUT Range Resistance Input Current VIN VIN VIN VIN = = = = 5Vp-p 5Vp-p 5Vp-p 5Vp-p at at at at 10kHz 10kHz 10kHz 50kHz CONDITIONS MIN TYP MAX MIN T T T T T T 12 ±0.8 0.15 0.1 30 70 ±2 ±3 1.0 ±4 1.0 ±0.5 T T T T ±1 ±1 T T ±3 T ADS7841EB, PB TYP MAX T T T UNITS Positive Input - Negative Input Positive Input Negative Input 0 –0.2 –0.2 25 ±1 12 12 VREF +VCC +0.2 +1.25 V V V pF µA Bits Bits LSB(1) LSB LSB LSB LSB LSB µVrms dB Clk Cycles Clk Cycles kHz ns ns ps dB dB dB dB V GΩ µA µA µA 12 3 200 500 30 100 –78 71 79 120 –72 70 76 T T T –80 72 81 T T T T –76 68 72 0.1 DCLK Static fSAMPLE = 12.5kHz DCLK Static 5 40 2.5 0.001 CMOS | IIH | ≤ +5µA | IIL | ≤ +5µA IOH = –250µA IOL = 250µA 3.0 –0.3 3.5 Straight Binary Specified Performance f SAMPLE = 12.5kHz Power-Down Mode(3), CS = +VCC 4.75 550 300 +VCC 100 3 T T T T T T T T T DIGITAL INPUT/OUTPUT Logic Family Logic Levels VIH VIL VOH VOL Data Format POWER SUPPLY REQUIREMENTS +VCC Quiescent Current 5.5 +0.8 0.4 T T T T T T T V V V V 5.25 900 3 4.5 T T T T T T Power Dissipation TEMPERATURE RANGE Specified Performance T Same specifications as ADS7841E, P. –40 V µA µA µA mW °C +85 T T NOTE: (1) LSB means Least Significant Bit. With VREF equal to +5.0V, one LSB is 1.22mV. (2) First five harmonics of the test frequency. (3) Auto power-down mode (PD1 = PD0 = 0) active or SHDN = GND. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® ADS7841 2 SPECIFICATION: +2.7V At TA = –40°C to +85°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted. ADS7841E, P PARAMETER ANALOG INPUT Full-Scale Input Span Absolute Input Range Capacitance Leakage Current SYSTEM PERFORMANCE Resolution No Missing Codes Integral Linearity Error Differential Linearity Error Offset Error Offset Error Match Gain Error Gain Error Match Noise Power Supply Rejection SAMPLING DYNAMICS Conversion Time Acquisition Time Throughput Rate Multiplexer Settling Time Aperture Delay Aperture Jitter DYNAMIC CHARACTERISTICS Total Harmonic Distortion(2) Signal-to-(Noise + Distortion) Spurious Free Dynamic Range Channel-to-Channel Isolation REFERENCE INPUT Range Resistance Input Current VIN VIN VIN VIN = = = = 2.5Vp-p 2.5Vp-p 2.5Vp-p 2.5Vp-p at at at at 10kHz 10kHz 10kHz 50kHz CONDITIONS MIN TYP MAX MIN T T T T T T 12 ±0.8 0.15 0.1 30 70 ±2 ±3 1.0 ±4 1.0 ±0.5 T T T T ±1 ±1 T T ±3 T ADS7841EB, PB TYP MAX T T T UNITS Positive Input - Negative Input Positive Input Negative Input 0 –0.2 –0.2 25 ±1 12 12 VREF +VCC +0.2 +0.2 V V V pF µA Bits Bits LSB(1) LSB LSB LSB LSB LSB µVrms dB Clk Cycles Clk Cycles kHz ns ns ps dB dB dB dB V GΩ µA µA µA 12 3 125 500 30 100 –77 71 78 100 –72 70 76 T T T –79 72 80 T T T T –76 68 72 0.1 DCLK Static fSAMPLE = 12.5kHz DCLK Static 5 13 2.5 0.001 CMOS | IIH | ≤ +5µA | IIL | ≤ +5µA IOH = –250µA IOL = 250µA +VCC • 0.7 –0.3 +VCC • 0.8 Straight Binary Specified Performance fSAMPLE = 12.5kHz Power-Down Mode(3), CS = +VCC 2.7 280 220 +VCC 40 3 T T T T T T T T T DIGITAL INPUT/OUTPUT Logic Family Logic Levels VIH VIL VOH VOL Data Format POWER SUPPLY REQUIREMENTS +VCC Quiescent Current 5.5 +0.8 0.4 T T T T T T T V V V V 3.6 650 3 1.8 T T T T T T T Power Dissipation TEMPERATURE RANGE Specified Performance T Same specifications as ADS7841E, P. –40 V µA µA µA mW °C +85 T T NOTE: (1) LSB means Least Significant Bit. With VREF equal to +2.5V, one LSB is 610mV. (2) First five harmonics of the test frequency. (3) Auto power-down mode (PD1 = PD0 = 0) active or SHDN = GND. ® 3 ADS7841 PIN CONFIGURATIONS Top View DIP SSOP +VCC CH0 CH1 CH2 CH3 COM SHDN VREF 1 2 3 4 5 6 7 8 ADS7841 16 15 14 13 12 11 10 9 DCLK CS DIN BUSY DOUT MODE GND +VCC +VCC CH0 CH1 CH2 CH3 COM SHDN VREF 1 2 3 4 5 6 7 8 ADS7841 16 15 14 13 12 11 10 9 DCLK CS DIN BUSY DOUT MODE GND +VCC PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME +VCC CH0 CH1 CH2 CH3 COM SHDN VREF +VCC GND MODE DOUT BUSY DIN CS DCLK DESCRIPTION Power Supply, 2.7V to 5V. Analog Input Channel 0. Analog Input Channel 1. Analog Input Channel 2. Analog Input Channel 3. Ground Reference for Analog Inputs. Sets zero code voltage in single-ended mode. Connect this pin to ground or ground reference point. Shutdown. When LOW, the device enters a very low power shutdown mode. Voltage Reference Input Power Supply, 2.7V to 5V. Ground Conversion Mode. When LOW, the device always performs a 12-bit conversion. When HIGH, the resolution is set by the MODE bit in the CONTROL byte. Serial Data Output. Data is shifted on the falling edge of DCLK. This output is high impedance when CS is HIGH. Busy Output. This output is high impedance when CS is HIGH. Serial Data Input. If CS is LOW, data is latched on rising edge of DCLK. Chip Select Input. Controls conversion timing and enables the serial input/output register. External Clock Input. This clock runs the SAR conversion process and synchronizes serial data I/O. ABSOLUTE MAXIMUM RATINGS(1) +VCC to GND ......................................................................... –0.3V to +6V Analog Inputs to GND ............................................ –0.3V to +VCC + 0.3V Digital Inputs to GND ........................................................... –0.3V to +6V Power Dissipation .......................................................................... 250mW Maximum Junction Temperature ................................................... +150°C Operating Temperature Range ....................................... –40°C to +85°C Storage Temperature Range ......................................... –65°C to +150°C Lead Temperature (soldering, 10s) ............................................... +300°C NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE DRAWING NUMBER(1) 322 " 180 322 " 180 PACKAGE/ORDERING INFORMATION MINIMUM RELATIVE ACCURACY (LSB) ±2 " ±2 ±1 " ±1 DIFFERENTIAL NONLINEARITY (LSB) 68 " 68 70 " 70 SPECIFICATION TEMPERATURE RANGE –40°C to " –40°C to –40°C to " –40°C to +85°C +85°C +85°C +85°C PRODUCT ADS7841E " ADS7841P ADS7841EB " ADS7841PB PACKAGE 16-Lead SSOP " 16-Pin PDIP 16-Lead SSOP " 16-Pin PDIP ORDERING NUMBER(2) ADS7841E ADS7841E/2K5 ADS7841P ADS7841EB ADS7841EB/2K5 ADS7841PB TRANSPORT MEDIA Rails Tape and Reel Rails Rails Tape and Reel Rails NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “ADS7841/2K5” will get a single 2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book. ® ADS7841 4 TYPICAL PERFORMANCE CURVES:+5V At TA = +25°C, +VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE = 3.2MHz, unless otherwise noted. FREQUENCY SPECTRUM (4096 Point FFT; fIN = 1,123Hz, –0.2dB) 0 –20 Amplitude (dB) FREQUENCY SPECTRUM (4096 Point FFT; fIN = 10.3kHz, –0.2dB) 0 –20 –40 –60 –80 –100 –120 Amplitude (dB) –40 –60 –80 –100 –120 0 25 50 Frequency (kHz) 75 100 0 25 50 Frequency (kHz) 75 100 SIGNAL-TO-NOISE RATIO AND SIGNAL-TO(NOISE+DISTORTION) vs INPUT FREQUENCY 74 SNR 73 SNR and SINAD (dB) 80 85 SPURIOUS FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY –85 SFDR –80 72 SFDR (dB) SINAD 71 70 75 THD –75 70 –70 69 68 1 10 Input Frequency (kHz) 100 65 1 10 Input Frequency (kHz) –65 100 EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY 12.0 CHANGE IN SIGNAL-TO-(NOISE+DISTORTION) vs TEMPERATURE 0.6 0.4 Delta from +25°C (dB) Effective Number of Bits 11.8 0.2 0.0 –0.2 –0.4 fIN = 10kHz, –0.2dB –0.6 11.6 11.4 11.2 11.0 1 10 Input Frequency (kHz) 100 –40 –20 0 20 40 60 80 100 Temperature (°C) ® 5 ADS7841 THD (dB) TYPICAL PERFORMANCE CURVES:+2.7V At TA = +25°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted. FREQUENCY SPECTRUM (4096 Point FFT; fIN = 1,129Hz, –0.2dB) 0 –20 Amplitude (dB) FREQUENCY SPECTRUM (4096 Point FFT; fIN = 10.6kHz, –0.2dB) 0 –20 –40 –60 –80 –100 –120 Amplitude (dB) –40 –60 –80 –100 –120 0 15.6 31.3 Frequency (kHz) 46.9 62.5 0 15.6 31.3 Frequency (kHz) 46.9 62.5 SIGNAL-TO-NOISE RATIO AND SIGNAL-TO(NOISE+DISTORTION) vs INPUT FREQUENCY 78 SNR 74 SPURIOUS FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY 90 85 SFDR 80 –80 –75 –70 THD 65 60 –65 –60 –55 –50 1 10 Input Frequency (kHz) 100 75 70 –90 –85 SNR and SINAD (dB) 70 SFDR (dB) 66 SINAD 62 58 54 1 10 Input Frequency (kHz) 100 55 50 EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY 12.0 11.5 Effective Number of Bits CHANGE IN SIGNAL-TO-(NOISE+DISTORTION) vs TEMPERATURE 0.4 fIN = 10kHz, –0.2dB 0.2 Delta from +25°C (dB) 11.0 10.5 10.0 9.5 9.0 1 10 Input Frequency (kHz) 100 0.0 –0.2 –0.4 –0.6 –0.8 –40 –20 0 20 40 60 80 100 Temperature (˚C) ® ADS7841 6 THD (dB) TYPICAL PERFORMANCE CURVES:+2.7V (CONT) At TA = +25°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted. SUPPLY CURRENT vs TEMPERATURE 400 350 Supply Current (µA) 140 120 POWER DOWN SUPPLY CURRENT vs TEMPERATURE 300 250 200 150 100 –40 –20 0 20 40 60 80 100 Temperature (˚C) Supply Current (nA) 100 80 60 40 20 –40 –20 0 20 40 60 80 100 Temperature (˚C) INTEGRAL LINEARITY ERROR vs CODE 1.00 0.75 0.50 ILE (LSB) 1.00 0.75 0.50 DIFFERENTIAL LINEARITY ERROR vs CODE 0.25 0.00 –0.25 –0.50 –0.75 –1.00 000H DLE (LSB) 800H Output Code FFFH 0.25 0.00 –0.25 –0.50 –0.75 –1.00 000H 800H Output Code FFFH CHANGE IN GAIN vs TEMPERATURE 0.15 0.10 CHANGE IN OFFSET vs TEMPERATURE 0.6 0.4 Delta from +25˚C (LSB) 0.05 0.00 –0.05 –0.10 –0.15 –40 –20 0 20 40 60 80 100 Temperature (˚C) Delta from +25˚C (LSB) 0.2 0.0 –0.2 –0.4 –0.6 –40 –20 0 20 40 60 80 100 Temperature (˚C) ® 7 ADS7841 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted. REFERENCE CURRENT vs SAMPLE RATE 14 12 Reference Current (µA) REFERENCE CURRENT vs TEMPERATURE 18 16 Reference Current (µA) 10 8 6 4 2 0 0 25 50 75 100 125 Sample Rate (kHz) 14 12 10 8 6 –40 –20 0 20 40 60 80 100 Temperature (˚C) SUPPLY CURRENT vs +VCC 320 300 fSAMPLE = 12.5kHz MAXIMUM SAMPLE RATE vs +VCC 1M Supply Current (µA) Sample Rate (Hz) 280 VREF = +VCC 260 240 220 200 180 2 2.5 3 3.5 +VCC (V) 4 4.5 5 100k 10k VREF = +VCC 1k 2 2.5 3 3.5 +VCC (V) 4 4.5 5 ® ADS7841 8 THEORY OF OPERATION The ADS7841 is a classic successive approximation register (SAR) analog-to-digital (A/D) converter. The architecture is based on capacitive redistribution which inherently includes a sample/hold function. The converter is fabricated on a 0.6µs CMOS process. The basic operation of the ADS7841 is shown in Figure 1. The device requires an external reference and an external clock. It operates from a single supply of 2.7V to 5.25V. The external reference can be any voltage between 100mV and +VCC. The value of the reference voltage directly sets the input range of the converter. The average reference input current depends on the conversion rate of the ADS7841. The analog input to the converter is differential and is provided via a four-channel multiplexer. The input can be provided in reference to a voltage on the COM pin (which is generally ground) or differentially by using two of the four input channels (CH0 - CH3). The particular configuration is selectable via the digital interface. ANALOG INPUT Figure 2 shows a block diagram of the input multiplexer on the ADS7841. The differential input of the converter is derived from one of the four inputs in reference to the COM pin or two of the four inputs. Table I and Table II show the relationship between the A2, A1, A0, and SGL/DIF control bits and the configuration of the analog multiplexer. The control bits are provided serially via the DIN pin, see the Digital Interface section of this data sheet for more details. When the converter enters the hold mode, the voltage difference between the +IN and –IN inputs (see Figure 2) is captured on the internal capacitor array. The voltage on the –IN input is limited between –0.2V and 1.25V, allowing the input to reject small signals which are common to both the +IN and –IN input. The +IN input has a range of –0.2V to +VCC + 0.2V. The input current on the analog inputs depends on the conversion rate of the device. During the sample period, the source must charge the internal sampling capacitor (typically 25pF). After the capacitor has been fully charged, there is no further input current. The rate of charge transfer from the analog source to the converter is a function of conversion rate. A2 0 1 0 1 A1 0 0 1 1 A0 1 1 0 0 CH0 +IN +IN +IN +IN CH1 CH2 CH3 COM –IN –IN –IN –IN TABLE I. Single-Ended Channel Selection (SGL/DIF HIGH). A2 0 1 0 1 A1 0 0 1 1 A0 1 1 0 0 CH0 +IN –IN CH1 –IN +IN +IN –IN –IN +IN CH2 CH3 COM TABLE II. Differential Channel Control (SGL/DIF LOW). A2-A0 (Shown 001B) CH0 CH1 CH2 CH3 +IN Converter –IN COM SGL/DIF (Shown HIGH) FIGURE 2. Simplified Diagram of the Analog Input. +2.7V to +5V ADS7841 1µF + to 10µF 0.1µF 1 2 Single-ended or differential analog inputs 3 4 5 6 7 8 0.1µF +VCC CH0 CH1 CH2 CH3 COM SHDN VREF DCLK 16 CS 15 DIN 14 BUSY 13 DOUT 12 MODE 11 GND 10 +VCC 9 Serial Data Out Serial/Conversion Clock Chip Select Serial Data In FIGURE 1. Basic Operation of the ADS7841. ® 9 ADS7841 REFERENCE INPUT The external reference sets the analog input range. The ADS7841 will operate with a reference in the range of 100mV to +VCC. Keep in mind that the analog input is the difference between the +IN input and the –IN input as shown in Figure 2. For example, in the single-ended mode, a 1.25V reference, and with the COM pin grounded, the selected input channel (CH0 - CH3) will properly digitize a signal in the range of 0V to 1.25V. If the COM pin is connected to 0.5V, the input range on the selected channel is 0.5V to 1.75V. There are several critical items concerning the reference input and its wide voltage range. As the reference voltage is reduced, the analog voltage weight of each digital output code is also reduced. This is often referred to as the LSB (least significant bit) size and is equal to the reference voltage divided by 4096. Any offset or gain error inherent in the A/D converter will appear to increase, in terms of LSB size, as the reference voltage is reduced. For example, if the offset of a given converter is 2 LSBs with a 2.5V reference, then it will typically be 10 LSBs with a 0.5V reference. In each case, the actual offset of the device is the same, 1.22mV. Likewise, the noise or uncertainty of the digitized output will increase with lower LSB size. With a reference voltage of 100mV, the LSB size is 24µV. This level is below the internal noise of the device. As a result, the digital output code will not be stable and vary around a mean value by a number of LSBs. The distribution of output codes will be gaussian and the noise can be reduced by simply averaging consecutive conversion results or applying a digital filter. With a lower reference voltage, care should be taken to provide a clean layout including adequate bypassing, a clean (low noise, low ripple) power supply, a low-noise reference, and a low-noise input signal. Because the LSB size is lower, the converter will also be more sensitive to nearby digital signals and electromagnetic interference. The voltage into the VREF input is not buffered and directly drives the capacitor digital-to-analog converter (CDAC) portion of the ADS7841. Typically, the input current is 13µA with a 2.5V reference. This value will vary by microamps depending on the result of the conversion. The reference current diminishes directly with both conversion rate and reference voltage. As the current from the reference is drawn on each bit decision, clocking the converter more quickly during a given conversion period will not reduce overall current drain from the reference. DIGITAL INTERFACE Figure 3 shows the typical operation of the ADS7841’s digital interface. This diagram assumes that the source of the digital signals is a microcontroller or digital signal processor with a basic serial interface (note that the digital inputs are over-voltage tolerant up to 5.5V, regardless of +VCC). Each communication between the processor and the converter consists of eight clock cycles. One complete conversion can be accomplished with three serial communications, for a total of 24 clock cycles on the DCLK input. ® The first eight clock cycles are used to provide the control byte via the DIN pin. When the converter has enough information about the following conversion to set the input multiplexer appropriately, it enters the acquisition (sample) mode. After three more clock cycles, the control byte is complete and the converter enters the conversion mode. At this point, the input sample/hold goes into the hold mode. The next twelve clock cycles accomplish the actual analogto-digital conversion. A thirteenth clock cycle is needed for the last bit of the conversion result. Three more clock cycles are needed to complete the last byte (DOUT will be LOW). These will be ignored by the converter. Control Byte Also shown in Figure 3 is the placement and order of the control bits within the control byte. Tables III and IV give detailed information about these bits. The first bit, the ‘S’ bit, must always be HIGH and indicates the start of the control byte. The ADS7841 will ignore inputs on the DIN pin until the start bit is detected. The next three bits (A2 - A0) select the active input channel or channels of the input multiplexer (see Tables I and II and Figure 2). The MODE bit and the MODE pin work together to determine the number of bits for a given conversion. If the MODE pin is LOW, the converter always performs a 12-bit conversion regardless of the state of the MODE bit. If the MODE pin is HIGH, then the MODE bit determines the number of bits for each conversion, either 12 bits (LOW) or 8 bits (HIGH). Bit 7 (MSB) S Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) PD0 A2 A1 A0 MODE SGL/DIF PD1 TABLE III. Order of the Control Bits in the Control Byte. BIT 7 NAME S DESCRIPTION Start Bit. Control byte starts with first HIGH bit on DIN. A new control byte can start every 15th clock cycle in 12-bit conversion mode or every 11th clock cycle in 8-bit conversion mode. Channel Select Bits. Along with the SGL/DIF bit, these bits control the setting of the multiplexer input as detailed in Tables I and II. 12-Bit/8-Bit Conversion Select Bit. If the MODE pin is HIGH, this bit controls the number of bits for the next conversion: 12-bits (LOW) or 8-bits (HIGH). If the MODE pin is LOW, this bit has no function and the conversion is always 12 bits. Single-Ended/Differential Select Bit. Along with bits A2 - A0, this bit controls the setting of the multiplexer input as detailed in Tables I and II. Power-Down Mode Select Bits. See Table V for details. 6-4 A2 - A0 3 MODE 2 SGL/DIF 1-0 PD1 - PD0 TABLE IV. Descriptions of the Control Bits within the Control Byte. ADS7841 10 CS tACQ DCLK 1 8 1 8 1 8 DIN S A2 A1 Idle SGL/ A0 MODE DIF PD1 PD0 Acquire Conversion Idle (START) BUSY DOUT 11 (MSB) 10 9 8 7 6 5 4 3 2 1 0 (LSB) Zero Filled... FIGURE 3. Conversion Timing, 24-Clocks per Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated serial port. CS DCLK 1 8 1 8 1 8 1 DIN S CONTROL BITS S CONTROL BITS BUSY DOUT 11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 FIGURE 4. Conversion Timing, 16-Clocks per Conversion, 8-bit Bus Interface. No DCLK delay required with dedicated serial port. CS tCSS tCH tCL tBD tBD tD0 tCSH DCLK tDS tDH PD0 tBDV tBTR DIN BUSY tDV tTR 11 10 DOUT FIGURE 5. Detailed Timing Diagram. ® 11 ADS7841 The SGL/DIF bit controls the multiplexer input mode: either single-ended (HIGH) or differential (LOW). In single-ended mode, the selected input channel is referenced to the COM pin. In differential mode, the two selected inputs provide a differential input. See Tables I and II and Figure 2 for more information. The last two bits (PD1 - PD0) select the powerdown mode as shown in Table V. If both inputs are HIGH, the device is always powered up. If both inputs are LOW, the device enters a power-down mode between conversions. When a new conversion is initiated, the device will resume normal operation instantly—no delay is needed to allow the device to power up and the very first conversion will be valid. 16-Clocks per Conversion The control bits for conversion n+1 can be overlapped with conversion ‘n’ to allow for a conversion every 16 clock cycles, as shown in Figure 4. This figure also shows possible serial communication occurring with other serial peripherals between each byte transfer between the processor and the converter. This is possible provided that each conversion completes within 1.6ms of starting. Otherwise, the signal that has been captured on the input sample/hold may droop enough to affect the conversion result. In addition, the ADS7841 is fully powered while other serial communications are taking place. Digital Timing PD1 0 PD0 0 Description Power-down between conversions. When each conversion is finished, the converter enters a low power mode. At the start of the next conversion, the device instantly powers up to full power. There is no need for additional delays to assure full operation and the very first conversion is valid. Reserved for future use. Reserved for future use. No power-down between conversions, device always powered. 0 1 1 1 0 1 TABLE V. Power-Down Selection. SYMBOL tACQ tDS tDH tDO tDV tTR tCSS tCSH tCH tCL tBD tBDV tBTR DESCRIPTION Acquisition Time DIN Valid Prior to DCLK Rising DIN Hold After DCLK HIGH DCLK Falling to DOUT Valid CS Falling to DOUT Enabled CS Rising to DOUT Disabled CS Falling to First DCLK Rising CS Rising to DCLK Ignored DCLK HIGH DCLK LOW DCLK Falling to BUSY Rising CS Falling to BUSY Enabled CS Rising to BUSY Disabled 100 0 200 200 200 200 200 MIN 1.5 100 10 200 200 200 TYP MAX UNITS µs ns ns ns ns ns ns ns ns ns ns ns ns TABLE VI. Timing Specifications (+VCC = +2.7V to 3.6V, TA = –40°C to +85°C, CLOAD = 50pF). SYMBOL DESCRIPTION Acquisition Time DIN Valid Prior to DCLK Rising DIN Hold After DCLK HIGH DCLK Falling to DOUT Valid CS Falling to DOUT Enabled CS Rising to DOUT Disabled CS Falling to First DCLK Rising CS Rising to DCLK Ignored DCLK HIGH DCLK LOW DCLK Falling to BUSY Rising CS Falling to BUSY Enabled CS Rising to BUSY Disabled 50 0 150 150 100 70 70 MIN 900 50 10 100 70 70 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 5 and Tables VI and VII provide detailed timing for the digital interface of the ADS7841. 15-Clocks per Conversion Figure 6 provides the fastest way to clock the ADS7841. This method will not work with the serial interface of most microcontrollers and digital signal processors as they are generally not capable of providing 15 clock cycles per serial transfer. However, this method could be used with field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs). Note that this effectively increases the maximum conversion rate of the converter beyond the values given in the specification tables, which assume 16 clock cycles per conversion. tACQ tDS tDH tDO tDV tTR tCSS tCSH tCH tCL tBD tBDV tBTR TABLE VII. Timing Specifications (+VCC = +4.75V to +5.25V, TA = –40°C to +85°C, CLOAD = 50pF). CS DCLK 1 A2 A1 A0 MODE SGL/ PD1 PD0 DIF 15 1 A2 A1 A0 MODE SGL/ PD1 PD0 DIF 15 1 DIN S S S A2 A1 A0 BUSY DOUT 11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 8 7 6 5 4 3 2 FIGURE 6. Maximum Conversion Rate, 15-Clocks per Conversion. ® ADS7841 12 Data Format The ADS7841 output data is in straight binary format as shown in Figure 7. This figure shows the ideal output code for the given input voltage and does not include the effects of offset, gain, or noise. FS = Full-Scale Voltage = VREF 1 LSB = VREF/4096 1 LSB 11...111 11...110 Output Code remain approximately equal. However, if the DCLK frequency is kept at the maximum rate during a conversion, but conversion are simply done less often, then the difference between the two modes is dramatic. Figure 8 shows the difference between reducing the DCLK frequency (“scaling” DCLK to match the conversion rate) or maintaining DCLK at the highest frequency and reducing the number of conversion per second. In the later case, the converter spends an increasing percentage of its time in power-down mode (assuming the auto power-down mode is active). If DCLK is active and CS is LOW while the ADS7841 is in auto power-down mode, the device will continue to dissipate some power in the digital logic. The power can be reduced to a minimum by keeping CS HIGH. The differences in supply current for these two cases are shown in Figure 9. Operating the ADS7841 in auto power-down mode will result in the lowest power dissipation, and there is no conversion time “penalty” on power-up. The very first conversion will be valid. SHDN can be used to force an immediate power-down. 11...101 00...010 00...001 00...000 0V Input Voltage(1) (V) Note 1: Voltage at converter input, after multiplexer: +IN–(–IN). See Figure 2. FS – 1 LSB FIGURE 7. Ideal Input Voltages and Output Codes. 8-Bit Conversion The ADS7841 provides an 8-bit conversion mode that can be used when faster throughput is needed and the digital result is not as critical. By switching to the 8-bit mode, a conversion is complete four clock cycles earlier. This could be used in conjunction with serial interfaces that provide a 12-bit transfer or two conversions could be accomplished with three 8-bit transfers. Not only does this shorten each conversion by four bits (25% faster throughput), but each conversion can actually occur at a faster clock rate. This is because the internal settling time of the ADS7841 is not as critical, settling to better than 8 bits is all that is needed. The clock rate can be as much as 50% faster. The faster clock rate and fewer clock cycles combine to provide a 2x increase in conversion rate. POWER DISSIPATION There are three power modes for the ADS7841: full power (PD1 - PD0 = 11B), auto power-down (PD1 - PD0 = 00B), and shutdown (SHDN LOW). The affects of these modes varies depending on how the ADS7841 is being operated. For example, at full conversion rate and 16 clocks per conversion, there is very little difference between full power mode and auto power-down. Likewise, if the device has entered auto power-down, a shutdown (SHDN LOW) will not lower power dissipation. When operating at full-speed and 16-clocks per conversion (as shown in Figure 4), the ADS7841 spends most of its time acquiring or converting. There is little time for auto powerdown, assuming that this mode is active. Thus, the difference between full power mode and auto power-down is negligible. If the conversion rate is decreased by simply slowing the frequency of the DCLK input, the two modes 13 Supply Current (µA) 1000 fCLK = 16 • fSAMPLE 100 10 fCLK = 2MHz TA = 25°C +VCC = +2.7V VREF = +2.5V PD1 = PD0 = 0 1k 10k fSAMPLE (Hz) 100k 1M 1 FIGURE 8. Supply Current vs Directly Scaling the Frequency of DCLK with Sample Rate or Keeping DCLK at the Maximum Possible Frequency. 14 12 Supply Current (µA) 10 8 6 4 2 0 0.09 0.00 1k TA = 25°C +VCC = +2.7V VREF = +2.5V fCLK = 16 • fSAMPLE PD1 = PD0 = 0 CS LOW (GND) CS HIGH (+VCC) 10k fSAMPLE (Hz) 100k 1M FIGURE 9. Supply Current vs State of CS. ® ADS7841 LAYOUT For optimum performance, care should be taken with the physical layout of the ADS7841 circuitry. This is particularly true if the reference voltage is low and/or the conversion rate is high. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. Thus, during any single conversion for an n-bit SAR converter, there are n “windows” in which large external transient voltages can easily affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, and high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. The error can change if the external event changes in time with respect to the DCLK input. With this in mind, power to the ADS7841 should be clean and well bypassed. A 0.1µF ceramic bypass capacitor should be placed as close to the device as possible. In addition, a 1µF to 10µF capacitor and a 5Ω or 10Ω series resistor may be used to lowpass filter a noisy supply. The reference should be similarly bypassed with a 0.1µF capacitor. Again, a series resistor and large capacitor can be used to lowpass filter the reference voltage. If the reference voltage originates from an op amp, make sure that it can drive the bypass capacitor without oscillation (the series resistor can help in this case). The ADS7841 draws very little current from the reference on average, but it does place larger demands on the reference circuitry over short periods of time (on each rising edge of DCLK during a conversion). The ADS7841 architecture offers no inherent rejection of noise or voltage variation in regards to the reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply will appear directly in the digital results. While high frequency noise can be filtered out as discussed in the previous paragraph, voltage variation due to line frequency (50Hz or 60Hz) can be difficult to remove. The GND pin should be connected to a clean ground point. In many cases, this will be the “analog” ground. Avoid connections which are too near the grounding point of a microcontroller or digital signal processor. If needed, run a ground trace directly from the converter to the power supply entry point. The ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry. ® ADS7841 14