ADS
784
4
ADS7844
ADS
784
4
SBAS100A – JANUARY 1998 – REVISED OCTOBER 2003
12-Bit, 8-Channel Serial Output Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
● SINGLE SUPPLY: 2.7V to 5V
The ADS7844 is an 8-channel, 12-bit sampling analog-todigital converter (ADC) with a synchronous serial interface.
Typical power dissipation is 3mW at a 200kHz throughput
rate and a +5V supply. The reference voltage (VREF) can be
varied between 100mV and VCC, providing a corresponding
input voltage range of 0V to VREF. The device includes a
shutdown mode that reduces power dissipation to under
1µW. The ADS7844 is ensured down to 2.7V operation.
● 8-CHANNEL SINGLE-ENDED OR
4-CHANNEL DIFFERENTIAL INPUT
● UP TO 200kHz CONVERSION RATE
●
●
●
●
●
±1 LSB MAX INL AND DNL
NO MISSING CODES
72dB SINAD
SERIAL INTERFACE
20-LEAD QSOP AND
20-LEAD SSOP PACKAGES
● ALTERNATE SOURCE FOR MAX147
Low power, high speed, and onboard multiplexer make the
ADS7844 ideal for battery-operated systems such as personal
digital assistants, portable multichannel data loggers, and
measurement equipment. The serial interface also provides
low-cost isolation for remote data acquisition. The ADS7844
is available in a 20-lead QSOP package and the MAX147
equivalent 20-lead SSOP package and is ensured over the
–40°C to +85°C temperature range.
APPLICATIONS
●
●
●
●
●
DATA ACQUISITION
TEST AND MEASUREMENT
INDUSTRIAL PROCESS CONTROL
PERSONAL DIGITAL ASSISTANTS
BATTERY-POWERED SYSTEMS
CH0
SAR
CH1
DCLK
CH2
CH3
CH4
Eight
Channel
Multiplexer
CS
Comparator
Serial
Interface
and
Control
CH5
CH6
CDAC
CH7
COM
SHDN
DIN
DOUT
BUSY
VREF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright © 1998-2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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SPECIFICATION: +5V
At TA = –40°C to +85°C, +VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE = 3.2MHz, unless otherwise noted.
ADS7844E, N
PARAMETER
ANALOG INPUT
Full-Scale Input Span
Absolute Input Range
CONDITIONS
MIN
Positive Input - Negative Input
Positive Input
Negative Input
0
–0.2
–0.2
TYP
Capacitance
Leakage Current
VREF
+VCC +0.2
+1.25
✻
✻
✻
TYP
0.15
0.1
30
70
±2
±0.5
±3
1.0
±4
1.0
✻
✻
✻
✻
REFERENCE INPUT
Range
Resistance
Input Current
10kHz
10kHz
10kHz
50kHz
500
30
100
✻
✻
✻
–76
71
76
120
–78
72
78
✻
dB
dB
dB
dB
+VCC
5
45
2.5
0.001
fSAMPLE = 12.5kHz
DCLK Static
✻
✻
3.0
–0.3
3.5
100
3
5.5
+0.8
✻
✻
✻
4.75
550
300
fSAMPLE = 12.5kHz
Power-Down Mode(3), CS = +VCC
✻
–40
V
V
V
V
✻
5.25
900
✻
✻
✻
✻
✻
V
µA
µA
µA
mW
✻
°C
✻
3
4.5
Power Dissipation
✻
✻
✻
0.4
Specified Performance
✻
V
GΩ
µA
µA
µA
✻
Straight Binary
TEMPERATURE RANGE
Specified Performance
✻
✻
✻
✻
✻
CMOS
| IIH | ≤ +5µA
| IIL | ≤ +5µA
IOH = –250µA
IOL = 250µA
Bits
Bits
LSB(1)
LSB
LSB
LSB
LSB
LSB
µVrms
dB
Clk Cycles
Clk Cycles
kHz
ns
ns
ps
0.1
DCLK Static
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels
VIH
VIL
VOH
VOL
Data Format
±1
±1
✻
✻
±3
✻
✻
200
at
at
at
at
V
V
V
pF
µA
✻
12
3
5VPP
5VPP
5VPP
5VPP
✻
✻
✻
✻
±0.8
=
=
=
=
UNITS
✻
12
VIN
VIN
VIN
VIN
MAX
✻
✻
12
SAMPLING DYNAMICS
Conversion Time
Acquisition Time
Throughput Rate
Multiplexer Settling Time
Aperture Delay
Aperture Jitter
POWER SUPPLY REQUIREMENTS
+VCC
Quiescent Current
MIN
25
±1
SYSTEM PERFORMANCE
Resolution
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Offset Error
Offset Error Match
Gain Error
Gain Error Match
Noise
Power Supply Rejection
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion(2)
Signal-to-(Noise + Distortion)
Spurious Free Dynamic Range
Channel-to-Channel Isolation
ADS7844EB, NB
MAX
+85
✻
✻ Same specifications as ADS7844E, ADS7844N.
NOTE: (1) LSB means Least Significant Bit. With VREF equal to +5.0V, one LSB is 1.22mV. (2) First five harmonics of the test frequency. (3) Auto power-down mode
(PD1 = PD0 = 0) active or SHDN = GND.
2
ADS7844
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SBAS100A
SPECIFICATION: +2.7V
At TA = –40°C to +85°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted.
ADS7844E, N
PARAMETER
ANALOG INPUT
Full-Scale Input Span
Absolute Input Range
CONDITIONS
MIN
Positive Input - Negative Input
Positive Input
Negative Input
0
–0.2
–0.2
TYP
Capacitance
Leakage Current
VREF
+VCC +0.2
+0.2
✻
✻
✻
TYP
0.15
0.1
30
70
±2
±0.5
±3
1.0
±4
1.0
✻
✻
✻
✻
REFERENCE INPUT
Range
Resistance
Input Current
10kHz
10kHz
10kHz
50kHz
500
30
100
✻
✻
✻
–75
71
78
100
–77
72
80
✻
dB
dB
dB
dB
+VCC
5
13
2.5
0.001
fSAMPLE = 12.5kHz
DCLK Static
✻
✻
+VCC • 0.7
–0.3
+VCC • 0.8
40
3
5.5
+0.8
✻
✻
✻
2.7
280
220
fSAMPLE = 12.5kHz
Power-Down Mode(3), CS = +VCC
✻
–40
V
V
V
V
✻
3.6
650
✻
✻
✻
3
1.8
Power Dissipation
✻
✻
✻
0.4
Specified Performance
✻
V
GΩ
µA
µA
µA
✻
Straight Binary
TEMPERATURE RANGE
Specified Performance
✻
✻
✻
✻
✻
CMOS
| IIH | ≤ +5µA
| IIL | ≤ +5µA
IOH = –250µA
IOL = 250µA
Bits
Bits
LSB(1)
LSB
LSB
LSB
LSB
LSB
µVrms
dB
Clk Cycles
Clk Cycles
kHz
ns
ns
ps
0.1
DCLK Static
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels
VIH
VIL
VOH
VOL
Data Format
±1
±1
✻
✻
±3
✻
✻
125
at
at
at
at
V
V
V
pF
µA
✻
12
3
2.5VPP
2.5VPP
2.5VPP
2.5VPP
✻
✻
✻
✻
±0.8
=
=
=
=
UNITS
✻
12
VIN
VIN
VIN
VIN
MAX
✻
✻
12
SAMPLING DYNAMICS
Conversion Time
Acquisition Time
Throughput Rate
Multiplexer Settling Time
Aperture Delay
Aperture Jitter
POWER SUPPLY REQUIREMENTS
+VCC
Quiescent Current
MIN
25
±1
SYSTEM PERFORMANCE
Resolution
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Offset Error
Offset Error Match
Gain Error
Gain Error Match
Noise
Power Supply Rejection
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion(2)
Signal-to-(Noise + Distortion)
Spurious Free Dynamic Range
Channel-to-Channel Isolation
ADS7844EB, NB
MAX
+85
✻
✻
✻
✻
✻
V
µA
µA
µA
mW
✻
°C
✻ Same specifications as ADS7844E, ADS7844N.
NOTE: (1) LSB means Least Significant Bit. With VREF equal to +2.5V, one LSB is 610mV. (2) First five harmonics of the test frequency. (3) Auto power-down mode
(PD1 = PD0 = 0) active or SHDN = GND.
ADS7844
SBAS100A
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3
PACKAGE/ORDERING INFORMATION(1)
PRODUCT
MINIMUM
RELATIVE
ACCURACY
(LSB)
MAXIMUM
GAIN ERROR
(LSB)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE-LEAD
PACKAGE
DESIGNATOR
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
±2
"
"
"
±1
"
"
"
±4
"
"
"
±3
"
"
"
–40°C to +85°C
"
"
"
–40°C to +85°C
"
"
"
QSOP-20
"
SSOP-20
"
QSOP-20
"
SSOP-20
"
DBQ
"
DB
"
DBQ
"
DB
"
ADS7844E
ADS7844E/2K5
ADS7844N
ADS7844N/1K
ADS7844EB
ADS7844EB/2K5
ADS7844NB
ADS7844NB/1K
Rails, 56
Tape and Reel, 2500
Rails, 68
Tape and Reel,1000
Rails, 56
Tape and Reel, 2500
Rails, 68
Tape and Reel, 1000
ADS7844E
"
ADS7844N
"
ADS7844EB
"
ADS7844NB
"
NOTES: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet.
PIN DESCRIPTIONS
PIN CONFIGURATION
Top View
CH0
1
20
+VCC
CH1
2
19
DCLK
CH2
3
18
CS
CH3
4
17
DIN
CH4
5
16
BUSY
PIN
NAME
DESCRIPTION
1
2
3
4
5
6
7
8
9
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
Analog Input Channel 0.
Analog Input Channel 1.
Analog Input Channel 2.
Analog Input Channel 3.
Analog Input Channel 4.
Analog Input Channel 5.
Analog Input Channel 6.
Analog Input Channel 7.
Ground reference for analog inputs. Sets zero code
voltage in single ended mode. Connect this pin to ground
or ground reference point.
Shutdown. When LOW, the device enters a very low
power shutdown mode.
Voltage Reference Input. See Specification Table for
ranges.
Power Supply, 2.7V to 5V.
Ground
Ground
Serial Data Output. Data is shifted on the falling edge of
DCLK. This output is high impedance when
CS is high.
Busy Output. Busy goes low when the DIN control bits
are being read and also when the device is converting.
The Output is high impedance when CS is High.
Serial Data Input. If CS is LOW, data is latched on rising
edge of DCLK.
Chip Select Input. Active LOW. Data will not be clocked
into DIN unless CS is low. When CS is high DOUT is high
impedance.
External Clock Input. The clock speed determines the
conversion rate by the equation fCLK = 16 • fSAMPLE.
Power Supply
ADS7844
CH5
6
15
DOUT
CH6
7
14
GND
10
SHDN
CH7
8
13
GND
11
VREF
COM
9
12
+VCC
SHDN 10
11
VREF
12
13
14
15
+VCC
GND
GND
DOUT
16
BUSY
17
DIN
18
CS
19
CLK
20
+VCC
(1)
ABSOLUTE MAXIMUM RATINGS
+VCC to GND ........................................................................ –0.3V to +6V
Analog Inputs to GND ............................................ –0.3V to +VCC + 0.3V
Digital Inputs to GND ........................................................... –0.3V to +6V
Power Dissipation .......................................................................... 250mW
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ........................................ –40°C to +85°C
Storage Temperature Range ......................................... –65°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet its published specifications.
4
ADS7844
www.ti.com
SBAS100A
TYPICAL PERFORMANCE CURVES:+5V
At TA = +25°C, +VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE = 3.2MHz, unless otherwise noted.
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 10.3kHz, –0.2dB)
0
0
–20
–20
–40
–40
Amplitude (dB)
Amplitude (dB)
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 1,123Hz, –0.2dB)
–60
–80
–60
–80
–100
–100
–120
–120
0
25
50
75
0
100
25
50
75
100
Frequency (kHz)
Frequency (kHz)
SIGNAL-TO-NOISE RATIO AND SIGNAL-TO(NOISE+DISTORTION) vs INPUT FREQUENCY
SPURIOUS FREE DYNAMIC RANGE AND TOTAL
HARMONIC DISTORTION vs INPUT FREQUENCY
74
–85
85
SNR
SFDR
SINAD
71
THD
75
–75
70
–70
70
69
1
10
1
100
10
Input Frequency (kHz)
Input Frequency (kHz)
EFFECTIVE NUMBER OF BITS
vs INPUT FREQUENCY
CHANGE IN SIGNAL-TO-(NOISE+DISTORTION)
vs TEMPERATURE
12.0
0.6
0.4
11.8
Delta from +25°C (dB)
Effective Number of Bits
–65
100
65
68
11.6
11.4
11.2
0.2
0.0
–0.2
–0.4
fIN = 10kHz, –0.2dB
11.0
–0.6
1
10
–40
100
ADS7844
SBAS100A
–20
0
20
40
60
80
100
Temperature (°C)
Input Frequency (kHz)
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5
THD (dB)
–80
80
72
SFDR (dB)
SNR and SINAD (dB)
73
TYPICAL PERFORMANCE CURVES:+2.7V
At TA = +25°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted.
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 10.6kHz, –0.2dB)
0
0
–20
–20
–40
–40
Amplitude (dB)
–60
–80
–100
–80
–100
–120
–120
0
15.6
31.3
46.9
62.5
0
15.6
31.3
46.9
62.5
Frequency (kHz)
Frequency (kHz)
SIGNAL-TO-NOISE RATIO AND SIGNAL-TO(NOISE+DISTORTION) vs INPUT FREQUENCY
SPURIOUS FREE DYNAMIC RANGE AND TOTAL
HARMONIC DISTORTION vs INPUT FREQUENCY
90
78
SNR
–90
85
74
–85
SFDR
70
SFDR (dB)
SNR and SINAD (dB)
–60
66
SINAD
62
58
80
–80
75
–75
70
–70
THD
65
–65
60
–60
55
–55
50
54
1
10
Input Frequency (kHz)
–50
1
100
10
100
Input Frequency (kHz)
EFFECTIVE NUMBER OF BITS
vs INPUT FREQUENCY
CHANGE IN SIGNAL-TO-(NOISE+DISTORTION)
vs TEMPERATURE
12.0
0.4
11.5
0.2
Delta from +25°C (dB)
Effective Number of Bits
fIN = 10kHz, –0.2dB
11.0
10.5
10.0
–0.2
–0.4
–0.6
9.5
–0.8
9.0
1
10
100
–40
–20
0
20
40
60
80
100
Temperature (˚C)
Input Frequency (kHz)
6
0.0
ADS7844
www.ti.com
SBAS100A
THD (dB)
Amplitude (dB)
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 1,129Hz, –0.2dB)
TYPICAL PERFORMANCE CURVES:+2.7V
(CONT)
At TA = +25°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted.
POWER DOWN SUPPLY CURRENT
vs TEMPERATURE
400
140
350
120
Supply Current (nA)
Supply Current (µA)
SUPPLY CURRENT vs TEMPERATURE
300
250
200
100
80
60
40
150
20
100
–40
–20
0
20
40
60
80
–40
100
–20
0
40
60
80
100
DIFFERENTIAL LINEARITY ERROR vs CODE
1.00
1.00
0.75
0.75
0.50
0.50
DLE (LSB)
ILE (LSB)
INTEGRAL LINEARITY ERROR vs CODE
0.25
0.00
–0.25
0.25
0.00
–0.25
–0.50
–0.50
–0.75
–0.75
–1.00
000H
–1.00
000H
FFFH
800H
800H
Output Code
FFFH
Output Code
CHANGE IN GAIN vs TEMPERATURE
CHANGE IN OFFSET vs TEMPERATURE
0.15
0.6
0.10
0.4
Delta from +25˚C (LSB)
Delta from +25˚C (LSB)
20
Temperature (˚C)
Temperature (˚C)
0.05
0.00
–0.05
0.2
0.0
–0.2
–0.4
–0.10
–0.6
–0.15
–40
–20
0
20
40
60
80
–40
100
ADS7844
SBAS100A
–20
0
20
40
60
80
100
Temperature (˚C)
Temperature (˚C)
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7
TYPICAL PERFORMANCE CURVES
(CONT)
At TA = +25°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted.
REFERENCE CURRENT vs TEMPERATURE
18
12
16
Reference Current (µA)
Reference Current (µA)
REFERENCE CURRENT vs SAMPLE RATE
14
10
8
6
4
14
12
10
8
2
6
0
0
25
50
75
100
–40
125
–20
0
20
40
60
80
100
Temperature (˚C)
Sample Rate (kHz)
MAXIMUM SAMPLE RATE vs +VCC
SUPPLY CURRENT vs +VCC
1M
320
300
Sample Rate (Hz)
Supply Current (µA)
fSAMPLE = 12.5kHz
280
VREF = +VCC
260
240
220
100k
10k
VREF = +VCC
200
1k
180
2
2.5
3
3.5
4
4.5
2
5
8
2.5
3
3.5
4
4.5
5
+VCC (V)
+VCC (V)
ADS7844
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SBAS100A
THEORY OF OPERATION
ANALOG INPUT
Figure 2 shows a block diagram of the input multiplexer on
the ADS7844. The differential input of the converter is
derived from one of the eight inputs in reference to the COM
pin or four of the eight inputs. Table I and Table II show the
relationship between the A2, A1, A0, and SGL/DIF control
bits and the configuration of the analog multiplexer. The
control bits are provided serially via the DIN pin, see the
Digital Interface section of this data sheet for more details.
The ADS7844 is a classic successive approximation register
(SAR) analog-to-digital (A/D) converter. The architecture is
based on capacitive redistribution which inherently includes
a sample/hold function. The converter is fabricated on a
0.6µs CMOS process.
The basic operation of the ADS7844 is shown in Figure 1.
The device requires an external reference and an external
clock. It operates from a single supply of 2.7V to 5.25V. The
external reference can be any voltage between 100mV and
+VCC. The value of the reference voltage directly sets the
input range of the converter. The average reference input
current depends on the conversion rate of the ADS7844.
When the converter enters the hold mode, the voltage
difference between the +IN and –IN inputs (see Figure 2) is
captured on the internal capacitor array. The voltage on the
–IN input is limited between –0.2V and 1.25V, allowing the
input to reject small signals which are common to both the
+IN and –IN input. The +IN input has a range of –0.2V to
+VCC + 0.2V.
The analog input to the converter is differential and is
provided via an eight-channel multiplexer. The input can be
provided in reference to a voltage on the COM pin (which
is generally ground) or differentially by using four of the
eight input channels (CH0 - CH7). The particular configuration is selectable via the digital interface.
A2
A1
A0
0
0
0
1
0
0
0
0
1
1
0
1
0
1
0
1
1
0
0
1
1
1
1
1
The input current on the analog inputs depends on the
conversion rate of the device. During the sample period, the
source must charge the internal sampling capacitor (typi-
A2
A1
A0
CH0
CH1
–IN
0
0
0
+IN
–IN
–IN
0
0
1
–IN
0
1
0
–IN
0
1
1
–IN
1
0
0
–IN
1
0
1
–IN
1
1
0
–IN
1
1
1
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
+IN
+IN
+IN
+IN
+IN
+IN
+IN
+IN
TABLE I. Single-Ended Channel Selection (SGL/DIF HIGH).
–IN
CH2
CH3
+IN
–IN
CH4
CH5
+IN
–IN
CH6
CH7
+IN
–IN
–IN
+IN
+IN
–IN
+IN
–IN
+IN
TABLE II. Differential Channel Control (SGL/DIF LOW).
+2.7V to +5V
ADS7844
Single-ended
or differential
analog inputs
0.1µF
1µF to 10µF
1
CH0
+VCC 20
2
CH1
DCLK 19
3
CH2
CS 18
Chip Select
4
CH3
DIN 17
Serial Data In
5
CH4
BUSY 16
6
CH5
DOUT 15
7
CH6
GND 14
8
CH7
GND 13
9
COM
+VCC 12
10 SHDN
Serial/Conversion Clock
Serial Data Out
VREF 11
1µF to 10µF
FIGURE 1. Basic Operation of the ADS7844.
ADS7844
SBAS100A
www.ti.com
9
Likewise, the noise or uncertainty of the digitized output will
increase with lower LSB size. With a reference voltage of
100mV, the LSB size is 24µV. This level is below the
internal noise of the device. As a result, the digital output
code will not be stable and vary around a mean value by a
number of LSBs. The distribution of output codes will be
gaussian and the noise can be reduced by simply averaging
consecutive conversion results or applying a digital filter.
A2-A0
(shown 000B)(1)
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
+IN
Converter
−IN
With a lower reference voltage, care should be taken to
provide a clean layout including adequate bypassing, a clean
(low noise, low ripple) power supply, a low-noise reference,
and a low-noise input signal. Because the LSB size is lower,
the converter will also be more sensitive to nearby digital
signals and electromagnetic interference.
The voltage into the VREF input is not buffered and directly
drives the capacitor digital-to-analog converter (CDAC)
portion of the ADS7844. Typically, the input current is
13µA with a 2.5V reference. This value will vary by
microamps depending on the result of the conversion. The
reference current diminishes directly with both conversion
rate and reference voltage. As the current from the reference
is drawn on each bit decision, clocking the converter more
quickly during a given conversion period will not reduce
overall current drain from the reference.
COM
NOTE: (1) See Truth Tables, Table 1,
and Table 2 for address coding.
DIGITAL INTERFACE
SGL/DIF
(shown HIGH)
FIGURE 2. Simplified Diagram of the Analog Input.
cally 25pF). After the capacitor has been fully charged, there
is no further input current. The rate of charge transfer from
the analog source to the converter is a function of conversion
rate.
REFERENCE INPUT
The external reference sets the analog input range. The
ADS7844 will operate with a reference in the range of
100mV to +VCC. Keep in mind that the analog input is the
difference between the +IN input and the –IN input as shown
in Figure 2. For example, in the single-ended mode, a 1.25V
reference, and with the COM pin grounded, the selected input
channel (CH0 - CH7) will properly digitize a signal in the
range of 0V to 1.25V. If the COM pin is connected to 0.5V,
the input range on the selected channel is 0.5V to 1.75V.
There are several critical items concerning the reference input
and its wide voltage range. As the reference voltage is reduced, the analog voltage weight of each digital output code
is also reduced. This is often referred to as the LSB (least
significant bit) size and is equal to the reference voltage
divided by 4096. Any offset or gain error inherent in the A/D
converter will appear to increase, in terms of LSB size, as the
reference voltage is reduced. For example, if the offset of a
given converter is 2 LSBs with a 2.5V reference, then it will
typically be 10 LSBs with a 0.5V reference. In each case, the
actual offset of the device is the same, 1.22mV.
10
Figure 3 shows the typical operation of the ADS7844’s
digital interface. This diagram assumes that the source of the
digital signals is a microcontroller or digital signal processor
with a basic serial interface (note that the digital inputs are
over-voltage tolerant up to 5.5V, regardless of +VCC). Each
communication between the processor and the converter
consists of eight clock cycles. One complete conversion can
be accomplished with three serial communications, for a
total of 24 clock cycles on the DCLK input.
The first eight clock cycles are used to provide the control
byte via the DIN pin. When the converter has enough
information about the following conversion to set the input
multiplexer appropriately, it enters the acquisition (sample)
mode. After three more clock cycles, the control byte is
complete and the converter enters the conversion mode. At
this point, the input sample/hold goes into the hold mode.
The next twelve clock cycles accomplish the actual analogto-digital conversion. A thirteenth clock cycle is needed for
the last bit of the conversion result. Three more clock cycles
are needed to complete the last byte (DOUT will be LOW).
These will be ignored by the converter.
Control Byte
Also shown in Figure 3 is the placement and order of the
control bits within the control byte. Tables III and IV give
detailed information about these bits. The first bit, the ‘S’ bit,
must always be HIGH and indicates the start of the control
byte. The ADS7844 will ignore inputs on the DIN pin until
the start bit is detected. The next three bits (A2 - A0) select
the active input channel or channels of the input multiplexer
(see Tables I and II and Figure 2).
ADS7844
www.ti.com
SBAS100A
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
S
A2
A1
A0
—
SGL/DIF
PD1
PD0
The SGL/DIF bit controls the multiplexer input mode: either
single-ended (HIGH) or differential (LOW). In single-ended
mode, the selected input channel is referenced to the COM
pin. In differential mode, the two selected inputs provide a
differential input. See Tables I and II and Figure 2 for more
information. The last two bits (PD1 - PD0) select the powerdown mode as shown in Table V. If both inputs are HIGH,
the device is always powered up. If both inputs are LOW, the
device enters a power-down mode between conversions.
When a new conversion is initiated, the device will resume
normal operation instantly—no delay is needed to allow the
device to power up and the very first conversion will be
valid.
TABLE III. Order of the Control Bits in the Control Byte.
BIT
NAME
7
6-4
DESCRIPTION
S
Start Bit. Control byte starts with first HIGH bit on
DIN. A new control byte starts with every 15th clock
cycle.
A2 - A0
Channel Select Bits. Along with the SGL/DIF bit,
these bits control the setting of the multiplexer input
as detailed in Tables I and II.
3
—
2
SGL/DIF
1-0
Not Used.
PD1 - PD0
16-Clocks per Conversion
Single-Ended/Differential Select Bit. Along with bits
A2 - A0, this bit controls the setting of the multiplexer
input as detailed in Tables I and II.
The control bits for conversion n+1 can be overlapped with
conversion ‘n’ to allow for a conversion every 16 clock
cycles, as shown in Figure 4. This figure also shows possible
serial communication occurring with other serial peripherals
between each byte transfer between the processor and the
converter. This is possible provided that each conversion
completes within 1.6ms of starting. Otherwise, the signal
that has been captured on the input sample/hold may droop
enough to affect the conversion result. In addition, the
ADS7844 is fully powered while other serial communications are taking place.
Power-Down Mode Select Bits. See Table V for
details.
TABLE IV. Descriptions of the Control Bits within the
Control Byte.
CS
tACQ
DCLK
DIN
1
S
8
A2
A1
A0
8
1
1
8
SGL/ PD1 PD0
DIF
(START)
Idle
Acquire
Conversion
Idle
BUSY
DOUT
11
10
9
8
7
6
5
4
3
2
1
(MSB)
0
Zero Filled...
(LSB)
FIGURE 3. Conversion Timing, 24-Clocks per Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated
serial port.
CS
DCLK
1
DIN
8
1
8
S
1
8
1
S
CONTROL BITS
CONTROL BITS
BUSY
DOUT
11 10 9
8
7
6
5
4
3
2
1
0
11 10 9
FIGURE 4. Conversion Timing, 16-Clocks per Conversion, 8-bit Bus Interface. No DCLK delay required with dedicated
serial port.
ADS7844
SBAS100A
www.ti.com
11
PD1
PD0
0
0
Description
SYMBOL
DESCRIPTION
MIN
Power-down between conversions. When each
conversion is finished, the converter enters a low
power mode. At the start of the next conversion,
the device instantly powers up to full power. There
is no need for additional delays to assure full
operation and the very first conversion is valid.
tACQ
Acquisition Time
1.5
TYP
MAX
UNITS
tDS
DIN Valid Prior to DCLK Rising
100
ns
tDH
DIN Hold After DCLK HIGH
10
ns
µs
tDO
DCLK Falling to DOUT Valid
200
ns
tDV
CS Falling to DOUT Enabled
200
ns
200
ns
0
1
Reserved for future use.
tTR
CS Rising to DOUT Disabled
1
0
Reserved for future use.
tCSS
CS Falling to First DCLK Rising
100
ns
tCSH
CS Rising to DCLK Ignored
0
ns
tCH
DCLK HIGH
200
ns
tCL
DCLK LOW
200
tBD
DCLK Falling to BUSY Rising
200
ns
tBDV
CS Falling to BUSY Enabled
200
ns
tBTR
CS Rising to BUSY Disabled
200
ns
1
1
No power-down between conversions, device always powered.
TABLE V. Power-Down Selection.
Digital Timing
ns
TABLE VI. Timing Specifications (+VCC = +2.7V to 3.6V,
TA = –40°C to +85°C, CLOAD = 50pF).
Figure 5 and Tables VI and VII provide detailed timing for
the digital interface of the ADS7844.
SYMBOL
DESCRIPTION
MIN
tACQ
Acquisition Time
900
tDS
DIN Valid Prior to DCLK Rising
50
ns
tDH
DIN Hold After DCLK HIGH
10
ns
15-Clocks per Conversion
Figure 6 provides the fastest way to clock the ADS7844.
This method will not work with the serial interface of most
microcontrollers and digital signal processors as they are
generally not capable of providing 15 clock cycles per serial
transfer. However, this method could be used with field
programmable gate arrays (FPGAs) or application specific
integrated circuits (ASICs). Note that this effectively increases the maximum conversion rate of the converter beyond the values given in the specification tables, which
assume 16 clock cycles per conversion.
TYP
MAX
UNITS
ns
tDO
DCLK Falling to DOUT Valid
100
ns
tDV
CS Falling to DOUT Enabled
70
ns
70
ns
tTR
CS Rising to DOUT Disabled
tCSS
CS Falling to First DCLK Rising
50
ns
tCSH
CS Rising to DCLK Ignored
0
ns
tCH
DCLK HIGH
150
ns
tCL
DCLK LOW
150
tBD
DCLK Falling to BUSY Rising
100
ns
tBDV
CS Falling to BUSY Enabled
70
ns
tBTR
CS Rising to BUSY Disabled
70
ns
ns
TABLE VII. Timing Specifications (+VCC = +4.75V to
+5.25V, TA = –40°C to +85°C, CLOAD = 50pF).
CS
tCSS
tCL
tCH
tBD
tBD
tD0
tCSH
DCLK
tDH
tDS
DIN
PD0
tBDV
tBTR
BUSY
tDV
tTR
DOUT
11
10
FIGURE 5. Detailed Timing Diagram.
CS
DCLK
15
1
DIN
S
A2 A1 A0
SGL/ PD1 PD0
DIF
1
S
15
SGL/ PD1 PD0
DIF
A2 A1 A0
1
S
A2
5
4
A1 A0
BUSY
DOUT
11 10
9
8
7
6
5
4
3
2
1
0
11 10
9
8
7
6
3
2
FIGURE 6. Maximum Conversion Rate, 15-Clocks per Conversion.
12
ADS7844
www.ti.com
SBAS100A
Data Format
FS = Full-Scale Voltage = VREF
1 LSB = VREF/4096
1 LSB
1000
fCLK = 16 • fSAMPLE
Supply Current (µA)
The ADS7844 output data is in straight binary format as
shown in Figure 7. This figure shows the ideal output code
for the given input voltage and does not include the effects
of offset, gain, or noise.
100
fCLK = 2MHz
10
TA = 25°C
+VCC = +2.7V
VREF = +2.5V
PD1 = PD0 = 0
11...111
Output Code
11...110
1
11...101
1k
10k
100k
1M
fSAMPLE (Hz)
00...010
FIGURE 8. Supply Current vs Directly Scaling the Frequency of DCLK with Sample Rate or Keeping
DCLK at the Maximum Possible Frequency.
00...001
00...000
FS – 1 LSB
0V
Input Voltage(1) (V)
14
Note 1: Voltage at converter input, after
multiplexer: +IN–(–IN). See Figure 2.
POWER DISSIPATION
There are three power modes for the ADS7844: full power
(PD1 - PD0 = 11B), auto power-down (PD1 - PD0 = 00B),
and shutdown (SHDN LOW). The affects of these modes
varies depending on how the ADS7844 is being operated. For
example, at full conversion rate and 16 clocks per conversion, there is very little difference between full power mode
and auto power-down. Likewise, if the device has entered
auto power-down, a shutdown (SHDN LOW) will not lower
power dissipation.
When operating at full-speed and 16-clocks per conversion
(as shown in Figure 4), the ADS7844 spends most of its time
acquiring or converting. There is little time for auto powerdown, assuming that this mode is active. Thus, the difference between full power mode and auto power-down is
negligible. If the conversion rate is decreased by simply
slowing the frequency of the DCLK input, the two modes
remain approximately equal. However, if the DCLK frequency is kept at the maximum rate during a conversion, but
conversion are simply done less often, then the difference
between the two modes is dramatic. Figure 8 shows the
difference between reducing the DCLK frequency (“scaling” DCLK to match the conversion rate) or maintaining
DCLK at the highest frequency and reducing the number of
conversion per second. In the later case, the converter
spends an increasing percentage of its time in power-down
mode (assuming the auto power-down mode is active).
If DCLK is active and CS is LOW while the ADS7844 is in
auto power-down mode, the device will continue to dissipate
some power in the digital logic. The power can be reduced
to a minimum by keeping CS HIGH. The differences in
supply current for these two cases are shown in Figure 9.
Supply Current (µA)
FIGURE 7. Ideal Input Voltages and Output Codes.
10
8
6
CS LOW
(GND)
4
2
CS HIGH (+VCC)
0
0.09
0.00
1k
10k
100k
1M
fSAMPLE (Hz)
FIGURE 9. Supply Current vs State of CS.
Operating the ADS7844 in auto power-down mode will
result in the lowest power dissipation, and there is no
conversion time “penalty” on power-up. The very first
conversion will be valid. SHDN can be used to force an
immediate power-down.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS7844 circuitry. This is particularly true if the reference voltage is low and/or the conversion rate is high.
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the
output of the analog comparator. Thus, during any single
conversion for an n-bit SAR converter, there are n “windows” in which large external transient voltages can easily
affect the conversion result. Such glitches might originate
from switching power supplies, nearby digital logic, and
ADS7844
SBAS100A
TA = 25°C
+VCC = +2.7V
VREF = +2.5V
fCLK = 16 • fSAMPLE
PD1 = PD0 = 0
12
www.ti.com
13
high power devices. The degree of error in the digital output
depends on the reference voltage, layout, and the exact
timing of the external event. The error can change if the
external event changes in time with respect to the DCLK
input.
With this in mind, power to the ADS7844 should be clean
and well bypassed. A 0.1µF ceramic bypass capacitor should
be placed as close to the device as possible. In addition, a
1µF to 10µF capacitor and a 5Ω or 10Ω series resistor may
be used to lowpass filter a noisy supply.
The reference should be similarly bypassed with a 0.1µF
capacitor. Again, a series resistor and large capacitor can be
used to lowpass filter the reference voltage. If the reference
voltage originates from an op amp, make sure that it can
drive the bypass capacitor without oscillation (the series
resistor can help in this case). The ADS7844 draws very
little current from the reference on average, but it does place
larger demands on the reference circuitry over short periods
of time (on each rising edge of DCLK during a conversion).
14
The ADS7844 architecture offers no inherent rejection of
noise or voltage variation in regards to the reference input.
This is of particular concern when the reference input is tied
to the power supply. Any noise and ripple from the supply
will appear directly in the digital results. While high frequency noise can be filtered out as discussed in the previous
paragraph, voltage variation due to line frequency (50Hz or
60Hz) can be difficult to remove.
The GND pin should be connected to a clean ground point.
In many cases, this will be the “analog” ground. Avoid
connections which are too near the grounding point of a
microcontroller or digital signal processor. If needed, run a
ground trace directly from the converter to the power supply
entry point. The ideal layout will include an analog ground
plane dedicated to the converter and associated analog
circuitry.
ADS7844
www.ti.com
SBAS100A
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
ADS7844E
ACTIVE
SSOP
DBQ
20
50
RoHS & Green
Call TI
Level-2-260C-1 YEAR
ADS7844E
Samples
ADS7844E/2K5
ACTIVE
SSOP
DBQ
20
2500
RoHS & Green
Call TI
Level-2-260C-1 YEAR
ADS7844E
Samples
ADS7844EB
ACTIVE
SSOP
DBQ
20
50
RoHS & Green
Call TI
Level-2-260C-1 YEAR
ADS7844E
B
Samples
ADS7844EB/2K5
ACTIVE
SSOP
DBQ
20
2500
RoHS & Green
Call TI
Level-2-260C-1 YEAR
ADS7844E
B
Samples
ADS7844EBG4
ACTIVE
SSOP
DBQ
20
50
RoHS & Green
Call TI
Level-2-260C-1 YEAR
ADS7844E
B
Samples
ADS7844EG4
ACTIVE
SSOP
DBQ
20
50
RoHS & Green
Call TI
Level-2-260C-1 YEAR
ADS7844E
Samples
ADS7844N
ACTIVE
SSOP
DB
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
ADS7844N
Samples
ADS7844N/1K
ACTIVE
SSOP
DB
20
1000
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 85
ADS7844N
Samples
ADS7844N/1KG4
ACTIVE
SSOP
DB
20
1000
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 85
ADS7844N
Samples
ADS7844NB
ACTIVE
SSOP
DB
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
ADS7844N
B
Samples
ADS7844NB/1K
ACTIVE
SSOP
DB
20
1000
RoHS & Green
Call TI
Level-2-260C-1 YEAR
ADS7844N
B
Samples
ADS7844NBG4
ACTIVE
SSOP
DB
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
ADS7844N
B
Samples
ADS7844NG4
ACTIVE
SSOP
DB
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
ADS7844N
Samples
-40 to 85
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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