ADS7861IRHBT

ADS7861 ADS 7 86 1 AD S78 61 SBAS110D – DECEMBER 1998 – REVISED AUGUST 2007 Dual, 500kSPS, 12-Bit, 2 + 2 Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● ● ● ● ● ● ● ● The ADS7861 is a dual, 12-bit, 500kSPS, Analog-to-Digital (A/D) converter with four fully differential input channels grouped into two pairs for high speed, simultaneous signal acquisition. Inputs to the sample-and-hold amplifiers are fully differential and are maintained differential to the input of the A/D converter. This provides excellent common-mode rejection of 80dB at 50kHz which is important in high noise environments. 4 INPUT CHANNELS FULLY DIFFERENTIAL INPUTS 2µs TOTAL THROUGHPUT PER CHANNEL NO MISSING CODES 1MHz EFFECTIVE SAMPLING RATE LOW POWER: 40mW SSI SERIAL INTERFACE OPERATING TEMPERATURE RANGE: –40°C to +125°C The ADS7861 offers a high-speed, dual serial interface and control inputs to minimize software overhead. The output data for each channel is available as a 12-bit word. The ADS7861 is offered in both an SSOP-24 and a QFN-32 package and is fully specified over the –40°C to +125°C operating range. APPLICATIONS ● MOTOR CONTROL ● MULTI-AXIS POSITIONING SYSTEMS ● 3-PHASE POWER CONTROL CH A0+ SAR CH A0– COMP SHA SERIAL DATA A CDAC CH A1+ SERIAL DATA B CH A1– M0 M1 REFIN Serial Interface Internal 2.5V Reference REFOUT A0 CLOCK CS CH B0+ CH B0– RD SHA COMP CDAC BUSY CONVST CH B1+ CH B1– SAR Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 1998-2007, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) Analog Inputs to AGND, Any Channel Input ........ –0.3V to (+VD + 0.3V) REFIN ..................................................................... –0.3V to (+VD + 0.3V) Digital Inputs to DGND .......................................... –0.3V to (+VD + 0.3V) Ground Voltage Differences: AGND, DGND ................................... ±0.3V +VD to AGND ......................... –0.3V to +6V Power Dissipation .......................................................................... 325mW Maximum Junction Temperature ................................................... +150°C Operating Temperature Range ...................................... –40°C to +125°C Storage Temperature Range ......................................... –65°C to +150°C This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. TRUTH TABLE M0 M1 A0 TWO-CHANNEL/FOUR-CHANNEL OPERATION DATA ON SERIAL OUTPUTS CHANNELS CONVERTED 0 0 0 Two Channel A and B A0, B0 0 0 1 Two Channel A and B A1, B1 0 1 0 Two Channel A Only A0, B0 0 1 1 Two Channel A Only A1, B1 1 0 X Four Channel A and B Sequential 1 1 X Four Channel A Only Sequential X = Don’t Care. BASIC CIRCUIT CONFIGURATION ADS7861 1 DGND 2 CH B1+ SERIAL DATA A 23 3 CH B1– SERIAL DATA B 22 4 CH B0+ BUSY 21 5 CH B0– CLOCK 20 Clock Input 6 CH A1+ CS 19 Chip Select 7 CH A1– RD 18 Read Input 8 CH A0+ CONVST 17 9 CH A0– A0 16 A0 Address Select 10 REFIN M0 15 M0 Address Select 11 REFOUT M1 14 M1 Address Select 12 AGND 2 +VD 24 +VA 13 BUSY Output Conversion Start + 10µF + +5V Analog Supply 0.1µF ADS7861 SBAS110D ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range at TA = –40°C to +125°C, +VA + VD = +5V, VREF = internal +2.5V, fCLK = 8MHz, and fSAMPLE = 500kSPS, unless otherwise noted. ADS7861I, E PARAMETER CONDITIONS MIN TYP RESOLUTION ANALOG INPUT Input Voltage Range-Bipolar Input Capacitance Input Leakage Current SYSTEM PERFORMANCE No Missing Codes Integral Linearity Integral Linearity Match Differential Linearity Bipolar Offset Error Bipolar Offset Error Match Positive Gain Error Positive Gain Error Match Negative Gain Error Negative Gain Error Match Common-Mode Rejection Ratio VCENTER = Internal VREF at 2.5V MIN –VREF +VREF TYP ✻ TA = –40°C to +85°C TA = –40°C to +125°C ±0.75 0.5 ±1 ±0.5 ±0.5 Referenced to REFIN ±0.15 Referenced to REFIN ±0.15 At DC VIN = ±1.25VPP at 50kHz 80 80 120 0.5 ±2 ±1 ±0.5 ✻ ±0.5 ✻ ✻ ±3 ±3.5 3 ±0.75 2 ±0.75 2 ±0.10 ±0.10 ✻ ✻ ✻ ✻ 2 DIGITAL INPUT/OUTPUT Logic Family Logic Levels: VIH VIL VOH VOL External Clock, Optional Data Format –72 –71 TA = –40°C to +85°C TA = –40°C to +125°C TA = –40°C to +85°C TA = –40°C to +125°C V pF µA ±1 ✻ ±1 ✻ ✻ 2 ±0.50 1 ±0.50 1 ✻ ✻ 76 75 70 72 71 ✻ –80 2.5 ±25 50 2 0.005 80 2.5 0.05 5 2.525 ✻ 2.6 1 ✻ 3.0 –0.3 3.5 +VDD + 0.3 1 ✻ ✻ ✻ ✻ ✻ ✻ dB dB dB dB dB dB V ppm/°C µVPP mA mV/µA dB V µA pF ✻ 0.4 0.2 8 Binary Two's Complement ✻ 4.75 ✻ 5 5 5 25 25 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ Bits LSB LSB LSB LSB LSB LSB % of FSR LSB % of FSR LSB dB dB µVrms LSB µs µs kSPS ns ps ps MHz –76 –75 CMOS IIH = +5µA IIL = +5µA IOH = –0.5mA IOL = –0.5mA ✻ ✻ ✻ ✻ ✻ 3.5 100 50 40 1.2 Bits ✻ 500 2.475 ✻ ✻ ✻ 1.625 0.375 VOLTAGE REFERENCE Internal Internal Drift Internal Noise Internal Source Current Internal Load Rejection Internal PSRR External Voltage Range Input Current Input Capacitance UNITS ✻ 12 DYNAMIC CHARACTERISTICS (VIN = ±2.5VPP at 100kHz) Total Harmonic Distortion TA = –40°C to +85°C TA = –40°C to +125°C SINAD Spurious Free Dynamic Range TA = –40°C to +85°C TA = –40°C to +125°C Channel-to-Channel Isolation MAX ✻ ✻ 15 ±1 SAMPLING DYNAMICS Conversion Time per A/D Acquisition Time Throughput Rate Aperture Delay Aperture Delay Matching Aperture Jitter Small-Signal Bandwidth Power Dissipation MAX 12 Noise Power Supply Rejection Ratio POWER SUPPLY REQUIREMENTS Power Supply Voltage, +V Quiescent Current, +VA ADS7861IB, EB 5.25 8 8.5 40 42.5 ✻ ✻ ✻ ✻ V V V V MHz ✻ ✻ ✻ ✻ ✻ V mA mA mW mW ✻ ✻ ✻ ✻ ✻ ✻ ✻ Specifications same as ADS7861I, ADS7861E. ADS7861 SBAS110D 3 PIN CONFIGURATIONS CLOCK 20 6 CH A1+ CS 19 7 CH A1– RD 18 CONVST 17 +VD NC(2) SERIAL DATA A 25 SERIAL DATA B CH B1− 23 BUSY CH B0+ 3 22 CLOCK CH B0− 4 21 CS CH A1+ 5 20 RD CH A1− 6 19 CONVST CH A0+ 7 18 A0 CH A0− 8 17 M0 ADS7861(1) +VA 13 13 14 15 16 +VA NC(2) NC(2) M1 M1 14 12 11 REFOUT AGND M0 15 11 10 REFIN 10 A0 16 CH A0– 12 AGND 24 2 NC(2) 9 CH A0+ 1 REFOUT 8 QFN CH B1+ 9 CH B0– 26 BUSY 21 DGND CH B0+ 27 4 28 SERIAL DATA B 22 NC(2) CH B1– 29 3 NC(2) SERIAL DATA A 23 30 CH B1+ NC(2) 2 5 +VD 24 31 DGND NC(2) 1 Top View 32 SSOP ADS7861 REFIN Top View NOTE: (1) The thermal pad is internally connected to the substrate. This pad can be connected to the analog ground or left floating. Keep the thermal pad separate from the digital ground, if possible. (2) NC = Not Connected. PIN DESCRIPTIONS SSOP QFN PIN PIN 4 NAME DESCRIPTION 1 28 DGND Digital Ground. Connect directly to analog ground (pin 12). 2 1 CH B1+ Noninverting Input Channel B1 3 2 CH B1– Inverting Input Channel B1 4 3 CH B0+ Noninverting Input Channel B0 5 4 CH B0– Inverting Input Channel B0 6 5 CH A1+ Noninverting Input Channel A1 7 6 CH A1– Inverting Input Channel A1 8 7 CH A0+ Noninverting Input Channel A0 9 8 CH A0– Inverting Input Channel A0 Reference Input 10 9 REFIN 11 10 REFOUT 12 12 AGND 13 13 +VA Analog Power Supply, +5VDC. Connect directly to digital power supply (pin 24). Decouple to analog ground with a 0.1µF ceramic capacitor and a 10µF tantalum capacitor. 14 16 M1 Selects between the Serial Outputs. When M1 is LOW, both Serial Output A and Serial Output B are selected for data transfer. When M1 is HIGH, Serial output A is configured for both Channel A data and Channel B data; Serial Output B goes into tri-state (i.e., high impedance). 15 17 M0 Selects between two-channel and four-channel operation. When M0 is LOW, two-channel operation is selected and operates in conjunction with A0. When A0 is HIGH, Channel A1 and Channel B1 are being converted. When A0 is LOW, Channel A0 and Channel B0 are being converted. When M0 is HIGH, four-channel operation is selected. In this mode, all four channels are converted in sequence starting with Channels A0 and B0, followed by Channels A1 and B1. 16 18 A0 A0 operates in conjunction with M0. With M0 LOW and A0 HIGH, Channel A1 and Channel B1 are converted. With M0 LOW and A0 LOW, Channel A0 and Channel B0 are converted. 17 19 CONVST Convert Start. When CONVST switches from LOW to HIGH, the device switches from the sample to hold mode, independent of the status of the external clock. 18 20 RD 19 21 CS 20 22 CLOCK An external CMOS-compatible clock can be applied to the CLOCK input to synchronize the conversion process to an external source. The CLOCK pin controls the sampling rate by the equation: CLOCK = 16 • fSAMPLE. 21 23 BUSY BUSY goes HIGH during a conversion and returns LOW after the third LSB has been transmitted on either the Serial A or Serial B output pin. 22 24 SERIAL DATA B The Serial Output data word is comprised of channel information and 12 bits of data. In operation, data is valid on the falling edge of DCLOCK for 16 edges after the rising edge of RD. 23 25 SERIAL DATA A The Serial Output data word is comprised of channel information and 12 bits of data. In operation, data is valid on the falling edge of DCLOCK for 16 edges after the rising edge of RD. When M1 is HIGH, both Channel A data and Channel B data are available. 24 27 +VD 2.5V Reference Output Analog Ground. Connect directly to digital ground (pin 1). Synchronization Pulse for the Serial Output. Chip Select. When LOW, the Serial Output A and Serial Output B outputs are active; when HIGH, the serial outputs are tri-stated. Digital Power Supply, +5VDC. Connect directly to pin 13. Must be ≤ +VA. ADS7861 SBAS110D TYPICAL CHARACTERISTICS At TA = +25°C, +VA + VD = +5V, and VREF = internal +2.5V, fCLK = 8MHz, fSAMPLE = 500kSPS, unless otherwise noted. FREQUENCY SPECTRUM (4096 Point FFT; fIN = 199.9kHz, –0.5dB) 0 0 –20 –20 Amplitude (dB) Amplitude (dB) FREQUENCY SPECTRUM (4096 Point FFT; fIN = 99.9kHz, –0.5dB) –40 –60 –80 –100 –40 –60 –80 –100 –120 –120 0 62.5 125 187.5 250 0 62.5 125 Frequency (kHz) SIGNAL-TO-NOISE RATIO and SIGNAL-TO-(NOISE+DISTORTION) vs INPUT FREQUENCY 0.7 0.6 74 SNR Delta from +25°C (dB) SNR and SINAD (dB) 250 CHANGE IN SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-(NOISE+DISTORTION) vs TEMPERATURE 76 72 SINAD 70 68 66 0.5 0.4 0.3 0.2 SINAD SNR 0.1 0 64 1k 10k 100k –0.1 –40 1M 85 Temperature (°C) CHANGE IN SPURIOUS FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs TEMPERATURE CHANGE IN POSITIVE GAIN MATCH vs TEMPERATURE (Maximum Deviation for All Four Channels) +1 6 0 5 –0.5 THD 4 –1 3 –1.5 2 –2 SFDR 1 –2.5 0 –3 –1 –3.5 –40 25 Temperature (°C) ADS7861 85 0.6 Change in Positive Gain Match (LSB) 7 SBAS110D 25 Input Frequency (Hz) THD Delta from +25°C (dB) SFDR Delta from +25°C (dB) 187.5 Frequency (kHz) 0.5 0.4 0.3 0.2 0.1 0 –40 25 85 150 Temperature (°C) 5 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, +VA + VD = +5V, and VREF = internal +2.5V, fCLK = 8MHz, fSAMPLE = 500kSPS, unless otherwise noted. CHANGE IN REFERENCE VOLTAGE vs TEMPERATURE 2.51 0.2 0.18 0.16 Change in Reference (V) Change in Negative Gain Match (LSB) CHANGE IN NEGATIVE GAIN MATCH vs TEMPERATURE (Maximum Deviation for All Four Channels) 0.14 0.12 0.1 0.08 0.06 0.04 2.505 2.5 2.495 2.49 0.02 0 –40 25 85 2.485 –40 150 CHANGE IN BIPOLAR ZERO vs TEMPERATURE 150 CHANGE IN BPZ MATCH vs TEMPERATURE Change in Bipolar Match (LSB) Change in Bipolar Zero (LSB) 85 1 0.75 0.5 25 Temperature (°C) Temperature (°C) B Channel 0.25 0 –0.25 A Channel –0.5 –0.75 –40 25 85 0.75 0.5 0.25 0 –40 150 25 85 150 Temperature (°C) Temperature (°C) INTEGRAL LINEARITY ERROR vs CODE CHANGE IN CMRR vs TEMPERATURE 86 1 85 0.75 84 0.5 83 0.25 ILE (LSB) Change in CMRR (dB) Typical of All Four Channels 82 81 –0.25 80 –0.5 79 –0.75 78 –40 –5 25 Temperature (°C) 6 0 55 85 –1 800 000 7FF Hex BTC Code ADS7861 SBAS110D TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, +VA + VD = +5V, and VREF = internal +2.5V, fCLK = 8MHz, fSAMPLE = 500kSPS, unless otherwise noted. DIFFERENTIAL LINEARITY ERROR vs CODE INTEGRAL LINEARITY ERROR vs TEMPERATURE 1 0.8 Typical of All Four Channels 0.7 0.5 0.6 Change in ILE (LSB) 0.75 DLE (LSB) 0.25 0 –0.25 –0.5 0.2 0 –0.2 Negative ILE –0.6 –1 800 000 –0.8 –40 7FF 25 85 Hex BTC Code Temperature (°C) DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE INTEGRAL LINEARITY ERROR MATCH vs CODE CHANNEL A0/CHANNEL A1 (Same Converter, Different Channels) 0.8 150 0.25 Positive DLE 0.2 0.6 0.15 0.4 0.1 0.2 ILE (LSB) DLE Error (LSB) 0.4 –0.4 –0.75 Positive ILE 0 –0.2 –0.4 Negative DLE 0.05 0 –0.05 –0.1 –0.15 –0.6 –0.8 –40 –0.2 25 85 150 INTEGRAL LINEARITY ERROR MATCH vs CODE CHANNEL A0/CHANNEL B1 (Different Converter, Different Channels) INTEGRAL LINEARITY ERROR MATCH vs TEMPERATURE Channel A0/Channel B0 (Different Converter, Different Channels) 0.46 Change in INL Match (LSB) 0.47 0.2 0.1 0.05 0 –0.05 –0.1 –0.15 000 Hex BTC Code SBAS110D 0.45 0.44 0.43 0.42 0.41 0.40 0.39 –0.2 ADS7861 7FF Hex BTC Code 0.25 –0.25 800 000 Temperature (°C) 0.15 ILE (LSB) –0.25 800 7FF 0.38 –40 25 85 150 Temperature (°C) 7 INTRODUCTION The ADS7861 is a high-speed, low power, dual, 12-bit A/D converter that operates from a single +5V supply. The input channels are fully differential with a typical common-mode rejection of 80dB. The part contains dual, 2µs successive approximation ADCs, two differential sample-and-hold amplifiers, an internal +2.5V reference with REFIN and REFOUT pins and a high-speed parallel interface. The ADS7861 requires an external clock. In order to achieve the maximum throughput rate of 500kSPS, the master clock must be set at 8MHz. A minimum of 16 clock cycles are required for each 12-bit conversion. There are four analog inputs that are grouped into two channels (A and B). Channel selection is controlled by the M0, M1 and A0 pins. Each channel has two inputs (A0 and A1 and B0 and B1) that can be sampled and converted simultaneously, thus preserving the relative phase information of the signals on both analog inputs. The part accepts an analog input voltage in the range of –VREF to +VREF, centered around the internal +2.5V reference. The part will also accept bipolar input ranges when a level shift circuit is used at the front end (see Figure 7). All conversions are initiated on the ADS7861 by bringing the CONVST pin HIGH for a minimum of 15ns. CONVST HIGH places both sample-and-hold amplifiers in the hold state simultaneously and the conversion process is started on both channels. The RD pin can be connected to CONVST to simplify operation. Depending on the status of the M0, M1 and A0 pins, the ADS7861 will (a) operate in either twochannel or four-channel mode and (b) output data on both the Serial A and Serial B output or both channels can be transmitted on the A output only. NOTE: See the Timing and Control section of this data sheet for more information. SAMPLE-AND-HOLD SECTION The sample-and-hold amplifiers on the ADS7861 allow the ADCs to accurately convert an input sine wave of full-scale amplitude to 12-bit accuracy. The input bandwidth of the sample-and-hold is greater than the Nyquist rate (Nyquist equals one-half of the sampling rate) of the ADC even when the ADC is operated at its maximum throughput rate of 500kSPS. The typical small-signal bandwidth of the sampleand-hold amplifiers is 40MHz. Typical aperture delay time or the time it takes for the ADS7861 to switch from the sample to the hold mode following the CONVST pulse is 3.5ns. The average delta of repeated aperture delay values is typically 50ps (also known as aperture jitter). These specifications reflect the ability of the ADS7861 to capture AC input signals accurately at the exact same moment in time. REFERENCE Under normal operation, the REFOUT pin should be directly connected to the REFIN pin to provide an internal +2.5V reference to the ADS7861. The ADS7861 can operate, however, with an external reference in the range of 1.2V to 2.6V for a corresponding full-scale range of 2.4V to 5.2V. The internal reference of the ADS7861 is double-buffered. If the internal reference is used to drive an external load, a buffer is provided between the reference and the load applied to pin 2 (the internal reference can typically source 2mA of current load—capacitance should not exceed 100pF). If an external reference is used, the second buffer provides isolation between the external reference and the CDAC. This buffer is also used to recharge all of the capacitors of both CDACs during conversion. ANALOG INPUT The analog input is bipolar and fully differential. There are two general methods of driving the analog input of the ADS7861: single-ended or differential (see Figures 1 and 2). When the input is single-ended, the –IN input is held at the common-mode voltage. The +IN input swings around the same common voltage and the peak-to-peak amplitude is the (common-mode +VREF) and the (common-mode –VREF). The value of VREF determines the range over which the common-mode voltage may vary (see Figure 3). When the input is differential, the amplitude of the input is the difference between the +IN and –IN input, or (+IN) – (–IN). The peak-to-peak amplitude of each input is ±1/2VREF around this common voltage. However, since the inputs are 180° out of phase, the peak-to-peak amplitude of the differential voltage is +VREF to –VREF. The value of VREF also determines the range of the voltage that may be common to both inputs (see Figure 4). –VREF to +VREF peak-to-peak ADS7861 Common Voltage Single-Ended Input VREF peak-to-peak Common Voltage ADS7861 VREF peak-to-peak Differential Input FIGURE 1. Methods of Driving the ADS7861 Single-Ended or Differential. 8 ADS7861 SBAS110D +IN CM +VREF +VREF CM Voltage –IN = CM Voltage –VREF t CM –VREF CM +1/2VREF Single-Ended Inputs +IN +VREF CM Voltage –VREF CM –1/2VREF –IN t Differential Inputs NOTES: Common-Mode Voltage (Differential Mode) = (IN+) + (IN–) Common-Mode Voltage (Single-Ended Mode) = IN–. 2 The maximum differential voltage between +IN and –IN of the ADS7861 is VREF. See Figures 3 and 4 for a further explanation of the common voltage range for single-ended and differential inputs. FIGURE 2. Using the ADS7861 in the Single-Ended and Differential Input Modes. 5 5 4.7 VCC = 5V VCC = 5V 4.1 3 2.7 Single-Ended Input 2.3 2 1 0.9 0 3 Differential Input 2 1.0 1 0.3 0 –1 1.0 4.0 4 Common Voltage Range (V) Common Voltage Range (V) 4 –1 1.2 1.5 2.0 2.5 2.6 3.0 VREF (V) 1.0 1.2 1.5 2.0 2.5 2.6 3.0 VREF (V) FIGURE 3. Single-Ended Input: Common-Mode Voltage Range vs VREF. FIGURE 4. Differential Input: Common-Mode Voltage Range vs VREF. In each case, care should be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are matched. Otherwise, this may result in offset error, gain error and linearity error which will change with both temperature and input voltage. capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (15pF) to a 12-bit settling level within 2 clock cycles. When the converter goes into the hold mode, the input impedance is greater than 1GΩ. The input current on the analog inputs depend on a number of factors: sample rate, input voltage, and source impedance. Essentially, the current into the ADS7861 charges the internal capacitor array during the sampling period. After this Care must be taken regarding the absolute analog input voltage. The +IN input should always remain within the range of GND – 300mV to VDD + 0.3V. ADS7861 SBAS110D 9 TRANSITION NOISE Figure 5 shows a histogram plot for the ADS7861 following 8,000 conversions of a DC input. The DC input was set at output code 2046. All but one of the conversions had an output code result of 2046 (one of the conversions resulted in an output of 2047). The histogram reveals the excellent noise performance of the ADS7861. DESCRIPTION ANALOG INPUT Full-Scale Input Span –VREF to +VREF (1) Least Significant Bit (LSB) (–VREF to +VREF +Full Scale Midscale Midscale – 1 LSB –Full Scale BIPOLAR INPUTS The differential inputs of the ADS7861 were designed to accept bipolar inputs (–VREF and +VREF) around the internal reference voltage (2.5V), which corresponds to a 0V to 5V input range with a 2.5V reference. By using a simple op amp circuit featuring a single amplifier and four external resistors, the ADS7861 can be configured to except bipolar inputs. The conventional ±2.5V, ±5V, and ±10V input ranges can be interfaced to the ADS7861 using the resistor values shown in Figure 7. 8000 Number of Conversions 7000 6000 5000 )/4096 (2) DIGITAL OUTPUT BINARY TWO’S COMPLEMENT BINARY CODE HEX CODE 4.99878V 0111 1111 1111 7FF 2.5V 0000 0000 0000 000 2.49878V 1111 1111 1111 FFF 0V 1000 0000 0000 800 NOTES: (1) –VREF to +VREF around VREF. With a 2.5V reference, this corresponds to a 0V to 5V input span. (2) 1.22mV with a 2.5V reference. TABLE I. Ideal Input Voltages and Output Codes. TIMING AND CONTROL The operation of the ADS7861 can be configured in four different modes by using the address pins M0, M1 and A0. The M0 pin selects between two- and four-channel operation (in two-channel operation, the A0 pin selects between Channels 0 and 1; in four-channel operation the A0 pin is ignored and the channels are switched automatically after each conversion). The M1 pin selects between having serial data transmitted simultaneously on both the Serial A data output and the Serial B data output or having both channels output data through the Serial A port. The A0 pin selects either Channel 0 or Channel 1 (see Pin Descriptions and Serial Output Truth Table for more information). The next four sections will explain the four different modes of operation. 4000 3000 2000 1000 0 2044 2045 2046 2047 2048 Code (decimal) Mode I (M0 = 0, M1 = 0) With the M0 and M1 pins both set to ‘0’, the ADS7861 will operate in two-channel operation (the A0 pin must be used to switch between Channels A and B). A conversion is initiated by bringing CONVST HIGH for a minimum of 15ns. It is very important that CONVST be brought HIGH a minimum of 10ns prior to a rising edge of the external clock or 5ns after the rising edge. If CONVST is brought FIGURE 5. Histogram of 8,000 Conversions of a DC Input. R1 1.4V 4kΩ OPA132 20kΩ 3kΩ Bipolar Input DATA +IN –IN Test Point ADS7861 100pF CLOAD R2 REFOUT 2.5V VOH DATA VOL tR tF BIPOLAR INPUT R1 R2 ±10V ±5V ±2.5V 1kΩ 2kΩ 4kΩ 5kΩ 10kΩ 20kΩ Voltage Waveforms for DATA Rise and Fall Times tR, and tF. FIGURE 6. Test Circuits for Timing Specifications. 10 FIGURE 7. Level Shift Circuit for Bipolar Input Ranges. ADS7861 SBAS110D HIGH within this window, it is then uncertain as to when the ADS7861 will initiate conversion (see Figure 8 for a more detailed description). Sixteen clock cycles are required to perform a single conversion. Immediately following CONVST switching to HIGH, the ADS7861 will switch from the sample mode to the hold mode asynchronous to the external clock. The BUSY output pin will then go HIGH and remain HIGH for the duration of the conversion cycle. On the falling edge of the first cycle of the external clock, the ADS7861 will latch in the address for the next conversion cycle depending on the status of the A0 pin (HIGH = Channel 1, LOW = Channel 0). The address must be selected 15ns prior to the falling edge of cycle one of the external clock and must remain ‘held’ for 15ns following the clock edge. For maximum throughput time, the CONVST and RD pins should be tied together. CS must be brought LOW to enable the two serial outputs. Data will be valid on the falling edge of all 16 clock cycles per conversion. The first bit of data will be a status flag for either Channel 0 or 1, the second bit will be a second status flag for either Channel A or B. The subsequent data will be MSB-first through the LSB, followed by two zeros (see Table II and Figures 9 and 10). tCKP 125ns CLOCK Cycle 1 Cycle 2 10ns 10ns 5ns CONVST A 5ns B C NOTE: All CONVST commands which occur more than 10ns before the rising edge of cycle ‘1’ of the external clock (Region ‘A’) will initiate a conversion on the rising edge of cycle ‘1’. All CONVST commands which occur 5ns after the rising edge of cycle ‘1’ or 10ns before the rising edge of cycle 2 (Region ‘B’) will initiate a conversion on the rising edge of cycle ‘2’. All CONVST commands which occur 5ns after the rising edge of cycle ‘2’ (Region ‘C’) will initiate a conversion on the rising edge of the next clock period. The CONVST pin should never be switched from LOW to HIGH in the region 10ns prior to the rising edge of the CLOCK and 5ns after the rising edge (gray areas). If CONVST is toggled in this gray area, the conversion could begin on either the same rising edge of the CLOCK or the following edge. FIGURE 8. Conversion Mode. TIMING SPECIFICATIONS SYMBOL tCONV tACQ tCKP tCKL tCKH tF tR t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 DESCRIPTION MIN Conversion Time Acquisition Time Clock Period Clock LOW Clock HIGH DOUT Fall Time DOUT Rise Time CONVST HIGH Address Setup Time Address Hold Time RD Setup Time RD to CS Hold Time CONVST LOW RD LOW CS to Data Valid CLOCK to Data Valid Delay Data Valid After CLOCK(1) 1.75 0.25 125 40 40 TYP MAX UNITS 5000 25 30 15 15 15 15 15 20 20 25 30 1 COMMENTS µs µs ns ns ns ns ns ns ns When TCKP = 125ns When TCKP = 125ns ns ns ns ns ns ns ns Before falling edge of CLOCK After falling edge of CLOCK Address latched on falling edge of CLK cycle ‘2’ Maximum delay following rising edge of CLOCK Time data is valid after second rising edge of CLOCK NOTE: (1) ‘n – 1’ data will remain valid 1ns after rising edge of next CLOCK cycle. CLOCK CYCLE SERIAL DATA 1 2 CH0 OR CH1 CHA OR CHB 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 TABLE II. Serial Data Output Format. ADS7861 SBAS110D 11 Mode II (M0 = 0, M1 = 1) With M1 set to ‘1’, the ADS7861 will output data on the Serial Data A pin only. All other pins function in the same manner as Mode I except that the Serial Data B output will tri-state (i.e., high impedance) after a conversion following M1 going HIGH. Another difference in this mode involves the CONVST pin. Since it takes 32 clock cycles to output the results from both A/D converters (rather than 16 when M1 = 0), the ADS7861 will take 4µs to complete a conversion on both A/Ds (See Figure 11). Mode III (M0 = 1, M1 = 0) With M0 set to ‘1’, the ADS7861 will cycle through Channels 0 and 1 sequentially (the A0 pin is ignored). At the same time, setting M1 to ‘0’ places both Serial Outputs, A and B, in the active mode (See Figure 12). Mode IV (M0 = 1, M1 = 1) Similar to Mode II, Mode IV uses the Serial A output line to transmit data exclusively. Following the first conversion after M1 goes HIGH, the serial B output will go into tristate. See Figure 13. As in Mode II, the second CONVST command is always ignored when M1 = 1. READING DATA In all four timing diagrams, the CONVST pin and the RD pins are tied together. If so desired, the two lines can be separated. Data on the Serial Output pins (A and B) will become valid following the third rising SCLK edge following RD rising edge. Refer to Table II for data output format. LAYOUT For optimum performance, care should be taken with the physical layout of the ADS7861 circuitry. This is particularly true if the CLOCK input is approaching the maximum throughput rate. 12 The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving any single conversion for an n-bit SAR converter, there are n “windows” in which large external transient voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic or high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. Their error can change if the external event changes in time with respect to the CLOCK input. With this in mind, power to the ADS7861 should be clean and well-bypassed. A 0.1µF ceramic bypass capacitor should be placed as close to the device as possible. In addition, a 1µF to 10µF capacitor is recommended. If needed, an even larger capacitor and a 5Ω or 10Ω series resistor may be used to low pass filter a noisy supply. On average, the ADS7861 draws very little current from an external reference as the reference voltage is internally buffered. However, glitches from the conversion process appear at the VREF input and the reference source must be able to handle this. Whether the reference is internal or external, the VREF pin should be bypassed with a 0.1µF capacitor. An additional larger capacitor may also be used, if desired. If the reference voltage is external and originates from an op amp, make sure that it can drive the bypass capacitor or capacitors without oscillation. No bypass capacitor is necessary when using the internal reference (tie pin 10 directly to pin 11). The GND pin should be connected to a clean ground point. In many cases, this will be the ‘analog’ ground. Avoid connections which are too near the grounding point of a microcontroller or digital signal processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry. ADS7861 SBAS110D Conversion 1 Start of Conversion 2 tCKH CLOCK 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 tCKL t6 t1 CONVST t2 t3 A0 t4 t5 t7 RD CS t9 t10 t8 SERIAL DATA A SERIAL DATA B 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 D11 D10 D9 D8 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 D11 D10 D9 D8 BUSY tCONV tACQ tCONV FIGURE 9. Mode I with Timing Specifications. 1 16 CLOCK A0 RD Conversion of Ch0 Conversion of Ch1 CONVST A0 HIGH, Next Conversion: Ch1 A0 LOW, Next Conversion: Ch0 RD Connected to CONVST CS CS HIGH, Outputs in Tri-State SERIAL DATA A 12-Bit Data of Chx 12-Bit Data of ChA1 SERIAL DATA B 12-Bit Data of Chx 12-Bit Data of ChB1 BUSY TIME 0 Conversion of Chx 1µs Conversion of Ch0 Conversion of Ch1 2µs 3µs 4µs 5µs 6µs Time (seconds) FIGURE 10. Mode I, Timing Diagram for M0 = 0 and M1 = 0. ADS7861 SBAS110D 13 1 16 CLOCK Conversion of Chx CONVST M1 = 1 and 1st CONVST Conversion A0 HIGH Next Conversion Ch1 A0 M1 = 1 and 2nd CONVST No Conversion M1 = 1 and 1st CONVST Conversion A0 LOW Next Conversion Ch0 M1 = 1 and 2nd CONVST No Conversion A0 LOW Next Conversion Ch0 M1 M1 HIGH Only Serial Data A Used as Output Starting with 1st Conversion RD RD Connected with CONVST CS LOW Output Active CS SERIAL DATA A 12-Bit Data of ChAx C h A C h B M1 = 1 and 1st CONVST Data of ChA M1 = 1 and 1st CONVST Conversion Conversion of Chx BUSY C h M1 = 1 and 2nd CONVST B Data of ChB M1 = 1 Serial Data B in Tri-state 12-Bit Data of ChBx SERIAL DATA B C h M1 = 1 and 1st CONVST A Data of ChA M1 = 1 and 2nd CONVST Data of ChB M1 = 1 and 2nd CONVST No Conversion TIME 0 M1 = 1 and 1st CONVST Conversion M1 = 1 and 2nd CONVST No Conversion 5µs 10µs Time (seconds) FIGURE 11. Mode II, Timing Diagram for M0 = 0 and M1 = 1. 1 16 CLOCK 4-Ch Operation and 1st Conversion Ch0 CONVST M0 = 1 A0 Ignored A0 M0 RD 4-Ch Operation and 2nd Conversion Ch1 M0 = 1, 4-Ch Operation Starts with Next Conversion RD Connected with CONVST CS CS LOW, Output is Active SERIAL DATA A 12-Bit Data of ChAx C h 0 12-Bit Data of ChA0 C h 1 12-Bit Data of ChA1 SERIAL DATA B 12-Bit Data of ChBx C h 0 12-Bit Data of ChB0 C h 1 12-Bit Data of ChB1 BUSY TIME 0 1µs 2µs 3µs 4µs 5µs 6µs Time (seconds) FIGURE 12. Mode III, Timing Diagram for M0 = 1 and M1 = 0. 14 ADS7861 SBAS110D 1 16 CLOCK Conversion of Chx CONVST M1 = 1 and 1st CONVST Conversion M1 = 1 and 2nd CONVST No Conversion M1 = 1 and 1st CONVST Conversion M1 = 1 and 2nd CONVST No Conversion M0 HIGH 4-Ch Operation Starts, A0 Ignored A0 M0 = 1 and 1st Active CONVST Ch0 M0 = 1 and 2nd Active CONVST Ch1 M0 M0 HIGH 4-Ch Operation Starts M1 M1 HIGH Only Serial Data A Used as Output Starting with 1st Conversion RD RD Connected with CONVST CS LOW Output Active CS SERIAL DATA A SERIAL DATA B BUSY TIME 0 12-Bit Data of ChAx CC hh 0A M1 = 1 and 1st CONVST Data of ChA0 C C h h M1 = 1 and 1st CONVST 1 A Data of ChA1 CC h h M1 = 1 and 2nd CONVST 1B Data of ChB1 M1 = 1 Serial Data B in Tri-state 12-Bit Data of ChBx Conversion of Chx CC h h M1 = 1 and 2nd CONVST 0 B Data of ChB0 M1 = 1 and 1st CONVST Conversion M1 = 1 and 2nd CONVST No Conversion 5µs M1 = 1 and 1st CONVST Conversion M1 = 1 and 2nd CONVST No Conversion 10µs Time (seconds) FIGURE 13. Mode IV, Timing Diagram for M0 = 1 and M1 = 1. ADS7861 SBAS110D 15 Revision History DATE REVISION PAGE 8/07 D SECTION DESCRIPTION 6 Pin Configuration Added Note (1) to QFN package. 1 Entire Document Changed Throughput Rate from 500kHz to 500kSPS throughout document. 1 Features 1 Description 2 Added Operating Temperature Range: –40°C to +125°C. Changed Operating Temperature Range upper limit from +85°C to +125°C. Absolute Maximum Ratings Changed Operating Temperature Range upper limit from +85°C to +125°C. Changed top-of-page header condition to begin with: "Over recommended operating free-air temperature range at..." 8/06 Changed "TMIN to TMAX" to "TA = –40°C to +125°C" in several locations. C 3 Electrical Characteristics Added TA = –40°C to +85°C to conditions for these parameters: Bipolar Offset Error, Total Harmonic Distortion, Spurious-Free Dynamic Range, Quiescent Current, and Power Dissipation. Added new row for TA = –40°C to +125°C condition for these parameters: Bipolar Offset Error, Total Harmonic Distortion, Spuriouse-Free Dynamic Range, Quiescent Current, and Power Dissipation. Moved "VIN = ±2.5VPP at 100kHz" from conditions of Dynamic Characteristics to section header. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 16 ADS7861 SBAS110D PACKAGE OPTION ADDENDUM www.ti.com 10-Aug-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS7861E ACTIVE SSOP/ QSOP DBQ 24 ADS7861E/2K5 ACTIVE SSOP/ QSOP DBQ ADS7861E/2K5G4 ACTIVE SSOP/ QSOP ADS7861EB ACTIVE ADS7861EB/2K5 56 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SSOP/ QSOP DBQ 24 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ACTIVE SSOP/ QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS7861EB/2K5G4 ACTIVE SSOP/ QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS7861EBG4 ACTIVE SSOP/ QSOP DBQ 24 56 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS7861EG4 ACTIVE SSOP/ QSOP DBQ 24 56 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS7861IBRHBR ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS7861IBRHBRG4 ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS7861IBRHBT ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS7861IBRHBTG4 ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS7861IRHBR ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS7861IRHBRG4 ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS7861IRHBT ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS7861IRHBTG4 ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 56 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 10-Aug-2007 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 This package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink. The thermal pad must be soldered directly to the printed circuit board (PCB). After soldering, the PCB can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit (IC). PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) ADS7861E ACTIVE SSOP DBQ 24 50 RoHS & Green Call TI Level-2-260C-1 YEAR ADS7861E/2K5 ACTIVE SSOP DBQ 24 2500 RoHS & Green Call TI ADS7861EB ACTIVE SSOP DBQ 24 50 RoHS & Green ADS7861EB/2K5 ACTIVE SSOP DBQ 24 2500 ADS7861EB/2K5G4 ACTIVE SSOP DBQ 24 ADS7861IBRHBT ACTIVE VQFN RHB 32 -40 to 125 ADS7861E Samples Level-2-260C-1 YEAR ADS7861E Samples Call TI Level-2-260C-1 YEAR ADS7861E B Samples RoHS & Green Call TI Level-2-260C-1 YEAR ADS7861E B Samples 2500 RoHS & Green Call TI Level-2-260C-1 YEAR ADS7861E B Samples 250 RoHS & Green Call TI Level-2-260C-1 YEAR ADS 7861I B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of