ADS7863A
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SBAS610 – DECEMBER 2013
Dual, 2-MSPS, 12-Bit, 2 + 2 or 3 + 3 Channel, Simultaneous-Sampling,
Analog-to-Digital Converter
Check for Samples: ADS7863A
FEATURES
DESCRIPTION
•
•
•
•
The ADS7863A is a dual, 12-bit, 2-MSPS, analog-todigital converter (ADC) with four fully-differential or six
pseudo-differential input channels grouped into two
pairs for high-speed, simultaneous signal acquisition.
Inputs to the sample-and-hold (S/H) amplifiers are
fully differential and are maintained differential to the
ADC input. This architecture provides excellent
common-mode rejection of 72 dB at 100 kHz, which
is a critical performance characteristic in noisy
environments.
1
2
•
•
•
•
•
Four Fully- or Six Pseudo-Differential Inputs
SNR: 71 dB
THD: –81 dB
Programmable and Buffered Internal 2.5-V
Reference
Flexible Power-Down Features
Variable Power-Supply Ranges: 2.7 V to 5.5 V
Low-Power Operation: 45 mW at 5 V
Operating Temperature Range:
–40°C to +125°C
Pin-Compatible with the ADS7861 and
ADS8361 (SSOP Package)
The device is pin-compatible with the ADS7861, but
offers additional features such as a programmable
reference output, flexible supply voltage (2.7 V to
5.5 V for AVDD and BVDD), a pseudo-differential input
multiplexer with three channels per ADC, and several
power-down features.
APPLICATIONS
•
•
•
The device is offered in an SSOP-24 and a 4-mm ×
4-mm QFN-24 package. The device is specified over
the extended operating temperature range of –40°C
to +125°C.
Motor Control
Multi-Axis Positioning Systems
Three-Phase Power Control
SAR
BVDD
AVDD
SDOA
CHA0+
CHA1+
SDOB
Input
MUX
S/H
M0
CDAC
CHA1-
Comparator
CHB0+
CHB0CHB1+
Input
MUX
S/H
CDAC
Serial Interface
CHA0-
M1
SDI
CLOCK
CS
RD
CHB1-
Comparator
BUSY
CONVST
REFIN
SAR
REFOUT
10-Bit DAC
BGND
2.5-V Reference
AGND
Functional Block Diagram
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
ADS7863A
SBAS610 – DECEMBER 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
Supply voltage
VALUE
UNIT
AVDD to AGND
–0.3 to +6
V
BVDD to BGND
–0.3 to +6
V
1.5 × AVDD
V
Analog and reference input voltage with respect to AGND
BVDD to AVDD
AGND – 0.3 to AVDD + 0.3
V
Digital input voltage with respect to BGND
BGND – 0.3 to BVDD + 0.3
V
0.3
V
Input current to any pin except supply pins
–10 to +10
mA
Maximum virtual junction temperature, TJ
+150
°C
Human body model (HBM),
JEDEC standard 22, test method
A114-C.01, all pins
±4000
V
Charged device model (CDM),
JEDEC standard 22, test method
C101, all pins
±1500
V
Ground voltage difference
|AGND – BGND|
Electrostatic discharge (ESD) ratings
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range, unless otherwise noted.
PARAMETER
Supply voltage
MIN
NOM
MAX
AVDD to AGND
2.7
5.0
5.5
V
BVDD to BGND, low voltage levels
2.7
3.6
V
BVDD to BGND, 5-V logic levels
4.5
5.0
5.5
V
0.5
2.5
2.525
V
–VREF
+VREF
V
–40
+125
°C
Reference input voltage on REFIN
Analog differential input voltage
(CHXX+) – (CHXX–)
Operating ambient temperature range, TA
UNIT
THERMAL INFORMATION
ADS7863A
THERMAL METRIC (1)
DBQ (SSOP)
RGE (QFN)
24 PINS
24 PINS
θJA
Junction-to-ambient thermal resistance
80.9
35.0
θJCtop
Junction-to-case (top) thermal resistance
44.6
36.1
θJB
Junction-to-board thermal resistance
34.2
12.8
ψJT
Junction-to-top characterization parameter
9.2
0.5
ψJB
Junction-to-board characterization parameter
33.8
12.8
θJCbot
Junction-to-case (bottom) thermal resistance
n/a
4.1
(1)
2
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SBAS610 – DECEMBER 2013
ELECTRICAL CHARACTERISTICS
At TA = –40°C to +125°C, entire power-supply range, VREF = 2.5 V (internal), fCLK = 32 MHz, and tDATA = 2 MSPS, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
RESOLUTION
Resolution
12
Bits
ANALOG INPUT
FSR
Full-scale differential input range
(CHxx+) – (CHxx–)
VIN
Absolute input voltage
CHxx+ or CHxx+ to AGND
CIN
Input capacitance
CHxx+ or CHxx– to AGND
CID
Differential input capacitance
IIL
Input leakage current
CMRR
Common-mode rejection ratio
–VREF
+VREF
–0.1
AVDD + 0.1
V
V
2
pF
4
–1
Both ADCs, dc to 100 kHz
pF
+1
nA
72
dB
DC ACCURACY
–1.25
±0.6
+1.25
LSB
–1
±0.5
+1
LSB
Differential nonlinearity
–1
±0.5
+1
LSB
Input offset error
–3
±0.5
+3
LSB
VOS match
–3
±0.5
+3
LSB
INL
Integral nonlinearity
DNL
VOS
dVOS/dT
Input offset thermal drift
GERR
Gain error
–40°C < TA < +125°C
–40°C < TA < +85°C
μV/°C
±3
Referred to voltage at REFIN
GERR match
–0.5%
–0.5%
+0.5%
±0.1%
+0.5%
GERR/dT
Gain error thermal drift
Referred to voltage at REFIN
±1
ppm/°C
PSRR
Power-supply rejection ratio
AVDD = 5.5 V
70
dB
dB
AC ACCURACY
SINAD
Signal-to-noise + distortion
VIN = 5 VPP at 100 kHz
69.8
71
SNR
Signal-to-noise ratio
VIN = 5 VPP at 100 kHz
70
71.5
THD
Total harmonic distortion
VIN = 5 VPP at 100 kHz
SFDR
Spurious-free dynamic range
VIN = 5 VPP at 100 kHz
76
1 MHz < fCLK ≤ 32 MHz
16
–81
dB
–76
dB
84
dB
SAMPLING DYNAMICS
tCONV
Conversion time per ADC
tACQ
Acquisition time
tDATA
Data rate
tA
Aperture delay
tCLK
2
1 MHz < fCLK ≤ 32 MHz
tCLK
62.5
2000
kSPS
6
tA match
50
tAJIT
Aperture jitter
50
fCLK
Clock frequency on CLOCK
TCLK
Clock period
ns
ps
ps
1
32
31.25
1000
MHz
ns
INTERNAL VOLTAGE REFERENCE
Resolution
Reference output DAC resolution
10
Over 20% to 100% DAC range
VREFOUT
Reference output voltage
dVREFOUT/dT
Reference voltage drift
DNLDAC
DAC differential nonlinearity
INLDAC
DAC integral nonlinearity
VOSDAC
DAC offset error
PSRR
Power-supply rejection ratio
IREFOUT
Reference output dc current
(1)
Bits
0.2 VREFOUT
VREFOUT
V
V
DAC = 3FFh,
–40°C < TA < +125°C
2.485
2.500
2.515
DAC = 3FFh at +25°C
2.495
2.500
2.505
±10
VREFOUT = 0.5 V
V
ppm/°C
–9.76
±2.44
9.76
mV
–4
±1
4
LSB
–9.76
±1.22
9.76
mV
–4
±0.5
4
LSB
–9.76
±2.44
9.76
mV
–4
±1
4
LSB
+2
mA
73
–2
dB
All typical values are at TA = +25°C.
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ELECTRICAL CHARACTERISTICS (continued)
At TA = –40°C to +125°C, entire power-supply range, VREF = 2.5 V (internal), fCLK = 32 MHz, and tDATA = 2 MSPS, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
INTERNAL VOLTAGE REFERENCE (continued)
IREFSC
Reference output short-circuit current (2)
50
mA
tREFON
Reference output settling time
0.5
ms
VOLTAGE REFERENCE INPUT
VREF
Reference input voltage range
IREF
Reference input current
0.5
50
2.525
μA
V
CREF
Reference input capacitance
10
pF
DIGITAL INPUTS (Logic Family: CMOS with Schmitt-Trigger)
VIH
High-level input voltage
0.7 × BVDD
BVDD + 0.3
VIL
Low-level input voltage
–0.3
0.3 × BVDD
V
IIN
Input current
–50
+50
nA
CIN
Input capacitance
VIN = BVDD to BGND
5
V
pF
DIGITAL OUTPUTS (Logic Family: CMOS)
VOH
High-level output voltage
BVDD = 4.5 V, IOH = –100 μA
VOL
Low-level output voltage
BVDD = 4.5 V, IOH = 100 μA
IOZ
High-impedance-state output current
COUT
Output capacitance
CLOAD
Load capacitance
BVDD – 0.2
V
–50
0.2
V
+50
nA
5
pF
30
pF
V
POWER SUPPLY
AVDD
Analog supply voltage
AVDD to AGND
2.7
5.0
5.5
BVDD
Buffer I/O supply voltage
BVDD to BGND
2.7
3.0
5.5
AVDD = 2.7 V
4.5
6
mA
AVDD = 5.0 V
6.5
8
mA
AVDD = 2.7 V, NAP power-down
1.1
1.5
mA
AVDD = 5.0 V, NAP power-down
1.4
2.0
mA
AVDD = 2.7 V, deep power-down
0.001
mA
AVDD = 5.0 V, deep power-down
0.001
mA
mA
AIDD
Analog supply current
BIDD
Buffer I/O supply current
PDISS
(2)
Power dissipation
V
BVDD = 2.7 V, CLOAD = 10 pF
0.5
1.3
BVDD = 3.3 V, CLOAD = 10 pF
0.9
1.6
mA
AVDD = 2.7 V, BVDD = 2.7 V
13.5
19.7
mW
AVDD = 5.0 V, BVDD = 3.3 V
35.5
45.3
mW
Reference output current is not limited internally.
PARAMETRIC MEASUREMENT INFORMATION
EQUIVALENT INPUT CIRCUIT
RSER = 200 W
RSW = 50 W
CHxx+
CPAR = 5 pF
CS = 2 pF
CPAR = 5 pF
CS = 2 pF
CHxxRSER = 200 W
RSW = 50 W
Figure 1. Equivalent Input Circuit
4
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SBAS610 – DECEMBER 2013
TIMING CHARACTERISTICS
Conversion 1
Conversion 2
tCKH
CLOCK
0
1
2
3
4
5
6
7
8
tCKL
9
10
11
12
13
14
15
t1
16
1
2
3
C1
C0
P1
4
t6
CONVST
t10
t11
tCONV
BUSY
t4
tACQ
t5
t7
RD
t3
SDI
C1
C0
P1
P0
t2
DP
N
AN
RP
S4
A2
A0
A1
t12
CS
t8
t9
Serial
Data A
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
D11
Serial
Data B
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
D11
Figure 2. Detailed Timing Diagram (Mode I)
CLOCK
Cycle 1
Cycle 2
10 ns
10 ns
5 ns
CONVST
A
B
5 ns
C
NOTE: All CONVST commands that occur more than 10 ns before the cycle 1 rising edge of the external clock (region A) initiate a
conversion on the cycle 1 rising edge. All CONVST commands that occur 5 ns after the cycle 1 rising edge or 10 ns before the cycle 2 rising
edge (region B) initiate a conversion on the cycle 2 rising edge. All CONVST commands that occur 5 ns after the cycle 2 rising edge (region
C) initiate a conversion on the rising edge of the next clock period.
The CONVST pin should never be switched from low to high in the region 10 ns prior to the CLOCK rising edge and 5 ns after the rising edge
(gray areas). If CONVST is toggled in this gray area, the conversion could begin on either the same CLOCK rising edge or the following
edge.
Figure 3. CONVST Timing
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TIMING REQUIREMENTS (1)
Over recommended operating free-air temperature range at –40°C to +125°C, AVDD = 5 V, and BVDD = 2.7 V to 5 V, unless
otherwise noted.
PARAMETER
COMMENTS
MIN
MAX
UNIT
tCONV
Conversion time
fCLOCK = 32 MHz
406.25
tACQ
Acquisition time
fCLOCK = 32 MHz
62.5
fCLOCK
CLOCK frequency
See Figure 2
1
32
tCLOCK
CLOCK period
See Figure 2
31.25
1000
tCKL
CLOCK low time
See Figure 2
9.4
ns
tCKH
CLOCK high time
See Figure 2
9.4
ns
t1
CONVST high time
See Figure 2
20
ns
t2
SDI setup time to CLOCK falling edge
See Figure 2
10
ns
t3
SDI hold time to CLOCK falling edge
See Figure 2
5
ns
t4
RD high setup time to CLOCK falling edge
See Figure 2
10
ns
t5
RD high hold time to CLOCK falling edge
See Figure 2
5
ns
t6
CONVST low time
See Figure 2
1
tCLOCK
t7
RD low time relative to CLOCK falling edge
See Figure 2
1
tCLOCK
t8
CS low to SDOx valid
See Figure 2
13
ns
t9
CLOCK rising edge to DATA valid delay
(MIN = minimum hold time of current data;
MAX = maximum delay to new data valid)
ns
ns
MHz
ns
See Figure 2,
2.7 V ≤ BVDD ≤ 3.6 V
4
11
ns
See Figure 2,
4.5 V ≤ BVDD ≤ 5.5 V
3
9
ns
t10
CONVST rising edge to BUSY high delay (2)
See Figure 2
3
ns
t11
CLOCK rising edge to BUSY low delay
See Figure 2
3
ns
t12
CS low to RD high delay
See Figure 2
10
ns
(1)
(2)
6
All input signals are specified with tR = tF = 1.5 ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH) / 2.
Not applicable in auto-NAP power-down mode.
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SBAS610 – DECEMBER 2013
PIN CONFIGURATIONS
DBQ PACKAGE
SSOP-24
(Top View)
CHA0-
9
16
SDI
REFIN
10
15
M0
REFOUT
11
14
M1
AGND
12
13
AVDD
CHB1-
CONVST
19
17
CHB1+
17
BGND
REFOUT
3
16
BVDD
AGND
4
15
SDOA
AVDD
5
14
SDOB
M1
6
13
BUSY
M0
12
RD
8
18
2
CLOCK
CHA1CHA0+
CHB0+
CS
18
CHB0-
19
7
20
6
1
REFIN
11
CHA1+
CHA0-
CS
CLOCK
RD
BUSY
20
CHA1+
21
5
21
4
CHB0-
22
CHB0+
9
SDOB
10
22
CONVST
3
CHA0+
SDOA
CHB1-
CHA1-
CHB1+
23
BVDD
23
8
24
2
7
1
SDI
BGND
24
RGE PACKAGE
4-mm × 4-mm QFN-24
(TOP VIEW)
PIN DESCRIPTIONS
PIN NUMBER
NAME
SSOP
QFN
AGND
12
4
DESCRIPTION
Analog ground. Connect to analog ground plane.
AVDD
13
5
Analog power supply, 2.7 V to 5.5 V. Decouple to AGND with a 1-μF ceramic capacitor.
BGND
1
17
Buffer I/O ground. Connect to digital ground plane.
BUSY
21
13
ADC busy indicator. BUSY goes high when the inputs are in hold mode and returns to low after the
conversion finishes.
BVDD
24
16
Buffer I/O supply, 2.7 V to 5.5 V. Decouple to BGND with a 1-μF ceramic capacitor.
CHA0–
9
1
Inverting analog input channel A0
CHA0+
8
24
Noninverting analog input channel A0
CHA1–
7
23
Inverting analog input channel A1
CHA1+
6
22
Noninverting analog input channel A1
CHB0–
5
21
Inverting analog input channel B0
CHB0+
4
20
Noninverting analog input channel B0
CHB1–
3
19
Inverting analog input channel B1
CHB1+
2
18
Noninverting analog input channel B1
CLOCK
20
12
External clock input
CONVST
17
9
Conversion start. The ADC switches from sample mode into hold mode on the CONVST rising edge,
independent of the CLOCK status. The conversion starts with the next CLOCK rising edge.
CS
19
11
Chip select. When low, the SDOx outputs are active; when high, the SDOx outputs 3-state.
M0
15
7
Mode pin 0. Selects between analog input channels (see Table 8).
M1
14
6
Mode pin 1. Selects between the SDOx digital outputs (see Table 8).
RD
18
10
Read data. Synchronization pulse for the SDOx outputs and SDI input. RD only triggers when CS is low.
REFIN
10
2
Reference voltage input. A 470-nF ceramic capacitor (min) is required at this terminal.
REFOUT
11
3
Reference voltage output. The programmable internal voltage reference output is available on this pin.
SDI
16
8
Serial data input. This pin allows the additional device features to be used but SDI can also be used in an
ADS7861-compatible manner.
SDOA
23
15
Serial data output for converter A. When M1 is high, both SDOA and SDOB are active. Data are valid on
the falling CLOCK edge.
SDOB
22
14
Serial data output for converter B. Data are valid on the falling CLOCK edge.
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TYPICAL CHARACTERISTICS
Over the entire supply voltage range, VREF = 2.5 V (internal), fCLK = 32 MHz, and tDATA = 2 MSPS, unless otherwise noted.
1
1
0.8
0.75
0.6
0.5
0.2
INL (LSB)
INL (LSB)
Positive
Positive
0.4
0
-0.2
Negative
-0.4
0.25
0
-0.25
Negative
-0.5
-0.6
-0.75
-0.8
-1
-40 -25 -10
-1
0.5
0.75
1
1.25
1.5
1.75
2
5
Data Rate (MSPS)
1
1
0.75
0.75
0.5
0.5
0.25
0.25
0
-0.25
95
110 125
0
-0.25
-0.5
-0.5
-0.75
-0.75
-1
-1
0
512
1024
1536
2048
2560
3072
3584
4096
0
512
1024
1536
Code
2048
2560
3072
3584
4096
Code
Figure 6. INTEGRAL NONLINEARITY vs CODE
Figure 7. DIFFERENTIAL NONLINEARITY vs CODE
1
1
0.8
0.75
0.6
Positive
0.4
0.5
Positive
DNL (LSB)
DNL (LSB)
80
Figure 5. INTEGRAL NONLINEARITY vs TEMPERATURE
DNL (LSB)
INL (LSB)
Figure 4. INTEGRAL NONLINEARITY vs DATA RATE
20 35 50 65
Temperature (°C)
0.2
0
-0.2
Negative
-0.4
0.25
0
-0.25
Negative
-0.5
-0.6
-0.75
-0.8
-1
0.5
0.75
1
1.25
1.5
1.75
2
-1
-40 -25 -10
Data Rate (MSPS)
Figure 8. DIFFERENTIAL NONLINEARITY vs DATA RATE
8
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 9. DIFFERENTIAL NONLINEARITY vs
TEMPERATURE
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TYPICAL CHARACTERISTICS (continued)
Over the entire supply voltage range, VREF = 2.5 V (internal), fCLK = 32 MHz, and tDATA = 2 MSPS, unless otherwise noted.
2
Offset and Offset Match (LSB)
Offset and Offset Match (LSB)
1
0.8
0.6
0.4
0.2
Offset Match
0
-0.2
Offset
-0.4
-0.6
-0.8
3
3.3
3.6
3.9
4.2
4.5
4.8
5.1
1
Offset Match
0.5
0
Offset
-0.5
-1
-1.5
-2
-40 -25 -10
-1
2.7
1.5
5.5
5
AVDD (V)
Figure 10. OFFSET ERROR AND OFFSET MATCH
vs ANALOG SUPPLY VOLTAGE
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 11. OFFSET ERROR AND OFFSET MATCH
vs TEMPERATURE
0.2
0.1
Gain and Gain Match (%)
Gain and Gain Match (%)
0.15
0.05
Gain Match
0
Gain
-0.05
Gain Match
0.1
0.05
0
Gain
-0.05
-0.1
-0.15
-0.2
-40 -25 -10
-0.1
2.7
3
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.5
5
AVDD (V)
74
74
73.5
73.5
73
73
72.5
72.5
72
71.5
70.5
70.5
70
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.5
70
-40 -25 -10
AVDD (V)
Figure 14. COMMON-MODE REJECTION RATIO
vs ANALOG SUPPLY VOLTAGE
110 125
71.5
71
3
95
72
71
2.7
80
Figure 13. GAIN ERROR AND GAIN MATCH
vs TEMPERATURE
CMRR (dB)
CMRR (dB)
Figure 12. GAIN ERROR AND GAIN MATCH
vs ANALOG SUPPLY VOLTAGE
20 35 50 65
Temperature (°C)
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 15. COMMON-MODE REJECTION RATIO
vs TEMPERATURE
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TYPICAL CHARACTERISTICS (continued)
0
0
-20
-20
-40
-40
Amplitude (dB)
Amplitude (dB)
Over the entire supply voltage range, VREF = 2.5 V (internal), fCLK = 32 MHz, and tDATA = 2 MSPS, unless otherwise noted.
-60
-80
-60
-80
-100
-100
-120
-120
-140
-140
0
200k
400k
600k
800k
1M
0
100
200
Frequency (Hz)
300
400
500
600
700 750
Frequency (kHz)
Figure 16. FREQUENCY SPECTRUM
(4096-Point FFT; fIN = 100 kHz)
Figure 17. FREQUENCY SPECTRUM
(4096-Point FFT; fIN = 100 kHz, fSAMPLE = 1.5 MSPS)
73
74
73
72.5
72
SINAD (dB)
SINAD (dB)
AVDD = 5 V
AVDD = 2.7 V
71
72
AVDD = 5 V
71.5
70
71
69
70.5
70
-40 -25 -10
68
20
40
60
80
100
120
140
160
180
AVDD = 2.7 V
200
5
fIN (kHz)
Figure 18. SIGNAL-TO-NOISE RATIO AND DISTORTION
vs INPUT SIGNAL FREQUENCY
95
110 125
73
73
72.5
AVDD = 5 V
AVDD = 5 V
72
72
AVDD = 2.7 V
SNR (dB)
SNR (dB)
80
Figure 19. SIGNAL-TO-NOISE RATIO AND DISTORTION
vs TEMPERATURE
74
71
71.5
70
71
69
70.5
68
20
40
60
80
100
120
140
160
180
200
Figure 20. SIGNAL-TO-NOISE RATIO
vs INPUT SIGNAL FREQUENCY
AVDD = 2.7 V
70
-40 -25 -10
fIN (kHz)
10
20 35 50 65
Temperature (°C)
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 21. SIGNAL-TO-NOISE RATIO vs TEMPERATURE
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TYPICAL CHARACTERISTICS (continued)
Over the entire supply voltage range, VREF = 2.5 V (internal), fCLK = 32 MHz, and tDATA = 2 MSPS, unless otherwise noted.
-78
-76
-78
-80
AVDD = 5 V
AVDD = 2.7 V
-80
THD (dB)
THD (dB)
-82
AVDD = 2.7 V
-82
-84
-86
-84
AVDD = 5 V
-86
-88
-88
-90
-90
-40 -25 -10
-92
20
fIN (kHz)
20 35 50 65
Temperature (°C)
Figure 22. TOTAL HARMONIC DISTORTION
vs INPUT SIGNAL FREQUENCY
Figure 23. TOTAL HARMONIC DISTORTION
vs TEMPERATURE
40
60
80
100
120
140
160
180
200
5
80
95
110 125
90
92
90
AVDD = 2.7 V
88
88
AVDD = 5 V
SFDR (dB)
SFDR (dB)
86
AVDD = 5 V
84
82
86
84
AVDD = 2.7 V
80
82
78
80
-40 -25 -10
76
20
fIN (kHz)
20 35 50 65
Temperature (°C)
Figure 24. SPURIOUS-FREE DYNAMIC RANGE
vs INPUT SIGNAL FREQUENCY
Figure 25. SPURIOUS-FREE DYNAMIC RANGE
vs TEMPERATURE
40
60
80
100
120
140
160
180
200
8
1
7
0.9
AVDD = 5 V
0.8
80
95
110 125
BVDD = 3.3 V
0.7
BVDD (mA)
AVDD (mA)
6
5
5
AVDD = 2.7 V
4
3
0.6
0.5
0.4
BVDD = 2.7 V
0.3
2
0.2
1
0.1
0
0
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 26. ANALOG SUPPLY CURRENT vs TEMPERATURE
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 27. DIGITAL SUPPLY CURRENT vs TEMPERATURE
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TYPICAL CHARACTERISTICS (continued)
Over the entire supply voltage range, VREF = 2.5 V (internal), fCLK = 32 MHz, and tDATA = 2 MSPS, unless otherwise noted.
1.4
6
1.2
5
AVDD = 5 V
Reference ON
1
AVDD (mA)
AVDD (mA)
4
3
Reference OFF
2
AVDD = 2.7 V
0.8
0.6
0.4
1
0.2
0
0
0
500
1000
1500
-40 -25 -10
2000
5
20 35 50 65
Temperature (°C)
Data Rate (kSPS)
Figure 28. ANALOG SUPPLY CURRENT vs DATA RATE
(Auto-NAP Mode)
95
110 125
Figure 29. ANALOG SUPPLY CURRENT vs TEMPERATURE
(Auto-NAP Mode)
2.505
1400
2.504
1200
2.503
Clock ON
1000
2.502
VREFOUT (V)
AVDD (mA)
80
800
600
2.501
2.5
2.499
2.498
400
2.497
200
2.496
Clock OFF
2.495
0
0
10
20
30
40
50
60
70
-40 -25 -10
Data Rate (kSPS)
Figure 30. ANALOG SUPPLY CURRENT vs DATA RATE
(Deep Power-Down Mode)
12
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 31. REFERENCE OUTPUT VOLTAGE
vs TEMPERATURE
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APPLICATIONS INFORMATION
GENERAL DESCRIPTION
The ADS7863A includes two 12-bit, analog-to-digital converters (ADCs) that operate based on the successiveapproximation register (SAR) principle. The ADCs sample and convert simultaneously. Conversion time can be
as low as 406.25 ns. Adding the 62.5-ns acquisition time and an additional clock cycle for setup and hold time
requirements and skew results in a maximum conversion rate of 2 MSPS.
Each ADC has a fully-differential, 2:1 multiplexer front-end. In many common applications, all negative input
signals remain at the same constant voltage (for example, 2.5 V). In this type of application, the multiplexer can
be used in a pseudo-differential 3:1 mode, where CHx0– functions as a common-mode input and the remaining
three inputs (CHx0+, CHx1–, and CHx1+) operate as separate inputs referred to the common-mode input.
The ADS7863A also includes a 2.5-V internal reference. The reference drives a 10-bit digital-to-analog converter
(DAC), allowing the voltage at the REFOUT pin to be adjusted via the serial interface in 2.44-mV steps. A lownoise operational amplifier with unity gain buffers the DAC output voltage and drives the REFOUT pin.
The ADS7863A offers a serial interface that is compatible with the ADS7861. However, instead of the A0 pin of
the ADS7861 controlling channel selection, the ADS7863A offers a serial data input (SDI) pin that supports
additional functions described in the Digital section (see also the ADS7861 Compatibility section).
ANALOG
This section addresses the analog input circuit, the ADCs, and the reference design of the device.
Analog Inputs
Each ADC is fed by an input multiplexer, as shown in Figure 32. Each multiplexer is either used in a fullydifferential 2:1 configuration (as described in Table 1) or a pseudo-differential 3:1 configuration (as shown in
Table 2). The channel selection is performed using bits C1 and C0 in the SDI register (see also the Serial Data
Input section).
CHx1+
CHx1CHx0+
Input
MUX
ADC+
ADC-
CHx0-
Figure 32. Input Multiplexer Configuration
The input path for the converter is fully differential and provides a common-mode rejection of 72 dB at 100 kHz.
The high CMRR also helps suppress noise in harsh industrial environments.
Table 1. Fully Differential 2:1 Multiplexer Configuration
C1
C0
ADC+
ADC–
0
0
CHx0+
CHx0–
1
1
CHx1+
CHx1–
Table 2. Pseudo-Differential 3:1 Multiplexer Configuration
C1
C0
ADC+
ADC–
0
0
CHx0+
CHx0–
0
1
CHx1–
CHx0–
1
0
CHx1+
CHx0–
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Each 2-pF sample-and-hold capacitor (defined as CS in Figure 1) is connected via switches to the multiplexer
output. Opening the switches holds the sampled data during the conversion process. After finishing the
conversion, both capacitors are pre-charged for the duration of one clock cycle to the voltage present at the
REFIN pin. After the pre-charging, the multiplexer outputs are connected to the sampling capacitors again. The
voltage at the analog input pin is usually different from the reference voltage; therefore, the sample capacitors
must be charged to within one-half LSB for 12-bit accuracy during the acquisition time tACQ (see the Timing
Characteristics).
Acquisition time is indicated with the BUSY signal being held low. tACQ starts by closing the input switches (after
finishing the previous conversion and pre-charging) and finishes with the rising edge of the CONVST signal. If
the ADS7863A operates at full speed, the acquisition time is typically 62.5 ns.
The minimum –3-dB bandwidth of the driving operational amplifier can be calculated as shown in Equation 1:
ln(2) ´ (n + 1)
f-3dB =
2p ´ tACQ
where:
•
n = 12 is the device resolution
(1)
With tACQ = 62.5 ns, the minimum bandwidth of the driving amplifier is 23 MHz. The required bandwidth can be
lower if the application allows a longer acquisition time.
A gain error occurs if a given application does not fulfill the settling requirement shown in Equation 1. As a result
of pre-charging the capacitors, linearity and THD are not directly affected, however.
The OPA365 from Texas Instruments is recommended as a driver; in addition to offering the required bandwidth,
the OPA365 provides a low offset and also offers excellent THD performance.
The phase margin of the driving operational amplifier is usually reduced by the ADC sampling capacitor. A
resistor placed between the capacitor and amplifier limits this effect; therefore, an internal 200-Ω resistor (RSER)
is placed in series with the switch. The switch resistance (RSW) is typically 50 Ω (see Figure 1).
The differential input voltage range of the ADC is ±VREF, the voltage at the REFIN pin.
The voltage to all inputs must be kept within the 0.3-V limit below AGND and above AVDD while not allowing dc
current to flow through the inputs. Current is only necessary to recharge the sample-and-hold capacitors.
Analog-to-Digital Converter (ADC)
The ADS7863A includes two SAR-type, 2-MSPS, 12-bit ADCs (see the functional block diagram on the front
page of this data sheet).
CONVST
The analog inputs are held with the rising edge of the CONVST (conversion start) signal. The CONVST setup
time referred to the next rising edge of CLOCK (system clock) is 10 ns (minimum). The conversion automatically
starts with the rising CLOCK edge. CONVST should not be issued during a conversion, that is, when BUSY is
high.
RD (read data) and CONVST can be shorted to minimize necessary software and wiring. The RD signal is
triggered by the ADS7863A on the falling CLOCK edge. Therefore, the combined signals must be activated with
the rising CLOCK edge. The conversion then starts with the subsequent rising CLOCK edge.
CLOCK
The ADC uses an external clock in the range of 1 MHz to 32 MHz. 12 clock cycles are needed for a complete
conversion; the following clock cycle is used for pre-charging the sample capacitors and a minimum of two clock
cycles are required for the sampling. With a minimum of 16 clocks used for the entire process, one clock cycle is
left for the required setup and hold times along with some margin for delay caused by layout. The clock input can
remain low between conversions (after applying the 16th falling edge to complete a running conversion). The
input can also remain low after applying the 14th falling edge during a DAC register write access if the device is
not required to perform a conversion on CHBx (for example, during an initiation phase after power-up).
The CLOCK duty cycle should be 50%. However, the ADS7863A functions properly with a duty cycle between
30% and 70%.
14
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RESET
The ADS7863A features an internal power-on-reset (POR) function. When the device is powered up, the POR
sets the device in default mode when AVDD reaches 1.8 V. An external software reset can be issued using the
SDI register bits A[2:0] (see the Digital section).
REFIN
The reference input is not buffered and is directly connected to the ADC. The converter generates spikes on the
reference input voltage because of internal switching. Therefore, an external capacitor to the analog ground
(AGND) should be used to stabilize the reference input voltage. This capacitor should be at least 470 nF.
Ceramic capacitors (X5R type) with values up to 1 μF are commonly available as SMD in 0402 size.
REFOUT
The ADS7863A includes a low-drift, 2.5-V internal reference source. This source feeds a 10-bit string DAC that is
controlled via the serial interface. As a result of this architecture, the voltage at the REFOUT pin is programmable
in 2.44-mV steps and can be adjusted to specific application requirements without the use of additional external
components.
However, the DAC output voltage should not be programmed below 0.5 V to ensure the correct functionality of
the reference output buffer. This buffer is connected between the DAC and the REFOUT pin, and is capable of
driving the capacitor at the REFIN pin. A minimum of 470 nF is required to keep the reference stable (see the
REFIN section). For applications that use an external reference source, the internal reference can be disabled
using bit RP in the SDI register (see the Digital section). The settling time of the REFOUT pin is 500 μs
(maximum) with the reference capacitor connected. The default value of the REFOUT pin after power-up is 2.5 V.
For operation with a 2.7-V analog supply and a 2.5-V reference, the internal reference buffer requires a rail-to-rail
input and output. Such buffers typically contain two input stages; when the input voltage passes the mid-range
area, a transition occurs at the output because of switching between the two input stages. In this voltage range,
rail-to-rail amplifiers generally show a very poor power-supply rejection.
As a result of this poor performance, the ADS7863A buffer has a fixed transition at DAC code 509 (1FDh). At this
code, the DAC may show a jump of up to 10 mV in the transfer function.
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DIGITAL
This section addresses the timing and control of the ADS7863A serial interface.
Serial Data Input (SDI)
The serial data input or SDI pin is coupled to RD and clocked into the ADS7863A on each falling CLOCK edge.
The data word length of the SDI register is 12 bits. Table 3 shows the register structure. Data must be
transferred MSB-first. Table 4 through Table 6 describe specific bits of this register. The default value of this
register after power-up is 000h.
Table 3. SDI Register Contents
SDI REGISTER BIT
11
10
9
8
7
6
5
4
3
2
1
0
C1
C0
P1
P0
DP
N
AN
RP
S4
A2
A1
A0
Table 4. C1 and C0: Channel Selection
C1
C0
0
0
0
1
1
ADC A, B
POSITIVE INPUT
NEGATIVE INPUT
CHA0+, CHB0+
CHA0–, CHB0–
1
CHA1–, CHB1–
CHA0–, CHB0–
0
CHA1+, CHB1+
CHA0–, CHB0–
1
CHA1+, CHB1+
CHA1–, CHB1–
Table 5. P1 and P0: Additional Features Enable
P1
P0
0
0
Additional features are not changed
FUNCTION
0
1
Update additional features
1
0
Reserved for factory test (do not use)
1
1
Additional features are not changed
DP:
Deep power-down enable (1 = device in deep power-down mode)
N:
NAP power-down enable (1 = device in NAP power-down mode)
AN:
AutoNAP power-down enable (1 = device in AutoNAP power-down mode)
RP:
Reference power-down(1 = reference turned off)
S4:
Special read mode for Modes II and IV (1 = special mode enabled)
Table 6. A2, A1, and A0: DAC Control and Device Reset
16
A2
A1
A0
FUNCTION
0
0
0
No action
0
0
1
DAC write with next access
0
1
0
No action
0
1
1
DAC read with next access
1
0
0
No action
1
0
1
Device reset
1
1
0
No action
1
1
1
No action
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All additional features become active with the rising edge of the 12th CLOCK signal after issuing the RD pulse.
The reference DAC is controlled by the 12-bit DAC register that can also be accessed using the SDI pin (refer to
Figure 41 for details). Table 7 shows the content of this register; the default value after power-up is 3FFh.
Table 7. DAC Register Contents
DAC REGISTER CONTENT
(1)
11
10
9
8
7
6
5
4
3
2
1
0
X (1)
X
MSB
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X = don't care.
Serial Data Output (SDOx)
Converted data on the SDOx pins become valid with the third falling CLOCK edge after generating an RD pulse.
The following sections explain the different modes of operation in detail.
The digital output code format of the ADS7863A is binary twos complement, as shown in Table 9. Conversion
results can be read out multiple times until a new conversion is issued from the CONVST input.
Timing and Control
IMPORTANT:
Consider the detailed timing diagram (Figure 2) and CONVST timing diagram (Figure 3) within the Timing
Characteristics section. For maximum data throughput, the descriptions and diagrams given in this data sheet
assume that the CONVST and RD pins are tied together. Note that these pins can also be controlled
independently.
Device operation can be configured in four different modes by using the M0 and M1 mode pins, as shown in
Table 8.
Pin M0 sets either manual or automatic channel selection. In manual mode, the SDI register bits C[1:0] are used
to select between channels CHx0 and CHx1; in automatic operation, the SDI register bits C[1:0] are ignored and
channel selection is controlled by the device after each conversion. Pin M1 selects between serial data being
transmitted simultaneously on both outputs SDOA and SDOB for each channel respectively, or using only the
SDOA output for transmitting data from both channels (see Figure 33 through Figure 40 and the associated text
for more information).
Table 8. M0, M1 Truth Table
M0
M1
0
0
Manual (via SDI)
CHANNEL SELECTION
SDOA and SDOB
SDOx USED
0
1
Manual (via SDI)
SDOA only
1
0
Automatic
SDOA and SDOB
1
1
Automatic
SDOA only
Additionally, the SDI pin is used for controlling device functionality; see the Serial Data Input section for details.
Table 9. ADS7863A Output Data Format
DESCRIPTION
DIFFERENTIAL INPUT VOLTAGE
(CHxx+) – (CHxx–)
INPUT VOLTAGE AT CHxx+
(CHxx– = VREF = 2.5 V)
BINARY CODE
HEXADECIMAL
CODE
Positive full-scale
VREF
5V
0111 1111 1111
7FF
Mid-scale
0V
2.5 V
0000 0000 0000
000
Mid-scale – 1LSB
–VREF / 4096
2.49878 V
1111 1111 1111
FFF
Negative fullscale
–VREF
0V
1000 0000 0000
800
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Mode I
With the M0 and M1 pins are both set to '0', the device enters manual channel control operation and outputs data
on both SDOA and SDOB, respectively. The SDI pin switches between the channels. A conversion is initiated by
bringing CONVST high.
16 clock cycles are required to perform a single conversion. With the CONVST rising edge, the ADS7863A
switches asynchronously to the external CLOCK from sample to hold mode.
After a delay (t12), the BUSY output pin goes high and remains high for the duration of the conversion cycle. On
the falling edge of the second CLOCK cycle, the ADS7863A latches in the channel for the next conversion cycle,
depending on the status of the SDI register bits C[1:0]. CS must be brought low to enable both serial outputs.
Data are valid on the falling edge of every 16 clock cycles per conversion. The first two bits are set to '0'. The
subsequent data contain the 12-bit conversion result (the most significant bit is transferred first), followed by two
'0's (see Figure 2 and Figure 33).
1
16 1
16
CLOCK
CONVST
SDI
C[1:0] = 11 ® Convert CHx1 Next
P[1:0] = 11 ® SDI Features Not Used
C[1:0] = 00 ® Convert CHx0 Next
P[1:0] = 00 ® SDI Features Not Used
C[1:0] = 00 ® Convert CHx0 Next
P[1:0] = 00 ® SDI Features Not Used
M0
M1
RD
CS
High-Z
SDOA
0 0
Previous 12-Bit Data CHAx
0 0 0 0
12-Bit Data CHA1
0 0
SDOB
0 0
Previous 12-Bit Data CHBx
0 0 0 0
12-Bit Data CHB1
0 0
High-Z
BUSY
Previous Conversion of Both CHxx
0 ms
Conversion of Both CHx1
0.5 ms
Conversion of Both CHx0
1.0 ms
Figure 33. Mode I Timing Diagram (M0 = 0, M1 = 0)
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Mode II
With M0 = 0 and M1 = 1, the device also operates in manual channel control mode and outputs data on the
SDOA pin only when SDOB is set to 3-state. All other pins function in the same manner as they do in Mode I.
Because 32 clock cycles are required to output the results from both ADCs (instead of 16 cycles, if M1 = 0), the
device requires 1.0 μs to perform a complete conversion or read cycle. If the CONVST signal is issued every 0.5
μs (required for the RD signal) as in Mode I, every second pulse is ignored, as shown in Figure 34.
Output data consist of a '0' followed by an ADC indicator ('0' for CHAx or '1' for CHBx), 12 bits of conversion
results, and another '00'.
16
1
1
16
1
16
1
16
1
16
1
1
CLOCK
Every 2nd
CONVST
Is Ignored
CONVST
Every 2nd
CONVST
Is Ignored
Every 2nd
CONVST
Is Ignored
SDI
C[1:0] = 00 ® CHx0 Next
P[1:0] = 00 ® No Features
C[1:0] Is Ignored
P[1:0] = 00 ® No Features
C[1:0] = 11 ® CHx1 Next
P[1:0] = 11 ® No Features
C[1:0] Is Ignored
P[1:0] = 11 ® No Features
C[1:0] = 00 ® CHx0 Next
P[1:0] = 00 ® No Features
C[1:0] Is Ignored
P[1:0] = 00 ® No Features
M0
M1
RD
CS
B
CHx
Previous 12-Bit
Data CHAx
SDOA
A
B
12-Bit
Data CHB0
12-Bit
Data CHA0
A
12-Bit
Data CHB1
12-Bit
Data CHA1
A
12-Bit
Data CHA0
CHx
BUSY
High-Z
Previous 12-Bit
Data
DataCHBx
CHBx
SDOB
Previous Conversion
of Both CHxx
0 ms
No Conversion,
Read Access Only
Conversion
of Both CHx0
0.5 ms
1.0 ms
No Conversion,
Read Access Only
Conversion
of Both CHx1
1.5 ms
2.0 ms
Conversion
of Both CHx0
2.5 ms
3.0 ms
Figure 34. Mode II Timing Diagram (M0 = 0, M1 = 1)
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Mode III
With M0 = 1 and M1 = 0, the device automatically cycles between the differential inputs (ignoring the SDI register
bits C[1:0]) while offering the conversion result of CHAx on SDOA and the conversion result of CHBx on SDOB
(as shown in Figure 35).
Output data consist of a channel indicator ('0' for CHx0 or '1' for CHx1), followed by a '0', 12 bits of conversion
results, and another '00'.
1
16 1
16
CLOCK
CONVST
SDI
C[1:0] is ignored
P[1:0] = 00 ® SDI features are not used
M0
C[1:0] is ignored
P[1:0] = 11 ® SDI features are not used
C[1:0] is ignored
P[1:0] = 11 ® SDI features are not used
Both channel 0s are converted first,
followed by conversion of both channel 1s.
M1
RD
CS
CH1
Previous 12-Bit Data CHAx
SDOA
CH0
12-Bit Data CHA1
12-Bit Data CHA0
CH1
Previous 12-Bit Data CHBx
SDOB
BUSY
CH0
Previous Conversion of Both CHxx
0 ms
12-Bit Data CHB1
12-Bit Data CHB0
Conversion of Both CHx0
0.5 ms
Conversion of Both CHx1
1.0 ms
Figure 35. Mode III Timing Diagram (M0 = 1, M1 = 0)
20
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Mode IV
In the same way as Mode II, Mode IV uses the SDOA output line exclusively to transmit data while the
differential channels are switched automatically. Following the first conversion after M1 goes high, the SDOB
output 3-states (as shown in Figure 36).
Output data consist of a channel indicator ('0' for CHx0 or '1' for CHx1), followed by the ADC indicator ('0' for
CHAx or '1' for CHBx), 12 bits of conversion results, and end with '00'.
16
1
1
16
1
16
1
16
16
1
1
1
CLOCK
Every 2nd
CONVST
Is Ignored
CONVST
Every 2nd
CONVST
Is Ignored
Every 2nd
CONVST
Is Ignored
SDI
C[1:0] is Ignored
P[1:0] = 00 ® No Features
C[1:0] is Ignored
P[1:0] = 00 ® No Features
C[1:0] is Ignored
P[1:0] = 00 ® No Features
C[1:0] is Ignored
P[1:0] = 00 ® No Features
C[1:0] is Ignored
P[1:0] = 00 ® No Features
C[1:0] is Ignored
P[1:0] = 00 ® No Features
M0
M1
Both channel 0s are converted first,
followed by conversion of both channel 1s.
RD
CS
CHx
0A
Previous 12-Bit
Data CHAx
SDOA
0B
1A
12-Bit
Data CHB0
12-Bit
Data CHA0
1B
12-Bit
Data CHA1
0A
12-Bit
Data CHA0
12-Bit
Data CHB1
CHx
SDOB
Previous 12-Bit
Data CHBx
BUSY
Previous Conversion
of Both CHxx
0 ms
High-Z
Conversion
of Both CHx0
0.5 ms
Conversion
of Both CHx1
No Conversion,
Read Access Only
1.0 ms
1.5 ms
Conversion
of Both CHx0
No Conversion,
Read Access Only
2.0 ms
2.5 ms
3.0 ms
Figure 36. Mode IV Timing Diagram (M0 = 1, M1 = 1)
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Special Mode II (Not ADS7861-Compatible)
For Mode II, a special read mode is available in the ADS7863A where both data results can be read out,
triggered by a single RD pulse. To activate this mode, bit S4 in the SDI register must be set to '1' (see also the
Serial Data Input section).
The CONVST and RD pins can remain tied together, but do not need to be issued every 16 CLOCK cycles.
Output data are presented on both terminals, SDOA and SDOB. Figure 37 illustrates the special read mode.
16
1
1
16
1
16
1
16
1
16
1
1
CLOCK
CONVST
SDI
C[1:0] = 00 ® CHx0
P[1:0] = 01 ® Features ON
® S4 = 1
C[1:0] = 11 ® CHx1
P[1:0] = 11 ® No Updates
® S4 Still = 1
C[1:0] = 11 ® CHx1
P[1:0] = 11 ® No Updates
® S4 Still = 1
C[1:0] = 11 ® CHx1
P[1:0] = 11 ® No Updates
® S4 Still = 1
M0
M1
RD
CS
B
B
SDOA
Previous 12-Bit
Data CHAx
SDOB
Previous 12-Bit
Data CHBx
BUSY
Previous Conversion
of Both CHxx
0 ms
A
12-Bit
Data CHB0
12-Bit
Data CHA0
A
12-Bit
Data CHA1
12-Bit
Data CHB1
A
12-Bit
Data CHA1
High-Z
Conversion
of Both CHx0
0.5 ms
Conversion
of Both CHx1
No Conversion,
Read Access Only
1.0 ms
1.5 ms
Conversion
of Both CHx1
No Conversion,
Read Access Only
2.0 ms
2.5 ms
3.0 ms
Figure 37. Special Mode II Timing Diagram (M0 = 0, M1 = 1, S4 = 1)
22
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Special Mode IV (Not ADS7861-Compatible)
Analogous to Special Mode II, the device also offers a special read mode for Mode IV in which both data results
of a conversion can be read, triggered by a single RD pulse. In this case as well, bit S4 in the SDI register must
be set to '1' while the CONVST and RD pins can still be tied together .
As with Special Mode II, these two pins do not need to be issued every 16 CLOCK cycles. Data are available on
the SDOA pin.
This special read mode (shown in Figure 38) is not available in Mode I or Mode III.
16
1
1
16
1
16
1
16
1
16
1
1
CLOCK
CONVST
SDI
C[1:0] is Ignored
P[1:0] = 01 ® Features ON
® S4 = 1
C[1:0] is Ignored
P[1:0] = 11 ® No Updates
® S4 Still = 1
C[1:0] is Ignored
P[1:0] = 11 ® No Updates
® S4 Still = 1
C[1:0] is Ignored
P[1:0] = 11 ® No Updates
® S4 Still = 1
M0
M1
Both channel 0s are converted first,
followed by conversion of both channel 1s.
RD
CS
CHX
0A
Previous 12-Bit
Data CHAx
SDOA
0B
1A
12-Bit
Data CHB0
12-Bit
Data CHA0
1B
12-Bit
Data CHA1
0A
12-Bit
Data CHA0
12-Bit
Data CHB1
CHX
BUSY
High-Z
Previous 12-Bit
Data CHBx
SDOB
Conversion
of Both CHx0
Previous Conversion
of Both CHxx
0 ms
0.5 ms
Conversion
of Both CHx1
No Conversion,
Read Access Only
1.0 ms
1.5 ms
Conversion
of Both CHx0
No Conversion,
Read Access Only
2.0 ms
2.5 ms
3.0 ms
Figure 38. Special Mode IV Timing Diagram (M0 = 1, M1 = 1, S4 = 1)
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Pseudo-Differential Mode I (Not ADS7861-Compatible)
In Mode I, the device input multiplexers can also operate in a pseudo-differential manner. In this case, the SDI
bits (C[1:0]) are used to choose the channels accordingly.
For more details, see the Serial Data Input section. Data are available on both output terminals, SDOA and
SDOB.
The input multiplexer cannot be used for pseudo-differential signals in Mode III or Mode IV.
16
1
1
16
1
16
1
16
1
16
1
1
CLOCK
CONVST
SDI
C[1:0] = 00 ® CHx0+, CHx0P[1:0] = 00 ® Features OFF
C[1:0] = 01 ® CHx1-, CHx0P[1:0] = 11 ® Features OFF
C[1:0] = 10 ® CHx1+, CHx0P[1:0] = 00 ® Features OFF
C[1:0] = 00 ® CHx0+, CHx0P[1:0] = 00 ® Features OFF
C[1:0] = 01 ® CHx1-, CHx0P[1:0] = 11 ® Features OFF
C[1:0] = 10 ® CHx1+, CHx0P[1:0] = 00 ® Features OFF
SDOA
Previous 12-Bit
Data CHAx
12-Bit Data
CHA0+, CHA0-
12-Bit Data
CHA1-, CHA0-
12-Bit Data
CHA1+, CHA0-
12-Bit Data
CHA0+, CHA0-
12-Bit Data
CHA1-, CHA0-
SDOB
Previous 12-Bit
Data CHBx
12-Bit Data
CHB0+, CHB0-
12-Bit Data
CHB1-, CHB0-
12-Bit Data
CHB1+, CHB0-
12-Bit Data
CHB0+, CHB0-
12-Bit Data
CHB1-, CHB0-
BUSY
Previous Conversion
of Both CHxx
M0
M1
RD
CS
0 ms
Conversion of Both
CHx0+, CHx00.5 ms
Conversion of Both
CHx1-, CHx01.0 ms
Conversion of Both
CHx1+, CHx01.5 ms
Conversion of Both
CHx0+, CHx02.0 ms
Conversion of Both
CHx1-, CHx02.5 ms
3.0 ms
Figure 39. Pseudo-Differential Mode I (M0 = 0, M1 = 0)
24
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Pseudo-Differential Mode II (Not ADS7861-Compatible)
In Mode II, the device input multiplexers can also operate in a pseudo-differential configuration. In this case,
output data are available on terminal SDOA only, while SDOB is held in 3-state.
Channel switching is performed by setting the C[1:0] bits in the SDI register accordingly (see also the Serial Data
Input section).
The input multiplexer cannot be used for pseudo-differential signals in Mode III or Mode IV.
16
1
1
16
1
16
1
16
1
16
1
1
CLOCK
Every 2nd
CONVST
Is Ignored
CONVST
Every 2nd
CONVST
Is Ignored
Every 2nd
CONVST
Is Ignored
SDI
C[1:0] = 00 ® CHx0+, CHx0-
C[1:0] Is Ignored
C[1:0] = 01 ® CHx1-, CHx0-
C[1:0] Is Ignored
C[1:0] = 10 ® CHx1+, CHx0-
C[1:0] Is Ignored
P[1:0] = 00 ® Features OFF
P[1:0] = 00 ® Features OFF
P[1:0] = 11 ® Features OFF
P[1:0] = 11 ® Features OFF
P[1:0] = 00 ® Features OFF
P[1:0] = 00 ® Features OFF
M0
M1
RD
CS
B
B
SDOA
Previous 12-Bit
Data CHAx
SDOB
Previous 12-Bit
Data CHBx
BUSY
Previous Conversion
of Both CHxx
0 ms
A
12-Bit Data
CHB0+, CHB0-
12-Bit Data
CHA0+, CHA0-
A
12-Bit Data
CHA1-, CHA0-
12-Bit Data
CHA1+, CHA0-
12-Bit Data
CHB1-, CHB0-
A
No Conversion,
Read Data Only
Conversion of Both
CHx1+, CHx0-
High-Z
Conversion of Both
CHx0+, CHx00.5 ms
No Conversion,
Read Data Only
1.0 ms
Conversion of Both
CHx1-, CHx01.5 ms
2.0 ms
2.5 ms
3.0 ms
Figure 40. Pseudo-Differential Mode II (M0 = 0, M1 = 1)
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Programming the Reference DAC (Not ADS7861-Compatible)
The internal reference DAC can be set by issuing an RD pulse while providing an SDI word with P[1:0] = 01 and
A[2:0] = 001. Thereafter, a second RD pulse must be generated with an SDI word starting with the first two bits
ignored, followed by the actual 10-bit DAC value (as shown in Figure 41).
To verify the DAC setting, an RD pulse must be generated while providing an SDI word containing P[1:0] = 01
and A[2:0] = 011 to initialize the DAC read access. Triggering the RD line again causes the SDOA output to send
'0000' followed by the 10-bit DAC value and another '00'. During the second RD access, data present on SDI are
ignored, while in Mode I and Mode III valid conversion data for channel B are present on SDOB; the conversion
results of channel A are lost. The default value of the DAC register after power-up is 3FFh, corresponding to a
2.5-V reference voltage on the REFOUT pin.
16
1
1
16
1
16
1
16
1
16
1
1
CLOCK
CONVST
10-Bit
DAC Value
SDI
C[1:0] = 00 ® CHx0 is Next
P[1:0] = 01 ® Features ON
A[2:0] = 001 ® Write DAC
Data Interpreted as
DAC Value Only
C[1:0] = 11 ® CHx1 is Next
P[1:0] = 01 ® Features ON
A[2:0] = 011 ® Read DAC
SDOA
Previous 12-Bit
Data CHAx
12-Bit
Data CHA0
12-Bit
Data CHA0
SDOB
Previous 12-Bit
Data CHBx
12-Bi
Data CHB0
12-Bit
Data CHB0
BUSY
Previous Conversion
of Both CHxx
SDI Data Ignored
C[1:0] = 00 ® CHx0 is Next
P[1:0] = 00 ® No Features
C[1:0] = '00' ® CHx0 is Next
P[1:0] = '00’ ® No Features
12-Bit
Data CHA1
12-Bit
Data CHA0
12-Bit
Data CHB1
12-Bit
Data CHB0
M0
M1
RD
CS
0 ms
Conversion of
Both CHx0
0.5 ms
10-Bit
DAC Value
12-Bit
Data CHB1
Conversion of
Both CHx1
Conversion of
Both CHx0
1.0 ms
1.5 ms
Conversion of
Both CHx1
2.0 ms
Conversion of
Both CHx0
2.5 ms
3.0 ms
Figure 41. DAC Write and Read Access Timing Diagram
26
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Power-Down Modes and Reset (Not ADS7861-Compatible)
The device has a comprehensive built-in power-down feature. There are three power-down modes: deep powerdown, NAP power-down, and auto-NAP power-down. All three power-down modes are activated with the 12th
falling CLOCK edge of the SDI access, during which the related bit asserts (DP = 1, N = 1, or AN = 1). All modes
are deactivated by de-asserting the respective bit in the SDI register. The SDI register contents are not affected
by the power-down modes. Any ongoing conversion aborts when deep or NAP power-down is initiated. Table 10
lists the differences among the three power-down modes.
In deep power-down mode, all functional blocks except the digital interface are disabled. The bias currents of the
analog block are turned off. In this mode, power dissipation reduces to 1 μA within 2 μs. The wake-up time from
deep power-down mode is 1 μs.
In NAP power-down mode, the device turns off the biasing of the comparator and the mid-voltage buffer within
200 ns. The device goes into NAP power-down mode regardless of the conversion state.
The auto-NAP power-down mode is very similar to NAP mode. The only differences are the methods of powering
down and waking up the device. The SDI register bit AN is only used to enable or disable this feature. If the autoNAP mode is enabled, the device turns off the biasing automatically after finishing a conversion; thus, the end of
conversion actually activates the auto-NAP power-down. The device powers down within 200 ns in this mode, as
well. Triggering a new conversion by applying a CONVST pulse puts the device back into normal operation and
automatically starts a new conversion six CLOCK cycles later. Therefore, a complete conversion cycle takes 19
CLOCK cycles; thus, the maximum throughput rate in auto-NAP power-down mode is reduced to 1.68 MSPS.
To issue a device reset, an RD pulse must be generated along with an SDI word containing A[2:0] = 101. With
the 12th falling edge after generating the RD pulse, the entire device (including the serial interface) is forced into
reset. After approximately 500 ns, the serial interface becomes active again.
Table 10. Power-Down Modes
POWER-DOWN
TYPE
ENABLED
BY
ACTIVATED BY
ACTIVATION
TIME
RESUMED
BY
REACTIVATION TIME
DISABLED
BY
Deep
DP = 1
13th clock
2μs
DP = 0
1 μs
DP = 0
NAP
N=1
13th clock
200ns
N=0
3 clocks
N=0
Each end of
conversion
200ns
CONVST pulse
3 clocks
AN = 0
Auto-NAP
AN = 1
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ADS7861 COMPATIBILITY
The ADS7863AIDBQ is pin-compatible with the ADS7861E, ADS7861EB, and ADS7861EG4. However, there are
some differences between the two devices that must be considered when migrating from the ADS7861 to the
ADS7863A in an existing design.
SDI versus A0
One of the differences is that pin 16 (A0), which updates the internal SDI register of the ADS7863A, is used in
conjunction with M0 to select the input channel on the ADS7861.
In an existing design, if the ADS7861 is used in two-channel mode (M0 = 0) and the status of the A0 pin is
unchanged within the first four clock cycles after issuing a conversion start (CONVST rising edge), the
ADS7863A acts similarly to the ADS7861 and converts either channels CHx0 (if SDI is held low during the entire
period) or channels CHx1 (if SDI is held high during the entire period). Figure 34 describes the behavior of the
ADS7863A in such a situation.
The ADS7863A can also be used to replace the ADS7861 when run in four-channel mode (M0 = 1). In this case,
the A0 pin is held static (high or low) which is also required in the case of SDI to prevent accidentally updating
the SDI register.
In both cases, the additional features of the ADS7863A (pseudo-differential input mode, programmable reference
voltage output, and the different power-down modes) cannot be accessed but the hardware and software remain
backward-compatible to the ADS7861.
REFIN
The ADS7863A offers an unbuffered REFIN input with a code-dependent input impedance while featuring a
programmable and buffered reference output (REFOUT). The ADS7861 offers a high-impedance (buffered)
reference input. If an existing ADS7861-based design uses the internal reference of the device and relies on an
external resistor divider to adjust the input voltage range of the ADC, migration to ADS7863A requires one of the
following conditions:
• a software change to setup the internal reference DAC properly via SDI while removing the external resistors,
or
• an additional external buffer between the resistor divider and the required 470-nF (minimum) capacitor on the
REFIN input.
In the latter case, while the capacitor stabilizes the reference voltage during the entire conversion, the buffer
must recharge the capacitor by providing an average current only. The required minimum bandwidth of the buffer
can be calculated using Equation 2:
ln(2) ´ 2
f-3dB =
2p ´ 16 ´ TCLK
(2)
The buffer must also be capable of driving the 470-nF load while maintaining stability.
Timing
The only timing requirement that may cause the ADS7863A to malfunction in an existing ADS7861-based design
is the CONVST high time (t1) which is specified to be 20 ns minimum while the ADS7861 works properly with a
pulse as short as 15 ns. All other required minimum setup and hold times are specified to be either the same as
or lower than the ADS7863A; therefore, there are no conflicts with the ADS7861 requirements.
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APPLICATION INFORMATION
The absolute minimum configuration of the ADS7863A is shown in Figure 42. In this case, the ADS7863A is
used in dual-channel mode only, with the default settings of the device after power up.
The input signal for the amplifiers must fulfill the common-mode voltage requirements of the ADS7863A in this
configuration. The actual values of the resistors and capacitors depend on the bandwidth and performance
requirements of the application.
BVDD
1 mF
0.1 mF
ADS7863A
AVDD
BGND
OPA2365
AGND
AGND
OPA2365
AGND
AVDD
470 nF
(min)
1
BGND
BVDD 24
2
CHB1+
SDOA 23
3
CHB1-
SDOB 22
4
CHB0+
BUSY 21
5
CHB0-
CLOCK 20
6
CHA1+
CS 19
7
CHA1-
RD 18
8
CHA0+
CONVST 17
9
CHA0-
SDI 16
BGND
10
REFIN
M0 15
BVDD
11
REFOUT
12
AGND
Controller
Device
BGND
M1 14
AVDD 13
OPA2365
0.1 mF (min)
1 mF
AGND
OPA2365
AGND
Figure 42. Minimum ADS7863A Configuration
These values can be calculated using Equation 3, with n = 12 is the device resolution of the ADS7863A.
ln(2) ´ (n + 1)
fFILTER =
2´p´2´R´C
where:
•
n = 12 is the resolution of the ADS7863A
(3)
TI recommends using a capacitor value of at least 20 pF.
Keep the acquisition time in mind; the resistor value can be calculated as shown in Equation 4 for each of the
series resistors.
tACQ
R=
ln(2) ´ (n + 1) ´ 2 ´ C
where:
•
n = 12 is the resolution of the ADS7863A
(4)
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LAYOUT
For optimum performance, care should be taken with the physical layout of the ADS7863A circuitry. This
condition is particularly true if the CLOCK input is approaching the maximum throughput rate. In this case, TI
recommends having a fixed phase relationship between CLOCK and CONVST. Best performance can be
achieved when the digital interface is run in SPI mode; thus, the CLOCK signal is switched off after the 16th
cycle and remains low when CONVST is issued.
Additionally, the basic SAR architecture is quite sensitive to glitches or sudden changes on the power-supply,
reference, ground connections, and digital inputs that occur just before latching the output of the analog
comparator. Therefore, when driving any single conversion for an n-bit SAR converter, there are n windows in
which large external transient voltages can affect the conversion result. Such glitches might originate from
switching power supplies, nearby digital logic, or high-power devices. The degree of error in the digital output
depends on the reference voltage, layout, and the exact timing of the external event. These errors can change if
the external event also changes in time with respect to the CLOCK input.
With this possibility in mind, power to the device should be clean and well-bypassed. A 0.1-μF ceramic bypass
capacitor should be placed as close to the device as possible. In addition, a 1-μF to 10-μF capacitor is
recommended. If needed, an even larger capacitor and a 5-Ω or 10-Ω series resistor may be used to low-pass
filter a noisy supply.
If the reference voltage is external and originates from an operational amplifier, be sure that the reference
voltage can drive the reference capacitor without oscillation. The connection between the output of the external
reference driver and REFIN should be of low resistance (10 Ω max) to minimize any code-dependent voltage
drop on this path.
Grounding
The xGND pins should be connected to a clean ground reference. These connections should be kept as short as
possible to minimize the inductance of these paths. TI recommends using vias connecting the pads directly to the
ground plane. In designs without ground planes, the ground trace should be kept as wide as possible. Avoid
connections that are too near the grounding point of a microcontroller or digital signal processor (DSP).
Depending on the circuit density of the board, placement of the analog and digital components, and the related
current loops, a single solid ground plane for the entire printed circuit board (PCB) or a dedicated analog ground
area may be used. In an instance of a separated analog ground area, ensure a low-impedance connection
between the analog and digital ground of the ADC by placing a bridge underneath (or next to) the ADC.
Otherwise, even short undershoots on the digital interface with a value lower than –300 mV lead to conduction of
ESD diodes, causing current flow through the substrate and degrading the analog performance.
During PCB layout, care should also be taken to avoid any return currents crossing any sensitive analog areas or
signals. No signal must exceed the limit of –300 mV with respect to the according ground plane. Figure 43
illustrates the recommended layout of the ground and power-supply connections for both package options.
Supply
The ADS7863A has two separate supplies: the BVDD pin for the digital interface and the AVDD pin for all
remaining circuits.
BVDD can range from 2.7 V to 5.5 V, allowing the device to easily interface with processors and controllers. To
limit the injection of noise energy from external digital circuitry, BVDD should be filtered properly. Bypass
capacitors of 0.1 μF and 10 μF should be placed between the BVDD pin and ground plane.
AVDD supplies the internal analog circuitry. For optimum performance, a linear regulator (for example, the
UA7805 family) is recommended to generate the analog supply voltage in the range of 2.7 V to 5.5 V for the
ADS7863A and the necessary analog front-end circuitry.
Bypass capacitors should be connected to the ground plane such that the current is allowed to flow through the
pad of the capacitor (that is, the vias should be placed on the opposite side of the connection between the
capacitor and the power-supply pin of the ADC).
30
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Digital Interface
To further optimize device performance, a resistor of 10 Ω to 100 Ω can be used on each digital pin of the
ADS7863A. In this way, the slew rate of the input and output signals is reduced, limiting the noise injection from
the digital interface.
ADS7863AIDBQ
ADS7863AIRGE
Figure 43. Optimized Layout Recommendation
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ADS7863ADBQ
ACTIVE
SSOP
DBQ
24
50
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
ADS7863A
ADS7863ADBQR
ACTIVE
SSOP
DBQ
24
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
ADS7863A
ADS7863ARGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
ADS
7863A
ADS7863ARGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
ADS
7863A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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