ADS7868

Burr Brown Products from Texas Instruments ADS7884 ADS7885 SLAS567 – MARCH 2008 10-/8-BIT, 3-MSPS, MICRO-POWER, MINIATURE SAR ANALOG-TO-DIGITAL CONVERTERS 1 FEATURES 3-MHz Sample Rate Serial Device 10-Bit Resolution – ADS7884 8-Bit Resolution – ADS7885 Zero Latency 48-MHz Serial Interface Supply Range: 2.7 V to 5.5 V Low Power Dissipation: – 6.8 mW at 3-V VDD, 2.5 MSPS – 15 mw at 5-V VDD, 3 MSPS ±0.3 LSB INL, ±0.3 LSB DNL – ADS7884 ±0.15 LSB INL, ±0.1 LSB DNL – ADS7885 61.7 dB SINAD, –81 dB THD – ADS7884 49.8 dB SINAD, –68 dB THD – ADS7885 Unipolar Input Range: 0 V to VDD Powerdown Current: 1 µA Wide Input Bandwidth: 30 MHz at 3 dB 6-Pin SOT23 Package APPLICATIONS • • • • • • • • Base Band Converters in Radio Communication Motor Current/Bus Voltage Sensors in Digital Drives Optical Networking (DWDM, MEMS Based Switching) Optical Sensors Battery Powered Systems Medical Instrumentations High-Speed Data Acquisition Systems High-Speed Closed-Loop Systems • • • • • • • • • • • • • • • DESCRIPTION The ADS7884 is a 10-bit, 3-MSPS analog-to-digital converter (ADC), and the ADS7885 is a 8-bit, 3-MSPS ADC. The devices include a capacitor based SAR A/D converter with inherent sample and hold. The serial interface in each device is controlled by the CS and SCLK signals for glueless connections with microprocessors and DSPs. The input signal is sampled with the falling edge of CS, and SCLK is used for conversion and serial data output. The devices operate from a wide supply range from 2.7 V to 5.5 V. The low power consumption of the devices make them suitable for battery-powered applications. The devices also include a power saving powerdown feature for when the devices are operated at lower conversion speeds. The high level of the digital input to the device is not limited to device VDD. This means the digital input can go as high as 5.5 V when device supply is 2.7 V. This feature is useful when digital signals are coming from other circuit with different supply levels. Also this relaxes restriction on power up sequencing. The ADS7884 and ADS7885 are available in a 6-pin SOT23 package and are specified for operation from –40°C to 125°C. Micro-Power Miniature SAR Converter Family BIT 12-Bit 10-Bit 8-Bit < 300 KSPS ADS7866 (1.2 VDD to 3.6 VDD) ADS7867 (1.2 VDD to 3.6 VDD) ADS7868 (1.2 VDD to 3.6 VDD) 300 KSPS – 1.25 MSPS ADS7886 (2.35 VDD to 5.25 VDD) ADS7887 (2.35 VDD to 5.25 VDD) ADS7888 (2.35 VDD to 5.25 VDD) — ADS7884 (2.7 VDD to 5.5 VDD) ADS7885 (2.7 VDD to 5.5 VDD) 3 MSPS 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated ADS7884 ADS7885 SLAS567 – MARCH 2008 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. SAR +IN CDAC COMPARATOR VDD OUTPUT LATCHES & 3−STATE DRIVERS SDO ADS7884/ADS7885 CONVERSION & CONTROL LOGIC SCLK CS PACKAGE/ORDERING INFORMATION (1) DEVICE MAXIMUM INTEGRAL LINEARITY (LSB) MAXIMUM DIFFERENTIAL LINEARITY (LSB) NO MISSING CODES AT RESOLUTION (BIT) PACKAGE TYPE PACKAGE DESIGNAT OR TEMPERATURE RANGE PACKAGE MARKING ORDERING INFORMATION TRANSPORT MEDIA QUANTITY Tape and reel 250 Tape and reel 3000 Tape and reel 250 Tape and reel 3000 7884 ADS7884 ±0.8 ±0.8 10 6-Pin SOT23 DBV –40°C to 125°C 7884 7885 ADS7885 ±0.4 ±0.4 8 6-Pin SOT23 DBV –40°C to 125°C 7885 ADS7884SDBVT ADS7884SDBVR ADS7885SDBVT ADS7885SDBVR (1) For most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) UNIT +IN to AGND +VDD to AGND Digital input voltage to GND Digital output to GND Operating temperature range Storage temperature range Junction temperature (TJ Max) Power dissipation, SOT23 package Thermal impedance, θJA Lead temperature, soldering (1) SOT23 Vapor phase (60 sec) Infrared (15 sec) –0.3 V to +VDD +0.3 V –0.3 V to 7.0 V –0.3V to (7.0 V) –0.3 V to (+VDD + 0.3 V) –40°C to 125°C –65°C to 150°C 150°C (TJ Max–TA)/θJA 295.2°C/W 215°C 220°C Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. 2 Submit Documentation Feedback Product Folder Link(s): ADS7884 ADS7885 Copyright © 2008, Texas Instruments Incorporated www.ti.com ADS7884 ADS7885 SLAS567 – MARCH 2008 ADS7884 SPECIFICATIONS +VDD = 2.7 V to 5.5 V, TA = –40°C to 125°C, fsample = 2.5 MSPS for VDD = 2.7 V to 3.6 V, fsample = 3 MSPS for VDD = 3.6 V to 5.5 V PARAMETER ANALOG INPUT Full-scale input voltage span (1) Absolute input voltage range Ci IIlkg Input capacitance (2) TEST CONDITIONS MIN 0 TYP MAX VDD VDD+0.20 UNIT V V pF nA Bits Bits +IN TA = 125°C –0.20 27 40 10 10 –0.8 –0.8 –1 –1 ±0.3 ±0.3 ±0.2 ±0.2 240 93.3 Input leakage current Resolution No missing codes SYSTEM PERFORMANCE INL DNL EO EG Integral nonlinearity Differential nonlinearity Offset error (4) (5) (6) Gain error (5) Conversion time Acquisition time Maximum throughput rate Aperture delay 48-MHz SCLK, VDD = 5 V 48-MHz SCLK, VDD = 5 V 0.8 0.8 1 1 LSB (3) LSB LSB LSB ns ns SAMPLING DYNAMICS 224 3 10 MHz ns dB dB dB MHz DYNAMIC CHARACTERISTICS THD SINAD SFDR Total harmonic distortion (7) Signal-to-noise and distortion Spurious free dynamic range Full power bandwidth DIGITAL INPUT/OUTPUT Logic family — CMOS VIH VIL VOH VOL +VDD High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Supply voltage At VDD = 3.0 V, 2.5-MSPS throughput Supply current (normal mode) At VDD = 3.0 V, static state At VDD = 5.0 V, 3-MSPS throughput At VDD = 5.0 V, static state Power down state supply current Power dissipation SCLK off SCLK on (48 MHz) VDD = 5 V, 3 MSPS VDD = 3 V, 2.5 MSPS 90 15 6.8 VDD = 2.7 V to 3.6 V VDD = 3.6 V to 5.5 V VDD = 5 V VDD = 3 V At Isource = 200 µA At Isink = 200 µA 2.7 3.3 2.25 1.8 3 2 1 200 20 µA mW 4 VDD–0.2 0.4 5.5 3 mA 1.5 2.2 5.5 5.5 0.8 0.4 V V V 100 kHz 100 kHz 100 kHz At –3 dB 30 60 –81 61.7 81 POWER SUPPLY REQUIREMENTS V (1) (2) (3) (4) (5) (6) (7) Ideal input span; does not include gain or offset error. Refer to Figure 43 for details on sampling circuit LSB means least significant bit Measured relative to an ideal full-scale input Offset error and gain error ensured by characterization. First transition of 000H to 001H at (Vref/210) Calculated on the first nine harmonics of the input frequency Submit Documentation Feedback Product Folder Link(s): ADS7884 ADS7885 3 Copyright © 2008, Texas Instruments Incorporated ADS7884 ADS7885 SLAS567 – MARCH 2008 www.ti.com ADS7884 SPECIFICATIONS (continued) +VDD = 2.7 V to 5.5 V, TA = –40°C to 125°C, fsample = 2.5 MSPS for VDD = 2.7 V to 3.6 V, fsample = 3 MSPS for VDD = 3.6 V to 5.5 V PARAMETER Power dissipation in static state Powerdown time Powerup time TEMPERATURE RANGE Specified performance –40 125 °C VDD = 5 V VDD = 3 V TEST CONDITIONS MIN TYP 10 5.4 0.1 0.8 MAX UNIT mW µs µs 4 Submit Documentation Feedback Product Folder Link(s): ADS7884 ADS7885 Copyright © 2008, Texas Instruments Incorporated www.ti.com ADS7884 ADS7885 SLAS567 – MARCH 2008 ADS7885 SPECIFICATIONS +VDD = 2.7 V to 5.5 V, TA = –40°C to 125°C, fsample = 2.5 MSPS for VDD = 2.7 V to 3.6 V, fsample = 3 MSPS for VDD = 3.6 V to 5.5 V PARAMETER ANALOG INPUT Full-scale input voltage span (1) Absolute input voltage range Ci IIlkg Input capacitance (2) TEST CONDITIONS MIN 0 TYP MAX VDD VDD+0.20 UNIT V V pF nA Bits Bits +IN TA = 125°C –0.20 27 40 8 8 –0.4 –0.4 –0.4 –0.5 ±0.15 ±0.1 ±0.1 ±0.1 198 135 Input leakage current Resolution No missing codes SYSTEM PERFORMANCE INL DNL EO EG Integral nonlinearity Differential nonlinearity Offset error (4) (5) (6) Gain error (5) Conversion time Acquisition time Maximum throughput rate Aperture delay 48-MHz SCLK, VDD = 5 V 3 MSPS mode 48-MHz SCLK, VDD = 5 V 0.4 0.4 0.4 0.5 LSB (3) LSB LSB LSB ns ns SAMPLING DYNAMICS 182 3 10 MHz ns dB dB dB MHz DYNAMIC CHARACTERISTICS THD SINAD SFDR Total harmonic distortion (7) Signal-to-noise and distortion Spurious free dynamic range Full power bandwidth DIGITAL INPUT/OUTPUT Logic family — CMOS VIH VIL VOH VOL +VDD High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Supply voltage At VDD = 3.0 V, 2.5-MSPS throughput Supply current (normal mode) At VDD = 3.0 V, static state At VDD = 5.0 V, 3-MSPS throughput At VDD = 5.0 V, static state Power down state supply current Power dissipation SCLK off SCLK on (48 MHz) VDD = 5 V, 3 MSPS VDD = 3 V, 2.5 MSPS 90 15 6.8 VDD = 2.7 V to 3.6 V VDD = 3.6 V to 5.5 V VDD = 5 V VDD = 3 V At Isource = 200 µA At Isink = 200 µA 2.7 3.3 2.25 1.8 3 2 1 200 20 µA mW 4 VDD–0.2 0.4 5.5 3 mA 1.5 2.2 5.5 5.5 0.8 0.4 V V V 100 kHz 100 kHz 100 kHz At –3 dB 30 49 –68 49.8 74 POWER SUPPLY REQUIREMENTS V (1) (2) (3) (4) (5) (6) (7) Ideal input span; does not include gain or offset error. Refer to Figure 43 for details on sampling circuit LSB means least significant bit Measured relative to an ideal full-scale input Offset error and gain error ensured by characterization. First transition of 000H to 001H at (Vref/28) Calculated on the first nine harmonics of the input frequency Submit Documentation Feedback Product Folder Link(s): ADS7884 ADS7885 5 Copyright © 2008, Texas Instruments Incorporated ADS7884 ADS7885 SLAS567 – MARCH 2008 www.ti.com ADS7885 SPECIFICATIONS (continued) +VDD = 2.7 V to 5.5 V, TA = –40°C to 125°C, fsample = 2.5 MSPS for VDD = 2.7 V to 3.6 V, fsample = 3 MSPS for VDD = 3.6 V to 5.5 V PARAMETER Power dissipation in static state Powerdown time Powerup time TEMPERATURE RANGE Specified performance –40 125 °C VDD = 5 V VDD = 3 V TEST CONDITIONS MIN TYP 10 5.4 0.1 0.8 MAX UNIT mW µs µs TIMING REQUIREMENTS (see Figure 1) All specifications typical at TA = –40°C to 125°C, VDD = 2.7 V to 5.5 V, unless otherwise specified. PARAMETER TEST CONDITIONS (1) VDD = 3 V ADS7884 tconv Conversion time ADS7885 tacq tq td1 tsu1 td2 th1 td3 tw1 td4 twH twL Aquisition time Minimum quiet time needed from bus 3-state to start of next conversion Delay time, CS low to first data (0) out Setup time, CS low to SCLK low Delay time, SCLK falling to SDO Hold time, SCLK falling to data valid (2) Delay time, 16th SCLK falling edge to SDO 3-state Pulse duration, CS Delay time, CS high to SDO 3-state, Pulse duration, SCLK high Pulse duration, SCLK low Frequency, SCLK Delay time, second falling edge of clock and CS to enter in powerdown (use min spec not to accidently enter in powerdown) Figure 3 VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD < 3 V VDD > 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V –2 –2 0.45 × tSCLK 0.45 × tSCLK 0.45 × tSCLK 0.45 × tSCLK 40 48 4 3 ns 10 10 9 8 15 11 5.5 4 9 8 15 11 7 5 11 9 20 12 62.5 52 10 10 9 8 15 11 MIN TYP MAX 11.5 × tSCLK 11.5 × tSCLK 9.5 × tSCLK 9.5 × tSCLK ns ns ns ns ns ns ns ns ns ns ns MHz ns UNIT td5 (1) (2) 6 3-V Specifications apply from 2.7 V to 3.6 V, and 5-V specifications apply from 4.5 V to 5.5 V. With 10-pf load. Submit Documentation Feedback Product Folder Link(s): ADS7884 ADS7885 Copyright © 2008, Texas Instruments Incorporated www.ti.com ADS7884 ADS7885 SLAS567 – MARCH 2008 TIMING REQUIREMENTS (see Figure 1) (continued) All specifications typical at TA = –40°C to 125°C, VDD = 2.7 V to 5.5 V, unless otherwise specified. PARAMETER td6 Delay time, CS and 10th falling edge of clock to enter in powerdown (use max spec not to accidently enter in powerdown) Figure 3 TEST CONDITIONS (1) VDD = 3 V VDD = 5 V MIN –2 –2 TYP MAX 4 3 ns UNIT DEVICE INFORMATION SOT23 PACKAGE (TOP VIEW) VDD GND VIN 1 2 3 6 5 4 CS SDO SCLK TERMINAL FUNCTIONS TERMINAL NAME VDD GND VIN SCLK SDO CS NO. 1 2 3 4 5 6 I/O – – I I O I DESCRIPTION Power supply input also acts like a reference voltage to ADC. Ground for power supply, all analog and digital signals are referred with respect to this pin. Analog signal input Serial clock Serial data out Chip select signal, active low ADS7884 NORMAL OPERATION The cycle begins with the falling edge of CS. This point is indicated as a in Figure 1. With the falling edge of CS, the input signal is sampled and the conversion process is initiated. The device outputs data while the conversion is in progress. The data word contains 2 leading zeros, followed by 10-bit data in MSB first format and padded by 4 lagging zeros. The falling edge of CS clocks out the first zero, and a second zero is clocked out on FIRST falling edge of the clock. Data is in MSB first format with the MSB being clocked out on the 2nd falling edge. Data is padded with four lagging zeros as shown in Figure 1. The conversion ends on the first rising edge of SCLK after the 11th falling edge. At this point the device enters the acquisition phase. This point is indicated by b in Figure 1. Figure 1 shows device data is read in a sixteen clock frame. However, CS can be asserted (pulled high) any time after 11 clocks have elapsed. SDO goes to 3-state with the CS high level. The next conversion should not be started (by pulling CS low) until the end of the quiet sampling time (tq) after SDO goes to 3-state or until the minimum acquisition time (tacq) has elapsed. To continue normal operation, it is necessary that CS is not pulled high until point b. Without this, the device does not enter the acquisition phase and no valid data is available in the next cycle. (Also refer to the Powerdown Mode section for more details.) CS going high any time after the conversion start aborts the ongoing conversion and SDO goes to 3-state. The high level of the digital input to the device is not limited to device VDD. This means the digital input can go as high as 5.5 V when the device supply is 2.7 V. This feature is useful when digital signals are coming from another circuit with different supply levels. Also, this relaxes the restriction on powerup sequencing. However, the digital output levels (VOH and VOL) are governed by VDD as listed in the Specifications table. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS7884 ADS7885 7 ADS7884 ADS7885 SLAS567 – MARCH 2008 www.ti.com a tconv CS tsu1 SCLK td1 SDO 0 1 td2 0 D9 2 3 th1 D8 11 td4 D0 0 0 0 0 tq 12 13 14 15 16 td3 b tacq tw1 a Figure 1. ADS7884 Interface Timing Diagram ADS7885 NORMAL OPERATION The cycle begins with the falling edge of CS . This point is indicated as a in Figure 2. With the falling edge of CS, the input signal is sampled and the conversion process is initiated. The device outputs data while the conversion is in progress. The data word contains 2 leading zeros, followed by 8-bit data in MSB first format and padded by 6 lagging zeros. The falling edge of CS clocks out the first zero, and a second zero is clocked out on FIRST falling edge of the clock. Data is in MSB first format with the MSB being clocked out on the 3rd falling edge. Data is padded with six lagging zeros as shown in Figure 2. On the 16th falling edge of SCLK, SDO goes to the 3-state condition. The conversion ends on the first rising edge of SCLK after the 9th falling edge. At this point the device enters the acquisition phase. This point is indicated by b in Figure 2. Figure 2 shows device data is read in a sixteen clock frame. However, CS can be asserted (pulled high) any time after 9 clocks have elapsed (after the 10th falling edge of SCLK). SDO goes to 3-state with the CS high level. The next conversion should not be started (by pulling CS low) until the end of the quiet sampling time (tq) after SDO goes to 3-state or until the minimum acquisition time (tacq) has elapsed. To continue normal operation, it is necessary that CS is not pulled high until point b. Without this, the device does not enter the acquisition phase and no valid data is available in the next cycle. (Also refer to the Powerdown Mode section for more details.) CS going high any time after the conversion start aborts the ongoing conversion and SDO goes to 3-state. The high level of the digital input to the device is not limited to device VDD. This means the digital input can go as high as 5.5 V when the device supply is 2.7 V. This feature is useful when digital signals are coming from another circuit with different supply levels. Also, this relaxes the restriction on powerup sequencing. However, the digital output levels (VOH and VOL) are governed by VDD as listed in the Specifications section. a tconv CS tsu1 SCLK td1 SDO 0 1 td2 0 D7 2 3 th1 D6 9 td4 D0 0 0 0 0 0 tq 10 11 14 15 16 td3 b tacq tw1 a Figure 2. ADS7885 Interface Timing Diagram POWER DOWN MODE The device enters powerdown mode if CS goes high anytime after the 2nd SCLK falling edge to before the 10th SCLK falling edge. Ongoing conversion stops and SDO goes to 3-state under this powerdown condition as shown in Figure 3. 8 Submit Documentation Feedback Product Folder Link(s): ADS7884 ADS7885 Copyright © 2008, Texas Instruments Incorporated www.ti.com ADS7884 ADS7885 SLAS567 – MARCH 2008 td5 CS 1 SCLK 2 3 4 5 9 td6 10 16 SDO Figure 3. Entering Power Down Mode A dummy cycle with CS low for more than 10 SCLK falling edges brings the device out of powerdown mode. For the device to come to the fully powered up condition it takes 0.8 µs. CS can be pulled high any time after the 10th falling edge as shown in Figure 4. Note that the powerup time of 0.8 µsec is more than a single conversion cycle at 3 MSPS speed. This means the device requires three dummy conversion frames at 3 MSPS speed or one elongated dummy conversion frame. The data during dummy conversion frames is invalid. Device Starts Powering Up CS Device Fully Powered-Up SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SDO Invalid Data Valid Data Figure 4. Exiting Power Down Mode Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS7884 ADS7885 9 ADS7884 ADS7885 SLAS567 – MARCH 2008 www.ti.com TYPICAL CHARACTERISTICS ADS7884 SUPPLY CURRENT vs SUPPLY VOLTAGE 3.2 SUPPLY CURRENT vs SCLK FREQUENCY 3.5 3 SUPPLY CURRENT vs SAMPLE RATE TA = 25°C, SCLK = 48 MHz at VDD = 5 V, SCLK = 40 MHz at VDD = 3 V, Power Down, SCLK = Free Running 5V 1.5 3 ICC - Supply Current - mA ICC - Supply Current - mA 2.5 2 1.5 1 0.5 0 3V 2.8 3 MSPS ICC - Supply Current - mA TA = 25°C, fs = 3MSPS at VDD = 5 V, fs = 2.5 MSPS at VDD = 3 V TA = 25°C 3 5V 2.5 2 2.6 2.5 MSPS 2.4 1 0.5 0 0 3V 2.2 2 2.7 3.4 4.1 4.8 VDD - Supply Voltage - V 5.5 0 10 20 30 40 fSCLK - Frequency - MHz 50 100 200 300 400 500 fs - Sample Rate - KSPS 600 700 Figure 5. INPUT LEAKAGE CURRENT vs FREE-AIR TEMPERATURE 30 VDD = 5 V 20 Figure 6. SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY 62 61.9 62 Figure 7. SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY 61.9 Input Leakage Current - nA 10 0 -10 0V -20 -30 5V Signal-to-Noise Ratio - dB 61.8 61.7 61.6 61.5 61.4 61.3 61.2 61.1 Signal-to-Noise + Distortion - dB TA = 25°C, fs = 3 MSPS, VDD = 5 V SNR 5 V 61.8 61.7 61.6 61.5 61.4 61.3 61.2 61.1 TA = 25°C, fs = 3 MSPS, VDD = 5 V SINAD 5 V -40 -40 -20 0 20 40 60 80 100 120 TA - Free-Air Temperature - °C 61 0 200 400 600 800 fi - Input Frequency - KHz 1000 61 0 200 400 600 800 fi - Input Frequency - KHz 1000 Figure 8. SIGNAL-TO-NOISE + DISTORTION vs SUPPLY VOLTAGE SINAD - Signal-to-Noise and Distortion - dB Figure 9. SIGNAL-TO-NOISE + DISTORTION vs FREE-AIR TEMPERATURE SINAD - Signal-to-Noise and Distortion - dB 62 61.9 61.8 61.7 61.6 61.5 61.4 61.3 61.2 61.1 61 -40 -20 0 20 40 60 80 100 120 TA - Free-Air Temperature - °C 5V, 3 MSPS 3V, 2.5MSPS DNL - Differential Nonlinearity - LSBs 0.8 Figure 10. DIFFERENTIAL NONLINEARITY vs FREE-AIR TEMPERATURE TA = 25°C 0.6 VDD = 5 V at 3 MSPS, VDD = 3 V at 2.5 MSPS MAXDNL, 5 V, 3MSPS 0.4 0.2 MAXDNL, 3 V, 2.5 MSPS 0 MINDNL, 3 V, 2.5 MSPS -0.2 -0.4 -0.6 -0.8 -40 MINDNL, 5 V, 3MSPS 62 61.9 61.8 61.7 61.6 61.5 61.4 61.3 61.2 61.1 61 2.7 3.4 4.1 4.8 VDD - Supply Voltage - V 5.5 3 MSPS TA = 25°C, fs = 3 MSPS or 2.5 MSPS 2.5 MSPS VDD = 5 V at 3 MSPS, VDD = 3 V at 2.5 MSPS -20 0 20 40 60 80 100 120 TA - Free-Air Temperature - °C Figure 11. Figure 12. Figure 13. 10 Submit Documentation Feedback Product Folder Link(s): ADS7884 ADS7885 Copyright © 2008, Texas Instruments Incorporated www.ti.com ADS7884 ADS7885 SLAS567 – MARCH 2008 TYPICAL CHARACTERISTICS ADS7884 (continued) INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE 0.8 INL - Integral Nonlinearity - LSBs DIFFERENTIAL NONLINEARITY vs SUPPLY VOLTAGE 0.8 INTEGRAL NONLINEARITY vs SUPPLY VOLTAGE 0.8 0.4 0.2 MAXINL, 5 V, 3MSPS 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 2.7 MAXDNL, 2.5 MSPS MAXDNL, 3MSPS INL - Integral Nonlinearity - LSBs 0.6 DNL - Differential Nonlinearity - LSBs TA = 25°C VDD = 5 V at 3 MSPS, VDD = 3 V at 2.5 MSPS TA = 25°C 0.6 TA = 25°C 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 2.7 MININL, 3MSPS MAXINL, 2.5 MSPS MININL, 2.5 MSPS MAXINL, 3MSPS MAXINL, 3 V, 2.5 MSPS 0 -0.2 MININL, 3 V, 2.5 MSPS -0.4 -0.6 -0.8 -40 MININL, 5 V, 3MSPS MINDNL, 2.5 MSPS MINDNL, 3MSPS -20 0 20 40 60 80 100 120 TA - Free-Air Temperature - °C 3.4 4.1 4.8 VDD - Supply Voltage - V 5.5 3.4 4.1 4.8 5.5 VDD - Supply Voltage - V Figure 14. OFFSET ERROR vs SUPPLY VOLTAGE 0.5 Figure 15. OFFSET ERROR vs FREE-AIR TEMPERATURE 0.5 0.4 0.3 0.5 0.4 0.3 Figure 16. GAIN ERROR vs SUPPLY VOLTAGE TA = 25°C, fs = 3 MSPS or 2.5 MSPS, VDD = 5 V at 3 MSPS, VDD = 3 V at 2.5 MSPS 0.25 Offset Error - LSBs Offset Error - LSBs Gain Error - LSBs 2.5 MSPS 3 MSPS 0 3 V, 2.5 MSPS 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -40 -20 0 fs = 3 MSPS or 2.5 MSPS, VDD = 5 V at 3 MSPS, VDD = 3 V at 2.5 MSPS 20 40 60 80 100 120 5 V, 3MSPS 0.2 0.1 0 -0.1 2.5 MSPS 3 MSPS -0.2 -0.3 -0.4 -0.5 2.7 3.4 4.1 4.8 VDD - Supply Voltage - V 5.5 -0.25 TA = 25°C, fs = 3 MSPS or 2.5 MSPS, VDD = 5 V at 3 MSPS, VDD = 3 V at 2.5 MSPS 3.4 4.1 4.8 VDD - Supply Voltage - V 5.5 -0.5 2.7 TA - Free-Air Temperature - °C Figure 17. Figure 18. GAIN ERROR vs FREE-AIR TEMPERATURE 0.2 0.15 0.1 Gain Error - LSBs Figure 19. fs = 3 MSPS or 2.5 MSPS, VDD = 5 V at 3 MSPS, VDD = 3 V at 2.5 MSPS 0.05 3 V, 2.5 MSPS 0 -0.05 -0.1 -0.15 -0.2 -40 -20 0 20 40 60 80 100 120 TA - Free-Air Temperature - °C 5 V, 3 MSPS Figure 20. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS7884 ADS7885 11 ADS7884 ADS7885 SLAS567 – MARCH 2008 www.ti.com TYPICAL CHARACTERISTICS ADS7884 (continued) DNL 0.8 0.6 0.4 DNL - LSBs VDD = 5 V, fs = 3 MSPS, TA = 25°C 0.2 0 -0.2 -0.4 -0.6 -0.8 0 256 512 Output Code Figure 21. INL 768 1024 0.8 0.6 0.4 INL - LSBs VDD = 5 V, fs = 3 MSPS, TA = 25°C 0.2 0 -0.2 -0.4 -0.6 -0.8 0 256 512 Output Code Figure 22. FFT 768 1024 0 -20 power - dB -40 -60 -80 -100 -120 -140 0 250 500 750 f - Frequency - kHz Figure 23. 1000 fs = 3 MSPS, fin - 100 kHz, VDD = 5 V, 16384 N Points 1250 1500 12 Submit Documentation Feedback Product Folder Link(s): ADS7884 ADS7885 Copyright © 2008, Texas Instruments Incorporated www.ti.com ADS7884 ADS7885 SLAS567 – MARCH 2008 TYPICAL CHARACTERISTICS ADS7885 SUPPLY CURRENT vs SUPPLY VOLTAGE 2.8 2.7 SUPPLY CURRENT vs SCLK FREQUENCY 3 3 SUPPLY CURRENT vs SAMPLE RATE TA = 25°C, SCLK = 48 MHz at VDD = 5 V, SCLK = 40 MHz at VDD = 3 V, Power Down, SCLK = Free Running ICC - Supply Current - mA ICC - Supply Current - mA 2.6 2.5 2.4 2.3 2.2 2.1 2 2.7 2.5 MSPS 3 MSPS ICC - Supply Current - mA TA = 25°C, fs = 3 MSPS at VDD = 5 V, fs = 2.5 MSPS at VDD = 3 V TA = 25°C 2.5 5V 2.5 2 5V 2 3V 1.5 1.5 3V 1 1 0.5 0.5 0 3.4 4.1 4.8 5.5 0 0 VDD - Supply Voltage - V 10 20 30 40 fSCLK - Frequency - MHz 50 0 100 200 300 400 500 600 fs - Sample Rate - KSPS 700 Figure 24. INPUT LEAKAGE CURRENT vs FREE-AIR TEMPERATURE 30 51 Figure 25. SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY 51 50.8 5V 50.6 Figure 26. SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY 50.8 VDD = 5 V 20 Signal-to-Noise + Distortion - dB Input Leakage Current - nA 10 0 -10 -20 -30 -40 -40 0V Signal-to-Noise Ratio - dB TA = 25°C, fs = 3 MSPS, VDD = 5 V 50.6 50.4 50.2 50 49.8 49.6 49.4 49.2 TA = 25°C, fs = 3 MSPS, VDD = 5 V 50.4 50.2 50 49.8 49.6 49.4 49.2 SNR 5 V SINAD 5 V -20 0 20 40 60 80 100 120 TA - Free-Air Temperature - °C 49 0 200 400 600 800 fi - Input Frequency - KHz 1000 49 0 200 400 600 800 fi - Input Frequency - KHz 1000 Figure 27. SIGNAL-TO-NOISE + DISTORTION vs SUPPLY VOLTAGE SINAD - Signal-to-Noise and Distortion - dB Figure 28. SIGNAL-TO-NOISE + DISTORTION vs FREE-AIR TEMPERATURE SINAD - Signal-to-Noise and Distortion - dB 51 DNL - Differential Nonlinearity - LSBs Figure 29. DIFFERENTIAL NONLINEARITY vs FREE-AIR TEMPERATURE 0.4 0.3 0.2 0.1 0 -0.1 MINDNL, 3 V, 2.5 MSPS MINDNL, 5 V, 3 MSPS MAXDNL, 3 V, 2.5 MSPS 51 50.8 50.6 50.4 50.2 50 49.8 2.5 MSPS 49.6 49.4 49.2 49 2.7 3.4 4.1 4.8 5.5 3 MSPS TA = 25°C, fs = 3 MSPS or 2.5 MSPS 50.8 50.6 50.4 50.2 50 49.8 49.6 49.4 49.2 49 -40 VDD = 5 V at 3 MSPS, VDD = 3 V at 2.5 MSPS TA = 25°C VDD = 5 V at 3 MSPS, VDD = 3 V at 2.5 MSPS MAXDNL, 5 V, 3 MSPS 5 V, 3 MSPS 3 V, 2.5MSPS -0.2 -0.3 -0.4 -40 VDD - Supply Voltage - V -20 0 20 40 60 80 100 TA - Free-Air Temperature - °C 120 -20 0 20 40 60 80 100 120 TA - Free-Air Temperature - °C Figure 30. Figure 31. Figure 32. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS7884 ADS7885 13 ADS7884 ADS7885 SLAS567 – MARCH 2008 www.ti.com TYPICAL CHARACTERISTICS ADS7885 (continued) INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE 0.4 0.4 DIFFERENTIAL NONLINEARITY vs SUPPLY VOLTAGE 0.4 INTEGRAL NONLINEARITY vs SUPPLY VOLTAGE TA = 25°C INL - Integral Nonlinearity - LSBs DNL - Differential Nonlinearity - LSBs INL - Integral Nonlinearity - LSBs 0.3 0.2 0.1 0 -0.1 TA = 25°C VDD = 5 V at 3 MSPS, VDD = 3 V at 2.5 MSPS MAXINL, 5 V, 3 MSPS MAXINL, 3 V, 2.5 MSPS MININL, 3 V, 2.5 MSPS TA = 25°C 0.3 0.2 MAXDNL, 2.5 MSPS MAXDNL, 3 MSPS 0.3 0.2 MAXINL, 2.5 MSPS MAXINL, 3 MSPS 0.1 0 -0.1 MINDNL, 2.5 MSPS MINDNL, 3 MSPS 0.1 0 -0.1 MININL, 2.5 MSPS MININL, 3 MSPS MININL, 5 V, 3 MSPS -0.2 -0.3 -0.4 -40 -0.2 -0.3 -0.4 2.7 -0.2 -0.3 -0.4 2.7 -20 0 20 40 60 80 100 120 TA - Free-Air Temperature - °C 3.4 4.1 4.8 VDD - Supply Voltage - V 5.5 3.4 4.1 4.8 5.5 VDD - Supply Voltage - V Figure 33. OFFSET ERROR vs SUPPLY VOLTAGE 0.4 0.3 0.2 TA = 25°C, fs = 3 MSPS or 2.5 MSPS, VDD = 5 V at 3 MSPS, VDD = 3 V at 2.5 MSPS 0.4 0.3 0.2 Figure 34. OFFSET ERROR vs FREE-AIR TEMPERATURE 0.4 fs = 3 MSPS or 2.5 MSPS, VDD = 5 V at 3 MSPS, VDD = 3 V at 2.5 MSPS Figure 35. GAIN ERROR vs SUPPLY VOLTAGE 0.3 0.2 TA = 25°C, fs = 3 MSPS or 2.5 MSPS, VDD = 5 V at 3 MSPS, VDD = 3 V at 2.5 MSPS 2.5 MSPS Offset Error - LSBs Offset Error - LSBs 0.1 0 2.5 MSPS 3 MSPS 0.1 3V, 2.5 MSPS 0 5V, 3 MSPS -0.1 -0.2 -0.3 -0.4 -40 Gain Error - LSBs 0.1 0 -0.1 -0.2 -0.3 -0.4 2.7 -0.1 -0.2 -0.3 -0.4 2.7 3 MSPS 3.4 4.1 4.8 VDD - Supply Voltage - V 5.5 -20 0 20 40 60 80 100 120 TA - Free-Air Temperature - °C 3.4 4.1 4.8 VDD - Supply Voltage - V 5.5 Figure 36. Figure 37. GAIN ERROR vs FREE-AIR TEMPERATURE 0.2 0.15 0.1 Gain Error - LSBs Figure 38. fs = 3 MSPS or 2.5 MSPS, VDD = 5 V at 3 MSPS, VDD = 3 V at 2.5 MSPS 3V, 2.5 MSPS 0.05 0 5V, 3 MSPS -0.05 -0.1 -0.15 -0.2 -40 -20 0 20 40 60 80 100 TA - Free-Air Temperature - °C 120 Figure 39. 14 Submit Documentation Feedback Product Folder Link(s): ADS7884 ADS7885 Copyright © 2008, Texas Instruments Incorporated www.ti.com ADS7884 ADS7885 SLAS567 – MARCH 2008 TYPICAL CHARACTERISTICS ADS7885 (continued) DNL 0.4 0.3 DNL - LSBs 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 0 VDD = 5 V, fs = 3 MSPS, TA = 25°C 64 128 Output Code Figure 40. INL 192 256 0.4 0.3 VDD = 5 V, fs = 3 MSPS, TA = 25°C INL - LSBs 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 0 64 128 Output Code 192 256 Figure 41. FFT 0 -20 fs = 3 MSPS, fin - 100 kHz, VDD = 5 V, 16384 N Points Power - dB -40 -60 -80 -100 -120 0 750 F - Frequency - kHz 250 500 1000 1250 1500 Figure 42. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS7884 ADS7885 15 ADS7884 ADS7885 SLAS567 – MARCH 2008 www.ti.com APPLICATION INFORMATION VDD 50 W 20 W IN 50 W GND 20 pF 7 pF Figure 43. Typical Equivalent Sampling Circuit Driving the VIN and VDD Pins of the ADS7884 and ADS7885 The VIN input to the ADS7884 and ADS7885 should be driven with a low impedance source. In most cases additional buffers are not required. In cases where the source impedance exceeds 200 Ω, using a buffer would help achieve the rated performance of the converter. The THS4031 is a good choice for the driver amplifier buffer. The reference voltage for the ADS7884 and ADS7885 A/D converters are derived from the supply voltage internally. The devices offer limited low-pass filtering functionality on-chip. The supply to these converters should be driven with a low impedance source and should be decoupled to the ground. A 1-µF storage capacitor and a 10-nF decoupling capacitor should be placed close to the device. Wide, low impedance traces should be used to connect the capacitor to the pins of the device. The ADS7884 and ADS7885 draw very little current from the supply lines. The supply line can be driven by either: • Directly from the system supply. • A reference output from a low drift and low drop out reference voltage generator like REF3030 or REF3130. The ADS7884 and ADS7885 can operate off a wide range of supply voltages. The actual choice of the reference voltage generator would depend upon the system. Figure 45 shows one possible application circuit. • A low-pass filtered version of the system supply followed by a buffer like the zero-drift OPA735 can also be used in cases where the system power supply is noisy. Care should be taken to ensure that the voltage at the VDD input does not exceed 7 V (especially during power up) to avoid damage to the converter. This can be done easily using single supply CMOS amplifiers like the OPA735. Figure 46 shows one possible application circuit. VDD VDD VIN 1 mF 10 nF GND SCLK CS SDO Figure 44. Supply/Reference Decoupling Capacitors 5V REF3030 IN 1 mF GND VIN 1 mF 10 nF GND SCLK SDO OUT 3V VDD CS Figure 45. Using the REF3030 Reference 16 Submit Documentation Feedback Product Folder Link(s): ADS7884 ADS7885 Copyright © 2008, Texas Instruments Incorporated www.ti.com ADS7884 ADS7885 SLAS567 – MARCH 2008 5V C1 R1 10 W 7V _ + 1 mF VIN 1 mF 10 nF GND SCLK SDO R2 VDD CS Figure 46. Buffering with the OPA735 Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS7884 ADS7885 17 PACKAGE OPTION ADDENDUM www.ti.com 31-Mar-2008 PACKAGING INFORMATION Orderable Device ADS7884SDBVR ADS7884SDBVT ADS7885SDBVR ADS7885SDBVT (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE Package Type SOT-23 SOT-23 SOT-23 SOT-23 Package Drawing DBV DBV DBV DBV Pins Package Eco Plan (2) Qty 6 6 6 6 3000 Pb-Free (RoHS Exempt) 250 Pb-Free (RoHS Exempt) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR 3000 Pb-Free (RoHS Exempt) 250 Pb-Free (RoHS Exempt) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SOT-23 SOT-23 SOT-23 SOT-23 DBV DBV DBV DBV 6 6 6 6 SPQ Reel Reel Diameter Width (mm) W1 (mm) 177.8 177.8 177.8 177.8 9.7 9.7 9.7 9.7 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 4.0 4.0 4.0 4.0 W Pin1 (mm) Quadrant 8.0 8.0 8.0 8.0 Q3 Q3 Q3 Q3 ADS7884SDBVR ADS7884SDBVT ADS7885SDBVR ADS7885SDBVT 3000 250 3000 250 3.2 3.2 3.2 3.2 3.1 3.1 3.1 3.1 1.39 1.39 1.39 1.39 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2008 *All dimensions are nominal Device ADS7884SDBVR ADS7884SDBVT ADS7885SDBVR ADS7885SDBVT Package Type SOT-23 SOT-23 SOT-23 SOT-23 Package Drawing DBV DBV DBV DBV Pins 6 6 6 6 SPQ 3000 250 3000 250 Length (mm) 184.0 184.0 184.0 184.0 Width (mm) 184.0 184.0 184.0 184.0 Height (mm) 50.0 50.0 50.0 50.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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