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ADS7886
SLAS492B – SEPTEMBER 2005 – REVISED AUGUST 2016
ADS7886 12-Bit, 1-MSPS, Micro-Power, Miniature
SAR Analog-to-Digital Converters
1 Features
3 Description
•
•
•
•
•
•
The ADS7886 is a 12-bit, 1-MSPS analog-to-digital
converter (ADC). The device includes a capacitor
based SAR A/D converter with inherent sample and
hold. The serial interface in each device is controlled
by the CS and SCLK signals for glueless connections
with microprocessors and DSPs. The input signal is
sampled with the falling edge of CS, and SCLK is
used for conversion and serial data output.
1
•
•
•
•
•
•
•
1-MHz Sample Rate Serial Device
12-Bit Resolution
Zero Latency
20-MHz Serial Interface
Supply Range: 2.35 V to 5.25 V
Typical Power Dissipation at 1 MSPS:
– 3.9 mW at 3-V VDD
– 7.5 mW at 5-V VDD
INL ±1.25 LSB Maximum, ±0.65 LSB (Typical)
DNL ±1 LSB Maximum, +0.4 / –0.65 LSB (Typical)
Typical AC Performance:
72.25-dB SINAD, –84-dB THD
Unipolar Input Range: 0 V to VDD
Power Down Current: 1 µA
Wide Input Bandwidth: 15 MHz at 3 dB
6-Pin SOT-23 and SC70 Packages
2 Applications
•
•
•
•
•
•
•
•
Base Band Converters in Radio
Communication
Motor Current and Bus Voltage Sensors in Digital
Drives
Optical Networking (DWDM, MEMS Based
Switching)
Optical Sensors
Battery-Powered Systems
Medical Instrumentations
High-Speed Data Acquisition Systems
High-Speed Closed-Loop Systems
The device operates from a wide supply range from
2.35 V to 5.25 V. The low power consumption of the
device makes it suitable for battery-powered
applications. The device also includes a power down
feature for power saving at lower conversion speeds.
The high level of the digital input to the device is not
limited to device VDD. This means the digital input can
go as high as 5.25 V when device supply is 2.35 V.
This feature is useful when digital signals are coming
from other circuit with different supply levels. Also this
relaxes restriction on power-up sequencing.
The ADS7886 is available in 6-pin SOT-23 and SC70
packages and is specified for operation from –40°C to
125°C.
Device Information(1)
PART NUMBER
ADS7886
PACKAGE
BODY SIZE (NOM)
SOT-23 (6)
2.90 mm × 1.60 mm
SC70 (6)
2.00 mm × 1.25 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Block Diagram
SAR
+IN
CDAC
OUTPUT
LATCHES
and
3−STATE
DRIVERS
SDO
COMPARATOR
VDD
CONVERSION
and
CONTROL
LOGIC
SCLK
CS
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS7886
SLAS492B – SEPTEMBER 2005 – REVISED AUGUST 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
7
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ...............................................
Typical Characteristics ..............................................
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 15
9
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application .................................................. 16
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 19
12 Device and Documentation Support ................. 20
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (November 2009) to Revision B
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Deleted Package/Ordering Information table, see POA at the end of the datasheet. ........................................................... 1
•
Changed RθJA values from: 295.2 °C/W to: 113.4 °C/W for DBV package ............................................................................ 4
•
Changed RθJA values from: 351.3 °C/W to: 149.6 °C/W for DCK package ........................................................................... 4
Changes from Original (September 2005) to Revision A
Page
•
Added VIH information............................................................................................................................................................. 5
•
Changed VIH information ........................................................................................................................................................ 5
2
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SLAS492B – SEPTEMBER 2005 – REVISED AUGUST 2016
5 Device Comparison Table
Table 1. Micro-Power Miniature SAR Converter Family
BIT
< 300 KSPS
300 KSPS – 1.25 MSPS
12-Bit
ADS7866 (1.2 VDD to 3.6 VDD)
ADS7886 (2.35 VDD to 5.25 VDD)
10-Bit
ADS7867 (1.2 VDD to 3.6 VDD)
ADS7887 (2.35 VDD to 5.25 VDD)
8-Bit
ADS7868 (1.2 VDD to 3.6 VDD)
ADS7888 (2.35 VDD to 5.25 VDD)
6 Pin Configuration and Functions
DBV and DCK Packages
6-Pin SOT-23 and SC70
Top View
VDD
1
6
CS
GND
2
5
SDO
VIN
3
4
SCLK
Not to scale
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
VDD
—
Power supply input also acts like a reference voltage to ADC.
2
GND
—
Ground for power supply, all analog and digital signals are referred with respect to this pin.
3
VIN
I
Analog signal input
4
SCLK
I
Serial clock
5
SDO
O
Serial data out
6
CS
I
Chip select signal, active low
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SLAS492B – SEPTEMBER 2005 – REVISED AUGUST 2016
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
+IN to AGND
–0.3
VDD +0.3
V
+VDD to AGND
–0.3
7
V
Digital input voltage to GND
–0.3
7
V
Digital output to GND
–0.3
(VDD + 0.3)
V
Power dissipation, SOT-23 and SC70 packages
Lead
temperature,
soldering
(TJ Max–TA)/RθJA
Vapor phase (60 s)
215
Infrared (15 s)
220
Junction temperature (TJ Max)
Storage temperature, Tstg
(1)
–65
°C
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±3000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
TA
Operating temperature
MIN
MAX
UNIT
–40
125
°C
7.4 Thermal Information
ADS7886
THERMAL METRIC (1)
DBV (SOT-23)
DCK (SC70)
6 PINS
6 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
113.4
149.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
54.3
58.9
°C/W
RθJB
Junction-to-board thermal resistance
35.3
41.9
°C/W
ψJT
Junction-to-top characterization parameter
4.6
1.5
°C/W
ψJB
Junction-to-board characterization parameter
35
41.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
+VDD = 2.35 V to 5.25 V, TA = –40°C to 125°C, f(sample) = 1 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0
VDD
V
–0.2
VDD+0.2
ANALOG INPUT
Full-scale input voltage span (1)
Absolute input voltage range
CI
Input capacitance (2)
Ilkg
Input leakage current
+IN
TA = 125°C
V
21
pF
40
nA
12
Bits
SYSTEM PERFORMANCE
Resolution
No missing codes
INL
Integral nonlinearity
DNL
Differential nonlinearity
EO
Offset error (4)
EG
Gain error
ADS7886SB
12
ADS7886S
11
ADS7886SB
ADS7886S
–1.25
–1
ADS7886S
–2
VDD = 4.75 V to 5.25 V
±0.65
2
ADS7886SB
VDD = 2.35 V to 3.6 V
Bits
1.25
2
+0.4/-0.65
1
2
–2.5
±0.5
2.5
–2
±0.5
2
–1.75
±0.5
1.75
760
800
LSB (3)
LSB
LSB
LSB
SAMPLING DYNAMICS
Conversion time
20-MHz SCLK
Acquisition time
Maximum throughput rate
ns
325
ns
20-MHz SCLK
1
Aperture delay
MHz
5
ns
Step Response
160
ns
Overvoltage recovery
160
ns
DYNAMIC CHARACTERISTICS
VDD = 2.35 V to 3.6 V, fI = 100 kHz
69
71.25
VDD = 4.75 V to 5.25 V, fI = 100 kHz
70
72.25
VDD = 2.35 V to 3.6 V, fI = 100 kHz
69
71.25
VDD = 4.75 V to 5.25 V, fI = 100 kHz
70
72.25
SNR
Signal-to-noise ratio
dB
SINAD
Signal-to-noise and distortion
THD
Total harmonic distortion (5)
fI = 100 kHz
–84
dB
SFDR
Spurious free dynamic range
fI = 100 kHz
85.5
dB
Full power bandwidth
At –3 dB
dB
15
MHz
DIGITAL INPUT/OUTPUT
Logic family — CMOS
VDD = 2.35 V to 3.6 V
1.8
5.25
VDD = 3.6 V to 5.25 V
2.4
5.25
VIH
High-level input voltage
VIL
Low-level input voltage
VOH
High-level output voltage
I(source) = 200 µA
VOL
Low-level output voltage
I(sink) = 200 µA
(1)
(2)
(3)
(4)
(5)
VDD = 5 V
0.8
VDD = 3 V
0.4
VDD –
0.2
V
V
V
0.4
Ideal input span; does not include gain or offset error.
See Figure 27 for details on the sampling circuit.
LSB means least significant bit.
Measured relative to an ideal full-scale input.
Calculated on the first nine harmonics of the input frequency.
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Electrical Characteristics (continued)
+VDD = 2.35 V to 5.25 V, TA = –40°C to 125°C, f(sample) = 1 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.35
V
POWER SUPPLY REQUIREMENTS
+VDD
Supply voltage
Supply current (normal mode)
Power down state supply current
Power dissipation at 1-MHz throughput
Power dissipation in static state
3.3
5.25
VDD = 2.35 V to 3.6 V, 1-MHz
throughput
1.3
1.5
VDD = 4.75 V to 5.25 V, 1-MHz
throughput
1.5
2
VDD = 2.35 V to 3.6 V, static state
1.1
VDD = 4.75 V to 5.25 V, static state
1.5
SCLK off
200
VDD = 3 V
3.9
4.5
VDD = 5 V
7.5
10
VDD = 3 V
3.3
VDD = 5 V
7.5
Power-up time
0.1
Invalid conversions after
power up or reset
6
1
SCLK on (20 MHz)
mA
µA
mW
mW
µs
1
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7.6 Timing Requirements
All specifications typical at TA = –40°C to 125°C, VDD = 2.35 V to 5.25 V (see Figure 1 and Figure 2) (unless otherwise
specified) (1).
PARAMETER
TEST CONDITIONS
tconv
Conversion time
ADS7866
tq
Minimum quiet time needed from bus 3-state to start
of next conversion
td1
Delay time, CS low to first data (0) out
tsu1
Setup time, CS low to SCLK low
td2
Delay time, SCLK falling to SDO
th1
Hold time, SCLK falling to data valid (2)
td3
Delay time, 16th SCLK falling edge to SDO 3-state
tw1
Pulse duration, CS
td4
Delay time, CS high to SDO 3-state
twH
Pulse duration, SCLK high
twL
Pulse duration, SCLK low
Frequency, SCLK
td5
Delay time, second falling edge of clock and CS to
enter in power down (use min spec not to accidently
enter in power down) Figure 2
td6
(1)
(2)
MIN
NOM
MAX
VDD = 3 V
16 × tSCLK
VDD = 5 V
16 × tSCLK
VDD = 3 V
40
VDD = 5 V
40
15
25
VDD = 5 V
13
25
10
VDD = 5 V
10
15
25
VDD = 5 V
13
25
7
VDD > 5 V
5.5
10
25
VDD = 5 V
8
20
VDD = 3 V
25
40
VDD = 5 V
25
40
17
30
VDD = 5 V
15
25
0.4 × tSCLK
0.4 × tSCLK
VDD = 3 V
0.4 × tSCLK
VDD = 5 V
0.4 × tSCLK
ns
ns
VDD = 3 V
VDD = 5 V
ns
ns
VDD = 3 V
VDD = 3 V
ns
ns
VDD = 3 V
VDD < 3 V
ns
ns
VDD = 3 V
VDD = 3 V
UNIT
ns
ns
ns
VDD = 3 V
20
VDD = 5 V
20
VDD = 3 V
–2
5
VDD = 5 V
–2
5
Delay time, CS and 10th falling edge of clock to
VDD = 3 V
enter in power down (use max spec not to accidently
VDD = 5 V
enter in power down) Figure 2
2
–5
2
–5
MHz
ns
ns
3-V Specifications apply from 2.35 V to 3.6 V, and 5-V specifications apply from 4.75 V to 5.25 V.
With 50-pf load.
a
tconv
t w1
b
CS
t su1
1
SCLK
4
0
13
6
5
15
14
16
th1
t d2
t d1
SDO
2
0
0
D11
t d3
D10
D3
D2
D1
D0
tq
1/throughput
Figure 1. Interface Timing Diagram
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td6
td5
CS
1
2
3
4
5
9
10
16
SCLK
SDO
Figure 2. Entering Power Down Mode
8
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7.7 Typical Characteristics
1.6
1.6
fs = 1 MSPS,
fSCLK = 20 MHz
o
TA = 25 C
IDD − Supply Current − mA
IDD − Supply Current − mA
1.4
o
125 C
1.5
o
25 C
1.4
1.3
1.2
o
−40 C
1.2
5V
1
2.35 V
0.8
0.6
0.4
1.1
0.2
1
0
2.35
3.075
3.8
4.525
5.25
5
0
VDD − Supply Voltage − V
Figure 3. Supply Current vs Supply Voltage
1.4
20
40
30
1
20
Leakage Current − nA
IDD − Supply Current − mA
15
Figure 4. Supply Current vs SCLK Frequency
fSCLK = 20 MHz,
o
TA = 25 C,
Power Down Wih SCLK = Free Running
1.2
10
f − SCLK Frequency − MHz
0.8
5V
0.6
0.4
10
5 V Input
0
−10
0 V Input
−20
2.35 V
0.2
−30
0
0
50
100
150
200
250
300
−40
−40
350
15
fs − Sample Rate − KSPS
Figure 6. Analog Input Leakage Current vs Free-Air
Temperature
73
73
72.5
72.5
SNR − Signal-to-Noise Ratio − dB
SNR − Signal-to-Noise Ratio − dB
125
o
Figure 5. Supply Current vs Sample Rate
72
71.5
71
70.5
fs = 1 MSPS,
VDD = 5 V,
70
70
TA − Free-Air Temperature − C
o
TA = 25 C
69.5
72
71.5
71
70.5
fs = 1 MSPS,
70
fI = 100 kHz,
o
TA = 25 C
69.5
69
69
1
10
100
fI − Input Frequency − kHz
2.35
1000
3.075
3.8
4.525
5.25
VDD − Supply Voltage − V
Figure 7. Signal-to-Noise Ratio vs Input Frequency
Figure 8. Signal-to-Noise Ratio vs Supply Voltage
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Typical Characteristics (continued)
−84
73
THD − Total Harmonic Distortion − dB
SNR − Signal-to-Noise Ratio − dB
fS = 1 MSPS,
o
TA 25 C,
VDD = 5 V
−85
72.5
5V
72
71.5
2.35 V
71
70.5
fs = 1 MSPS,
70
fI = 100 kHz
69.5
69
−40
15
70
−86
−87
−88
−89
−90
−91
−92
−93
−94
125
1
10
o
100
TA − Free-Air Temperature − C
fi − Input Frequency − kHz
Figure 9. Signal-to-Noise Ratio vs Free-Air Temperature
Figure 10. Total Harmonic Distortion vs Input Frequency
-80
fs = 1 MSPS,
THD − Total Harmonic Distortion − dB
THD − Total Harmonic Distortion − dB
-80
fI = 100 kHz,
TA = 25oC
-82
-84
-86
-88
fs = 1 MSPS,
-81
fI = 100 kHz
-82
-83
2.35 V
-84
-85
5V
-86
-87
-88
-89
-90
2.35
-90
3.075
3.8
4.525
5.25
15
−40
VDD − Supply Voltage − V
Figure 12. Total Harmonic Distortion vs Free-Air
Temperature
87
SFDR − Spurious Free Dynamic Range − dB
87
SFDR − Spurious Free Dynamic Range − dB
125
o
Figure 11. Total Harmonic Distortion vs Supply Voltage
86.5
86
85.5
fs = 1 MSPS,
85
VDD = 5 V,
84.5
o
TA = 25 C
84
83.5
83
82.5
82
1
10
86.5
86
85.5
85
84.5
84
83.5
83
fs = 1 MSPS,
fI = 100 kHz,
o
TA = 25 C
82.5
82
2.35
100
fi − Input Frequency − kHz
3.075
3.8
4.525
5.25
VDD − Supply Voltage − V
Figure 13. Spurious Free Dynamic Range vs Input
Frequency
10
70
TA − Free-Air Temperature − C
Figure 14. Spurious Free Dynamic Range vs Supply Voltage
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Typical Characteristics (continued)
1.5
86.4
fs = 1 MSPS,
o
TA = 25 C
5V
1
EO − Offset Error - LSBs
SFDR − Spurious Free Dynamic Range - dB
86.6
86.2
86
fs = 1 MSPS,
fI = 100 kHz,
o
TA = 25 C
85.8
85.6
2.35 V
0.5
0
-0.5
-1
85.4
85.2
−40
15
70
-1.5
2.35
125
3.075
o
TA − Free-Air Temperature − C
Figure 15. Spurious Free Dynamic Range vs Supply Voltage
4.525
5.25
Figure 16. Offset Error vs Supply Voltage
1
1
fs = 1 MSPS,
o
TA = 25 C
0.8
fs = 1 MSPS,
VDD = 5 V
0.75
0.6
0.5
EG − Gain Error - LSBs
EO − Offset Error - LSBs
3.8
VDD − Supply Voltage − V
0.25
0
-0.25
0.4
0.2
0
−0.2
−0.4
-0.5
−0.6
-0.75
−0.8
-1
−40
−1
15
70
125
2.35
o
TA − Free-Air Temperature − C
5.25
1
fs = 1 MSPS,
VDD = 5 V
DNL − Differential Linearity Error - LSBs
EG − Gain Error - LSBs
4.525
Figure 18. Gain Error vs Supply Voltage
1
0.6
3.8
VDD − Supply Voltage − V
Figure 17. Offset Error vs Free-Air Temperature
0.8
3.075
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
fs = 1 MSPS,
o
TA = 25 C
0.8
0.6
Max
0.4
0.2
0
−0.2
−0.4
Min
−0.6
−0.8
−1
−1
−40
15
70
125
2.35
o
3.075
3.8
4.525
5.25
TA − Free-Air Temperature − C
VDD − Supply Voltage − V
Figure 19. Gain Error vs Free-Air Temperature
Figure 20. Differential Linearity Error vs Supply Voltage
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Typical Characteristics (continued)
1.25
1
INL − Integral Nonlinearity - LSBs
DNL − Differential Nonlinearity - LSBs
ffs == 11 MSPS,
MSPS,
s
o
oC
TTA == 25
A 25 C
fs = 1 MSPS,
VDD = 5 V
0.8
0.6
Max
0.4
0.2
0
−0.2
−0.4
Min
−0.6
0.75
Max
0.25
−0.25
Min
−0.75
−0.8
−1
−40
15
70
−1.25
2.35
125
3.075
3.8
4.525
5.25
VDD − Supply Voltage − V
o
TA − Free-Air Temperature − C
Figure 22. Integral Nonlinearity vs Supply Voltage
Figure 21. Differential Nonlinearity vs Free-Air Temperature
1.25
INL − Integral Nonlinearity - LSBs
fs = 1 MSPS,
VDD = 5 V
0.75
Max
0.25
−0.25
Min
−0.75
−1.25
−40
15
70
125
o
TA − Free-Air Temperature − C
Figure 23. Integral Nonlinearity vs Free-Air Temperature
1
0.8
0.4
0.2
0.6
INL - LSBs
0.6
DNL - LSBs
1
0.8
VDD = 2.35 V,
fs = 1 MSPS,
o
TA = 25 C
0
−0.2
−0.4
−0.6
−0.8
0.4
0.2
0
−0.2
−0.4
VDD = 2.35 V,
fs = 1 MSPS,
TA = 25oC
−0.6
−0.8
−1
−1
0
1024
2048
3072
4096
0
Output Code
2048
3072
4096
Output Code
Figure 24. DNL
12
1024
Figure 25. INL
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Typical Characteristics (continued)
0
VDD = 2.35 V,
fs = 1 MSPS,
TA = 25oC,
Amplitude − dB
−20
−40
−60
fI = 100 kHz,
8192 Points
−80
−100
−120
−140
−160
0
100000
200000
300000
400000
500000
f − Frequency − Hz
Figure 26. FFT
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8 Detailed Description
8.1 Overview
The ADS7886 is 12-bit, 1-MSPS analog-to-digital converter (ADC). The device includes a capacitor-based SAR
A/D converter with inherent sample and hold circuitry. The serial interface in device is controlled by the CS and
SCLK signals for easy interface with microprocessors and DSPs. The input signal is sampled with the falling
edge of CS, and SCLK is used for conversion and serial data output. The device operates from a wide supply
range from 2.35 V to 5.25 V. The low power consumption of the device makes it suitable for battery-powered
applications. The device also includes a power-saving, power-down feature which is useful when the device is
operated at lower conversion speeds. The high level of the digital input to the device is not limited to device
VDD. This means the digital input can go as high as 5.25 V when device supply is 2.35 V. This feature is useful
when digital signals are coming from other circuit with different supply levels. This also relaxes the restrictions on
power-up sequencing.
8.2 Functional Block Diagram
SAR
+IN
OUTPUT
LATCHES
and
3−STATE
DRIVERS
CDAC
SDO
COMPARATOR
VDD
CONVERSION
and
CONTROL
LOGIC
SCLK
CS
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8.3 Feature Description
8.3.1 Driving the VIN and VDD Pins
The VIN input should be driven with a low impedance source. In most cases additional buffers are not required.
In cases where the source impedance exceeds 200 Ω, using a buffer would help achieve the rated performance
of the converter. The THS4031 is a good choice for the driver amplifier buffer.
The reference voltage for the A/D converter is derived from the supply voltage internally. The devices offer
limited low-pass filtering functionality on-chip. The supply to these converters should be driven with a low
impedance source and should be decoupled to the ground. A 1-µF storage capacitor and a 10-nF decoupling
capacitor should be placed close to the device. Wide, low impedance traces should be used to connect the
capacitor to the pins of the device. The ADS7886 draws very little current from the supply lines. The supply line
can be driven by either:
• Directly from the system supply.
• A reference output from a low drift and low drop out reference voltage generator like REF3030 or REF3130.
The ADS7886 operates from a wide range of supply voltages. The actual choice of the reference voltage
generator would depend upon the system. Figure 33 shows one possible application circuit.
• A low-pass filtered system supply followed by a buffer, like the zero-drift OPA735, can also be used in cases
where the system power supply is noisy. Care must be taken to ensure that the voltage at the VDD input does
not exceed 7 V to avoid damage to the converter. This can be done easily using single supply CMOS
amplifiers like the OPA735. Figure 34 shows one possible application circuit.
14
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Feature Description (continued)
VDD
20 W
60 W
IN
16 pF
60 W
5 pF
GND
Figure 27. Typical Equivalent Sampling Circuit
8.4 Device Functional Modes
8.4.1 Normal Operation
The cycle begins with the falling edge of CS. This point is indicated as a in Figure 1. With the falling edge of CS,
the input signal is sampled and the conversion process is initiated. The device outputs data while the conversion
is in progress. The data word contains 4 leading zeros, followed by 12-bit data in MSB first format.
The falling edge of CS clocks out the first zero, and a zero is clocked out on every falling edge of the clock until
the third edge. Data is in MSB first format with the MSB being clocked out on the 4th falling edge. On the 16th
falling edge of SCLK, SDO goes to the 3-state condition. The conversion ends on the 16th falling edge of SCLK.
The device enters the acquisition phase on the first rising edge of SCLK after the 13th falling edge. This point is
indicated by b in Figure 1.
CS can be asserted (pulled high) after 16 clocks have elapsed. It is necessary not to start the next conversion by
pulling CS low until the end of the quiet time (tq) after SDO goes to 3-state. To continue normal operation, it is
necessary that CS is not pulled high until point b. Without this, the device does not enter the acquisition phase
and no valid data is available in the next cycle. (Also refer to power down mode for more details.) CS going high
any time after the conversion start aborts the ongoing conversion and SDO goes to 3-state.
The high level of the digital input to the device is not limited to device VDD. This means the digital input can go as
high as 5.25 V when the device supply is 2.35 V. This feature is useful when digital signals are coming from
another circuit with different supply levels. Also, this relaxes the restriction on power up sequencing. However,
the digital output levels (VOH and VOL) are governed by VDD as listed in the Electrical Characteristics table.
8.4.2 Power Down Mode
The device enters power down mode if CS goes high anytime after the 2nd SCLK falling edge to before the 10th
SCLK falling edge. Ongoing conversion stops and SDO goes to 3-state under this power down condition as
shown in Figure 2.
A dummy cycle with CS low for more than 10 SCLK falling edges brings the device out of power down mode. For
the device to come to the fully powered up condition it takes 1 µs. CS can be pulled high any time after the 10th
falling edge as shown in Figure 28. It is not necessary to continue until the 16th clock if the next conversion
starts 1 µs after CS going low of the dummy cycle and the quiet time (tq) condition is met.
Device Starts
Powering Up
Device Fully
Powered-Up
CS
SCLK
1
SDO
2
3
4
5
6
7
8
9 10 11 12 13 14 15
16
1
2
3
4
5
6
Invalid Data
7
8
9
10 11 12 13 14 15 16
Valid Data
Figure 28. Exiting Power Down Mode
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The primary circuits required to maximize the performance of a high-precision, successive approximation register
(SAR), analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This section details
some general principles for designing the input driver circuit, reference driver circuit, and provides some
application circuits designed for the ADS7886.
9.2 Typical Application
AVDD
AVDD
OPA365
33
±
VDD
VIN
+
+
VSOURCE
Device
±
680 pF
GND
GND
Device: 12-Bit, 1-MSPS,
Single-Ended Input
Input Driver
Copyright © 2016, Texas Instruments Incorporated
Figure 29. Typical Data Acquisition (DAQ) Circuit: Single-Supply DAQ
9.2.1 Design Requirements
The goal of this application is to design a single-supply digital acquisition (DAQ) circuit based on the ADS7886
with SNR greater than 72.5 dB and THD less than –84 dB for input frequencies of 2 kHz to 100 kHz at a
throughput of 1 MSPS.
9.2.2 Detailed Design Procedure
To achieve a SINAD of 61 dB, the operational amplifier must have high bandwidth to settle the input signal within
the acquisition time of the ADC. The operational amplifier must have low noise to keep the total system noise
below 20% of the input-referred noise of the ADC. For the application circuit shown in Figure 29, OPA365 is
selected for its high bandwidth (50 MHz) and low noise (4.5 nV√Hz).
The reference voltage for the ADS7887 and ADS7888 A/D converters are derived from the supply voltage
internally. The supply to these converters must be driven with a low impedance source and must be decoupled to
the ground. To drive supply pin of ADS7887 ultra-low noise fast transient response low dropout voltage regulator
TPS73201 is selected. Alternatively one can drive supply pin with low impedance voltage reference similar to
REF3030.
For a step-by-step design procedure for low power, small form factor digital acquisition (DAQ) circuit based on
similar SAR ADCs, see TI Precision Design, Three 12-Bit Data Acquisition Reference Designs Optimized for Low
Power and Ultra-Small Form Factor (TIDU390).
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Typical Application (continued)
9.2.3 Application Curves
0
0
-20
-20
-40
-60
Amplitude (dB)
Amplitude (dB)
-40
-80
-100
-120
-60
-80
-100
-120
-140
-140
-160
-180
-160
0
75000
150000 225000 300000
Frequency (Hz)
375000
450000
0
D001
Figure 30. Test Results for the ADS7886 and OPA365 for a
2-kHz Input
75000
150000 225000 300000
Frequency (Hz)
375000
450000
D002
Figure 31. Test Results for the ADS7886 and OPA365 for a
100-kHz Input
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10 Power Supply Recommendations
The reference voltage for the ADS7886 A/D converter is derived from the supply voltage internally. The supply to
ADS7886 should be driven with a low impedance source and should be decoupled to the ground. Decouple the
VDD with 1-µF ceramic decoupling capacitors, as shown in Figure 32. Always set the VDD supply to be greater
than or equal to the maximum input signal to avoid saturation of codes.
VDD
1 mF
VDD
CS
VIN
SDO
GND
SCLK
10 nF
Figure 32. Supply/Reference Decoupling Capacitors
5V
REF3030
IN
3V
1 mF
OUT
VDD
CS
VIN
SDO
GND
SCLK
VDD
CS
VIN
SDO
GND
SCLK
GND
1 mF
10 nF
Figure 33. Using the REF3030 Reference
5V
C1
R1
10 W
7V
_
R2
+
1 mF
1 mF
10 nF
Figure 34. Buffering With the OPA735
11 Layout
11.1 Layout Guidelines
Figure 35 shows a board layout example for the ADS7886. Some of the key considerations are
1. Use a ground plane underneath the device and partition the PCB into analog and digital sections.
2. Avoid crossing digital lines with the analog signal path.
3. The power sources to the device must be clean and well-bypassed. Use 1-µF ceramic bypass capacitors in
close proximity to the supply pin (VDD).
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Layout Guidelines (continued)
4. Avoid placing vias between the VDD and bypass capacitors.
5. Connect ground pin to the ground plane using short, low-impedance path.
6. The fly-wheel RC filters are placed close to the device.
Among ceramic surface-mount capacitors, COG (NPO) ceramic capacitors provide the best capacitance
precision. The type of dielectric used in COG (NPO) ceramic capacitors provides the most stable electrical
properties over voltage, frequency, and temperature changes.
11.2 Layout Example
Analog
Pins
Digital
Pins
VDD
1
6
CS
5
SDO
4
SCLK
1 PF
GND
2
VIN
3
ADS7886
CFLT
RFLT
Figure 35. ADS7886 Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• OPAx365 50-MHz, Zerø-Crossover, Low-Distortion, High CMRR, RRI/O, Single-Supply Operational Amplifier
(SBOS365)
• Cap-Free NMOS 250-mA Low Dropout Regulator With Reverse Current Protection (SGLS346)
• Three 12-Bit Data Acquisition Reference Designs Optimized for Low Power and Ultra-Small Form Factor
(TIDU390)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ADS7886SBDBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
BBAQ
ADS7886SBDBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
BBAQ
ADS7886SBDCKR
ACTIVE
SC70
DCK
6
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
BNL
ADS7886SBDCKT
ACTIVE
SC70
DCK
6
250
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
BNL
ADS7886SDBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
BBAQ
ADS7886SDBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
BBAQ
ADS7886SDCKR
ACTIVE
SC70
DCK
6
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
BNL
ADS7886SDCKT
ACTIVE
SC70
DCK
6
250
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
BNL
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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