ADS7887M
SLAS750A – JUNE 2011 – REVISED JUNE 2011
www.ti.com
10-BIT 1.25-MSPS MICRO-POWER MINIATURE
SAR ANALOG-TO-DIGITAL CONVERTER
Check for Samples: ADS7887M
FEATURES
xxxxxx
xxxxxx
1
•
•
•
•
•
•
•
•
•
•
•
•
1.25-MHz Sample Rate Serial Device
10-Bit Resolution
Zero Latency
25-MHz Serial Interface
Supply Range: 2.35 V to 5.25 V
Typical Power Dissipation at 1.25 MSPS:
– 3.8 mW at 3-V VDD
– 8 mW at 5-V VDD
±0.35 LSB INL, DNL
61-dB SINAD, –84-dB THD
Unipolar Input Range: 0 V to VDD
Power Down Current: 10 µA Max
Wide Input Bandwidth: 15 MHz at 3 dB
6-Pin SOT23 Package
APPLICATIONS
•
•
•
•
•
•
•
•
Base Band Converters in Radio
Communication
Motor Current/Bus Voltage Sensors in Digital
Drives
Optical Networking (DWDM, MEMS Based
Switching)
Optical Sensors
Battery Powered Systems
Medical Instrumentations
High-Speed Data Acquisition Systems
High-Speed Closed-Loop Systems
DESCRIPTION
The ADS7887 is a 10-bit 1.25-MSPS analog-to-digital converter (ADC). The device includes a capacitor-based
SAR A/D converter with inherent sample and hold. The serial interface is controlled by the CS and SCLK signals
for glueless connections with microprocessors and DSPs. The input signal is sampled with the falling edge of CS,
and SCLK is used for conversion and serial data output.
The device operates from a wide supply range from 2.35 V to 5.25 V. The low power consumption of the device
makes it suitable for battery-powered applications. The device also includes a power-saving powerdown feature
for when the device is operated at lower conversion speeds.
The high level of the digital input to the device is not limited to device VDD. This means the digital input can go as
high as 5.25 V when device supply is 2.35 V. This feature is useful when digital signals are coming from other
circuits with different supply levels. Also, this relaxes restriction on power-up sequencing.
The ADS7887 is available in a 6-pin SOT23 package and is specified for operation from –55°C to 125°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
ADS7887M
SLAS750A – JUNE 2011 – REVISED JUNE 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
–55°C to 125°C
(1)
(2)
SOT-23 – DBV
Reel of 250
ORDERABLE PART NUMBER
TOP-SIDE MARKING
ADS7887MDBVT
BCNM
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
SAR
+IN
CDAC
OUTPUT
LATCHES
AND
3-STATE
DRIVERS
SDO
COMPARATOR
VDD
CONVERSION
AND
CONTROL
LOGIC
SCLK
CS
ABSOLUTE MAXIMUM RATINGS (1)
–0.3 V to +VDD +0.3 V
+IN to AGND
+VDD to AGND
–0.3 V to 7.0 V
Digital input voltage to GND
–0.3V to (7.0 V)
–0.3 V to (+VDD + 0.3 V)
Digital output to GND
Operating temperature range
–55°C to 125°C
Storage temperature range
–65°C to 150°C
Junction temperature (TJ Max)
150°C
Power dissipation
(TJ Max–TA)/θJA
θJA Thermal impedance (2)
Lead temperature, soldering
(1)
(2)
2
295.2°C/W
Vapor phase (60 sec)
215°C
Infrared (15 sec)
220°C
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
The package thermal impedance is calculated in accordance with JESD 51-7, except for through-hole packages, which use a trace
length of zero.
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ELECTRICAL SPECIFICATIONS
+VDD = 2.35 V to 5.25 V, TA = –55°C to 125°C, fsample = 1.25 MHz
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0
VDD
V
–0.20
VDD+0.20
ANALOG INPUT
Full-scale input voltage span (1)
Absolute input voltage range
Ci
Input capacitance (2)
IIlkg
Input leakage current
+IN
TA = 125°C
V
21
pF
40
nA
10
Bits
SYSTEM PERFORMANCE
Resolution
No missing codes
10
Bits
INL
Integral nonlinearity
–1.2
±0.35
1.2
LSB (3)
DNL
Differential nonlinearity
–1 (4)
±0.35
1.35
LSB
–2.5
±0.5
2.5
LSB
–2
±0.5
2
LSB
530
560
(5) (6) (7)
EO
Offset error
EG
Gain error (6)
SAMPLING DYNAMICS
Conversion time
25-MHz SCLK
Acquisition time
Maximum throughput rate
ns
260
ns
25-MHz SCLK
1.25
MHz
Aperture delay
5
ns
Step response
160
ns
Overvoltage recovery
160
ns
DYNAMIC CHARACTERISTICS
THD
Total harmonic distortion (8)
100 kHz
SINAD
Signal-to-noise and distortion
100 kHz
59
61
SFDR
Spurious free dynamic range
100 kHz
70
81
dB
Full power bandwidth
At –3 dB
15
MHz
–84
–67
dB
dB
DIGITAL INPUT/OUTPUT
Logic family — CMOS
VDD = 2.35 V to 5.25 V
VIH
High-level input voltage
VIL
Low-level input voltage
VOH
High-level output voltage
At Isource = 200 µA
VOL
Low-level output voltage
At Isink = 200 µA
VDD –
0.4
5.25
VDD = 5 V
0.8
VDD = 3 V
0.4
VDD–0.2
0.4
V
V
V
POWER SUPPLY REQUIREMENTS
+VDD
Supply voltage
Supply current (normal mode)
Power-down state supply current
Power dissipation at 1.25 MHz
throughput
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
2.35
3.3
At VDD = 2.35 V to 5.25 V, 1.25-MHz throughput
5.25
2
At VDD = 2.35 V to 5.25 V, static state
1.5
SCLK off
10
SCLK on (25 MHz)
200
VDD = 5 V
8
10
VDD = 3 V
3.8
6
V
mA
µA
mW
Ideal input span; does not include gain or offset error.
Refer Figure 21 for details on sampling circuit
LSB means least significant bit
Exclusive
Measured relative to an ideal full-scale input
Offset error and gain error ensured by characterization.
First transition of 000H to 001H at 0.5 × (Vref/210)
Calculated on the first nine harmonics of the input frequency
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ELECTRICAL SPECIFICATIONS (continued)
+VDD = 2.35 V to 5.25 V, TA = –55°C to 125°C, fsample = 1.25 MHz
PARAMETER
Power dissipation in static state
TEST CONDITIONS
MIN
TYP
MAX
VDD = 5 V
5.5
7.5
VDD = 3 V
3
4.5
UNIT
mW
Power down time
0.1
µs
Power up time
0.8
µs
Invalid conversions after power up
1
TEMPERATURE RANGE
–55
Specified performance
°C
125
TIMING REQUIREMENTS (see Figure 1)
All specifications typical at TA = –55°C to 125°C, VDD = 2.35 V to 5.25 V, unless otherwise specified.
TEST CONDITIONS (1)
PARAMETER
tconv
Conversion time
tq
Minimum quiet time needed from bus 3-state to start of
next conversion
td1
Delay time, CS low to first data (0) out
tsu1
Setup time, CS low to SCLK low
td2
Delay time, SCLK falling to SDO
th1
Hold time, SCLK falling to data valid (2)
td3
Delay time, 16th SCLK falling edge to SDO 3-state
tw1
Pulse duration, CS
td4
Delay time, CS high to SDO 3-state
twH
Pulse duration, SCLK high
twL
Pulse duration, SCLK low
Frequency, SCLK
td5
Delay time, second falling edge of clock and CS to
enter in powerdown (use minimum specification to
avoid accidently entering powerdown) Figure 2
td6
(1)
(2)
4
MIN
TYP
MAX
UNIT
VDD = 3 V
14 × tSCLK
VDD = 5 V
14 × tSCLK
VDD = 3 V
40
VDD = 5 V
40
ns
VDD = 3 V
15
25
VDD = 5 V
13
25
VDD = 3 V
10
VDD = 5 V
10
15
25
VDD = 5 V
13
25
7
VDD > 5 V
5.5
10
25
VDD = 5 V
8
20
VDD = 3 V
25
40
VDD = 5 V
25
40
17
30
VDD = 5 V
15
25
0.4 × tSCLK
0.4 × tSCLK
VDD = 3 V
0.4 × tSCLK
VDD = 5 V
0.4 × tSCLK
ns
ns
VDD = 3 V
VDD = 5 V
ns
ns
VDD = 3 V
VDD = 3 V
ns
ns
VDD = 3 V
VDD < 3 V
ns
ns
ns
ns
VDD = 3 V
25
VDD = 5 V
25
VDD = 3 V
-2
5
VDD = 5 V
-2
5
Delay time, CS and 10th falling edge of clock to enter in VDD = 3 V
powerdown (use maximum specification to avoid
VDD = 5 V
accidently entering powerdown) Figure 2
2
-5
2
-5
MHz
ns
ns
3-V Specifications apply from 2.35 V to 3.6 V, and 5-V specifications apply from 4.75 V to 5.25 V.
With 50-pf load.
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DEVICE INFORMATION
SOT23 PACKAGE
(TOP VIEW)
VDD
1
6
CS
GND
2
5
SDO
VIN
3
4
SCLK
TERMINAL FUNCTIONS
TERMINAL
NAME
I/O
NO.
DESCRIPTION
VDD
1
–
Power supply input also acts like a reference voltage to ADC.
GND
2
–
Ground for power supply, all analog and digital signals are referred with respect to this pin.
VIN
3
I
Analog signal input
SCLK
4
I
Serial clock
SDO
5
O
Serial data out
CS
6
I
Chip select signal, active low
NORMAL OPERATION
The cycle begins with the falling edge of CS. This point is indicated as a in Figure 1. With the falling edge of CS,
the input signal is sampled and the conversion process is initiated. The device outputs data while the conversion
is in progress. The data word contains 4 leading zeros, followed by 10-bit data in MSB first format and padded by
2 lagging zeros.
The falling edge of CS clocks out the first zero, and a zero is clocked out on every falling edge of the clock until
the third edge. Data is in MSB first format with the MSB being clocked out on the 4th falling edge. Data is padded
with two lagging zeros as shown in Figure 1. On the 16th falling edge of SCLK, SDO goes to the 3-state
condition. The conversion ends on the 14th falling edge of SCLK. The device enters the acquisition phase on the
first rising edge of SCLK after the 13th falling edge. This point is indicated by b in Figure 1.
CS can be asserted (pulled high) after 16 clocks have elapsed. Do not start the next conversion by pulling CS
low until the end of the quiet time (tq) after SDO goes to 3-state. To continue normal operation, do not pull CS
high until point b. Without this, the device does not enter the acquisition phase and no valid data is available in
the next cycle. (Also refer to power down mode for more details.) CS going high any time after the conversion
start aborts the ongoing conversion and SDO goes to 3-state.
The high level of the digital input to the device is not limited to device VDD. This means the digital input can go as
high as 5.25 V when the device supply is 2.35 V. This feature is useful when digital signals are coming from
another circuit with different supply levels. Also, this relaxes the restriction on power up sequencing. However,
the digital output levels (VOH and VOL) are governed by VDD as listed in the SPECIFICATIONS table.
a
tconv
tw1
b
CS
tsu1
1
SCLK
4
0
13
6
5
15
14
16
th1
td2
td1
SDO
2
0
0
D9
td3
D8
D1
D0
0
0
tq
1/throughput
Figure 1. Interface Timing Diagram
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POWER-DOWN MODE
The device enters power down mode if CS goes high anytime after the second SCLK falling edge to before the
tenth SCLK falling edge. Ongoing conversion stops and SDO goes to 3-state under this power-down condition as
shown in Figure 2.
td6
td5
CS
1
2
3
4
5
9
10
16
SCLK
SDO
Figure 2. Entering Power Down Mode
A dummy cycle with CS low for more than ten SCLK falling edges brings the device out of power-down mode.
For the device to come to the fully powered up condition it takes 0.8 µs. CS can be pulled high any time after the
10th falling edge as shown in Figure 3. It is not necessary to continue until the 16th clock if the next conversion
starts 0.8 µs after CS going low of the dummy cycle and the quiet time (tq) condition is met.
Device Starts
Powering Up
Device Fully
Powered-Up
CS
SCLK
1
SDO
2
3
4
5
6
7
8
9 10 11 12 13 14 15
16
1
2
3
4
5
6
Invalid Data
7
8
9
10 11 12 13 14 15 16
Valid Data
Figure 3. Exiting Power Down Mode
6
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TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
SCLK FREQUENCY
1.80
1.8
1255C
1.4
−405C
1.3
1.2
1.40
1.20
2.35 V VDD
1
0.80
0.60
1
0.8
0.6
0.4
0.40
1.1
0.2
0.20
1
2.35
3.075
3.8
4.525
0
0
5.25
0
5
10
15
20
fSCLK − SCLK Frequency − MHz
VDD − Supply Voltage − V
100
150 200 250
300 350 400
SIGNAL-TO-NOISE
AND DISTORTION
vs
INPUT FREQUENCY
SIGNAL-TO-NOISE
AND DISTORTION
vs
SUPPLY VOLTAGE
−10
@ 0 V Input
−20
−30
61.7
61.5
61.3
61.1
60.9
60.7
60.5
−40
−40 −20
20
60
80 100
0
40
TA − Free-Air Temperature − 5C
SINAD − Signal-to-Noise and Distortion − dB
SINAD − Signal-to-Noise and Distortion − dB
0
62
fs = 1.25 MSPS,
TA = 255C,
VDD = 5 V
61.9
1
10
100
fi − Input Frequency − kHz
120
450
fs − Sample Rate − KSPS
ANALOG INPUT
LEAKAGE CURRENT
vs
FREE-AIR TEMPERATURE
@ 5 V Input
fs = 1.25 MSPS,
fi = 100 kHz,
TA = 255C
61.9
61.8
61.7
61.6
61.5
61.4
61.3
61.2
61.1
61
2.35
1000
3.075
3.8
4.525
VDD − Supply Voltage − V
5.25
Figure 7.
Figure 8.
Figure 9.
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
TOTAL HARMONIC DISTORTION
vs
SUPPLY VOLTAGE
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY
85
−80
THD − Total Harmonic Distortion − dB
−81
−82
−83
−84
−85
−86
−87
−88
−89
fs = 1.25 MSPS,
fi = 100 kHz,
TA = 255C
SFDR − Spurious Free Dynamic Range − dB
fs = 1.25 MSPS,
TA = 255C,
VDD = 5 V
−82
−83
−84
−85
−86
−87
−88
−89
−90
−90
1
50
Figure 6.
10
−81
0
Figure 5.
20
−80
25
Figure 4.
30
Leakage Current − nA
I DD − Supply Current − mA
255C
VDD = 5 V,
fSCLK = 25 MHz,
TA = 255C,
Power Down SCLK = Free Running
1.2
5 V VDD
I DD − Supply Current − mA
I DD − Supply Current − mA
1.60
1.6
1.5
1.4
TA = 255C
fs = 1.25 MSPS,
fSCLK = 25 MHz
1.7
THD − Total Harmonic Distortion − dB
SUPPLY CURRENT
vs
SAMPLE RATE
10
fi − Input Frequency − kHz
100
Figure 10.
2.35
3.075
3.8
4.525
VDD − Supply Voltage − V
Figure 11.
5.25
fs = 1.25 MSPS,
TA = 255C,
VDD = 5 V
84.5
84
83.5
83
82.5
82
81.5
81
80.5
80
1
10
Figure 12.
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fi − Input Frequency − kHz
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TYPICAL CHARACTERISTICS (continued)
SPURIOUS FREE DYNAMIC RANGE
vs
SUPPLY VOLTAGE
OFFSET ERROR
vs
SUPPLY VOLTAGE
1
1
fs = 1.25 MSPS,
fi = 100 kHz,
TA = 255C
84.5
0.8
fs = 1.25 MSPS,
TA = 255C
0.8
0.6
83.5
83
82.5
82
81.5
0.4
0.2
0
−0.2
−0.4
81
−0.6
80.5
−0.8
80
2.35
3.8
3.075
4.525
VDD − Supply Voltage − V
5.25
−1
2.35
−0.4
−1
−40
5.25
−20
0
20
40
60
80
100 120
TA − Free-Air Temperature − °C
Figure 15.
GAIN ERROR
vs
FREE-AIR TEMPERATURE
1
fs = 1.25 MSPS,
TA = 255C
0.8
0.6
fs = 1.25 MSPS,
VDD = 5 V
0.6
E G − Gain Error − LSBs
E G − Gain Error − LSBs
0
−0.2
Figure 14.
1
8
0.2
−0.8
3.075
3.8
4.525
VDD − Supply Voltage − V
GAIN ERROR
vs
SUPPLY VOLTAGE
0.4
0.2
0
−0.2
−0.4
0.4
0.2
0
−0.2
−0.4
−0.6
−0.6
−0.8
−0.8
−1
2.35
0.4
−0.6
Figure 13.
0.8
fs = 1.25 MSPS,
VDD = 5 V
0.6
E O − Offset Error − LSBs
84
E O − Offset Error − LSBs
SFDR − Spurious Free Dynamic Range − dB
85
OFFSET ERROR
vs
FREE-AIR TEMPERATURE
3.075
3.8
4.525
VDD − Supply Voltage − V
Figure 16.
5.25
−1
−40 −20
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0
20
40
60
80
100
120
TA − Free-Air Temperature − °C
Figure 17.
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TYPICAL CHARACTERISTICS (continued)
DNL
DNL − LSBs
0.5
0.4
0.3
VDD = 2.35 V,
fs = 1.25 MSPS,
TA = 255C
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
−0.5
0
256
512
768
1024
768
1024
Output Code
Figure 18.
INL − LSBs
INL
0.5
0.4
0.3
0.2
0.1
VDD = 2.35 V,
fs = 1.25 MSPS,
TA = 255C
0
−0.1
−0.2
−0.3
−0.4
−0.5
0
256
512
Output Code
Figure 19.
FFT
0
VDD = 2.35 V,
fs = 1.25 MSPS,
TA = 255C
fi = 100 kHz,
8192 Points
Amplitude − dB
−20
−40
−60
−80
−100
−120
−140
0
125000
250000
375000
fi − Input Frequency − kHz
500000
625000
Figure 20.
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APPLICATION INFORMATION
VDD
20 W
60 W
IN
16 pF
60 W
5 pF
GND
Figure 21. Typical Equivalent Sampling Circuit
Driving the VIN and VDD Pins
The VIN input to the ADS7887 should be driven with a low-impedance source. In most cases, additional buffers
are not required. In cases where the source impedance exceeds 200 Ω, using a buffer helps achieve the rated
performance of the converter. The THS4031 is a good choice for the driver amplifier buffer.
The reference voltage for the ADS7887 A/D converter is derived internally from the supply voltage. The device
offer limited low-pass filtering functionality on-chip. The supply to the converter should be driven with a
low-impedance source and should be decoupled to ground. A 1-µF storage capacitor and a 10-nF decoupling
capacitor should be placed close to the device. Wide low-impedance traces should be used to connect the
capacitor to the pins of the device. The ADS7887 draws very little current from the supply lines. The supply line
can be driven:
• Directly from the system supply.
• From a reference output from a low-drift and low-dropout reference voltage generator like REF3030 or
REF3130. The ADS7887 can operate off a wide range of supply voltages. The actual choice of the reference
voltage generator depends upon the system. Figure 23 shows one possible application circuit.
• A low-pass filtered version of the system supply followed by a buffer such as the zero-drift OPA735 can also
be used in cases where the system power supply is noisy. Care should be taken to ensure that the voltage at
the VDD input does not exceed 7 V (especially during power up) to avoid damage to the converter. This can
be done easily using single supply CMOS amplifiers like the OPA735. Figure 24 shows one possible
application circuit.
VDD
1 mF
VDD
CS
VIN
SDO
GND
SCLK
10 nF
Figure 22. Supply/Reference Decoupling Capacitors
5V
REF3030
IN
1 mF
3V
OUT
VDD
CS
VIN
SDO
GND
SCLK
GND
1 mF
10 nF
Figure 23. Using the REF3030 Reference
10
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5V
C1
R1
10 W
7V
_
R2
VDD
CS
VIN
SDO
GND
SCLK
+
1 mF
1 mF
10 nF
Figure 24. Buffering with the OPA735
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PACKAGE OPTION ADDENDUM
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30-Jan-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
ADS7887MDBVT
NRND
Package Type Package Pins Package
Drawing
Qty
SOT-23
DBV
6
250
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Pb-Free (RoHS
Exempt)
CU SN
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-55 to 125
BCNM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
