ADS7945
ADS7946
SBAS539B – JUNE 2011 – REVISED SEPTEMBER 2011
www.ti.com
14-Bit, 2 MSPS, Dual-Channel, Differential/Single-Ended,
Ultralow-Power Analog-to-Digital Converters
Check for Samples: ADS7945, ADS7946
FEATURES
DESCRIPTION
•
•
The ADS7945/6 are 14-bit, 2 MSPS analog-to-digital
converters (ADCs), with differential and single-ended
inputs, respectively. The devices operate at a 2
MSPS sample rate with a standard 16-clock data
frame. The devices feature both outstanding dc
precision and excellent dynamic performance; the
ADS7946 is pin-compatible with the 8/10/12-bit
ADS7947/8/9 devices. The devices include a
two-channel input multiplexer and a low-power
successive approximation register (SAR) ADC with
an inherent sample-and-hold (S/H) input stage.
1
23
•
•
•
•
•
•
Sample Rate: 2 MSPS
14-Bit, Pin-Compatible with 8/10/12-bit
ADS7947/8/9 Family (ADS7946)
Outstanding Performance:
– SNR: 84 dB (ADS7945)
– No Missing Codes
– INL: 1.5 LSB (max) (ADS7945)
Low Power:
– 11.6 mW at 2 MSPS Operation
– Auto Power-Down at Lower Speeds:
– 7.2 mW at 500 kSPS
– 1.4 mW at 100 kSPS
– 0.3 mW at 20 kSPS
Wide Supply Range:
– Analog: 2.7 V to 5.25 V
– Digital: 1.65 V to AVDD
Simple Serial Interface (SPI)
Fully Specified from –40°C to +125°C
Tiny Footprint: 3 mm × 3 mm QFN
The ADS7945/6 support a wide analog supply range
that allows the full-scale input range to extend to ±5 V
differential or 5 V single-ended. A simple SPI™, with
a digital supply that can operate as low as 1.65 V,
allows for easy interfacing to a wide variety of digital
controllers. Automatic power-down can be enabled
when operating at slower speeds to dramatically
reduce power consumption.
Offered in a tiny 3 mm × 3 mm QFN package, the
ADS7945/6 are fully specified over the extended
temperature range of –40°C to +125°C and are
suitable for a wide variety of data acquisition
applications where high performance, low power, and
small package size are key.
APPLICATIONS
•
•
•
•
Optical Networking
Medical Instrumentation
Battery-Powered Equipment
Data Acquisition Systems
AVDD
REF
REFGND
DVDD
ADS7945
AIN0P
AIN0N
AVDD
PDEN
CS
MUX
S/H
SAR
ADC
SPI
AIN1P
CH SEL
GND
REFGND
DVDD
ADS7946
AIN0
AIN0GND
PDEN
CS
MUX
SCLK
SDO
AIN1N
REF
S/H
SAR
ADC
SPI
SCLK
SDO
AIN1GND
AIN1
CH SEL
GND
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI is a trademark of Motorola.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
ADS7945
ADS7946
SBAS539B – JUNE 2011 – REVISED SEPTEMBER 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FAMILY AND ORDERING INFORMATION (1)
(1)
PRODUCT
RESOLUTION (Bits)
INPUT
ADS7945
14
Unipolar, differential
ADS7946
14
Unipolar, single-ended
ADS7947
12
Unipolar, single-ended
ADS7948
10
Unipolar, single-ended
ADS7949
8
Unipolar, single-ended
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
VALUE
UNIT
AINxP to GND or AINxN to GND (ADS7945)
–0.3 to AVDD + 0.3
V
AINx to GND (ADS7946)
–0.3 to AVDD + 0.3
V
–0.3 to +0.3
V
–0.3 to 7
V
Digital input voltage to GND
–0.3 to DVDD + 0.3
V
Digital output to GND
–0.3 to DVDD + 0.3
V
Operating temperature range
–40 to +125
°C
Storage temperature range
AINxGND to GND (ADS7946)
AVDD to GND or DVDD to GND
ESD ratings
(1)
2
–65 to +150
°C
Human body model (HBM)
2000
V
Charged device model (CDM)
500
V
Machine model (MM)
200
V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under electrical characteristics is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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ADS7946
SBAS539B – JUNE 2011 – REVISED SEPTEMBER 2011
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ELECTRICAL CHARACTERISTICS: ADS7945 (Differential)
Minimum/maximum specifications at TA = –40°C to +125°C, AVDD = 2.7 V to 5.25 V, DVDD = 1.65 V to AVDD, input
common-mode = VREF/2 ± 0.2, and fSAMPLE = 2 MSPS, unless otherwise noted.
Typical specifications at TA = +25°C, AVDD = 5 V, DVDD = 1.8 V, input common-mode = VREF/2 ± 0.2, and fSAMPLE = 2 MSPS.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
–VREF
VREF
V
AIN0P, AIN1P
–0.2
AVDD + 0.2
V
AIN0N, AIN1N
–0.2
AVDD + 0.2
V
ANALOG INPUT
Full-scale input span (1)
Absolute input range
Input common-mode range (2)
Input capacitance
AINxP – AINxN
(AINxP + AINxN)/2
VREF/2 ± 0.2
(3)
Input leakage current
At +125°C
V
32
pF
1.5
nA
14
Bits
SYSTEM PERFORMANCE
Resolution
No missing codes
14
Integral linearity
Differential linearity
Offset error
(5)
Gain error
Bits
–1.5
±0.8
1.5
LSB (4)
–1
±0.8
1.5
LSB
–4
±1.5
4
LSB
–4
±1.5
4
LSB
25
µVRMS
Transition noise
Power-supply rejection
With 500 Hz sine wave on AVDD
60
dB
SAMPLING DYNAMICS
Conversion time
16
Acquisition time
Maximum sample rate (throughput rate)
ns
40 MHz SCLK with a 16-clock frame
Aperture delay (6)
Aperture jitter (6)
Step response
SCLK
80
(6) (3)
2
MSPS
10
ns
10
ps
80
ns
–92
dB
84
dB
83
dB
DYNAMIC CHARACTERISTICS
Total harmonic distortion (THD) (7)
Signal-to-noise ratio (SNR)
20 kHz, VREF = 4.0 V
20 kHz, VREF = 4.0 V
100 kHz, VREF = 4.0 V
82
Signal-to-noise and distorion ratio (SINAD)
20 kHz, VREF = 4.0 V
83.5
dB
Spurious-free dynamic range (SFDR)
20 kHz, VREF = 4.0 V
94
dB
At –3 dB
15
MHz
Full-power bandwidth
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(8)
Ideal input span; does not include gain or offset error.
Refer to the Input Common-Mode Range section in Application Information.
Refer to Figure 76 for sampling circuit details.
LSB means least significant bit.
Measured relative to an ideal full-scale input.
Ensured by simulation.
Calculated on the first nine harmonics of the input frequency.
Indicates signal bandwidth for undersampling applications.
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ELECTRICAL CHARACTERISTICS: ADS7945 (Differential) (continued)
Minimum/maximum specifications at TA = –40°C to +125°C, AVDD = 2.7 V to 5.25 V, DVDD = 1.65 V to AVDD, input
common-mode = VREF/2 ± 0.2, and fSAMPLE = 2 MSPS, unless otherwise noted.
Typical specifications at TA = +25°C, AVDD = 5 V, DVDD = 1.8 V, input common-mode = VREF/2 ± 0.2, and fSAMPLE = 2 MSPS.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUT/OUTPUT
Logic family
CMOS
VIH
Logic level
Input leakage current
0.7DVDD
V
VIL
0.3DVDD
VOH
SDO load 20 pF
VOL
SDO load 20 pF
IIH, IIL
0 < VIN < DVDD
External reference
0.8DVDD
V
V
0.2DVDD
±20
2.5
V
nA
AVDD
V
V
POWER-SUPPLY REQUIREMENTS
AVDD
2.7
3.3
5.25
DVDD
1.65
3.3
AVDD
3.5
4
mA
4
5
mA
IDYNAMIC
AVDD supply current
ISTATIC
DVDD supply current (9)
Power-down state
AVDD supply current
AVDD = 3.3 V, fSAMPLE = 2 MSPS
AVDD = 5 V, fSAMPLE = 2 MSPS
AVDD = 3.3 V, SCLK off
2.3
AVDD = 5 V, SCLK off
2.5
DVDD = 3.3 V, fSAMPLE = 2 MSPS,
SDO load 20 pF
750
V
mA
3
mA
µA
IPD-DYNAMIC
SCLK = 40 MHz
550
µA
IPD-STATIC
SCLK off
2.5
µA
1
µs
+125
°C
Power-up time
From power-down state using PDEN pin
TEMPERATURE RANGE
–40
Specified performance
(9)
4
DVDD consumes only dynamic current. IDVDD = CLOAD × DVDD × number of 0→1 transitions in SDO × fSAMPLE.
This is a load-dependent current and there is no DVDD current when the output is not toggling.
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ADS7946
SBAS539B – JUNE 2011 – REVISED SEPTEMBER 2011
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ELECTRICAL CHARACTERISTICS: ADS7946 (Single-Ended)
Minimum/maximum specifications at TA = –40°C to +125°C, AVDD = 2.7 V to 5.25 V, DVDD = 1.65 V to AVDD,
and fSAMPLE = 2 MSPS, unless otherwise noted.
Typical specifications at TA = +25°C, AVDD = 5 V, DVDD = 1.8 V, and fSAMPLE = 2 MSPS.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
0
VREF
V
AIN0, AIN1
–0.2
AVDD + 0.2
V
AIN0GND, AIN1GND
–0.2
0.2
ANALOG INPUT
Full-scale input span (1)
AINx – AINxGND
Absolute input range
Input capacitance (2)
Input leakage current
At +125°C
V
32
pF
1.5
nA
14
Bits
SYSTEM PERFORMANCE
Resolution
No missing codes
14
Bits
–2.5
±1.25
2.5
LSB (3)
Differential linearity
–1
±0.8
2.0
LSB
Offset error (4)
–4
±1.5
4
LSB
Gain error
–4
±1.5
Integral linearity
Transition noise
Power-supply rejection
With 500 Hz sine wave on AVDD
4
LSB
25
µVRMS
60
dB
SAMPLING DYNAMICS
Conversion time
Acquisition time
16
SCLK
2
MSPS
10
ns
80
Maximum sample rate (throughput rate)
ns
40 MHz SCLK with a 16-clock frame
Aperture delay (5)
Aperture jitter (5)
10
ps
Step response (5) (2)
80
ns
–85
dB
82
dB
DYNAMIC CHARACTERISTICS
Total harmonic distortion (THD) (6)
Signal-to-noise ratio (SNR)
20 kHz, VREF = 4.0 V
20 kHz, VREF = 4.0 V
79
80
dB
Signal-to-noise and distortion ratio (SINAD)
100 kHz, VREF = 4.0 V
20 kHz, VREF = 4.0 V
78.8
dB
Spurious-free dynamic range (SFDR)
20 kHz, VREF = 4.0 V
86
dB
Full-power bandwidth (7)
At –3 dB
15
MHz
DIGITAL INPUT/OUTPUT
Logic family
CMOS
VIH
Logic level
Input leakage current
0.7DVDD
VIL
0.3DVDD
VOH
SDO load 20 pF
VOL
SDO load 20 pF
IIH, IIL
0 < VIN < DVDD
External reference
(1)
(2)
(3)
(4)
(5)
(6)
(7)
V
0.8DVDD
V
0.2DVDD
±20
2.5
V
V
nA
AVDD
V
Ideal input span; does not include gain or offset error.
Refer to Figure 76 for sampling circuit details.
LSB means least significant bit.
Measured relative to an ideal full-scale input.
Ensured by simulation.
Calculated on the first nine harmonics of the input frequency.
Indicates signal bandwidth for undersampling applications.
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ELECTRICAL CHARACTERISTICS: ADS7946 (Single-Ended) (continued)
Minimum/maximum specifications at TA = –40°C to +125°C, AVDD = 2.7 V to 5.25 V, DVDD = 1.65 V to AVDD,
and fSAMPLE = 2 MSPS, unless otherwise noted.
Typical specifications at TA = +25°C, AVDD = 5 V, DVDD = 1.8 V, and fSAMPLE = 2 MSPS.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
2.7
3.3
5.25
V
1.65
3.3
AVDD
3.5
4
mA
4
5
mA
POWER-SUPPLY REQUIREMENTS
AVDD
DVDD
AVDD = 3.3 V, fSAMPLE = 2 MSPS
IDYNAMIC
AVDD = 5 V, fSAMPLE = 2 MSPS
AVDD supply current
ISTATIC
DVDD supply current
(8)
Power-down state
AVDD supply current
AVDD = 3.3 V, SCLK off
2.3
AVDD = 5 V, SCLK off
2.5
DVDD = 3.3 V, fSAMPLE = 2 MSPS,
SDO load 20 pF
750
V
mA
3
mA
µA
IPD-DYNAMIC
SCLK = 40 MHz
550
µA
IPD-STATIC
SCLK off
2.5
µA
1
µs
+125
°C
Power-up time
From power-down state using PDEN pin
TEMPERATURE RANGE
–40
Specified performance
(8)
DVDD consumes only dynamic current. IDVDD = CLOAD × DVDD × number of 0→1 transitions in SDO × fSAMPLE.
This is a load-dependent current and there is no DVDD current when the output is not toggling.
THERMAL INFORMATION
ADS7945/6
THERMAL METRIC (1)
RTE
UNITS
16 PINS
θJA
Junction-to-ambient thermal resistance
54.3
θJCtop
Junction-to-case (top) thermal resistance
53.7
θJB
Junction-to-board thermal resistance
19.2
ψJT
Junction-to-top characterization parameter
0.3
ψJB
Junction-to-board characterization parameter
14.5
θJCbot
Junction-to-case (bottom) thermal resistance
5.2
(1)
6
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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PARAMETER MEASUREMENT INFORMATION
TIMING DIAGRAM: ADS7945, ADS7946
Sample
N
Sample
N+1
1/fSAMPLE
tACQ
tCONV
CS
tSU1
1
SCLK
tWH
2
3
4
tD1
D13
SDO
tWL
5
6
7
tH1
D12
D11
8
9
10
tW1
tD4
11
12
13
15
14
16
tD3
tD2
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Data from Sample N - 1
Table 1. TIMING REQUIREMENTS: ADS7945, ADS7946 (1) (2)
TEST CONDITIONS (2)
PARAMETER
tCONV
Conversion time
tACQ
Acquisition time
fSAMPLE
Sample rate (throughput rate)
tW1
Pulse width CS high
tD1
tH1
Delay time, SCLK falling to SDO
Hold time, SCLK falling to data valid
MSPS
Delay time, CS high to SDO 3-state
ns
ns
DVDD = 3 V
12.5
ns
DVDD = 5 V
8.5
ns
DVDD = 1.8 V
3.5
ns
DVDD = 3 V
3.5
ns
DVDD = 5 V
3.5
ns
11
ns
DVDD = 3 V
9
ns
DVDD = 5 V
7.1
ns
DVDD = 1.8 V
4
ns
DVDD = 3 V
3
ns
DVDD = 5 V
2
ns
15
ns
DVDD = 3 V
12.5
ns
DVDD = 5 V
8.5
ns
tD4
tWH
Pulse duration, SCLK high
8
tWL
Pulse duration, SCLK low
8
10
SCLK frequency
ns
ns
ns
40
tPDSU
Setup time, PDEN high to CS rising edge
(refer to Figure 84 and Figure 85)
tPDH
Hold time, CS rising edge to PDEN falling edge (refer to Figure 84)
(3)
ns
14.5
Delay time CS rising edge from conversion end
(refer to the tCONV specification for conversion time)
(1)
(2)
SCLK
DVDD = 1.8 V
DVDD = 1.8 V
tD3
UNIT
16
2
DVDD = 1.8 V
tD2
MAX
25
Setup time, CS low to first rising edge of SCLK
(3)
TYP
80
SCLK = 40 MHz,
16-clock frame
Delay time, CS low to first data (D0-15) out
tSU1
MIN
MHz
2
20
ns
ns
All specifications are ensured by simulations at TA = –40°C to +125°C, and DVDD = 1.65 V to AVDD, unless otherwise noted.
1.8 V specifications apply from 1.65 V to 2 V; 3 V specifications apply form 2.7 V to 3.6 V; 5 V specifications apply from 4.75 V to
5.25 V.
With 20 pF load.
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PIN CONFIGURATION ADS7945 (DIFFERENTIAL)
GND
1
AVDD
2
DVDD
SDO
SCLK
CS
16
15
14
13
RTE PACKAGE
QFN-16
(TOP VIEW)
12
PDEN
11
CH SEL
ADS7945
8
NC
AIN1P
9
7
4
AIN1N
REFGND
6
NC
AIN0N
10
5
3
AIN0P
REF
Table 2. PIN FUNCTIONS
8
PIN
NO.
PIN NAME
FUNCTION
1
GND
Analog/digital
2
AVDD
Analog
ADC power supply
3
REF
Analog
ADC positive reference input; decouple this pin with REFGND
4
REFGND
Analog
Reference return; short to analog ground plane
5
AIN0P
Analog input
Positive analog input, channel 0
6
AIN0N
Analog input
Negative analog input, channel 0
7
AIN1N
Analog input
Negative analog input, channel 1
8
AIN1P
Analog input
Positive analog input, channel 1
9
NC
—
Not connected internally, it is recommended to externally short this pin to GND
10
NC
—
Not connected internally, it is recommended to externally short this pin to GND
DESCRIPTION
Power supply ground; all analog and digital signals are referred with respect to this pin
11
CH SEL
Digital input
This pin selects the analog input channel.
Low = Channel 0
High = Channel 1
It is recommended to change the channel within a window of one clock; from half a clock after the CS
falling edge. This change ensures the settling on the multiplexer output before the sample start.
12
PDEN
Digital input
This pin enables a power-down feature if it is high at the CS rising edge
13
CS
Digital input
Chip select signal; active low
14
SCLK
Digital input
Serial SPI clock
15
SDO
Digital output
Serial data out
16
DVDD
Digital
Digital I/O supply
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PIN CONFIGURATION ADS7946 (SINGLE-ENDED)
GND
1
AVDD
2
DVDD
SDO
SCLK
CS
16
15
14
13
RTE PACKAGE
QFN-16
(TOP VIEW)
12
PDEN
11
CH SEL
ADS7946
8
NC
AIN1
9
7
4
AIN1GND
REFGND
6
NC
AIN0GND
10
5
3
AIN0
REF
Table 3. PIN FUNCTIONS
PIN
NO.
PIN NAME
FUNCTION
1
GND
Analog/digital
2
AVDD
Analog
ADC power supply
3
REF
Analog
ADC positive reference input; decouple this pin with REFGND
4
REFGND
Analog
Reference return; short to analog ground plane
5
AIN0
Analog input
Positive analog input, channel 0
6
AIN0GND
Analog input
Ground sense analog input, channel 0
7
AIN1GND
Analog input
Ground sense analog input, channel 1
8
AIN1
Analog input
Positive analog input, channel 1
9
NC
—
Not connected internally, it is recommended to externally short this pin to GND
10
NC
—
Not connected internally, it is recommended to externally short this pin to GND
DESCRIPTION
Power supply ground; all analog and digital signals are referred with respect to this pin
11
CH SEL
Digital input
This pin selects the analog input channel.
Low = Channel 0
High = Channel 1
It is recommended to change the channel within a window of one clock; from half a clock after the CS
falling edge. This change ensures the settling on the multiplexer output before the sample start.
12
PDEN
Digital input
This pin enables a power-down feature if it is high at the CS rising edge
13
CS
Digital input
Chip select signal; active low
14
SCLK
Digital input
Serial SPI clock
15
SDO
Digital output
Serial data out
16
DVDD
Digital
Digital I/O supply
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TYPICAL CHARACTERISTICS: ADS7945
At TA = +25°C, AVDD = 5 V, DVDD = 1.8 V, VREF = 2.5 V, and fSAMPLE = 2 MSPS, unless otherwise noted.
DNL vs ANALOG SUPPLY VOLTAGE
DNL vs REFERENCE VOLTAGE
1.5
1
Differential Nonlinearity (LSB)
Differential Nonlinearity (LSB)
1.5
Maximum DNL
0.5
0
Minimum DNL
−0.5
1
Maximum DNL
0.5
0
Minimum DNL
−0.5
AVDD = 5.25 V
−1
2.7
3.2
3.7
4.2
4.7
5.2
AVDD, Analog Supply Voltage (V)
−1
2.5
5.7
3
G006
Figure 1.
DNL vs FREE-AIR TEMPERATURE
1
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
G010
INL vs ANALOG SUPPLY VOLTAGE
Maximum DNL
0.5
0
Minimum DNL
−0.5
5
20 35 50 65 80
Free-Air Temperature (°C)
95
1
0.5
0
Minimum INL
−0.5
−1
−1.5
2.7
110 125
Maximum INL
3.2
G008
Figure 3.
3.7
4.2
4.7
5.2
AVDD, Analog Supply Voltage (V)
5.7
G007
Figure 4.
INL vs REFERENCE VOLTAGE
INL vs FREE-AIR TEMPERATURE
1.5
1.5
1
Integral Nonlinearity (LSB)
Integral Nonlinearity (LSB)
5.5
1.5
−1
−40 −25 −10
Maximum INL
0.5
0
Minimum INL
−0.5
−1
AVDD = 5.25 V
3
3.5
4
4.5
Reference Voltage (V)
5
5.5
1
Maximum INL
0.5
0
Minimum INL
−0.5
−1
−1.5
−40 −25 −10
G011
Figure 5.
10
5
Figure 2.
1.5
−1.5
2.5
3.5
4
4.5
Reference Voltage (V)
5
20 35 50 65 80
Free-Air Temperature (°C)
95
110 125
G009
Figure 6.
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TYPICAL CHARACTERISTICS: ADS7945 (continued)
At TA = +25°C, AVDD = 5 V, DVDD = 1.8 V, VREF = 2.5 V, and fSAMPLE = 2 MSPS, unless otherwise noted.
OFFSET ERROR vs REFERENCE VOLTAGE
4
3
3
2
2
Offset Error (LSB)
Offset Error (LSB)
OFFSET ERROR vs ANALOG SUPPLY VOLTAGE
4
1
0
−1
1
0
−1
−2
−2
−3
−3
AVDD = 5.25 V
−4
2.7
3.2
3.7
4.2
4.7
5.2
AVDD, Analog Supply Voltage (V)
−4
2.5
5.7
3
G012
Figure 7.
5
5.5
G014
Figure 8.
OFFSET ERROR vs FREE-AIR TEMPERATURE
GAIN ERROR vs ANALOG SUPPLY VOLTAGE
4
6
3
4
2
Gain Error (LSB)
Offset Error (LSB)
3.5
4
4.5
Reference Voltage (V)
1
0
−1
2
0
−2
−2
−4
−3
−4
−40 −25 −10
5
20 35 50 65 80
Free-Air Temperature (°C)
95
−6
2.7
110 125
3.2
G013
Figure 9.
5.7
G015
Figure 10.
GAIN ERROR vs REFERENCE VOLTAGE
GAIN ERROR vs FREE-AIR TEMPERATURE
6
6
4
4
Gain Error (LSB)
Gain Error (LSB)
3.7
4.2
4.7
5.2
AVDD, Analog Supply Voltage (V)
2
0
−2
−4
2
0
−2
−4
AVDD = 5.25 V
−6
2.5
3
3.5
4
4.5
Reference Voltage (V)
5
5.5
−6
−40 −25 −10
G017
Figure 11.
5
20 35 50 65 80
Free-Air Temperature (°C)
95
110 125
G016
Figure 12.
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TYPICAL CHARACTERISTICS: ADS7945 (continued)
At TA = +25°C, AVDD = 5 V, DVDD = 1.8 V, VREF = 2.5 V, and fSAMPLE = 2 MSPS, unless otherwise noted.
SNR vs ANALOG SUPPLY VOLTAGE
SNR vs REFERENCE VOLTAGE
85
Signal−to−Noise Ratio (dB)
Signal−to−Noise Ratio (dB)
85
83
81
79
77
83
81
79
77
AVDD = 5.25 V
fIN = 20 kHz
fIN = 20 kHz
75
2.7
3.2
3.7
4.2
4.7
5.2
AVDD, Analog Supply Voltage (V)
75
2.5
5.7
3
3.5
4
4.5
Reference Voltage (V)
G018
Figure 13.
5.5
G020
Figure 14.
SNR vs FREE-AIR TEMPERATURE
SNR vs INPUT FREQUENCY
85
Signal−to−Noise Ratio (dB)
85
Signal−to−Noise Ratio (dB)
5
83
81
79
77
83
81
79
77
fIN = 20 kHz
75
−40 −25 −10
5
20 35 50 65 80
Free-Air Temperature (°C)
95
75
110 125
0
20
G019
Figure 15.
SINAD vs ANALOG SUPPLY VOLTAGE
G021
SINAD vs REFERENCE VOLTAGE
Signal−to−Noise and Distortion (dB)
Signal−to−Noise and Distortion (dB)
100
85
83
81
79
77
fIN = 20 kHz
3.2
3.7
4.2
4.7
5.2
AVDD, Analog Supply Voltage (V)
5.7
83
81
79
77
AVDD = 5.25 V
fIN = 20 kHz
75
2.5
G022
Figure 17.
12
80
Figure 16.
85
75
2.7
40
60
fIN, Input Frequency (kHz)
3
3.5
4
4.5
Reference Voltage (V)
5
5.5
G024
Figure 18.
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TYPICAL CHARACTERISTICS: ADS7945 (continued)
At TA = +25°C, AVDD = 5 V, DVDD = 1.8 V, VREF = 2.5 V, and fSAMPLE = 2 MSPS, unless otherwise noted.
SINAD vs FREE-AIR TEMPERATURE
SINAD vs INPUT FREQUENCY
85
Signal−to−Noise and Distortion (dB)
Signal−to−Noise and Distortion (dB)
85
83
81
79
77
fIN = 20 kHz
75
−40 −25 −10
5
20 35 50 65 80
Free-Air Temperature (°C)
95
83
81
79
77
75
110 125
0
20
G023
Figure 19.
THD vs ANALOG SUPPLY VOLTAGE
G025
THD vs REFERENCE VOLTAGE
Total Harmonic Distortion (dB)
−88
−92
−96
−84
−88
−92
−96
AVDD = 5.25 V
fIN = 20 kHz
fIN = 20 kHz
3.2
3.7
4.2
4.7
5.2
AVDD,Analog Supply Voltage (V)
−100
2.5
5.7
3
3.5
4
4.5
Reference Voltage (V)
G030
Figure 21.
THD vs FREE-AIR TEMPERATURE
5.5
G032
THD vs INPUT FREQUENCY
Total Harmonic Distortion (dB)
−80
−84
−88
−92
−96
AVDD = 3 V
fIN = 20 kHz
−100
−40 −25 −10
5
Figure 22.
−80
Total Harmonic Distortion (dB)
100
−80
−84
−100
2.7
80
Figure 20.
−80
Total Harmonic Distortion (dB)
40
60
fIN, Input Frequency (kHz)
5
20 35 50 65 80
Free-Air Temperature (°C)
95
−84
−88
−92
−96
AVDD = 3 V
110 125
−100
0
G031
Figure 23.
20
40
60
fIN, Input Frequency (kHz)
80
100
G033
Figure 24.
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TYPICAL CHARACTERISTICS: ADS7945 (continued)
At TA = +25°C, AVDD = 5 V, DVDD = 1.8 V, VREF = 2.5 V, and fSAMPLE = 2 MSPS, unless otherwise noted.
SFDR vs ANALOG SUPPLY VOLTAGE
SFDR vs REFERENCE VOLTAGE
100
Spurious Free Dynamic Range (dB)
Spurious Free Dynamic Range (dB)
100
96
92
88
84
fIN = 20 kHz
80
2.7
3.2
3.7
4.2
4.7
5.2
AVDD, Analog Supply Voltage (V)
96
92
88
84
AVDD = 5.25 V
fIN = 20 kHz
80
2.5
5.7
3
3.5
4
4.5
Reference Voltage (V)
G026
Figure 25.
SFDR vs FREE-AIR TEMPERATURE
SFDR vs INPUT FREQUENCY
Spurious Free Dynamic Range (dB)
Spurious Free Dynamic Range (dB)
96
92
88
84
AVDD = 3 V
fIN = 20 kHz
5
20 35 50 65 80
Free-Air Temperature (°C)
95
96
92
88
84
AVDD = 3 V
80
110 125
0
20
G027
40
60
fIN, Input Frequency (kHz)
80
Figure 27.
Figure 28.
CROSSTALK vs INPUT FREQUENCY
ANALOG SUPPLY CURRENT (Dynamic)
vs ANALOG SUPPLY VOLTAGE
−80
100
G029
5
−90
AVDD Dynamic Current (mA)
−85
Crosstalk (dB)
G028
100
80
−40 −25 −10
Memory CrossTalk
−95
−100
−105
Isolation Crosstalk
−110
−115
0
20
40
60
fIN, Input Frequency (kHz)
80
100
4.5
4
3.5
3
2.5
2.7
3.2
G034
Figure 29.
14
5.5
Figure 26.
100
−120
5
3.7
4.2
4.7
5.2
AVDD, Analog Supply Voltage (V)
5.7
G001
Figure 30.
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TYPICAL CHARACTERISTICS: ADS7945 (continued)
At TA = +25°C, AVDD = 5 V, DVDD = 1.8 V, VREF = 2.5 V, and fSAMPLE = 2 MSPS, unless otherwise noted.
ANALOG SUPPLY CURRENT (Dynamic)
vs FREE-AIR TEMPERATURE
ANALOG SUPPLY CURRENT (Dynamic)
vs SAMPLE RATE
4
AVDD Supply Current (mA)
AVDD Dynamic Current (mA)
5
4.5
4
3.5
3
3
2.5
AVDD = 5 V
2
1.5
1
AVDD = 3 V
0.5
2.5
−40 −25 −10
5
20 35 50 65 80
Free-Air Temperature (°C)
95
0
110 125
0
100
200
G002
700
G005
ANALOG SUPPLY CURRENT (Static)
vs ANALOG SUPPLY VOLTAGE
ANALOG SUPPLY CURRENT (Static)
vs FREE-AIR TEMPERATURE
AVDD Static Current (mA)
3
2
1.5
1
2.7
3.2
3.7
4.2
4.7
5.2
AVDD, Analog Supply Voltage (V)
2.5
2
1.5
1
−40 −25 −10
5.7
G003
5
20 35 50 65 80
Free-Air Temperature (°C)
Figure 33.
95
110 125
G004
Figure 34.
DNL
INL
1.5
Integral Nonlinearity (LSB)
1.5
Differential Nonlinearity (LSB)
600
Figure 32.
2.5
1
0.5
0
−0.5
−1
300
400
500
Throughput (kSPS)
Figure 31.
3
AVDD Static Current (mA)
3.5
0
2048
4096
6144 8192 10240 12288 14336 16384
ADC output Code (LSB)
G037
1
0.5
0
−0.5
−1
−1.5
0
2048
Figure 35.
4096
6144 8192 10240 12288 14336 16384
ADC Output Code (LSB)
G036
Figure 36.
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TYPICAL CHARACTERISTICS: ADS7945 (continued)
At TA = +25°C, AVDD = 5 V, DVDD = 1.8 V, VREF = 2.5 V, and fSAMPLE = 2 MSPS, unless otherwise noted.
SPECTRAL RESPONSE
0
−20
Amplitude (dB)
−40
−60
−80
−100
−120
−140
−160
0
250
500
750
fIN, Input Frequency (kHz)
1000
G034
Figure 37.
16
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TYPICAL CHARACTERISTICS: ADS7946
At TA = +25°C, AVDD = 5 V, DVDD = 1.8 V, VREF = 2.5 V, and fSAMPLE = 2 MSPS, unless otherwise noted.
DNL vs ANALOG SUPPLY VOLTAGE
DNL vs REFERENCE VOLTAGE
2
Differential Nonlinearity (LSB)
Differential Nonlinearity (LSB)
2
1.5
Maximum DNL
1
0.5
0
Minimum DNL
−0.5
1.5
1
Maximum DNL
0.5
0
Minimum DNL
−0.5
AVDD = 5.25 V
−1
2.7
3.2
3.7
4.2
4.7
5.2
AVDD, Analog Supply Voltage (V)
−1
2.5
5.7
3
G043
Figure 38.
3.5
4
4.5
Reference Voltage (V)
5
5.5
G047
Figure 39.
DNL vs FREE-AIR TEMPERATURE
INL vs ANALOG SUPPLY VOLTAGE
2
2.5
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
2
1.5
Maximum DNL
1
0.5
0
Minimum DNL
−0.5
Maximum INL
1.5
1
0.5
0
Minimum INL
−0.5
−1
−1.5
−2
−1
−40 −25 −10
5
20 35 50 65 80
Free-Air Temperature (°C)
95
−2.5
2.7
110 125
3.2
G045
Figure 40.
2
2
Maximum INL
1
0.5
Minimum INL
−0.5
−1
−1.5
AVDD = 5.25 V
−2
−2.5
2.5
3
G044
INL vs FREE-AIR TEMPERATURE
2.5
Integral Nonlinearity (LSB)
Integral Nonlinearity (LSB)
INL vs REFERENCE VOLTAGE
0
5.7
Figure 41.
2.5
1.5
3.7
4.2
4.7
5.2
AVDD, Analog Supply Voltage (V)
3.5
4
4.5
Reference Voltage (V)
5
1.5
Maximum INL
1
0.5
0
Minimum INL
−0.5
−1
−1.5
−2
5.5
−2.5
−40 −25 −10
G048
Figure 42.
5
20 35 50 65 80
Free-Air Temperature (°C)
95
110 125
G046
Figure 43.
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TYPICAL CHARACTERISTICS: ADS7946 (continued)
At TA = +25°C, AVDD = 5 V, DVDD = 1.8 V, VREF = 2.5 V, and fSAMPLE = 2 MSPS, unless otherwise noted.
OFFSET ERROR vs REFERENCE VOLTAGE
4
3
3
2
2
Offset Error (LSB)
Offset Error (LSB)
OFFSET ERROR vs ANALOG SUPPLY VOLTAGE
4
1
0
−1
1
0
−1
−2
−2
−3
−3
AVDD = 5.25 V
−4
2.7
3.2
3.7
4.2
4.7
5.2
AVDD, Analog Supply Voltage (V)
−4
2.5
5.7
3
G049
Figure 44.
5.5
G051
GAIN ERROR vs ANALOG SUPPLY VOLTAGE
4
3
3
2
2
Gain Error (LSB)
Offset Error (LSB)
OFFSET ERROR vs FREE-AIR TEMPERATURE
1
0
−1
1
0
−1
−2
−2
−3
−3
5
20 35 50 65 80
Free-Air Temperature (°C)
95
−4
2.7
110 125
3.2
G050
Figure 46.
3.7
4.2
4.7
5.2
AVDD, Analog Supply Voltage (V)
5.7
G052
Figure 47.
GAIN ERROR vs REFERENCE VOLTAGE
GAIN ERROR vs FREE-AIR TEMPERATURE
4
4
3
3
2
2
Gain Error (LSB)
Gain Error (LSB)
5
Figure 45.
4
−4
−40 −25 −10
3.5
4
4.5
Reference Voltage (V)
1
0
−1
−2
1
0
−1
−2
−3
−3
AVDD = 5.25 V
−4
2.5
3
3.5
4
4.5
Reference Voltage (V)
5
5.5
−4
−40 −25 −10
G054
Figure 48.
18
5
20 35 50 65 80
Free-Air Temperature (°C)
95
110 125
G053
Figure 49.
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TYPICAL CHARACTERISTICS: ADS7946 (continued)
At TA = +25°C, AVDD = 5 V, DVDD = 1.8 V, VREF = 2.5 V, and fSAMPLE = 2 MSPS, unless otherwise noted.
SNR vs ANALOG SUPPLY VOLTAGE
SNR vs REFERENCE VOLTAGE
85
Signal−To−Noise Ratio (dB)
Signal−to−Noise Ratio (dB)
85
83
81
79
77
83
81
79
77
AVDD = 5.25 V
fIN = 20 kHz
fIN = 20 kHz
75
2.7
3.2
3.7
4.2
4.7
5.2
AVDD, Analog Supply Voltage (V)
75
2.5
5.7
3
3.5
4
4.5
Reference Voltage (V)
G055
Figure 50.
5.5
G057
Figure 51.
SNR vs FREE-AIR TEMPERATURE
SNR vs INPUT FREQUENCY
85
Signal−To−Noise Ratio (dB)
85
Signal−to−Noise Ratio (dB)
5
83
81
79
77
83
81
79
77
fIN = 20 kHz
75
−40 −25 −10
5
20 35 50 65 80
Free-Air Temperature (°C)
95
75
110 125
0
20
G056
Figure 52.
SINAD vs ANALOG SUPPLY VOLTAGE
100
G058
SINAD vs REFERENCE VOLTAGE
85
Signal−to−Noise and Distortion (dB)
Signal−to−Noise and Distortion (dB)
80
Figure 53.
85
83
81
79
77
fIN = 20 kHz
75
2.7
40
60
fIN, Input Frequency (kHz)
3.2
3.7
4.2
4.7
5.2
AVDD, Analog Supply Voltage (V)
5.7
83
81
79
77
AVDD = 5.25 V
fIN = 20 kHz
75
2.5
G059
Figure 54.
3
3.5
4
4.5
Reference Voltage (V)
5
5.5
G061
Figure 55.
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TYPICAL CHARACTERISTICS: ADS7946 (continued)
At TA = +25°C, AVDD = 5 V, DVDD = 1.8 V, VREF = 2.5 V, and fSAMPLE = 2 MSPS, unless otherwise noted.
SINAD vs FREE-AIR TEMPERATURE
SINAD vs INPUT FREQUENCY
85
Signal−to−Noise and Distortion (dB)
Signal−to−noise and distortion (dB)
85
83
81
79
77
fIN = 20 kHz
75
−40 −25 −10
5
20 35 50 65 80
Free-Air Temperature (°C)
95
83
81
79
77
75
110 125
0
20
G060
Figure 56.
−82
−82
−84
−86
−88
−90
−92
−94
−96
−98
3.7
4.2
4.7
5.2
AVDD, Analog Supply Voltage (V)
−86
−88
−90
−92
−94
−96
AVDD = 5.25 V
fIN = 20 kHz
−100
2.5
5.7
3
3.5
4
4.5
Reference Voltage (V)
G067
Figure 58.
5.5
G069
THD vs INPUT FREQUENCY
−80
−80
−82
−82
Total Harmonic Distortion (dB)
Total Harmonic Distortion (dB)
5
Figure 59.
THD vs FREE-AIR TEMPERATURE
−84
−86
−88
−90
−92
−94
−96
AVDD = 3 V
fIN = 20 kHz
−98
5
20 35 50 65 80
Free-Air Temperature (°C)
95
−84
−86
−88
−90
−92
−94
−96
−98
110 125
−100
AVDD = 3 V
0
G068
Figure 60.
20
G062
−84
−98
fIN = 20 kHz
−100
−40 −25 −10
100
THD vs REFERENCE VOLTAGE
−80
Total Harmonic Distortion (dB)
Total Harmonic Distortion (dB)
THD vs ANALOG SUPPLY VOLTAGE
3.2
80
Figure 57.
−80
−100
2.7
40
60
fIN, Input Frequency (kHz)
20
40
60
fIN, Input Frequency (kHz)
80
100
G070
Figure 61.
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TYPICAL CHARACTERISTICS: ADS7946 (continued)
At TA = +25°C, AVDD = 5 V, DVDD = 1.8 V, VREF = 2.5 V, and fSAMPLE = 2 MSPS, unless otherwise noted.
SFDR vs ANALOG SUPPLY VOLTAGE
SFDR vs REFERENCE VOLTAGE
100
Spurious Free Dynamic Range (dB)
Spurious Free Dynamic Range (dB)
100
98
96
94
92
90
88
86
84
82
80
2.7
fIN = 20 kHz
3.2
3.7
4.2
4.7
5.2
AVDD, Analog Supply Voltage (V)
98
96
94
92
90
88
86
84
AVDD = 5.25 V
fIN = 20 kHz
82
80
2.5
5.7
3
3.5
4
4.5
Reference Voltage (V)
G063
Figure 62.
SFDR vs FREE-AIR TEMPERATURE
SFDR vs INPUT FREQUENCY
Spurious Free Dynamic Range (dB)
Spurious Free Dynamic Range (dB)
G065
100
98
96
94
92
90
88
86
84
AVDD = 3 V
fIN = 20 kHz
82
80
−40 −25 −10
5
20 35 50 65 80
Free-Air Temperature (°C)
95
98
96
94
92
90
88
86
84
82
80
110 125
AVDD = 3 V
0
20
G064
40
60
fIN, Input Frequency (kHz)
80
Figure 64.
Figure 65.
CROSSTALK vs INPUT FREQUENCY
ANALOG SUPPLY CURRENT (Dynamic)
vs ANALOG SUPPLY VOLTAGE
0
100
G066
5
AVDD Dynamic Current (mA)
−20
−40
Crosstalk (dB)
5.5
Figure 63.
100
−60
Memory Crosstalk
−80
−100
Isolation Crosstalk
−120
−140
5
20
40
60
fIN, Input Frequency (kHz)
80
100
4.5
4
3.5
3
2.5
2
2.7
3.2
G071
Figure 66.
3.7
4.2
4.7
5.2
AVDD, Analog Supply Voltage (V)
5.7
G038
Figure 67.
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TYPICAL CHARACTERISTICS: ADS7946 (continued)
At TA = +25°C, AVDD = 5 V, DVDD = 1.8 V, VREF = 2.5 V, and fSAMPLE = 2 MSPS, unless otherwise noted.
ANALOG SUPPLY CURRENT (Dynamic)
vs FREE-AIR TEMPERATURE
ANALOG SUPPLY CURRENT (Dynamic)
vs SAMPLE RATE
4
4.5
AVDD Supply Current (mA)
AVDD Dynamic Current (mA)
5
4
3.5
3
2.5
3
2.5
AVDD = 5 V
2
1.5
1
AVDD = 3 V
0.5
2
−40 −25 −10
5
20 35 50 65 80
Free-Air Temperature (°C)
95
0
110 125
0
100
200
G039
300
400
500
Throughput (kSPS)
600
700
G042
Figure 68.
Figure 69.
ANALOG SUPPLY CURRENT (Static)
vs ANALOG SUPPLY VOLTAGE
ANALOG SUPPLY CURRENT (Static)
vs FREE-AIR TEMPERATURE
3
AVDD Static Current (mA)
3
AVDD Static Current (mA)
3.5
2.5
2
1.5
1
2.7
3.2
3.7
4.2
4.7
5.2
AVDD, Analog Supply Voltage (V)
2.5
2
1.5
1
−40 −25 −10
5.7
G040
5
20 35 50 65 80
Free-Air Temperature (°C)
Figure 70.
95
110 125
G041
Figure 71.
DNL
INL
2
2.5
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
2
1.5
1
0.5
0
−0.5
1.5
1
0.5
0
−0.5
−1
−1.5
−2
−1
0
2048
4096
6144 8192 10240 12288 14336 16384
ADC Output Code (LSB)
G074
−2.5
0
2048
Figure 72.
22
4096
6144 8192 10240 12288 14336 16384
ADC Output Code (LSB)
G073
Figure 73.
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TYPICAL CHARACTERISTICS: ADS7946 (continued)
At TA = +25°C, AVDD = 5 V, DVDD = 1.8 V, VREF = 2.5 V, and fSAMPLE = 2 MSPS, unless otherwise noted.
SPECTRAL RESPONSE
0
−20
Amplitude (dB)
−40
−60
−80
−100
−120
−140
−160
0
250
500
750
fIN, Input Frequency (kHz)
1000
G072
Figure 74.
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OVERVIEW
The ADS7945 and ADS7946 are 14-bit, miniature, dual-channel, low-power SAR ADCs. The ADS7945 is a
differential input device and the ADS7946 is a single-ended device with ground sensing input. These devices
feature very low power consumption at rated speed. The PDEN pin enables an auto power-down mode that
further reduces power consumption at lower speeds.
MULTIPLEXER AND ADC INPUT
The ADS7945/46 devices feature differential/single-ended inputs respectively with a double-pole, double-throw
multiplexer. The analog input circuit shown in Figure 75 is similar for for ADS7945 and ADS7946.
The ADS7945 features a differential input. Each of the positive (AINxP) and negative (AINxN) inputs can swing
from –VREF/2 to +VREF/2 around the common-mode voltage (AINxP + AINxN)/2 so that AINxP and AINxN swing
in opposite directions equally from common-mode voltage (differential input swing VAINxP – VAINxN ranges
from –VREF to +VREF). The ADC converts the difference in voltage: VAINxP – VAINxN. This feature allows the
devices to reject the common-mode noise in the input signal.
For the ADS7946, the ground sense inputs (AINxGND) can accept swings of ±0.2 V whereas the inputs (AINx)
allow signals in the range of 0 V to VREF over the ground sense input. The ADC converts the difference in
voltage: VAINx – VAINxGND. This feature can be used in multiple ways. For example, two signals can be connected
from different sensors with unequal ground potentials (within ±0.2 V) to a single ADC. The ADC rejects the
common-mode offset and noise. This feature also allows the use of a single-supply op amp. The signal and the
AINxGND input can be offset by +0.2 V, which provides the ground clearance required for a single-supply op
amp.
Figure 75 shows the electrostatic discharge (ESD) diodes to supply and ground at every analog input. Make sure
that these diodes do not turn on by keeping the supply voltage within the specified input range.
AVDD
AVDD
AIN0P
AIN0
GND
GND
AVDD
AVDD
AIN0N
AIN0GND
GND
GND
SAR
ADC
AVDD
AIN1N
SAR
ADC
AVDD
AIN1GND
GND
GND
AVDD
AVDD
AIN1P
AIN1
GND
ADS7945
GND
ADS7946
Figure 75. Analog Inputs
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Figure 76 shows an equivalent circuit of the multiplexer and ADC sampling stage. See the Application
Information section for details on the driving circuit. The positive and negative/ground sense inputs are
separately sampled on 32 pF sampling capacitors. The multiplexer and sampling switches are represented by an
ideal switch in series with a 12 Ω resistance. Note that this is dc resistance and can be used for step-settling
calculations (do not use the RC values shown in Figure 76 for 3 dB bandwidth calculations for undersampling
applications). During sampling, the devices connect the 32 pF sampling capacitor to the ADC driver. This
connection creates a glitch at the device input. It is recommended to connect a capacitor across the AINxP and
AINxN terminals or AINx and AINxGND terminals to reduce this glitch for the ADS7945 or ADS7946,
respectively. A driving circuit must have sufficient bandwidth to settle this glitch within the acquisition time.
12 W
12 W
AIN0P
AIN0
32 pF
32 pF
12 W
12 W
AIN1P
AIN1
12 W
12 W
AIN0N
AIN0GND
32 pF
32 pF
12 W
12 W
AIN1N
AIN1GND
ADS7945
ADS7946
Figure 76. Input Sampling Stage Equivalent Circuit
Figure 77 shows a timing diagram for the ADC analog input channel selection. As shown in Figure 77, the CH
SEL signal selects the analog input channel to the ADC. CH SEL = 0 selects channel 0 and CH SEL = 1 selects
channel 1. It is recommended not to toggle the CH SEL signal during an ADC acquisition phase until the device
sees the first valid SCLK rising edge after the device samples the analog input. If CH SEL is toggled during this
period, it can cause erroneous output code because the device might see unsettled analog input.
CH SEL can be toggled at any time during the window specified in Figure 77; however, it is recommended to
select the desired channel after the first SCLK rising edge and before the second SCLK rising edge. This timing
ensures that the multiplexer output is settled before the ADC starts acquisition of the analog input.
Sample N
(AIN0)
Sample N + 1
(AIN1)
tCONV
Conversion of Sample N
tACQ
Acquisition of AIN1
Sample N + 2
(AIN0)
tCONV
Conversion of Sample N + 1
tACQ
Acquisition of AIN0
CS
tSU1
SCLK
1
2
3
16
CH SEL
Window for
CH SEL Toggle
1
2
3
16
Do Not Toggle
CH SEL in
This Window
Figure 77. ADC Analog Input Channel Selection
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REFERENCE
The ADS7945/6 use an external reference voltage during the conversion of a sampled signal. The devices switch
the capacitors used in the conversion process to the reference terminal during conversion. The switching
frequency is the same as the SCLK frequency. It is necessary to decouple the REF terminal to REFGND with a 1
µF ceramic capacitor in order to get the best noise performance from the device. The capacitor must be placed
closest to these pins. The reference input can be driven with the REF50xx series precision references from TI.
Figure 78 shows a typical reference driving circuit.
Sometimes it is convenient to use AVDD as a reference. The ADS7945/6 allow reference ranges up to AVDD.
However, make sure that AVDD is well-bypassed and that there is a separate bypass capacitor between REF
and REFGND.
AVDD
AVDD
REF50xx
(1)
REF
1 mF
Ceramic
ADS7945
ADS7946
REFGND
AGND
GND
(1) Select the appropriate device as described by the required reference value. For example, select the REF5040 for a 4 V reference, the
REF5030 for a 3 V reference, and the REF5025 for a 2.5 V reference. Ensure that (AVDD – REF) > 0.2 V so that the REF50xx functions
properly.
Figure 78. Typical Reference Driving Circuit
CLOCK
The ADS7945/6 use SCLK for conversions (typically 40 MHz). A lower frequency SCLK can be used for
applications that require sample rates less than 2 MSPS. However, it is better to use a 40 MHz SCLK and slow
down the device speed by choosing a lower frequency for CS, which allows more acquisition time. This
configuration relaxes constraints on the output impedance of the driving circuit. Refer to the Application
Information section for calculation of the driving circuit output impedance.
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ADC TRANSFER FUNCTION
The ADS7945 is a differential input device and the ADS7946 is a single-ended input device. This section
describes the transfer characteristics for both devices.
The ADS7945 output is in twos compliment format. Figure 79 shows the ideal transfer characteristics for these
devices. Here, full-scale range for the ADC input (AINxP – AINxN) is equal to twice the reference input voltage to
the ADC 2 × (VREF). 1 LSB is equal to 2 × (VREF/2N), where N is the resolution of the ADC (N = 14 for the
ADS7945). The differential input of the ADC is bipolar around the common-mode voltage (AINxP + AINxN)/2 and
has a range of positive FSR (+VREF) to negative FSR (–VREF).
ADC Code (Hex)
1FFF
0000
3FFF
2001
Negative
FSR + 1 LSB
-1 LSB
0V
Positive
FSR - 1 LSB
VIN
Differential Analog Input (AINxP - AINxN)
Figure 79. ADS7945 Transfer Characteristics
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The ADS7946 output is in straight binary format. Figure 80 shows ideal transfer characteristics for this device.
Here, FSR is the full-scale range for the ADC input (AINx – AINxGND) and is equal to the reference input voltage
to the ADC (VREF). 1 LSB is equal to (VREF/2N), where N is the resolution of the ADC (N = 14 for the ADS7946).
ADC Code (Hex)
3FFF
2000
0001
1 LSB
FSR/2
FSR - 1 LSB
VIN
Single-Ended Analog Input
Figure 80. ADS7946 Transfer Characteristics
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DEVICE OPERATION
The ADS7945/6 operate with either a 16-clock frame or 32-clock frame for ease of interfacing with the host
processor.
16-CLOCK FRAME
Figure 81 shows the devices operating in 16-clock mode. This mode is the fastest mode for device operation. In
this mode, the devices output data from previous conversions while converting the recently sampled signal.
As shown in Figure 81, the ADS7945/6 start acquisition of the analog input from the 16th falling edge of SCLK.
The device samples the input signal on the CS falling edge. SDO comes out of 3-state and the device outputs
the MSB on the CS falling edge. The device outputs the next lower SDO bits on every SCLK falling edge after it
has first seen the SCLK rising edge. The data correspond to the sample and conversion completed in the
previous frame. During a CS low period, the device converts the recently sampled signal. It uses SCLK for
conversions. Conversion is complete on the 16th SCLK falling edge. CS can be high at any time after the 16th
SCLK falling edge (see the Parameter Measurement Information for more details). The CS rising edge after the
16th SCLK falling edge and before the 29th SCLK falling edge keeps the device in the 16-clock data frame. The
device output goes to 3-state when CS is high. It is also permissible to stop SCLK after the device has seen the
16th SCLK falling edge.
Sample N
Sample N + 1
tACQ
tCONV
CS
1
SCLK
SDO
2
3
4
D13 D12 D11 D10
5
6
7
8
9
10
11
12
13
14
D9
D8
D7
D6
D4
D3
D3
D2
D1
D0
15
16
Data From Sample N - 1
Figure 81. ADS7945/6 Operating in 16-Clock Mode without Power-Down (PDEN = 0)
32-CLOCK FRAME
Figure 82 shows the devices operating in 32-clock mode. In this mode, the devices convert and output the data
from the most recent sample before taking the next sample.
Sample N
Sample N + 1
1/fSAMPLE
tACQ
tCONV
CS
SCLK
1
2
11
SDO
12
16
17
18
D13 D12
23
24
25
26
27
28
29
30
D7
D6
D5
D4
D3
D2
D1
D0
31
32
Data From Sample N
Figure 82. ADS7945/6 Operation in 32-Clock Frame without Power-Down (PDEN = 0)
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CS can be held low past the 16th falling edge of SCLK. The devices continue to output recently converted data
starting with the 16th SCLK falling edge. If CS is held low until the 30th SCLK falling edge, then the devices
detect 32-clock mode. Note that the device data from recent conversions are already output with no latency
before the 30th SCLK falling edge. Once 32-clock mode is detected, the device outputs 16 zeros during the next
conversion (in fact, for the first 16 clocks), unlike 16-clock mode where the devices output the previous
conversion result. SCLK can be stopped after the devices have seen the 30th falling edge with CS low.
CONVERSION ABORT
For some event triggered applications such as latching position of absolute position sensor on marker or homing
pulse, it is essential to abort ongoing conversion on event and quickly start fresh acquisition. ADS794X features
conversion abort function. CS high during conversion (during first 16 clocks) will abort ongoing conversion and
start fresh acquisition. Device will sample acquired signal during CS high period on falling edge of CS and will
start conversion normally, however data on SDO (conversion results from aborted frame) will not be valid.
For example if conversion is aborted during ‘nth’ frame and (n+1) is first valid frame after conversion abort. SDO
data during frame number (n+1) (corresponding to nth conversion) will not be valid. Conversion results for sample
and conversion during frame number (n+1) will be available in frame number (n+2).
POWER-DOWN
The ADS7945/6 devices offer an easy-to-use power-down feature available through a dedicated PDEN pin (pin
12). A high level on PDEN at the CS rising edge enables the power-down mode for that particular cycle.
Figure 83 to Figure 85 illustrate device operation with power-down in both 32-clock and 16-clock mode.
Many applications must slow device operation. For speeds below approximately 500 kSPS, it is convenient to
use 32-clock mode with power-down. This configuration results in considerable power savings.
As shown in Figure 83, PDEN is held at a logic '1' level. Note that the device looks at the PDEN status only at
the CS rising edge; however, for continuous low-speed operation, it is convenient to continuously hold PDEN = 1.
The devices detect power-down mode on the CS rising edge with PDEN = 1.
t CONV
t ACQ
tACQ(MIN)+
1 ms
CS
SCLK
1
2
14
15
16
17
18
D13 D12
SDO
27
28
29
30
D3
D2
D1
D0
31
32
Power-Down State
(Internal)
IDYNAMIC
ISTATIC
IAVDD Profile
IPDDYNAMIC
IPDSTATIC if
SCLK is off,
otherwise
IPDDYNAMIC.
Figure 83. Operation with a 32-Clock Frame in Power-Down Mode (PDEN = 1)
On the CS falling edge, the devices start normal operation as previously described. The devices complete
conversions on the 16th SCLK falling edge. The devices enter the power-down state immediately after
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conversions complete. However, the devices can still output data as per the timings described previously. The
devices consume dynamic power-down current (IPD-DYNAMIC) during data out operations. It is recommended to
stop the clock after the 32nd SCLK falling edge to further save power down to the static power-down current
level (IPD-STATIC). The devices power up again on the SCLK rising edge. However, they require an extra 1 µs to
power up completely. CS must be high for the 1 µs + tACQ (min) period.
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In some applications, data collection is accomplished in burst mode. The system powers down after data
collection. 16-clock mode is convenient for these applications. Figure 84 and Figure 85 detail power saving in
16-clock burst mode.
tPDSU
tPDH
PDEN
Sample
N-1
Dummy
Sample
Sample
N
CS
1
SCLK
2
15
16
1
15
2
16
1
2
11
13
12
15
14
16
SDO
Data From Sample
N-2
Power-Down
(Internal)
Data From Sample
N-1
Data From Sample
N
Figure 84. Entry Into Power-Down with 16-Clock Burst Mode
As shown in Figure 84, the two frames capturing the N–1 and Nth samples are normal 16-clock frames. Keeping
PDEN = 1 before the CS rising edge in the next frame ensures that the devices detect the power-down mode.
Data from the Nth sample are read during this frame. It is expected that the Nth sample represents the last data
of interest in the burst of conversions. The devices enter the power-down state after the end of conversions. This
is the 16th SCLK falling edge. It is recommended to stop the clock after the 16th SCLK falling edge. Note that it
is mandatory not to have more than 29 SCLK falling edges during the CS low period. This limitation ensures that
the devices remain in 16-clock mode.
The devices remain in a power-down state as long as CS is low. A CS rising edge with PDEN = 0 brings the
devices out of the power-down state. It is necessary to ensure that the CS high time for the first sample after
power up is more than 1 µs + tACQ (min).
tPDSU
PDEN
Sample
N+1
Sample
N+3
Sample
N+2
CS
tW1 + 1 ms
1
SCLK
2
15
16
1
2
15
16
1
2
SDO
Invalid Data
Power-Down
(Internal)
Data From Sample
N+1
Data From Sample
N+2
Figure 85. Exit From Power-Down with 16-Clock Burst Mode
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APPLICATION INFORMATION: ADS7945
The ADS7945 employs a sample-and-hold stage at the input; see Figure 76 for a typical equivalent circuit of a
sample-and-hold stage. The device connects a 32 pF sampling capacitor during sampling. This configuration
results in a glitch at the input terminals of the device at the start of the sample. The external circuit must be
designed in such a way that the input can settle to the required accuracy during the sampling time chosen.
Figure 86 shows a typical driving circuit for the analog inputs.
0 - VREF
OPA836
+VA
+
AVDD
±VREF, with
VREF/2
Common-Mode
5Ω
AINxP
50 Ω
470 pF
VREF - 0
ADS7945
AINxN
OPA836
+
GND
5Ω
50 Ω
Figure 86. Typical Input Driving Circuit for the ADS7945
The 470 pF capacitor across the AINxP and AINxN terminals decouples the driving op amp from the sampling
glitch. It is recommended to split the series resistance of the input filter in two equal values as shown in
Figure 86. It is recommended that both input terminals see the same impedance from the external circuit. The
low-pass filter at the input limits noise bandwidth of the driving op amps. Select the filter bandwidth so that the
full-scale step at the input can settle to the required accuracy during the sampling time. Equation 1, Equation 2,
and Equation 3 are useful for filter component selection.
Sampling Time
Filter Time Constant (tAU) =
Settling Resolution ´ ln(2)
Where:
Settling resolution is the accuracy in LSB to which the input needs to settle. A typical settling resolution
for the 14-bit device is 15 or 16.
(1)
Filter Time Constant (tAU) = R ´ C
(2)
Filter Bandwidth =
1
2 ´ p ´ tAU
(3)
Also, make sure the driving op amp bandwidth does not limit the signal bandwidth below filter bandwidth. In
many applications, signal bandwidth may be much lower than filter bandwidth. In this case, an additional
low-pass filter may be used at the input of the driving op amp. This signal filter bandwidth can be selected in
accordance with the input signal bandwidth.
INPUT COMMON-MODE RANGE
The AIN+ and AIN– inputs to the ADS7945 should typically vary between 0 V and VREF with a common-mode of
VREF/2. The ADS7945 offers excellent CMRR which makes it possible to achieve close to the rated performance
of the converter even in cases where the common-mode input is not well-controlled. The device can accept a
±200 mV variation in the common-mode voltage at any VDD/VREF combination allowing use of the entire ADC
signal range (–VREF to +VREF differentially).
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DRIVING AN ADC WITHOUT A DRIVING OP AMP
For some low input signal bandwidth applications, such as battery power monitoring or mains monitoring, it is not
required to operate an ADC at high sampling rates. In fact, it is desirable to avoid using a driving op amp from a
cost perspective. In these cases, the ADC input sees the impedance of the signal source (such as a battery or
mains transformer). This section elaborates the effects of source impedance on sampling frequency.
Equation 1 can be rewritten as Equation 4:
Sampling Time = Filter Time Constant × Settling Resolution × ln(2)
(4)
As shown in Figure 87, it is recommended to use a bypass capacitor across the positive and negative ADC input
terminals.
RSOURCE
RS
AVDD
+
AINxP
CBYPASS
+
+
–
AINxN
ADS7945
RSOURCE
RS
GND
Signal Source
GND
Figure 87. Driving an ADS7945 ADC Without a Driving Op Amp
Source impedance (2 × RSOURCE + 2 × RS) with (CBYPASS + CSAMPLE) acts as a low-pass filter with Equation 5:
Filter Time Constant = 2 × (RSOURCE + RS) × (CBYPASS + CSAMPLE)
where:
CSAMPLE is the internal sampling capacitance of the ADC (equal to 32 pF).
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Table 4 lists the recommended bypass capacitor values and the filter time constant for different source
resistances. It is recommended to use a 10 pF bypass capacitor, at minimum. Table 4 assumes RS = 5 Ω;
however, depending on the application, RS can be chosen to be 0 Ω. In this case, there is an extra margin of 5 Ω
for RSOURCE.
Table 4. Filter Time Constant versus Source Resistance
2 × RSOURCE (Ω)
2 × (RSOURCE + RS)
APPROXIMATE CBYPASS
(pF)
CBYPASS + CSAMPLE (pF)
FILTER TIME
CONSTANT (ns)
18
28
220
252
7.2
44
54
100
132
7.2
81
91
47
79
7.2
161
171
10
42
7.2
21
500
510
10
42
1000
1010
10
42
42
5000
5010
10
42
210
Typically, settling resolution is selected as (ADC resolution + 2). For the ADS7945 (14-bit) the ideal settling
resolution is 16. Using Equation 2 and Equation 3, the sampling time can be easily determined for a given source
impedance and allows 80 ns of sampling time for a 14-bit ADC with 7.2 ns of filter time constant, which matches
the ADS7945 specifications. For net source impedance (2 × (RSOURCE + RS)) above 171 Ω, the filter time
constant continues to increase beyond the 7.2 ns required for an 80 ns sampling time. This increment increases
the minimum permissible sampling time for 14-bit settling and the device must be operated at a lower sampling
rate.
The device sampling rate can be maximized by using a 40 MHz clock even for lower throughputs. Table 5 shows
typical calculations for the ADS7945.
Table 5. Sampling Frequency versus Source Impedance for the ADS7945 (14-Bit)
2 × RSOURCE (Ω)
CBYPASS (pF)
SAMPLING TIME,
tACQ (ns)
CONVERSION TIME, CYCLE TIME, tACQ +
tCONV (ns)
tCONV (ns)
SAMPLING RATE
(MSPS)
161
10
80
420
(with 40 MHz clock)
500
2
500
10
235
420
(with 40 MHz clock)
655
1.5
1000
10
468
420
(with 40 MHz clock)
888
1.1
5000
10
2331
420
(with 40 MHz clock)
2751
0.4
It is necessary to allow 1000 ns additional sampling time over what is shown in Table 5 if PDEN (pin 12) is set
high.
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ADS7945
ADS7946
SBAS539B – JUNE 2011 – REVISED SEPTEMBER 2011
www.ti.com
APPLICATION INFORMATION: ADS7946
The ADS7946 employs a sample-and-hold stage at the input; see Figure 76 for a typical equivalent circuit of a
sample-and-hold stage. The device connects a 32 pF sampling capacitor during sampling. This configuration
results in a glitch at the input terminals of the device at the start of the sample. The external circuit must be
designed in such a way that the input can settle to the required accuracy during the sampling time chosen.
Figure 88 shows a typical driving circuit for the analog inputs.
OPA836
0 - VREF
+VA
+
AVDD
5Ω
AINxP
50 Ω
ADS7946
470 pF
AINxGND
GND
5Ω
Figure 88. Typical Input Driving Circuit For the ADS7946
The 470 pF capacitor across the AINx and AINxGND terminals decouples the driving op amp from the sampling
glitch. It is recommended to split the series resistance of the input filter in two equal values, as shown in
Figure 88. It is recommended that both input terminals see the same impedance from the external circuit. The
low-pass filter at the input limits noise bandwidth of the driving op amp. Select the filter bandwidth so that the
full-scale step at the input can settle to the required accuracy during the sampling time. Equation 6, Equation 7,
and Equation 8 are useful for filter component selection.
Sampling Time
Filter Time Constant (tAU) =
Settling Resolution ´ ln(2)
where:
Settling resolution is the accuracy in LSB to which the input must settle. A typical settling resolution for
the 14-bit device is 15 or 16.
(6)
Filter Time Constant (tAU) = R ´ C
(7)
Filter Bandwidth =
1
2 ´ p ´ tAU
(8)
Also, make sure the driving op amp bandwidth does not limit the signal bandwidth below filter bandwidth. In
many applications, signal bandwidth may be much lower than filter bandwidth. In this case, an additional
low-pass filter may be used at the input of the driving op amp. This signal filter bandwidth can be selected in
accordance with the input signal bandwidth.
36
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ADS7945
ADS7946
SBAS539B – JUNE 2011 – REVISED SEPTEMBER 2011
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DRIVING AN ADC WITHOUT A DRIVING OP AMP
For some low input signal bandwidth applications, such as battery power monitoring or mains monitoring, it is not
required to operate an ADC at high sampling rates. In fact, it is desirable to avoid using a driving op amp from a
cost perspective. In this case, the ADC input sees the impedance of the signal Equation 4 source (such as a
battery or mains transformer). This section elaborates the effects of source impedance on sampling frequency.
Equation 6 can be rewritten as Equation 9:
Sampling Time = Filter Time Constant × Settling Resolution × ln(2)
(9)
As shown in Figure 89, it is recommended to use a bypass capacitor across the positive and negative ADC input
terminals.
RSOURCE
AVDD
+
AINxP
Signal Source
CBYPASS
+
–
AINxGND
ADS7946
RS
GND
GND
Figure 89. Driving an ADS7946 ADC Without a Driving Op Amp
Source impedance (RSOURCE + RS) with (CBYPASS + CSAMPLE) acts as a low-pass filter with Equation 10:
Filter Time Constant = (RSOURCE + RS) × (CBYPASS + CSAMPLE)
Where:
CSAMPLE is the internal sampling capacitance of the ADC (equal to 32 pF).
(10)
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Table 6 lists the recommended bypass capacitor values and the filter time constant for different source
resistances. It is recommended to use a 10 pF bypass capacitor (minimum).
Table 6. Filter Time Constant versus Source Resistance
RSOURCE (Ω)
RSOURCE + RS
APPROXIMATE CBYPASS
(pF)
CBYPASS + CSAMPLE (pF)
FILTER TIME
CONSTANT (ns)
23
28
220
252
7.2
49
54
100
132
7.2
86
91
47
79
7.2
166
171
10
42
7.2
500
505
10
42
21
1000
1005
10
42
42
5000
5005
10
42
210
Typically, settling resolution is selected as (ADC resolution + 2). For the ADS7946 (14-bit) the ideal settling
resolution is 16. Using equations Equation 7 and Equation 8, the sampling time can be easily determined for a
given source impedance and allows 80 ns of sampling time for a 14-bit ADC with 7.2 ns of filter time constant,
which matches the ADS7946 specifications. For source impedance above 166 Ω, the filter time constant
continues to increase beyond the 7.2 ns required for an 80 ns sampling time. This increment increases the
minimum permissible sampling time for 14-bit settling and the device must be operated at a lower sampling rate.
The device sampling rate can be maximized by using a 40 MHz clock even for lower throughputs. Table 7 shows
typical calculations for the ADS7946.
Table 7. Sampling Frequency versus Source Impedance for the ADS7946 (14-Bit)
RSOURCE (Ω)
CBYPASS (pF)
SAMPLING TIME,
tACQ (ns)
CONVERSION TIME, CYCLE TIME, tACQ +
tCONV (ns)
tCONV (ns)
SAMPLING RATE
(MSPS)
166
10
80
420
(with 40 MHz clock)
500
2
500
10
235
420
(with 40 MHz clock)
655
1.5
1000
10
468
420
(with 40 MHz clock)
888
1.1
5000
10
2331
420
(with 40 MHz clock)
2751
0.4
It is necessary to allow 1000 ns additional sampling time over what is shown in Table 7 if PDEN (pin 12) is set
high.
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SBAS539B – JUNE 2011 – REVISED SEPTEMBER 2011
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PCB LAYOUT/SCHEMATIC GUIDELINES: ADS7945
The ADS7945 is a mixed-signal device. For maximum performance, proper decoupling, grounding, and proper
termination of digital signals are essential. Figure 90 shows the essential components around the ADC. All
capacitors shown are ceramic. These decoupling capacitors must be placed close to the respective signal pins.
There is a 47 Ω source series termination resistor shown on the SDO signal. This resistor must be placed as
close to pin 15 as possible. Series terminations for SCLK and CS must be placed close to the host.
Analog
Supply
4
5W
AIN0N
AIN1N
470 pF
5W
C1
AIN1P
1
0.1 mF
C5
AVDD
5
16
6
15
ADS7945
U0
7
14
8
13
NC
9
10
11
DVDD
1 mF
C6
Digital
Supply
SDO
SCLK
47 W
R1
CS
12
PDEN
470 pF
C2
2
CH SEL
5W
AIN0P
3
Digital Signals from Host
Differential Input Signals
5W
Common Analog/
Digital Ground Plane
REF
REFGND
1 mF
C4
GND
1 mF
C3
NC
Reference
Input
Figure 90. Recommended ADS7945 ADC Schematic
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ADS7945
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SBAS539B – JUNE 2011 – REVISED SEPTEMBER 2011
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A common ground plane for both analog and digital often enables better results. Typically, the second PCB layer
is the ground plane. The ADC ground pins are returned to the ground plane through multiple vias (PTH). It is a
good practice to place analog components on one side and digital components on other side of the ADC (or
ADCs). All signals must be routed, assuming there is a split ground plane for analog and digital. Furthermore, it
is better to split the ground initially during layout. Route all analog and digital traces so that the traces see the
respective ground all along the second layer. Then short both grounds to form a common ground plane.
Figure 91 shows a typical layout around the ADC.
Figure 91. Recommended ADS7945 ADC Layout
(Only top layer is shown; second layer is common ground for analog and digital)
40
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Product Folder Link(s): ADS7945 ADS7946
ADS7945
ADS7946
SBAS539B – JUNE 2011 – REVISED SEPTEMBER 2011
www.ti.com
PCB LAYOUT/SCHEMATIC GUIDELINES: ADS7946
The ADS7946 is a mixed-signal device. For maximum performance, proper decoupling, grounding, and proper
termination of digital signals are essential. Figure 92 shows the essential components around the ADC. All
capacitors shown are ceramic. These decoupling capacitors must be placed close to the respective signal pins.
There is a 47 Ω source series termination resistor shown on the SDO signal. This resistor must be placed as
close to pin 15 as possible. Series terminations for SCLK and CS must be placed close to the host.
Analog
Supply
1 F
C4
Common Analog/
Digital Ground Plane
Input
Signal
AIN0P
5Ω
3
2
0.1 F
C5
1
5
16
DVDD
6
15
ADS7946
SDO
5Ω
AIN1GND
5Ω
U0
7
14
8
13
470 pF
C1
AIN1P
SCLK
47 Ω
R1
CS
5Ω
11
12
PDEN
10
NC
NC
9
CH SEL
Input
Signal
Digital
Supply
470 pF
C2
AIN0GND
1 F
C6
Digital Signals From Host
4
GND
REF
REFGND
1 F
C3
AVDD
Reference
Input
Figure 92. Recommended ADS7946 ADC Schematic
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ADS7945
ADS7946
SBAS539B – JUNE 2011 – REVISED SEPTEMBER 2011
www.ti.com
A common ground plane for both analog and digital often enables better results. Typically, the second PCB layer
is the ground plane. The ADC ground pins are returned to the ground plane through multiple vias (PTH). It is a
good practice to place analog components on one side and digital components on other side of the ADC (or
ADCs). All signals must be routed, assuming there is a split ground plane for analog and digital. Furthermore, it
is better to split the ground initially during layout. Route all analog and digital traces so that the traces see the
respective ground all along the second layer. Then short both grounds to form a common ground plane.
Figure 93 shows a typical layout around the ADC.
Figure 93. Recommended ADS7946 ADC Layout
(Only top layer is shown; second layer is common ground for analog and digital)
42
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Feb-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS7945SRTER
ACTIVE
WQFN
RTE
16
3000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7945
ADS7945SRTET
ACTIVE
WQFN
RTE
16
250
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7945
ADS7946SRTER
ACTIVE
WQFN
RTE
16
3000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7946
ADS7946SRTET
ACTIVE
WQFN
RTE
16
250
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7946
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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