ADS7958SRGER

Order Now Product Folder Support & Community Tools & Software Technical Documents ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605C – JUNE 2008 – REVISED JULY 2018 ADS79xx Pin Compatible, 12-, 10-, 8-Bit, 1-MSPS, 16-, 12-, 8-, 4-Channel, Single-Ended, Serial Interface ADCs 1 Features 3 Description • • • • • • • The ADS79xx is a 12-, 10-, 8-bit pin compatible multichannel analog-to-digital converter family. The device comparison table shows all twelve devices from this product family. 1 • • • • • • • • 1-MHz Sample Rate Serial Devices Product Family of 12-, 10-, 8-Bit Resolution Zero Latency 20-MHz Serial Interface Analog Supply Range: 2.7 to 5.25 V I/O Supply Range: 1.7 to 5.25 V Two SW Selectable Unipolar, Input Ranges: 0 to VREF and 0 to 2 x VREF Auto and Manual Modes for Channel Selection 4-, 8-Channel Devices and 12-, 16-Channel Devices Share the Same Footprint Two Programmable Alarm Levels per Channel Four Individually Configurable GPIOs in TSSOP Package: One GPIO in VQFN Package Typical Power Dissipation: 14.5 mW (+VA = 5 V, +VBD = 3 V) at 1 MSPS Power-Down Current (1 μA) Input Bandwidth (47 MHz at 3 dB) 38-, 30-Pin TSSOP and 32-, 24-Pin VQFN Packages 2 Applications • • • • • • • PLC/IPC Optical Line Card Monitoring Medical Instrumentation Digital Power Supplies Multi-Channel, General-Purpose Signal Monitoring High-Speed Data Acquisition Systems High-Speed Closed-Loop Systems Detailed Block Diagram The devices include a capacitor based SAR A/D converter with inherent sample and hold. The devices accept a wide analog supply range from 2.7 V to 5.25 V. Very low power consumption makes these devices suitable for battery-powered and isolated power-supply applications. A wide 1.7-V to 5.25-V I/O supply range facilitates a glueless interface with the most commonly used digital hosts. The serial interface is controlled by CS and SCLK for easy connection with microprocessors and DSP. The input signal is sampled with the falling edge of CS. It uses SCLK for conversion, serial data output, and reading serial data in. The devices allow auto sequencing of preselected channels or manual selection of a channel for the next conversion cycle. There are two software selectable input ranges (0 V to VREF and 0 V to 2 × VREF), individually configurable GPIOs (four in case of the TSSOP and one on the VQFN package devices), and two programmable alarm thresholds per channel. These features make the devices suitable for most data acquisition applications. The devices offer an attractive power-down feature. This is extremely useful for power saving when the device is operated at lower conversion speeds. The 16-, 12-channel devices from this family are available in a 38-pin TSSOP and 32 pin VQFN package and the 4/8-channel devices are available in a 30-pin TSSOP and 24 pin VQFN packages. Device Information(1) PGA Gain Control High input impedance PGA (or non inverting buffer such as THS4031) PART NUMBER GPIO1 GPIO2 GPIO3 MXO AINP GPIO0 high-alarm low-alarm Ch0 Ch1 ADS79xx Ch2 ADC SDO SDI To Host PACKAGE BODY SIZE (NOM) TSSOP (30) 7.80 mm × 4.40 mm VQFN (24) 4.00 mm × 4.00 mm TSSOP (38) 9.70 mm × 4.40 mm VQFN (32) 5.00 mm × 5.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. SCLK Chn CS (1) REF 10 µF REF5025 o/p 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605C – JUNE 2008 – REVISED JULY 2018 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. 1 Applications ........................................................... 1 Description ............................................................. 1 Revision History..................................................... 2 Device Comparison Table..................................... 5 Pin Configuration and Functions ......................... 5 Specifications....................................................... 10 7.1 7.2 7.3 7.4 7.5 7.6 Absolute Maximum Ratings .................................... ESD Ratings............................................................ Recommended Operating Conditions..................... Thermal Information: TSSOP.................................. Thermal Information: VQFN.................................... Electrical Characteristics: ADS7950, ADS7951, ADS7952, ADS7953 ................................................ 7.7 Electrical Characteristics, ADS7954, ADS7955, ADS7956, ADS7957 ................................................ 7.8 Electrical Characteristics, ADS7958, ADS7959, ADS7960, ADS7961 ................................................ 7.9 Timing Requirements .............................................. 7.10 Typical Characteristics (All ADS79xx Family Devices) ................................................................... 7.11 Typical Characteristics (12-Bit Devices Only)....... 7.12 Typical Characteristics (12-Bit Devices Only)....... 8 Detailed Description ............................................ 28 8.1 8.2 8.3 8.4 8.5 9 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Programming........................................................... 28 29 29 29 41 Application and Implementation ........................ 46 9.1 Application Information............................................ 46 9.2 Typical Applications ................................................ 48 10 10 10 11 11 10 Power Supply Recommendations ..................... 51 11 Layout................................................................... 52 12 12 Device and Documentation Support ................. 54 14 15 17 20 21 27 11.1 Layout Guidelines ................................................. 52 11.2 Layout Examples................................................... 52 12.1 12.2 12.3 12.4 12.5 12.6 12.7 Documentation Support ........................................ Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 54 54 54 54 54 55 55 13 Mechanical, Packaging, and Orderable Information ........................................................... 55 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (July 2015) to Revision C Page • Changed 0 to 2.5 V and 0 to 5 V to 0 to VREF and 0 to 2 x VREF in Input Range Features bullet ......................................... 1 • Changed GPIO Features bullet ............................................................................................................................................. 1 • Changed Optical Line Card Monitoring and Multi-Channel, General-Purpose Signal Monitoring Applications bullets.......... 1 • Changed (0 V to 2.5 V and 0 V to 5 V) to (0 V to VREF and 0 V to 2 × VREF) in Description section ..................................... 1 • Deleted Companion Products table........................................................................................................................................ 5 • Changed RGE to RHB for two 32-pin VQFN pin diagrams ................................................................................................... 5 • Added 30-pin DBT package .................................................................................................................................................. 5 • Changed I/O column of Pin Functions: TSSOP Packages table to show full definition instead of abbreviation ................... 6 • Added active low to definition of CS pin in Pin Functions: TSSOP Packages table .............................................................. 7 • Changed pin name and description of Alarm pin in Pin Functions: TSSOP Packages table ............................................... 7 • Added settings to description of Range pin in Pin Functions: TSSOP Packages table: added (1) to high and (0) to low .... 7 • Added active low to description of CS pin in Pin Functions: VQFN Packages table ............................................................. 8 • Changed pin name and description of Alarm pin in Pin Functions: VQFN Packages table .................................................. 9 • Changed value of Input current to any pin except supply pins row from ±10 mA (max) to –10 mA (min) and 10 mA (max) in Absolute Maximum Ratings table........................................................................................................................... 10 • Changed VBD = 1.7 V to 5.25 V to VBD = 1.7 V to +VA in condition statement................................................................. 12 • Changed minimum specification from –1 LSB to –0.99 LSB in first row of Differential linearity parameter......................... 12 • Added input to Reference input resistance parameter name ............................................................................................... 13 • Changed maximum specification from FFC Hex to 4092 LSB in Alarm Setting parameters .............................................. 13 • Changed unit from Numbers to Conversion in Invalid conversions after power up or reset parameter ............................. 13 • Changed VBD = 1.7 V to 5.25 V to VBD = 1.7 V to +VA in condition statement ................................................................ 14 2 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605C – JUNE 2008 – REVISED JULY 2018 Revision History (continued) • Added input to Reference input resistance parameter name .............................................................................................. 14 • Changed maximum specification from FFC Hex to 4092 LSB in Alarm Setting parameters .............................................. 14 • Changed VBD = 1.7 V to 5.25 V to VBD = 1.7 V to +VA in condition statement ................................................................ 15 • Added input to Reference input resistance parameter name .............................................................................................. 16 • Changed maximum specification from FF Hex to 255 LSB in Alarm Setting parameters .................................................. 16 • Changed unit from Numbers to Conversion in Invalid conversions after power up or reset parameter ............................. 16 • Changed REF and GND pins to REFP and REFM pins in the Reference section ............................................................. 29 • Added Example Manual Mode Timing Diagram figure and corresponding text to Operating in Manual Mode section ...... 33 • Added Example Auto-1 Mode Timing Diagram figure and corresponding text to the Operating in Auto-1 Mode section ................................................................................................................................................................................. 35 • Added Example Auto-2 Mode Timing Diagram figure and corresponding text to the Operating in Auto-2 Mode section ................................................................................................................................................................................. 39 • Changed 2.5V to VREF in first DI06 row and 5V to 2xVREF in second DI06 row ................................................................... 40 • Changed binary code from 0001 1111 1111 to 0011 1111 1111 in Full scale row of Ideal Input Voltages for 10-Bit Devices and Digital Output Codes for 10-Bit Devices (ADS7954/55/56/57) table ............................................................... 41 • Changed 10-Bit to 8-Bit in title of Ideal Input Voltages for 8-Bit Devices and Digital Output Codes for 8-Bit Devices (ADS7958/59/60/61) table .................................................................................................................................................... 42 • Changed Application Diagram for an Unbuffered MXO figure note .................................................................................... 48 • Changed Recommended Layout figure title to Recommended Layout for the TSSOP Packaged Device .......................... 52 • Added Recommended Layout for the VQFN Packaged Device figure ................................................................................ 53 Changes from Revision A (April 2010) to Revision B • Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 Changes from Original (June 2008) to Revision A Page • Added QFN information to Features....................................................................................................................................... 1 • Added QFN information to Description................................................................................................................................... 1 • Changed VEE to AGND and VCC to +VA on 38-pin TSSOP pinout ..................................................................................... 5 • Added QFN pinout .................................................................................................................................................................. 5 • Added QFN pinout .................................................................................................................................................................. 5 • Added QFN pinout .................................................................................................................................................................. 6 • Added QFN pinout .................................................................................................................................................................. 6 • Added terminal functions for QFN packages.......................................................................................................................... 8 • Changed ADS7950/4/8 QFN package MXO pin from 7 to 3.................................................................................................. 8 • Added VREF = 2.5 V ± 0.1 V to Electrical Characteristics, ADS7950/51/52/53..................................................................... 12 • Added while 2VREF ≤ +VA to full-scale input span range 2 test conditions .......................................................................... 12 • Added while 2VREF ≤ +VA to Absolute input range span range 2 test conditions ................................................................ 12 • Added Total unadjusted error (TUE) specification ............................................................................................................... 12 • Changed reference voltage at REFP min and max values .................................................................................................. 13 • Added Note to Electrical Characteristics, ADS7950/51/52/53 ............................................................................................. 13 • Added VREF = 2.5 V ± 0.1 V to Electrical Characteristics, ADS7954/55/56/57 test conditions............................................. 14 • Added while 2VREF ≤ +VA to full-scale input span range 2 test conditions .......................................................................... 14 • Added while 2VREF ≤ +VA to full-scale input span range 2 test conditions .......................................................................... 14 Copyright © 2008–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 3 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605C – JUNE 2008 – REVISED JULY 2018 www.ti.com • Changed Vref reference voltage at REFP min value from 2.49 V to 2.0 V ........................................................................... 14 • Changed Vref reference voltage at REFP max value from 2.51 V to 3.0 V .......................................................................... 14 • Added Vref = 2.5 V ± 0.1 V to Electrical Characteristics, ADS7958/59/60/61 test conditions............................................... 15 • Added while 2VREF ≤ +VA to full-scale input span range 2 test conditions .......................................................................... 15 • Added while 2VREF ≤ +VA to full-scale input span range 2 test conditions .......................................................................... 15 • Changed Vref reference voltage at REFP min value from 2.49 V to 2.0 V ........................................................................... 16 • Changed Vref reference voltage at REFP max value from 2.51 V to 3.0 V .......................................................................... 16 • Changed tsu1 values from max to min................................................................................................................................... 17 • Changed tsu2 values from max to min................................................................................................................................... 17 • Added TOTAL UNADJUSTED ERROR (TUE Max) graph................................................................................................... 25 • Added TOTAL UNADJUSTED ERROR (TUE Min) graph.................................................................................................... 25 • Changed GPIO pins description ........................................................................................................................................... 28 • Added device powerdown through GPIO in the case of the TSSOP packaged devices ..................................................... 28 • Added note to Table 1 .......................................................................................................................................................... 33 • Added note to Table 2 .......................................................................................................................................................... 36 • Added note to Table 5 .......................................................................................................................................................... 40 • Added note to Programming GPIO Registers description.................................................................................................... 42 • Added QFN information to Table 11..................................................................................................................................... 43 • Changed DI12 = 1? from No or No to Yes or No in Figure 59............................................................................................. 44 • Added note to Figure 60 ....................................................................................................................................................... 46 4 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605C – JUNE 2008 – REVISED JULY 2018 5 Device Comparison Table RESOLUTION NUMBER OF CHANNELS 12 BIT 10 BIT 8 BIT 16 ADS7953 ADS7957 ADS7961 12 ADS7952 ADS7956 ADS7960 8 ADS7951 ADS7955 ADS7959 4 ADS7950 ADS7954 ADS7958 6 Pin Configuration and Functions DBT Package 38-Pin TSSOP Top View GPIO1 37 GPIO0 REFM 3 36 +VBD REFM 3 36 +VBD REFP 4 35 BDGND REFP 4 35 BDGND +VA 5 34 SDO +VA 5 34 SDO AGND 6 33 SDI AGND 6 33 SDI MXO 7 32 AINP 8 AINM 9 AGND 10 ADS7952 ADS7956 ADS7960 SCLK MXO 7 32 31 CS 30 AGND 31 CS AINP 8 30 AGND AINM 9 29 +VA AGND 10 ADS7953 ADS7957 ADS7961 SCLK 29 +VA 32 AGND SDI 38 2 SDO 1 GPIO3 +VBD GPIO2 GPIO0 BDGND GPIO1 37 GPIO 38 2 REFM 1 GPIO3 REFP GPIO2 +VA RHB Package 32-Pin VQFN Top View 25 24 1 MXO SCLK CS AGND AINP ADS7953/ ADS7957/ ADS7961 AINM +VA NC 11 28 CH0 CH15 11 28 CH0 CH15 NC 12 27 CH1 CH14 12 27 CH1 CH14 CH1 NC 13 26 CH2 CH13 13 26 CH2 CH2 NC 14 25 CH3 CH12 CH13 14 24 CH4 16 23 CH5 CH9 17 22 CH6 CH9 17 22 CH8 18 21 CH7 CH8 18 21 CH7 AGND 19 20 AGND AGND 19 20 AGND CH12 17 16 8 9 CH6 GPIO1 29 GPIO0 REFM 3 28 +VBD REFM 3 28 +VBD REFP 4 27 BDGND REFP 4 27 BDGND +VA 5 26 SDO +VA 5 26 SDO AGND 6 25 SDI AGND 6 25 SDI MXO 7 24 SCLK MXO 7 24 SCLK 23 CS AGND AINP 8 23 CS AINP 8 AINM 9 22 AGND AINM 9 22 AGND 10 21 +VA AGND 10 21 +VA NC 11 20 CH0 CH7 11 20 CH0 CH3 12 19 NC CH6 12 19 CH1 NC 13 18 CH1 CH5 13 18 CH2 14 17 NC CH4 14 17 CH3 NC 15 16 NC NC 15 16 NC MXO SCLK CS AGND AINP ADS7952/ ADS7956/ ADS7960 AINM NC +VA NC NC NC CH11 CH0 CH2 CH3 CH4 CH5 CH6 9 CH1 CH2 17 16 8 CH7 CH10 CH9 Copyright © 2008–2018, Texas Instruments Incorporated 25 24 1 CH8 ADS7951 ADS7955 ADS7959 32 AGND SDI 30 2 SDO 1 GPIO3 BDGND GPIO2 GPIO0 +VBD GPIO1 29 GPIO 30 2 REFP 1 GPIO3 +VA GPIO2 REFM RHB Package 32-Pin VQFN Top View DBT Package 30-Pin TSSOP Top View ADS7950 ADS7954 ADS7958 CH3 CH4 15 CH10 CH5 CH11 CH5 CH6 CH4 23 CH7 24 16 CH8 15 CH9 CH11 CH10 CH10 CH3 CH11 25 CH0 Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 5 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605C – JUNE 2008 – REVISED JULY 2018 www.ti.com CH0 NC CH1 CH2 CH3 CH4 AINP AINM BDGND +VBD GPIO SDO AGND +VA 6 13 12 7 NC 13 12 7 CH6 6 CH5 CH7 AGND CS NC NC AINM ADS7950/ ADS7954/ ADS7958 MXO +VA SDI SCLK AGND CS CH1 AINP 1 CH0 ADS7951/ ADS7955/ ADS7959 MXO REFM REFP +VA SCLK AGND 19 18 24 SDI CH2 1 CH3 19 18 24 +VA RGE Package 24-Pin VQFN Top View SDO BDGND +VBD GPIO REFM REFP RGE Package 24-Pin VQFN Top View Pin Functions: TSSOP Packages PIN ADS7953 ADS7957 ADS7961 ADS7952 ADS7956 ADS7960 ADS7951 ADS7955 ADS7959 ADS7950 ADS7954 ADS7958 REFP 4 4 4 4 Analog input Reference input REFM 3 3 3 3 Analog input Reference ground NAME I/O DESCRIPTION REFERENCE ADC ANALOG INPUT AINP 8 8 8 8 Analog input ADC input signal AINM 9 9 9 9 Analog input ADC input ground MXO 7 7 7 7 Analog output Multiplexer output Ch0 28 28 20 20 Analog input Analog channel for multiplexer Ch1 27 27 19 18 Analog input Analog channel for multiplexer Ch2 26 26 18 14 Analog input Analog channel for multiplexer Ch3 25 25 17 12 Analog input Analog channel for multiplexer Ch4 24 24 14 — Analog input Analog channel for multiplexer Ch5 23 23 13 — Analog input Analog channel for multiplexer Ch6 22 22 12 — Analog input Analog channel for multiplexer Ch7 21 21 11 — Analog input Analog channel for multiplexer Ch8 18 18 — — Analog input Analog channel for multiplexer Ch9 17 17 — — Analog input Analog channel for multiplexer MULTIPLEXER 6 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605C – JUNE 2008 – REVISED JULY 2018 Pin Functions: TSSOP Packages (continued) PIN NAME ADS7953 ADS7957 ADS7961 ADS7952 ADS7956 ADS7960 ADS7951 ADS7955 ADS7959 ADS7950 ADS7954 ADS7958 Ch10 16 16 — — Analog input Analog channel for multiplexer Ch11 15 15 — — Analog input Analog channel for multiplexer Ch12 14 — — — Analog input Analog channel for multiplexer Ch13 13 — — — Analog input Analog channel for multiplexer Ch14 12 — — — Analog input Analog channel for multiplexer Ch15 11 — — — Analog input Analog channel for multiplexer I/O DESCRIPTION DIGITAL CONTROL SIGNALS CS 31 31 23 23 Digital input Chip-select input pin; active low SCLK 32 32 24 24 Digital input Serial clock input pin SDI 33 33 25 25 Digital input Serial data input pin SDO 34 34 26 26 Digital output Serial data output pin GENERAL-PURPOSE INPUTS/OUTPUTS (1) GPIO0 Alarm Digital I/O 37 37 29 29 38 38 30 30 1 1 1 1 2 2 2 2 Digital input GPIO1 Low alarm Digital I/O GPIO2 Range Digital output Digital I/O GPIO3 PD Digital output Digital input Digital I/O General-purpose input or output Active high alarm output. For configuration, see the Programming section. General-purpose input or output Active high output indicating low alarm General-purpose input or output Selects ADC input range: High (1) -> Range 2 (0 to 2xVREF) / Low (0) -> Range 1 (0 to VREF) General-purpose input or output Active low power-down input POWER SUPPLY AND GROUND +VA 5, 29 5, 29 5, 21 5, 21 — Analog power supply AGND 6, 10, 19, 20, 30 6, 10, 19, 20, 30 6, 10, 22 6, 10, 22 — Analog ground +VBD 36 36 28 28 — Digital I/O supply BDGND 35 35 27 27 — Digital ground — 11, 12, 13, 14 15, 16 11, 13, 15, 16, 17, 19 — Pins internally not connected, do not float these pins, connect these pins to ground NC PINS — (1) These pins have programmable dual functionality. See Table 12 for functionality programming. Copyright © 2008–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 7 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605C – JUNE 2008 – REVISED JULY 2018 www.ti.com Pin Functions: VQFN Packages PIN ADS7953 ADS7957 ADS7961 ADS7952 ADS7956 ADS7960 ADS7951 ADS7955 ADS7959 ADS7950 ADS7954 ADS7958 REFP 31 31 24 24 Analog input Reference input REFM 30 30 23 23 Analog input Reference ground PIN NAME I/O DESCRIPTION REFERENCE ADC ANALOG INPUT AINP 3 3 4 4 Analog input ADC input signal AINM 4 4 5 5 Analog input ADC input ground MXO 2 2 3 3 Analog output Multiplexer output Ch0 20 18 13 11 Analog input Analog-input channel for multiplexer Ch1 19 17 12 10 Analog input Analog-input channel for multiplexer Ch2 18 16 11 9 Analog input Analog-input channel for multiplexer Ch3 17 15 10 8 Analog input Analog-input channel for multiplexer Ch4 16 14 9 — Analog input Analog-input channel for multiplexer Ch5 15 13 8 — Analog input Analog-input channel for multiplexer Ch6 14 12 7 — Analog input Analog-input channel for multiplexer Ch7 13 11 6 — Analog input Analog-input channel for multiplexer Ch8 12 10 — — Analog input Analog-input channel for multiplexer Ch9 11 9 — — Analog input Analog-input channel for multiplexer Ch10 10 8 — — Analog input Analog-input channel for multiplexer Ch11 9 7 — — Analog input Analog-input channel for multiplexer Ch12 8 — — — Analog input Analog-input channel for multiplexer Ch13 7 — — — Analog input Analog-input channel for multiplexer Ch14 6 — — — Analog input Analog-input channel for multiplexer Ch15 5 — — — Analog input Analog-input channel for multiplexer MULTIPLEXER DIGITAL CONTROL SIGNALS CS 23 23 16 16 Digital input Chip-select input pin; active low SCLK 24 24 17 17 Digital input Serial clock input pin SDI 25 25 18 18 Digital input Serial data input pin 8 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605C – JUNE 2008 – REVISED JULY 2018 Pin Functions: VQFN Packages (continued) PIN PIN NAME SDO ADS7953 ADS7957 ADS7961 ADS7952 ADS7956 ADS7960 ADS7951 ADS7955 ADS7959 ADS7950 ADS7954 ADS7958 26 26 19 19 22 22 Digital output I/O Digital output DESCRIPTION Serial data output pin GENERAL-PURPOSE INPUT/OUTPUT (1) GPIO0 Alarm Digital I/O 29 29 General purpose input or output Active high alarm output. For configuration, see the Programming section. POWER SUPPLY AND GROUND +VA 21, 32 21, 32 1, 14 1, 14 — Analog power supply AGND 1, 22 1, 22 2, 15 2, 15 — Analog ground +VBD 28 28 21 21 — Digital I/O supply BDGND 27 27 20 20 — Digital ground — 5, 6, 19, 20 — 6, 7, 12, 13 — Pins internally not connected, do not float these pins, connect these pins to ground NC PINS — (1) This pin has programmable dual functionality. See Table 12 for functionality programming. Copyright © 2008–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 9 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605C – JUNE 2008 – REVISED JULY 2018 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT AINP or CHn to AGND –0.3 VA +0.3 V +VA to AGND, +VBD to BDGND –0.3 7 V Digital input voltage to BDGND –0.3 7 V Digital output to BDGND –0.3 VA + 0.3 V Input current to any pin except supply pins –10 10 mA Operating temperature –40 125 °C 150 °C 150 °C Junction temperature (TJ Max) Storage temperature (Tstg) (1) (2) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DBT packaged versions of ADS79xx family devices are rated for MSL2 260°C per the JSTD-020 specifications and the RGE and RHB packaged versions of ADS79xx family devices are rated for MSL3 260C per JSTD-020 specifications 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT V(+VA) Analog power-supply voltage 2.7 3.3 5.25 V V(+VBD) Digital I/O-supply voltage 1.7 3.3 V(+VA) V V(REF) Reference voltage 2 2.5 3 V ƒ(SCLK) SCLK frequency 20 MHz TA Operating temperature range 125 °C 10 Submit Documentation Feedback –40 Copyright © 2008–2018, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605C – JUNE 2008 – REVISED JULY 2018 7.4 Thermal Information: TSSOP ADS795x THERMAL METRIC (1) DBT (TSSOP) DBT (TSSOP) 38 PINS 30 PINS UNIT RθJA Junction-to-ambient thermal resistance 83.6 89.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 29.8 22.9 °C/W RθJB Junction-to-board thermal resistance 44.7 43.1 °C/W ψJT Junction-to-top characterization parameter 2.9 0.8 °C/W ψJB Junction-to-board characterization parameter 44.1 42.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 7.5 Thermal Information: VQFN ADS7953, ADS7957, ADS7961 THERMAL METRIC (1) RHB (VQFN) RGE (VQFN) 32 PINS 24 PINS UNIT RθJA Junction-to-ambient thermal resistance 40.6 36.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 32.1 39.3 °C/W RθJB Junction-to-board thermal resistance 13.1 14.7 °C/W ψJT Junction-to-top characterization parameter 0.8 0.7 °C/W ψJB Junction-to-board characterization parameter 13 14.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 5.7 5.6 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Copyright © 2008–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 11 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605C – JUNE 2008 – REVISED JULY 2018 www.ti.com 7.6 Electrical Characteristics: ADS7950, ADS7951, ADS7952, ADS7953 VA = 2.7 V to 5.25 V, VBD = 1.7 V to +VA, VREF = 2.5 V ± 0.1 V, TA = –40°C to 125°C, fsample = 1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full-scale input span (1) Absolute input range Range 1 0 VREF Range 2 while 2xVREF ≤ +VA 0 2*VREF Range 1 –0.2 VREF + 0.2 Range 2 while 2xVREF ≤ +VA –0.2 2*VREF + 0.2 Input capacitance Input leakage current TA = 125°C V V 15 pF 61 nA 12 Bits SYSTEM PERFORMANCE Resolution No missing codes Integral linearity Differential linearity ADS795XSB (2) 12 ADS795XS (2) 11 ADS795XSB (2) ADS795XS (2) ADS795XSB (2) ADS795XS (2) Offset error (4) Range 1 Gain error Bits –1 ±0.5 1 –1.5 ±0.75 1.5 –0.99 ±0.5 1 –2 ±0.75 1.5 –3.5 ±1.1 3.5 –2 ±0.2 2 Range 2 ±0.2 Total unadjusted error (TUE) ±2 LSB (3) LSB LSB LSB LSB SAMPLING DYNAMICS Conversion time 20 MHz SCLK Acquisition time Maximum throughput rate 800 325 ns ns 20 MHz SCLK 1 MHz Aperture delay 5 ns Step response 150 ns Overvoltage recovery 150 ns (1) (2) (3) (4) 12 Ideal input span; does not include gain or offset error. ADS795X, where X indicates 0, 1, 2, or 3. LSB means least significant bit. Measured relative to an ideal full-scale input. Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605C – JUNE 2008 – REVISED JULY 2018 Electrical Characteristics: ADS7950, ADS7951, ADS7952, ADS7953 (continued) VA = 2.7 V to 5.25 V, VBD = 1.7 V to +VA, VREF = 2.5 V ± 0.1 V, TA = –40°C to 125°C, fsample = 1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP 100 kHz, ADS795XSB (2) 70 71.7 100 kHz, ADS795XS (2) 70 71.7 100 kHz, ADS795XSB (2) 69 71.3 100 kHz, ADS795XS (2) 68 71.3 MAX UNIT DYNAMIC CHARACTERISTICS Total harmonic distortion (5) Signal-to-noise ratio Signal-to-noise + distortion 100 kHz –82 dB dB dB Spurious free dynamic range 100 kHz 84 dB Small signal bandwidth At –3 dB 47 MHz Channel-to-channel crosstalk Any off-channel with 100 kHz, Full-scale input to channel being sampled with DC input (isolation crosstalk). –95 From previously sampled to channel with 100 kHz, Full-scale input to channel being sampled with DC input (memory crosstalk). –85 dB EXTERNAL REFERENCE INPUT VREF reference voltage at REFP (6) Reference input resistance 2 At fsample = 1 MHz 2.5 3 V 100 kΩ ALARM SETTING High threshold range 0 4092 LSB Low threshold range 0 4092 LSB DIGITAL INPUT/OUTPUT Logic family CMOS VIH Logic level 0.7*(+VBD) VIL +VBD = 5 V 0.8 VIL +VBD = 3 V 0.4 V VOH At Isource = 200 μA VOL At Isink = 200 μA +VBD-0.2 0.4 Data format MSB first MSB First POWER SUPPLY REQUIREMENTS +VA supply voltage 2.7 3.3 5.25 V +VBD supply voltage 1.7 3.3 5.25 V At +VA = 2.7 to 3.6 V and 1 MHz throughput Supply current (normal mode) At +VA = 2.7 to 3.6 V static state 1.05 At +VA = 4.7 to 5.25 V and 1 MHz throughput 2.3 3 At +VA = 4.7 to 5.25 V static state 1.1 1.5 Power-down state supply current +VBD supply current 1.8 +VA = 5.25 V, fs = 1MHz 1 μA 1 mA Power-up time 1 Invalid conversions after power up or reset 1 (5) (6) mA μs Conversion Calculated on the first nine harmonics of the input frequency. Device is designed to operate over VREF = 2 V to 3 V. However one can expect lower noise performance at Vref < 2.4 V. This is due to SNR degradation resulting from lowered signal range. Copyright © 2008–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 13 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605C – JUNE 2008 – REVISED JULY 2018 www.ti.com 7.7 Electrical Characteristics, ADS7954, ADS7955, ADS7956, ADS7957 +VA = 2.7 V to 5.25 V, +VBD = 1.7 V to +VA, VREF = 2.5 V ± 0.1 V, TA = –40°C to 125°C, fsample = 1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full-scale input span (1) Absolute input range Range 1 0 VREF Range 2 while 2xVREF ≤ +VA 0 2*VREF Range 1 –0.20 VREF +0.20 Range 2 while 2xVREF ≤ +VA –0.20 2*VREF +0.20 Input capacitance Input leakage current TA = 125°C V V 15 pF 61 nA 10 Bits SYSTEM PERFORMANCE Resolution No missing codes 10 Bits Integral linearity –0.5 ±0.2 0.5 LSB (2) Differential linearity –0.5 ±0.2 0.5 LSB Offset error (3) –1.5 ±0.5 1.5 LSB –1 ±0.1 1 Range 1 Gain error Range 2 ±0.1 LSB SAMPLING DYNAMICS Conversion time 20 MHz SCLK 800 Acquisition time Maximum throughput rate 325 ns ns 20 MHz SCLK 1 MHz Aperture delay 5 ns Step response 150 ns Overvoltage recovery 150 ns –80 dB DYNAMIC CHARACTERISTICS Total harmonic distortion (4) 100 kHz Signal-to-noise ratio 100 kHz 60 Signal-to-noise + distortion 100 kHz 60 Spurious free dynamic range 100 kHz 82 dB Full power bandwidth At –3 dB 47 MHz Channel-to-channel crosstalk dB Any off-channel with 100 kHz, Full-scale input to channel being sampled with DC input. –95 From previously sampled to channel with 100 kHz, Full-scale input to channel being sampled with DC input. –85 dB EXTERNAL REFERENCE INPUT VREF reference voltage at REFP Reference input resistance 2 fsample = 1 MHz 2.5 3 100 V kΩ ALARM SETTING High threshold range 000 4092 LSB Low threshold range 000 4092 LSB (1) (2) (3) (4) 14 Ideal input span; does not include gain or offset error. LSB means least significant bit. Measured relative to an ideal full-scale input. Calculated on the first nine harmonics of the input frequency. Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605C – JUNE 2008 – REVISED JULY 2018 Electrical Characteristics, ADS7954, ADS7955, ADS7956, ADS7957 (continued) +VA = 2.7 V to 5.25 V, +VBD = 1.7 V to +VA, VREF = 2.5 V ± 0.1 V, TA = –40°C to 125°C, fsample = 1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT Logic family CMOS VIH Logic level 0.7*(+VBD) VIL +VBD = 5 V 0.8 VIL +VBD = 3 V VOH At Isource = 200 μA VOL At Isink = 200 μA 0.4 V +VBD-0.2 0.4 Data format MSB first MSB First POWER SUPPLY REQUIREMENTS +VA supply voltage 2.7 3.3 5.25 V +VBD supply voltage 1.7 3.3 5.25 V At +VA = 2.7 to 3.6 V and 1MHz throughput Supply current (normal mode) 1.8 At +VA = 2.7 to 3.6 V static state 1.05 1 At +VA = 4.7 to 5.25 V and 1 MHz throughput 2.3 3 At +VA = 4.7 to 5.25 V static state 1.1 1.5 Power-down state supply current +VBD supply current +VA = 5.25V, fs = 1MHz mA 1 μA 1 mA Power-up time 1 Invalid conversions after power up or reset 1 μs Conversion 7.8 Electrical Characteristics, ADS7958, ADS7959, ADS7960, ADS7961 +VA = 2.7 V to 5.25 V, +VBD = 1.7 V to +VA, VREF = 2.5 V ± 0.1 V, TA = –40°C to 125°C, fsample = 1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full-scale input span (1) Absolute input range Range 1 0 VREF Range 2 while 2xVREF ≤ +VA 0 2*VREF Range 1 –0.20 VREF + 0.2 Range 2 while 2xVREF ≤ +VA –0.20 2*VREF + 0.2 Input capacitance Input leakage current TA = 125°C V V 15 pF 61 nA 8 Bits SYSTEM PERFORMANCE Resolution No missing codes 8 Bits Integral linearity –0.3 ±0.1 0.3 LSB (2) Differential linearity –0.3 ±0.1 0.3 LSB Offset error (3) –0.5 ±0.2 0.5 LSB –0.6 ±0.1 0.6 Gain error (1) (2) (3) Range 1 Range 2 ±0.1 LSB Ideal input span; does not include gain or offset error. LSB means least significant bit. Measured relative to an ideal full-scale input. Copyright © 2008–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 15 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605C – JUNE 2008 – REVISED JULY 2018 www.ti.com Electrical Characteristics, ADS7958, ADS7959, ADS7960, ADS7961 (continued) +VA = 2.7 V to 5.25 V, +VBD = 1.7 V to +VA, VREF = 2.5 V ± 0.1 V, TA = –40°C to 125°C, fsample = 1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 800 ns SAMPLING DYNAMICS Conversion time 20 MHz SCLK Acquisition time 325 Maximum throughput rate ns 20 MHz SCLK 1 MHz Aperture delay 5 ns Step response 150 ns Overvoltage recovery 150 ns –75 dB DYNAMIC CHARACTERISTICS Total harmonic distortion (4) 100 kHz Signal-to-noise ratio 100 kHz 49 Signal-to-noise + distortion 100 kHz 49 Spurious free dynamic range 100 kHz –78 dB Full power bandwidth At –3 dB 47 MHz Channel-to-channel crosstalk dB Any off-channel with 100 kHz, Full-scale input to channel being sampled with DC input. –95 From previously sampled to channel with 100 kHz, Full-scale input to channel being sampled with DC input. –85 dB EXTERNAL REFERENCE INPUT VREF reference voltage at REFP Reference input resistance 2 fsample = 1 MHz 2.5 3 V 100 kΩ ALARM SETTING High threshold range 000 255 LSB Low threshold range 000 255 LSB DIGITAL INPUT/OUTPUT Logic family CMOS VIH Logic level 0.7*(+VBD) VIL +VBD = 5 V VIL +VBD = 3 V VOH At Isource = 200 μA VOL At Isink = 200 μA Data format 0.8 0.4 V +VBD-0.2 0.4 MSB First POWER SUPPLY REQUIREMENTS +VA supply voltage 2.7 3.3 5.25 V +VBD supply voltage 1.7 3.3 5.25 V At +VA = 2.7 to 3.6 V and 1 MHz throughput Supply current (normal mode) At +VA = 2.7 to 3.6 V static state At +VA = 4.7 to 5.25 V and 1 MHz throughput 2.3 3 At +VA = 4.7 to 5.25 V static state 1.1 1.5 Power-down state supply current +VBD supply current 1.8 1.05 +VA = 5.25V, fs = 1MHz 1 μA 1 mA Power-up time 1 Invalid conversions after power up or reset 1 (4) 16 mA μs Conversion Calculated on the first nine harmonics of the input frequency. Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605C – JUNE 2008 – REVISED JULY 2018 7.9 Timing Requirements All specifications typical at –40°C to 125°C, +VA = 2.7 V to 5.25 V (unless otherwise specified) (1) (2) (see Figure 1, Figure 2, Figure 3, and Figure 4) MIN tconv tq td1 Conversion time Minimum quiet sampling time needed from bus 3state to start of next conversion Delay time, CS low to first data (DO–15) out td2 th1 td3 tsu2 th2 tw1 td4 twh twl Setup time, CS low to first rising edge of SCLK Delay time, SCLK falling to SDO next data bit valid Hold time, SCLK falling to SDO data bit valid Delay time, 16th SCLK falling edge to SDO 3-state Setup time, SDI valid to rising edge of SCLK Hold time, rising edge of SCLK to SDI valid Pulse duration CS high Delay time CS high to SDO 3-state Pulse duration SCLK high Pulse duration SCLK low Frequency SCLK (1) (2) MAX 16 +VBD = 3 V 16 +VBD = 5 V 16 +VBD = 1.8 V 40 +VBD = 3 V 40 +VBD = 5 V 40 UNIT SCLK ns +VBD = 1.8 V 38 +VBD = 3 V 27 +VBD = 5 V tsu1 NOM +VBD = 1.8 V ns 17 +VBD = 1.8 V 8 +VBD = 3 V 6 +VBD = 5 V 4 ns +VBD = 1.8 V 35 +VBD = 3 V 27 +VBD = 5 V 17 +VBD = 1.8 V 7 +VBD = 3 V 5 +VBD = 5 V 3 ns +VBD = 1.8 V 26 +VBD = 3 V 22 +VBD = 5 V 13 +VBD = 1.8 V 2 +VBD = 3 V 3 +VBD = 5 V 4 +VBD = 1.8 V 12 +VBD = 3 V 10 +VBD = 5 V 6 +VBD = 1.8 V 20 +VBD = 3 V 20 +VBD = 5 V 20 ns ns 24 +VBD = 3 V 21 +VBD = 5 V 12 20 +VBD = 3 V 20 +VBD = 5 V 20 +VBD = 1.8 V 20 +VBD = 3 V 20 +VBD = 5 V 20 ns ns +VBD = 1.8 V +VBD = 1.8 V ns ns ns ns +VBD = 1.8 V 20 +VBD = 3 V 20 +VBD = 5 V 20 MHz 1.8V specifications apply from 1.7 V to 1.9 V, 3 V specifications apply from 2.7 V to 3.6 V, 5 V specifications apply from 4.75 V to 5.25 V. With 50-pF load Copyright © 2008–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 17 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605C – JUNE 2008 – REVISED JULY 2018 www.ti.com Frame n Frame n + 1 CS 1 3 5 9 7 11 13 15 16 1 3 5 9 7 11 13 15 16 SCLK Top 4 Bit SDO Top 4 Bit 12-Bit Conversion Result SDI 12-Bit Conversion Result 16-Bit I/P Word 16-Bit I/P Word Mux Chan Change Mux Chan Change Analog I/P Settling After Chan Change MUX Sampling Instance Acquisition Acquisition Phase tacq Conversion Conversion Phase tcnv Conversion Phase Data Written (through SDI) in Frame n – 1 GPO Data Written (through SDI) in Frame n GPI GPI status is latched in on CS falling edge and transferred to SDO frame n Figure 1. Device Operation Timing Diagram a 1/t Throughput (Single Frame) CS tw1 tsu1 SCLK 1 td1 SDO 2 3 th1 DO15 DO-14 4 5 6 15 14 16 td3 td2 DO-13 DO-12 DO-11 MSB DO-10 MSB-1 DO-2 LSB+2 DO-1 LSB+1 DO-0 LSB tq tsu2 SDI DI-15 DI-14 DI-13 DI-12 DI-11 DI-10 DI-2 DI-1 DI-0 th2 Figure 2. Serial Interface Timing Diagram for 12-Bit Devices (ADS7950/51/52/53) 18 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605C – JUNE 2008 – REVISED JULY 2018 a 1/t Throughput (Single Frame) CS tw1 tsu1 SCLK 1 3 2 th1 td1 DO15 SDO 4 5 6 15 14 16 td3 td2 DO-14 DO-13 DO-12 DO-11 MSB DO-10 MSB-1 DO-2 LSB DO-1 DO-0 tq tsu2 SDI DI-15 DI-14 DI-13 DI-12 DI-11 DI-10 DI-2 DI-1 DI-0 th2 Figure 3. Serial Interface Timing Diagram for 10-Bit Devices (ADS7954/55/56/57) a 1/t Throughput (Single Frame) CS tw1 tsu1 SCLK 1 th1 td1 SDO 3 2 DO15 DO-14 4 5 6 12 13 16 td3 td2 DO-13 DO-12 DO-11 MSB DO-10 MSB-1 DO-4 LSB DO-3 DO-0 tq tsu2 SDI DI-15 DI-14 DI-13 DI-12 DI-11 DI-10 DI-4 DI-3 DI-0 th2 Figure 4. Serial Interface Timing Diagram for 8-Bit Devices (ADS7958/59/60/61) Copyright © 2008–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 19 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605C – JUNE 2008 – REVISED JULY 2018 www.ti.com 7.10 Typical Characteristics (All ADS79xx Family Devices) 1.5 3.5 TA = 25°C 1.4 3 +VA - Supply Current - mA +VA - Supply Current - mA fS = 1 MSPS, TA = 25°C 2.5 2 1.5 1 2.7 1.3 1.2 1.1 1 3.4 4.1 4.8 +VA - Supply Voltage - V 0.9 2.7 5.5 Figure 5. Supply Current vs Supply Voltage 3.4 4.1 4.8 +VA - Supply Voltage - V 5.5 Figure 6. Static Supply Current vs Supply Voltage 1.115 1.11 3.2 +VA - Supply Current - mA +VA - Supply Current - mA VDD = 5.5 V fS = 1 MSPS, VDD = 5.5 V 3.4 3 2.8 2.6 2.4 2.2 1.105 1.1 1.095 1.09 1.085 1.08 1.075 2 -40 15 70 TA - Free-Air Temperature - °C 1.07 -40 125 Figure 7. Supply Current vs Free-Air Temperature 2.5 No Powerdown, TA = 25°C With Powerdown, TA = 25°C 5V 2 +VA - Supply Current - mA +VA - Supply Current - mA 125 Figure 8. Static Supply Current vs Free-Air Temperature 2.5 2.7 V 1.5 1 0.5 2 5V 1.5 2.7 V 1 0.5 0 0 0 200 400 600 800 fS - Sample Rate - KSPS 1000 Figure 9. Supply Current vs Sample Rate 20 15 70 TA - Free-Air Temperature - °C Submit Documentation Feedback 0 100 200 300 400 fS - Sample Rate - KSPS 500 Figure 10. Supply Current vs Sample Rate Copyright © 2008–2018, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605C – JUNE 2008 – REVISED JULY 2018 7.11 Typical Characteristics (12-Bit Devices Only) Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves 1 fS = 1 MSPS, TA = 25°C 0.6 INL - Integral Nonlinearity - LSBs DNL - Differential Nonlinearity - LSBs 1 0.8 DNL max 0.4 0.2 0 -0.2 DNL min -0.4 -0.6 -0.8 -1 2.7 3.2 4.2 4.7 3.7 +VA - Supply Voltage - V 5.2 0.6 DNL max 0 -0.2 DNL min -0.4 -0.6 15 70 TA - Free-Air Temperature - °C 3.2 3.7 4.2 4.7 +VA - Supply Voltage - V 0.6 +VA = 5 V, +VBD = 5 V, fS = 1 MSPS 5.2 INL max 0.4 0.2 0 -0.2 INL min -0.4 -0.6 -1 -40 125 15 70 TA - Free-Air Temperature - °C 125 Figure 14. Integral Nonlinearity vs Free-Air Temperature 2 2 +VBD = 1.8 V, fS = 1 MSPS, TA = 25°C 1.8 1.6 Offset Error - LSBs Offset Error - LSBs -0.6 -0.8 Figure 13. Differential Nonlinearity vs Free-Air Temperature 1.4 1.2 1 0.8 0.6 1.2 1 0.8 0.6 0.4 0.2 0.2 3.4 4.1 4.8 +VA - Supply Voltage - V 5.5 Figure 15. Offset Error vs Supply Voltage Copyright © 2008–2018, Texas Instruments Incorporated +VA = 5.5 V, fS = 1 MSPS, TA = 25°C 1.4 0.4 0 2.7 INL min -0.4 Figure 12. Integral Nonlinearity vs Supply Voltage -0.8 1.6 0 -0.2 0.8 0.2 1.8 0.2 1 +VA = 5 V, +VBD = 5 V, fS = 1 MSPS 0.4 -1 -40 INL max 0.4 -1 2.7 5.5 INL - Integral Nonlinearity - LSBs DNL - Differential Nonlinearity - LSBs 0.8 0.6 fS = 1 MSPS, TA = 25°C -0.8 Figure 11. Differential Nonlinearity vs Supply Voltage 1 0.8 0 1.8 2.3 2.8 3.3 3.8 4.3 4.8 +VBD - Interace Supply - V 5.3 5.5 Figure 16. Offset Error vs Interface Supply Voltage Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 21 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605C – JUNE 2008 – REVISED JULY 2018 www.ti.com Typical Characteristics (12-Bit Devices Only) (continued) Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves 1 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 0.4 0.2 0 -0.2 -0.4 -0.6 -0.6 -0.8 -0.8 -1 2.7 3.4 4.1 4.8 +VA - Supply Voltage - V -1 1.8 5.5 Figure 17. Gain Error vs Supply Voltage 0.8 1.2 1 0.8 0.6 0.5 0.4 0.3 0.2 0.1 15 70 TA - Free-Air Temperature - °C 71 70.5 +VBD = 3 V, fS = 1 MSPS, fIN = 100 kHz TA = 25°C 69.5 3.4 4.1 4.8 +VA - Supply Voltage - V 5.5 Figure 21. Signal-to-Noise Ratio vs Supply Voltage Submit Documentation Feedback 15 70 TA - Free-Air Temperature - °C 125 Figure 20. Gain Error vs Free-Air Temperature SINAD - Signal-to-Noise and Distortion - dB 71.5 70 0 -40 125 72 SNR - Signal-to-Noise Ratio - dB 0.6 0.2 Figure 19. Offset Error vs Free-Air Temperature 22 0.7 0.4 69 2.7 5.3 5.5 +VA = 5.5 V, +VBD = 1.8 V, fS = 1 MSPS 0.9 1.4 0 -40 2.8 3.3 3.8 4.3 4.8 +VBD - Interace Supply - V 1 +VA = 5.5 V, +VBD = 1.8 V, fS = 1 MSPS Gain Error - LSBs Offset Error - LSBs 1.6 2.3 Figure 18. Gain Error vs Interface Supply Voltage 2 1.8 +VA = 5.5 V, fS = 1 MSPS, TA = 25°C 0.8 Gain Error - LSBs Gain Error - LSBs 0.6 +VBD = 1.8 V, fS = 1 MSPS, TA = 25°C 72 71.5 71 70.5 +VBD = 3 V, fS = 1 MSPS, fIN = 100 kHz TA = 25°C 70 69.5 69 2.7 3.4 4.1 4.8 +VA - Supply Voltage - V 5.5 Figure 22. Signal-to-Noise + Distortion vs Supply Voltage Copyright © 2008–2018, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605C – JUNE 2008 – REVISED JULY 2018 Typical Characteristics (12-Bit Devices Only) (continued) Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves SFDR - Spurious Free Dynamic Range - dB -80 THD - Total Harmonic Distortion - -81 -82 -83 -84 -85 -86 -87 -88 -89 -90 2.7 +VBD = 3 V, fS = 1 MSPS, fIN = 100 kHz TA = 25°C 3.4 4.1 4.8 +VA - Supply Voltage - V 5.5 Figure 23. Total Harmonic Distortion vs Supply Voltage 71.5 71 70.5 70 69.5 69 -40 +VA = 5 V +VBD = 3 V, fS = 1 MSPS, fIN = 100 kHz 15 70 TA - Free-Air Temperature - °C 125 Figure 25. Signal-To-Noise Ratio vs Free-Air Temperature -81 -82 -83 -84 -85 -86 -87 -88 -89 -90 -40 +VA = 5 V +VBD = 3 V, fS = 1 MSPS, fIN = 100 kHz 15 70 TA - Free-Air Temperature - °C 125 Figure 27. Total Harmonic Distortion vs Free-Air Temperature Copyright © 2008–2018, Texas Instruments Incorporated 88 87 +VBD = 3 V, fS = 1 MSPS, fIN = 100 kHz TA = 25°C 86 85 84 83 82 81 80 2.7 3.4 4.1 4.8 +VA - Supply Voltage - V 5.5 72 71.5 +VA = 5 V +VBD = 3 V, fS = 1 MSPS, fIN = 100 kHz 71 70.5 70 69.5 69 -40 15 70 TA - Free-Air Temperature - °C 125 Figure 26. Signal-to-Noise + Distortion vs Free-Air Temperature SFDR - Spurious Free Dynamic Range - dB THD - Total Harmonic Distortion - dB -80 89 Figure 24. Spurious Free Dynamic Range vs Supply Voltage SINAD - Signal-to-Noise and Distortion - dB SNR - Signal-to-Noise Ratio - dB 72 90 90 89 88 87 +VA = 5 V +VBD = 3 V, fS = 1 MSPS, fIN = 100 kHz 86 85 84 83 82 81 80 -40 15 70 TA - Free-Air Temperature - °C 125 Figure 28. Spurious Free Dynamic Range vs Free-Air Temperature Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 23 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605C – JUNE 2008 – REVISED JULY 2018 www.ti.com Typical Characteristics (12-Bit Devices Only) (continued) Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves SINAD - Signal-to-Noise and Distortion - dB SNR - Signal-to-Noise Ratio - dB 73 72.5 72 71.5 71 70.5 +VA = 5 V +VBD = 3 V, fS = 1 MSPS, TA = 25°C, MXO Shorted to AINP 70 69.5 69 10 30 50 70 90 110 130 fIN - Input Frequency - KHz 150 Figure 29. Signal-to-Noise Ratio vs Input Frequency -72 -74 -76 +VA = 5 V +VBD = 3 V, fS = 1 MSPS, TA = 25°C, MXO Shorted to AINP -78 -80 -82 -84 -86 -88 -90 10 30 50 70 90 110 130 fIN - Input Frequency - KHz 150 72 71.5 1000 W 71 10 W 70 69.5 69 20 100 W +VA = 5 V +VBD = 5 V, fS = 1 MSPS, TA = 25°C, Buffer Between MXO and AINP 40 60 80 fIN - Input Frequency - KHz 100 Figure 33. Signal-to-Noise + Distortion vs Input Frequency (Across Different Source Resistance Values) 24 71.5 71 70.5 70 69.5 69 10 30 50 70 90 110 130 fIN - Input Frequency - KHz 150 100 +VA = 5 V +VBD = 3 V, fS = 1 MSPS, TA = 25°C, MXO Shorted to AINP 95 90 85 80 75 70 10 30 50 70 90 110 130 fIN - Input Frequency - KHz 150 -70 500 W 70.5 72 Figure 32. Spurious Free Dynamic Range vs Input Frequency THD - Total Harmonic Distortion - dB SINAD - Signal-to-Noise and Distortion - dB Figure 31. Total Harmonic Distortion vs Input Frequency +VA = 5 V +VBD = 3 V, fS = 1 MSPS, TA = 25°C, MXO Shorted to AINP 72.5 Figure 30. Signal-to-Noise + Distortion vs Input Frequency SFDR - Spurious Free Dynamic Range - dB THD - Total Harmonic Distortion - dB -70 73 Submit Documentation Feedback +VA = 5 V +VBD = 5 V, fS = 1 MSPS, TA = 25°C, Buffer Between MXO and AINP -72 -74 -76 1000 W -78 500 W -80 -82 10 W -84 100 W -86 -88 -90 20 40 60 80 fIN - Input Frequency - KHz 100 Figure 34. Total Harmonic Distortion vs Input Frequency (Across Different Source Resistance Values) Copyright © 2008–2018, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605C – JUNE 2008 – REVISED JULY 2018 Typical Characteristics (12-Bit Devices Only) (continued) 1 90 DNL - Differential Nonlinearity - LSBs SFDR - Spurious Free Dynamic Range - dB Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves 88 10 W 86 100 W 84 82 80 1000 W 500 W 78 76 +VA = 5 V +VBD = 5 V, fS = 1 MSPS, TA = 25°C, Buffer Between MXO and AINP 74 72 70 20 40 60 80 fIN - Input Frequency - KHz 1 0.2 0 -0.2 -0.6 -0.8 0 -0.2 INL min -0.4 -0.6 +VA = 5 V, +VBD = 5 V, fS = 1 MSPS -0.8 -1 0 5 10 Channel Number 15 +VA = 5 V, +VBD = 5 V, fS = 1 MSPS 0.6 0.2 DNL min -0.4 1.4 INL max EO - Offset Error - LSBs INL - Integral Nonlinearity - LSBs 0.4 1.6 0.4 DNL max Figure 36. Differential Nonlinearity Variation Across Channels 0.8 1.2 1 0.8 0.6 0.4 0.2 0 5 10 Channel Number 15 Figure 37. Integral Nonlinearity Variation Across Channels 0 5 10 15 Channel Number 20 Figure 38. Offset Error Variation Across Channels 73 0.25 SNR - Signal-to-Noise Ratio - dB +VA = 5 V, +VBD = 5 V, fS = 1 MSPS 0.2 EG - Gain Error - LSBs 0.6 +VA = 5 V, +VBD = 5 V, fS = 1 MSPS -1 0 100 Figure 35. Spurious Free Dynamic Range vs Input Frequency (Across Different Source Resistance Values) 0.8 0.15 0.1 0.05 0 72.5 72 71.5 71 70.5 +VA = 5 V, +VBD = 5 V, fS = 1 MSPS 70 0 5 10 15 Channel Number 20 Figure 39. Gain Error Variation Across Channels Copyright © 2008–2018, Texas Instruments Incorporated 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Channel Number Figure 40. Signal-to-Noise Ratio Variation Across Channels Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 25 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605C – JUNE 2008 – REVISED JULY 2018 www.ti.com Typical Characteristics (12-Bit Devices Only) (continued) 120 73 72.5 +VA = 5 V, +VBD = 5 V, fS = 1 MSPS Isolation 100 72 Crosstalk - dB SINAD - Signal-to-Noise and Distortion - dB Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves 71.5 71 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Channel Number Figure 41. Signal-to-Noise + Distortion Variation Across Channels 40 +VA = 5 V, +VBD = 5 V, fS = 1 MSPS, CH0, CH1 50 100 150 200 fIN - Input Frequency - KHz 250 Figure 42. Crosstalk vs Input Frequency 100 25 +VA = 5 V, +VBD = 5 V 80 20 70 Number of Devices AINP - Leakage Current - nA 60 0 0 70 60 50 VI = 0 V 40 VI = 1.25 V 30 20 Memory 20 70.5 90 80 VI = 2.5 V 15 10 5 10 0 -40 -25 -10 5 0 20 35 50 65 80 95 110 125 0.25 0.5 0.75 1 1.25 1.5 1.75 TUE Max - LSB TA - Free-Air Temperature - °C Figure 43. Input Leakage Current vs Free-Air Temperature 2 Figure 44. Total Unadjusted Error (TUE Maximum) 25 Number of Devices 20 15 10 5 1 0.5 0.75 0 0.25 -0.5 -0.25 -1 -0.75 -1.5 -1.25 -1.75 0 TUE Min- LSB Figure 45. Total Unadjusted Error (TUE Minimum) 26 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605C – JUNE 2008 – REVISED JULY 2018 7.12 Typical Characteristics (12-Bit Devices Only) INL DNL 1 1 +VA = 5 V +VBD = 5 V, 0.8 0.6 fS = 1 MSPS, +VA = 5 V +VBD = 5 V, 0.6 fS = 1 MSPS 0.4 TA = 25°C INL - LSBs DNL - LSBs 0.4 0.8 0.2 0 -0.2 0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1 -1 0 1024 2048 3072 4096 0 1024 2048 4096 Figure 47. Typical INL for All Codes Figure 46. Typical DNL for All Codes FFT 0 Amplitude - dB 3072 Code Code -20 +VA = 5 V +VBD = 5 V, -40 fS = 1 MSPS, -60 fIN = 100 kHz Npoints = 16384 -80 -100 -120 -140 -160 0 100000 200000 300000 400000 500000 f - Frequency - Hz Figure 48. Typical FFT Plot Copyright © 2008–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 27 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605C – JUNE 2008 – REVISED JULY 2018 www.ti.com 8 Detailed Description 8.1 Overview The ADS7950 to ADS7961 are 12-, 10-, 8-bit multichannel pin-compatible devices. The ADS79xx is a family of 12-, 10-, 8-bit, high-speed, low-power, successive approximation register (SAR) analog-to-digital converter (ADC) that uses an external reference. The architecture is based on charge redistribution, which inherently includes a sample/hold function. The analog inputs to the ADS79xx are provided to CHX input channels. All input channels share a common analog ground AGND. ADS79xx has multiplexer breakout feature which allows user to connect the signal conditioning circuit between multiplexer output (MXO) and ADC input (AINP). This feature enables use of common signal conditioning block for the input signal which exhibit similar performance characteristics. ADS79xx can be programmed to select a channel manually or can be programmed into the auto channel select mode to sweep through the input channels automatically Figure 1, Figure 2, Figure 3, and Figure 4 show device operation timing. Device operation is controlled with CS, SCLK, and SDI. The device outputs its data on SDO. Each frame begins with the falling edge of CS. With the falling edge of CS, the input signal from the selected channel is sampled, and the conversion process is initiated. The device outputs data while the conversion is in progress. The 16-bit data word contains a 4-bit channel address, followed by a 12-bit conversion result in MSB first format. There is an option to read the GPIO status instead of the channel address. (Refer to Table 1, Table 2, and Table 5 for more details.) The device selects a new multiplexer channel on the second SCLK falling edge. The acquisition phase starts on the fourteenth SCLK rising edge. On the next CS falling edge the acquisition phase will end, and the device starts a new frame. The TSSOP packaged devices have four General Purpose IO (GPIO) pins while QFN versions have only one GPIO. These four pins can be individually programmed as GPO or GPI. It is also possible to use them for preassigned functions, refer to Table 11. GPO data can be written into the device through the SDI line. The device refreshes the GPO data on the CS falling edge as per the SDI data written in previous frame. Similarly the device latches GPI status on the CS falling edge and outputs the GPI data on the SDO line (if GPI read is enabled by writing DI04=1 in the previous frame) in the same frame starting with the CS falling edge. The falling edge of CS clocks out DO15 (first bit of the four bit channel address), and remaining address bits are clocked out on every falling edge of SCLK until the third falling edge. The conversion result MSB is clocked out on the 4th SCLK falling edge and LSB on the 15th/13th/11th falling edge respectively for 12/10/8-bit devices. On the 16th falling edge of SCLK, SDO goes to the 3-state condition. The conversion ends on the 16th falling edge of SCLK. CS can be asserted (pulled high) only after 16 clocks have elapsed The device reads a sixteen bit word on the SDI pin while it outputs the data on the SDO pin. SDI data is latched on every rising edge of SCLK starting with the 1st clock as shown in Figure 2, Figure 3, and Figure 4. CS can be asserted (pulled high) only after 16 clocks have elapsed. The device has two (high and low) programmable alarm thresholds per channel. If the input crosses these limits; the device flags out an alarm on GPIO0/GPIO1 depending on the GPIO program register settings (refer to Table 11). The alarm is asserted (under the alarm conditions) on the 12th falling edge of SCLK in the same frame when a data conversion is in progress. The alarm output is reset on the 10th falling edge of SCLK in the next frame. The device offers a power-down feature to save power when not in use. There are two ways to powerdown the device. It can be powered down by writing DI05 = 1 in the mode control register (refer to Table 1, Table 2, and Table 5); in this case the device powers down on the 16th falling edge of SCLK in the next data frame. Another way to powerdown the device is through GPIO in the case of the TSSOP packaged devices. GPIO3 can act as the PD input (refer to Table 11 to assign this functionality to GPIO3). This is an asynchronous and active low input. The device powers down instantaneously after GPIO3 (PD) = 0. The device will power up again on the CS falling edge with DI05 = 0 in the mode control register and GPIO3 (PD) = 1. 28 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605C – JUNE 2008 – REVISED JULY 2018 8.2 Functional Block Diagram REF MXO AINP Ch0 Ch1 +VA AGND ADC Ch2 SDO Compare Alarm Threshold Ch n* Control Logic & Sequencing GPIO BDGND SDI SCLK CS VBD NOTE: n* is number of channels (16,12,8, or 4) depending on the device from the ADS79xx product family. NOTE: There are 4 GPIOs in the TSSOP package and 1 GPIO in the QFN package.. 8.3 Feature Description 8.3.1 Reference The ADS79xx can operate with an external 2.5-V ± 10-mV reference. A clean, low noise, well-decoupled reference voltage on the REFP pin is required to ensure good performance of the converter. A low noise bandgap reference like the REF5025 can be used to drive this pin. A 10-μF ceramic decoupling capacitor is required between the REFP and REFM pins of the converter. The capacitor should be placed as close as possible to the pins of the device. 8.3.2 Power Saving The ADS79xx devices offer a power-down feature to save power when not in use. There are two ways to power down the device. It can be powered down by writing DI05 = 1 in the Mode Control register (refer to Table 1, Table 2 and Table 5); in this case the device powers down on the 16th falling edge of SCLK in the next data frame. Another way to powerdown the device is through GPIO. GPIO3 can act as a PD input (refer to Table 11, for assigning this functionality to GPIO3). This is an asynchronous and active low input. The device powers down instantaneously after GPIO3 (PD) = 0. The device will powerup again on the CS falling edge while DI05 = 0 in the Mode Control register and GPIO3 (PD) = 1. 8.4 Device Functional Modes 8.4.1 Channel Sequencing Modes There are three modes for channel sequencing, namely Manual mode, Auto-1 mode, Auto-2 mode. Mode selection is done by writing into the Mode Control Register (refer to Table 1, Table 2, and Table 5). A new multiplexer channel is selected on the second falling edge of SCLK (as shown in Figure 1) in all three modes. Manual mode: When configured to operate in Manual mode, the next channel to be selected is programmed in each frame and the device selects the programmed channel in the next frame. On powerup or after reset the default channel is 'Channel-0' and the device is in Manual mode. Auto-1 mode: In this mode the device scans pre-programmed channels in ascending order. A new multiplexer channel is selected every frame on the second falling edge of SCLK. There is a separate Program Register for pre-programming the channel sequence. Table 3 and Table 4 show Auto-1 ‘program register’ settings. Copyright © 2008–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 29 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605C – JUNE 2008 – REVISED JULY 2018 www.ti.com Device Functional Modes (continued) Once programmed the device retains ‘Program Register settings until the device is powered down, reset, or reprogrammed. It is allowed to exit and re-enter the Auto-1 mode any number of times without disturbing ‘program register’ settings. The Auto-1 program register is reset to FFFF/FFF/FF/F hex for the 16-, 12-, 8-, 4 channel devices respectively upon device powerup or reset; implying the device scans all channels in ascending order. Auto-2 mode: In this mode the user can configure the program register to select the last channel in the scan sequence. The device scans all channels from channel 0 up to and including the last channel in ascending order. The multiplexer channel is selected every frame on the second falling edge of SCLK. There is a separate ‘program register’ for pre-programming of the last channel in the sequence (multiplexer depth). Table 6 lists the ‘Auto-2 prog’ register settings for selection of the last channel in the sequence. Once programmed the device retains program register settings until the device is powered down, reset, or reprogrammed. It is allowed to exit and re-enter Auto-2 mode any number of times, without disturbing the ‘program register’ settings. On powerup or reset the bits D9-D6 of the Auto-2 program register are reset to F/B/7/3 hex for the 16/12/8/4 channel devices respectively; implying the device scans all channels in ascending order. 8.4.2 Device Programming and Mode Control The following section describes device programming and mode control. These devices feature two types of registers to configure and operate the devices in different modes. These registers are referred as ‘Configuration Registers’. There are two types of ‘Configuration Registers’ namely ‘Mode Control Registers’ and ‘Program Registers’. 8.4.2.1 Mode Control Register A ‘Mode Control Register’ is configured to operate the device in one of three channel sequencing modes, namely Manual mode, Auto-1 Mode, Auto-2 Mode. It is also used to control user programmable features like range selection, device power-down control, GPIO read control, and writing output data into the GPIO. 8.4.2.2 Program Registers The 'Program Registers’ are used for device configuration settings and are typically programmed once on powerup or after device reset. There are different program registers such as ‘Auto-1 mode programming’ for preprogramming the channel sequence, ‘Auto-2 mode programming’ for selection of the last channel in the sequence, ‘Alarm programming’ for all 16 channels (or 12, 8, 4 channels depending on the device) and GPIO for individual pin configuration as GPI or GPO or a pre-assigned function. 8.4.3 Device Power-Up Sequence The device power-up sequence is shown in Figure 49. By default, the Mode Control Register is configured for manual mode and the default channel is channel 0. As explained previously, these devices offer Program Registers to configure user programmable features like GPIOs, Alarms, and to pre-program the channel sequence for Auto modes. At ‘power up or on reset’ these registers are set to the default values listed in Table 1 to Table 11. On power up or after reset It is required to program Mode Control Register and Program Register to required mode of operation. Once configured; the device is ready to use in any of the three channel sequencing modes namely Manual, Auto-1, and Auto-2. 30 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605C – JUNE 2008 – REVISED JULY 2018 Device Functional Modes (continued) Device power up or reset Device operation in manual mode, Channel 0; SDO Invalid in first frame CS First frame CS Auto 1 register program (note 1) CS Auto 2 register program (note 1) CS Alarm register program (note 1) CS GPIO register program (note 1) CS CS Operation in Auto 1 mode Operation in manual mode CS Operation in Auto 2 mode (1) The device continues its operation in manual mode channel 0 throughout the programming sequence and outputs valid conversion results. It is possible to change channel, range, GPIO by inserting extra frames in between two programming blocks. It is also possible to bypass any programming block if the user does not intend to use that feature. (2) It is possible to reprogram the device at any time during operation, regardless of what mode the device is in. During programming the device continues its operation in whatever mode it is in and outputs valid data. Figure 49. Device Power-Up Sequence 8.4.4 Operating in Manual Mode The flowchart in Figure 50 illustrates the steps involved in operating in manual channel sequencing mode. Table 1 lists the mode control register settings for manual mode. There are no program registers in manual mode. Copyright © 2008–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 31 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605C – JUNE 2008 – REVISED JULY 2018 www.ti.com Device Functional Modes (continued) CS Frame: n-1 Device operation in Auto 1 or Auto 2 mode No Change to Manual mode? Yes CS Frame: n Request for Manual mode CS Frame: n+1 Entry into Manual Mode CS Frame: n+2 Operation in Manual mode * Sample: Samples and converts channel selected in ‘frame n-1’ * Mux : Selects channel incremented from previous frame as per auto sequence this channel will be acquired in this frame and sampled at start of ‘frame n+1’ * Range: As programmed in ‘frame n-1’ . Applies to channel selected for acquisition in current frame . * SDI : Programming for ‘frame n +1’ DI15..12 = 0001 binary …. Selects manual mode DI11=1 enables programming of ‘range and GPIO’ DI10..7 = binary address of channel DI6.. As per required range for channel to be selected DI5=0 .. No power down DI4..0… as per GPIO settings *SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n -1’ * GPIO : O/P: latched on CS falling edge as per DI3..0 written in frame n-1’ I/P: Input status latched on falling edge of CSand transferred serially on SDO in the same frame * Sample: Samples and converts channel selected in ‘frame n’ * Mux : Selects channel programmed in ‘frame n’(Manual mode) this channel will be acquired in this frame and sampled at start of ‘frame n+2’ * Range: As programmed in ‘frame n’. Applies to channel selected for acquisition in current frame .* SDI : Programming for ‘frame n+2’ DI15..12 = 0001 binary …. To continue in manual mode DI11=1 enables programming of ‘range and GPIO’ DI10..7 = binary address of channel DI6.. As per required range for channel to be selected DI5=0 .. No power down DI4..0… as per GPIO settings *SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n’ * GPIO : O/P: latched on CS falling edge as per DI3..0 written in frame ‘n’ I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same frame * Sample: Samples and converts channel selected in ‘frame n+1’ * Mux : Selects channel programmed in ‘frame n+1’ (Manual mode), this channel will be acquired in this frame and sampled at start of ‘frame n+3’ * Range: As programmed in ‘frame n+1’ . Applies to channel selected for acquisition in current frame.* SDI : Programming for ‘frame n+3’ DI15..12 = 0001 binary …. Selects manual mode DI11=1 enables programming of ‘range and GPIO’ DI10..7 = binary address of channel DI6.. As per required range for channel to be selected DI5=0 .. No power down DI4..0… as per GPIO settings *SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n+1’ * GPIO : O/P: latched on CS falling edge as per DI3..0 written in frame n+1’ I/P: Input status latched on falling edge of CSand transferred serially on SDO in the same frame CS Continue operation in manual mode Figure 50. Entering and Running in Manual Channel Sequencing Mode 32 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605C – JUNE 2008 – REVISED JULY 2018 Device Functional Modes (continued) Figure 51 shows an example in which manual mode is used to scan channels 4, 7, and 9. The command to select channel 4 (CH4) is issued in the Nth frame and the data corresponding to CH4 is available in the (N + 2)th frame. Internally, the SDI command is parsed and on the rising edge of CS of the (N+1)th frame and the MUX switches accordingly on the second falling edge of SCLK in this frame. On the rising edge of CS of the (N+2)th frame, the input signal for CH4 is sampled and the ADC sends the conversion data in this third frame. The device follows the same steps and the ADC sends the conversion data for CH7 and CH9 in the subsequent two frames. Sample CHx Sample CHy Sample CH4 Sample CH7 tCYCLE CS SCLK SDI Select CH4 Select CH7 Select CH9 Data CHx Data CHy Data CH4 SDO Frame N Frame (N + 1) Frame (N + 2) Figure 51. Example Manual Mode Timing Diagram Table 1. Mode Control Register Settings for Manual Mode RESET STATE BITS LOGIC STATE FUNCTION DI15-12 0001 0001 Selects Manual Mode DI11 0 1 Enables programming of bits DI06-00. 0 Device retains values of DI06-00 from the previous frame. DI10-07 0000 This four bit data represents the address of the next channel to be selected in the next frame. DI10: MSB and DI07: LSB. For example, 0000 represents channel- 0, 0001 represents channel-1 and so forth. DI06 0 0 Selects 0 to VREF input range (Range 1) 1 Selects 0 to 2xVREF input range (Range 2) 0 Device normal operation (no powerdown) 1 Device powers down on 16th SCLK falling edge 0 SDO outputs current channel address of the channel on DO15..12 followed by 12 bit conversion result on DO11..00. DI05 0 DI04 0 1 DI03-00 0000 GPIO3-GPIO0 data (both input and output) is mapped onto DO15-DO12 in the order shown below. Lower data bits DO11-DO00 represent 12-bit conversion result of the current channel. DOI5 DOI4 DOI3 DOI2 GPIO3 (1) GPIO2 (1) GPIO1 (1) GPIO0 (1) GPIO data for the channels configured as output. Device will ignore the data for the channel which is configured as input. SDI bit and corresponding GPIO information is given below DI03 GPIO3 (1) DI02 (1) GPIO2 DI01 (1) DI00 GPIO1 (1) GPIO0 (1) GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only. Copyright © 2008–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 33 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605C – JUNE 2008 – REVISED JULY 2018 www.ti.com 8.4.5 Operating in Auto-1 Mode Figure 52 illustrates the steps involved in entering and operating in Auto-1 Channel Sequencing mode. Table 2 lists the Mode Control Register settings for Auto-1 mode. CS Frame: n-1 Device operation in Manual or Auto-2 mode No Change to Auto -1 mode? Yes CS Frame: n Request for Auto-1 mode CS Frame: n+1 Entry into Auto-1 Mode CS Frame: n+2 Operation in Auto-1 mode * Sample: Samples and converts channel selected in ‘frame n -1’ * Mux : Selects channel incremented from previous frame as per Auto -2 sequence, or channel programmed in previous frame in case of manual mode. This channel will be acquired in this frame and sampled at start of ‘frame n +1’ * Range: As programmed in ‘frame n-1’ . Applies to channel selected for acquisition in current frame . * SDI : Programming for ‘frame n+1’ DI15..12 = 0010 binary …. Selects Auto-1 mode DI11=1 enables programming of ‘range and GPIO’ DI10 = x, Device automatically resets channel to lowest number in Auto -1 sequence. DI6.. As per required range for channel to be selected DI5=0 .. No power down DI4..0… as per GPIO settings *SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n -1’ * GPIO : O/P: latched on CS falling edge as per DI 3..0 written in frame n-1’ I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same frame * Sample: Samples and converts channel selected in ‘frame n’ * Mux : Selects lowest channel# in Auto-1 sequence; this channel will be acquired in this frame and sampled at start of ‘frame n+2’ * Range: As programmed in ‘frame n’. Applies to channel selected for acquisition in current frame . * SDI : Programming for ‘frame n +2’ DI15..12 = 0010 binary …. To continue in Auto-1 mode DI11=1 enables programming of ‘range and GPIO’ DI10 =0, not to reset channel sequence DI6.. As per required range for channel to be selected DI5=0 .. No power down DI4..0… as per GPIO settings *SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n’ * GPIO : O/P: latched on CS falling edge as per DI 3..0 written in frame ‘n’ I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same frame * Sample: Samples and converts channel selected in ‘frame n+1’ (ie. Lowest channel# in Auto-1 sequence) * Mux : Selects next higher channel in Auto -1 sequence, this channel will be acquired in this frame and sampled at start of ‘frame n +3’ * Range: As programmed in ‘frame n+1’ . Applies to channel selected for acquisition in current frame.* SDI : Programming for ‘frame n+3’ DI15..12 = 0010 binary …. To continue in Auto-1 mode DI11=1 enables programming of ‘range and GPIO’ DI10 =0 not to reset channel sequence DI6.. As per required range for channel to be selected DI5=0 .. No power down DI4..0… as per GPIO settings *SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n+1’ * GPIO : O/P: latched on CS falling edge as per DI3..0 written in frame n+1’ I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same frame CS Continue operation in Auto -1 mode Figure 52. Entering and Running in Auto-1 Channel Sequencing Mode 34 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605C – JUNE 2008 – REVISED JULY 2018 Consider a case where Auto-1 mode is selected to scan channels 2 (CH2), 5 (CH5), and 6 (CH6) as represented in Figure 53. The program register for Auto-1 mode must be programmed as described in Figure 53 before entering into this auto sequencing mode. The device enters into Auto-1 mode on receiving the Auto-1 mode command in the Nth frame. This step causes the device to find the first enabled channel in ascending order and switch the MUX for CH2 in the (N+1)th frame. In the (N+2)th frame, the ADC samples the signal on CH2, shifts out the conversion results, and the MUX also internally switches to CH5. In the (N+3)th frame, the ADC samples and shifts out the conversion result for CH5 and the MUX also internally switches to CH6. This process repeats until the last enabled channel is reached, in which case the process loops back to the first enabled channel. Entering Auto-1 mode from any other mode also causes the device to restart from the first enabled channel. However, modifying the contents of the Auto-1 mode program register while operating in Auto-1 mode causes the device to scan for the next enabled channel. Sample CHy Sample CH2 Sample CH5 Sample CH6 tCYCLE CS SCLK SDI SDO AUTO-1 Start AUTO-1 AUTO-1 AUTO1 AUTO-1 Data CHx Data CHy Data CH2 Data CH5 Data CH6 Frame N Frame (N + 1) Frame (N + 2) Frame (N + 3) Scan channels CH2 , CH5 and CH6 Figure 53. Example Auto-1 Mode Timing Diagram Copyright © 2008–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 35 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605C – JUNE 2008 – REVISED JULY 2018 www.ti.com Table 2. Mode Control Register Settings for Auto-1 Mode RESET STATE BITS LOGIC STATE FUNCTION DI15-12 0001 0010 Selects Auto-1 Mode DI11 0 1 Enables programming of bits DI10-00. 0 Device retains values of DI10-00 from previous frame. 1 The channel counter is reset to the lowest programmed channel in the Auto-1 Program Register DI10 0 0 The channel counter increments every conversion (No reset) DI09-07 000 xxx Do not care DI06 0 0 Selects 0 to VREF input range (Range 1) 1 Selects 0 to 2xVREF input range (Range 2) DI05 0 0 Device normal operation (no powerdown) 1 Device powers down on the 16th SCLK falling edge 0 SDO outputs current channel address of the channel on DO15..12 followed by 12-bit conversion result on DO11..00. DI04 0 1 DI03-00 (1) 36 0000 GPIO3-GPIO0 data (both input and output) is mapped onto DO15-DO12 in the order shown below. Lower data bits DO11-DO00 represent 12-bit conversion result of the current channel. DO15 DO14 DO13 DO12 GPIO3 (1) GPIO2 (1) GPIO1 (1) GPIO0 (1) GPIO data for the channels configured as output. Device will ignore the data for the channel which is configured as input. SDI bit and corresponding GPIO information is given below DI03 DI02 DI01 DI00 GPIO3 (1) GPIO2 (1) GPIO1 (1) GPIO0 (1) GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only. Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605C – JUNE 2008 – REVISED JULY 2018 The Auto-1 Program Register is programmed (once on powerup or reset) to pre-select the channels for the Auto1 sequence. Auto-1 Program Register programming requires two CS frames for complete programming. In the first CS frame the device enters the Auto-1 register programming sequence and in the second frame it programs the Auto-1 Program Register. Refer to Table 2, Table 3, and Table 4 for complete details. CS Device in any operation mode No Program Auto 1 register? Yes SDI: DI15..12 = 1000 (Device enters Auto 1 programming sequence) CS Entry into Auto 1 register programming sequence CS SDI: DI15..0 as per tables 4,5 Auto 1 register programming End of Auto 1 register programming NOTE: The device continues its operation in selected mode during programming. SDO is valid, however it is not possible to change the range or write GPIO data into the device during programming. Figure 54. Auto-1 Register Programming Flowchart Table 3. Program Register Settings for Auto-1 Mode BITS RESET STATE LOGIC STATE FUNCTION FRAME 1 DI15-12 NA 1000 DI11-00 NA Do not care Device enters Auto-1 program sequence. Device programming is done in the next frame. All 1s 1 (individual bit) FRAME 2 DI15-00 A particular channel is programmed to be selected in the channel scanning sequence. The channel numbers are mapped one-to-one with respect to the SDI bits; for example, DI15 → Ch15, DI14 → Ch14 … DI00 → Ch00 A particular channel is programmed to be skipped in the channel scanning sequence. The channel numbers are mapped one-to-one with respect to the SDI bits; for example DI15 → Ch15, DI14 → Ch14 … DI00 → Ch00 0 (individual bit) Table 4. Mapping of Channels to SDI Bits for 16, 12, 8, 4 Channel Devices Device (1) SDI BITS DI15 DI14 DI13 DI12 DI11 DI10 DI09 DI08 DI07 DI06 DI05 DI04 DI03 DI02 DI01 DI00 16 Chan 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 12 Chan X X X X 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 8 Chan X X X X X X X X 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 4 Chan X X X X X X X X X X X X 1/0 1/0 1/0 1/0 (1) When operating in Auto-1 mode, the device only scans the channels programmed to be selected. Copyright © 2008–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 37 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605C – JUNE 2008 – REVISED JULY 2018 www.ti.com 8.4.6 Operating in Auto-2 Mode Figure 55 illustrates the steps involved in entering and operating in Auto-2 channel sequencing mode. Table 5 lists the mode control register settings for Auto-2 mode. CS Frame: n-1 Device operation in Manual or Auto -1 mode No Change to Auto- 2 mode ? Yes CS Frame: n Request for Auto-2 mode CS Frame: n+1 Entry into Auto-2 Mode CS Frame: n+2 Operation in Auto-2 mode * Sample: Samples and converts channel selected in ‘frame n-1’ * Mux : Selects channel incremented from previous frame as per Auto-1 sequence, or channel programmed in previous frame in case of manual mode. . This channel will be acquired in this frame and sampled at start of ‘frame n +1’ * Range: As programmed in ‘frame n-1’. Applies to channel selected for acquisition in current frame . * SDI : Programming for ‘frame n+1’ DI15..12 = 0011 binary …. Selects Auto-2 mode DI11=1 enables programming of ‘range and GPIO’ DI10 = x, Device automatically resets to channel 0. DI6.. As per required range for channel to be selected DI5=0 .. No power down DI4..0… as per GPIO settings *SDO : DO15..0 address(or GPIO data) & conversion data of channel selected in ‘frame n -1’ * GPIO : O/P: latched on CS falling edge as per DI 3..0 written in frame n -1’ I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same frame * Sample: Samples and converts channel selected in ‘frame n’ * Mux : Selects channel0 (Auto-2 sequence always starts with Ch -0); this channel will be acquired in this frame and sampled at start of ‘frame n+2’ * Range: As programmed in ‘frame n’. Applies to channel selected for acquisition in current frame . * SDI : Programming for ‘frame n +2’ DI15..12 = 0011 binary …. To continue in Auto -2 mode DI11=1 enables programming of ‘range and GPIO’ DI10 =0, not to reset channel sequence DI6.. As per required range for channel to be selected DI5=0 .. No power down DI4..0… as per GPIO settings *SDO : DO15..0 address(or GPIO data) & conversion data of channel selected in ‘frame n’ * GPIO : O/P: latched on CS falling edge as per DI 3..0 written in frame ‘n’ I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same frame * Sample: Samples and converts channel 0 * Mux : Selects next higher channel in Auto -2 sequence, this channel will be acquired in this frame and sampled at start of ‘frame n+3’ * Range: As programmed in ‘frame n+1’. Applies to channel selected for acquisition in current frame.* SDI : Programming for ‘frame n+3’ DI15..12 = 0011 binary …. To continue in Auto -2 mode DI11=1 enables programming of ‘range and GPIO’ DI10 =0 not to reset channel sequence DI6.. As per required range for channel to be selected DI5=0 .. No power down DI4..0… as per GPIO settings *SDO : DO15..0 address(or GPIO data) & conversion data of channel selected in ‘frame n+1’ * GPIO : O/P: latched on CS falling edge as per DI 3..0 written in frame n+1’ I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same frame CS Continue operation in Auto-2 mode Figure 55. Entering and Running in Auto-2 Channel Sequencing Mode 38 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605C – JUNE 2008 – REVISED JULY 2018 Figure 56 shows an example in which Auto-2 mode is used to scan channels 0, 1, and 2. Auto-2 mode is selected to scan all channels until channel 2 (CH2) in ascending order by programming the Auto-2 register as described in Figure 56. The device enters Auto-2 mode on receiving the Auto-2 mode command in the Nth frame. This step causes the MUX to switch to CH0 in the (N+1)th frame. In the (N+2)th frame, the ADC samples and shifts out the conversion results for CH0 because the MUX internally switches to CH1. In the (N+3)th frame, the ADC samples and the shifts out the conversion result for CH1 and the MUX also switches to CH2, and so on. When this process reaches the maximum selected channel, CH2 in this case, the device returns to CH0 and repeats the cycle as long as the device remains in Auto-2 mode. Entering Auto-2 mode from any other mode also causes the device to restart from CH0. Additionally, modifying the contents of the for Auto-2 program register while operating in Auto-2 also causes the device to scan for restart from CH0. Sample CHy Sample CH0 Sample CH1 Sample CH2 tCYCLE CS SCLK SDI SDO AUTO-2 Start AUTO-2 AUTO-2 AUTO2 AUTO-2 Data CHx Data CHy Data CH0 Data CH1 Data CH2 Frame N Frame (N + 1) Frame (N + 2) Frame (N + 3) Scan channels CH0 ,CH1 and CH2 Figure 56. Example Auto-2 Mode Timing Diagram Copyright © 2008–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 39 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605C – JUNE 2008 – REVISED JULY 2018 www.ti.com Table 5. Mode Control Register Settings for Auto-2 Mode RESET STATE BITS LOGIC STATE FUNCTION DI15-12 0001 0011 Selects Auto-2 Mode DI11 0 1 Enables programming of bits DI10-00. 0 Device retains values of DI10-00 from the previous frame. 1 Channel number is reset to Ch-00. DI10 0 0 Channel counter increments every conversion.(No reset). DI09-07 000 xxx Do not care DI06 0 0 Selects VREF i/p range (Range 1) 1 Selects 2xVREF i/p range (Range 2) DI05 0 0 Device normal operation (no powerdown) 1 Device powers down on the 16th SCLK falling edge 0 SDO outputs the current channel address of the channel on DO15..12 followed by the 12-bit conversion result on DO11..00. DI04 0 1 DI03-00 (1) 0000 GPIO3-GPIO0 data (both input and output) is mapped onto DO15-DO12 in the order shown below. Lower data bits DO11-DO00 represent the 12-bit conversion result of the current channel. DO15 DO14 DO13 DO12 GPIO3 (1) GPIO2 (1) GPIO1 (1) GPIO0 (1) GPIO data for the channels configured as output. Device ignores data for the channel which is configured as input. SDI bit and corresponding GPIO information is given below DI03 DI02 DI01 DI00 GPIO3 (1) GPIO2 (1) GPIO1 (1) GPIO0 (1) GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only. The Auto-2 Program Register is programmed (once on powerup or reset) to pre-select the last channel (or sequence depth) in the Auto-2 sequence. Unlike Auto-1 Program Register programming, Auto-2 Program Register programming requires only 1 CS frame for complete programming. See Figure 57 and Table 6 for complete details. CS Device in any operation mode No Program Auto 2 register? Yes CS SDI: Di15..12 = 1001 DI9..6 = binary address of last channel in the sequence refer tables 6 Auto 2 register programming End of Auto 2 register programming NOTE: The device continues its operation in the selected mode during programming. SDO is valid, however it is not possible to change the range or write GPIO data into the device during programming. Figure 57. Auto-2 Register Programming Flowchart 40 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605C – JUNE 2008 – REVISED JULY 2018 Table 6. Program Register Settings for Auto-2 Mode BITS RESET STATE LOGIC STATE FUNCTION DI15-12 NA 1001 Auto-2 program register is selected for programming DI11-10 NA Do not care DI09-06 NA aaaa DI05-00 NA Do not care This 4-bit data represents the address of the last channel in the scanning sequence. During device operation in Auto-2 mode, the channel counter starts at CH-00 and increments every frame until it equals “aaaa”. The channel counter roles over to CH-00 in the next frame. 8.4.7 Continued Operation in a Selected Mode Once a device is programmed to operate in one of the modes, the user may want to continue operating in the same mode. Mode Control Register settings to continue operating in a selected mode are detailed in Table 7. Table 7. Continued Operation in a Selected Mode BITS RESET STATE LOGIC STATE FUNCTION DI15-12 0001 0000 The device continues to operate in the selected mode. In Auto-1 and Auto-2 modes the channel counter increments normally, whereas in the Manual mode it continues with the last selected channel. The device ignores data on DI11-DI00 and continues operating as per the previous settings. This feature is provided so that SDI can be held low when no changes are required in the Mode Control Register settings. DI11-00 All '0' Device ignores these bits when DI15-12 is set to 0000 logic state 8.5 Programming 8.5.1 Digital Output As discussed previously in Overview, the digital output of the ADS79xx devices is SPI compatible. The following tables list the output codes corresponding to various analog input voltages. Table 8. Ideal Input Voltages for 12-Bit Devices and Output Codes for 12-Bit Devices (ADS7950/51/52/53) DESCRIPTION ANALOG VALUE DIGITAL OUTPUT Full scale range Range 1 → VREF Range 2 → 2×VREF Least significant bit (LSB) VREF / 4096 2VREF / 4096 Full scale VREF – 1 LSB 2VREF – 1 LSB 1111 1111 1111 FFF Midscale VREF / 2 VREF 1000 0000 0000 800 Midscale – 1 LSB VREF / 2 – 1 LSB VREF – 1 LSB 0111 1111 1111 7FF Zero 0V 0V 0000 0000 0000 000 STRAIGHT BINARY BINARY CODE HEX CODE Table 9. Ideal Input Voltages for 10-Bit Devices and Digital Output Codes for 10-Bit Devices (ADS7954/55/56/57) DESCRIPTION ANALOG VALUE DIGITAL OUTPUT Full scale range Range 1 → VREF Range 2 → 2×VREF Least significant bit (LSB) VREF / 1024 2VREF / 1024 Full scale VREF – 1 LSB 2VREF – 1 LSB 0011 1111 1111 3FF Midscale VREF / 2 VREF 0010 0000 0000 200 Midscale – 1 LSB VREF / 2 – 1 LSB VREF – 1 LSB 0001 1111 1111 1FF Zero 0V 0V 0000 0000 0000 000 Copyright © 2008–2018, Texas Instruments Incorporated STRAIGHT BINARY BINARY CODE HEX CODE Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 41 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605C – JUNE 2008 – REVISED JULY 2018 www.ti.com Table 10. Ideal Input Voltages for 8-Bit Devices and Digital Output Codes for 8-Bit Devices (ADS7958/59/60/61) DESCRIPTION ANALOG VALUE DIGITAL OUTPUT Full scale range Range 1 → VREF Range 2 → 2×VREF Least significant bit (LSB) VREF / 256 2VREF / 256 Full scale VREF – 1 LSB 2VREF – 1 LSB 1111 1111 FF Midscale VREF / 2 VREF 1000 0000 80 Midscale – 1 LSB VREF / 2 – 1 LSB VREF – 1 LSB 0111 1111 7F Zero 0V 0V 0000 0000 00 STRAIGHT BINARY BINARY CODE HEX CODE 8.5.2 GPIO Registers NOTE GPIO 0, 1, 2, and 3 are available in the TSSOP packages. Only GPIO 0 is available in the VQFN packages. The device has four general purpose input and output (GPIO) pins. Each of the four pins can be independently programmed as general purpose output (GPO) or general purpose input (GPI). It is also possible to use the GPIOs for some pre-assigned functions (refer to Table 11 for details). GPO data can be written into the device through the SDI line. The device refreshes the GPO data on every CS falling edge as per the SDI data written in the previous frame. Similarly, the device latches GPI status on the CS falling edge and outputs it on SDO (if GPI is read enabled by writing DI04 = 1 during the previous frame) in the same frame starting on the CS falling edge. The details regarding programming the GPIO registers are illustrated in the flowchart in Figure 58. Table 11 lists the details regarding GPIO Register programming settings. CS Device in any operation mode No Program GPIO register? Yes CS SDI: DI15..12 = 0100 Refer table 9 for DI11..00 data GPIO register programming End of GPIO register programming NOTE: The device continues its operation in selected mode during programming. SDO is valid, however it is not possible to change the range or write GPIO data into the device during programming. Figure 58. GPIO Program Register Programming Flowchart 42 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605C – JUNE 2008 – REVISED JULY 2018 Table 11. GPIO Program Register Settings RESET STATE BITS LOGIC STATE FUNCTION DI15-12 NA 0100 Device selects GPIO Program Registers for programming. DI11-10 00 00 Do not program these bits to any logic state other than ‘00’ DI09 0 1 Device resets all registers in the next CS frame to the reset state shown in the corresponding tables (it also resets itself). 0 Device normal operation DI08 0 1 Device configures GPIO3 as the device power-down input. 0 GPIO3 remains general purpose I or O. Program 0 for QFN packaged devices. 1 Device configures GPIO2 as device range input. 0 GPIO2 remains general purpose I or O. Program 0 for QFN packaged devices. 000 GPIO1 and GPIO0 remain general purpose I or O. Valid setting for QFN packaged devices. xx1 Device configures GPIO0 as ‘high or low’ alarm output. This is an active high output. GPIO1 remains general purpose I or O. Valid setting for QFN packaged devices. 010 Device configures GPIO0 as high alarm output. This is an active high output. GPIO1 remains general purpose I or O. Valid setting for QFN packaged devices. 100 Device configures GPIO1 as low alarm output. This is an active high output. GPIO0 remains general purpose I or O. Setting not allowed for QFN packaged devices. 110 Device configures GPIO1 as low alarm output and GPIO0 as a high alarm output. These are active high outputs. Setting not allowed for QFN packaged devices. DI07 0 DI06-04 000 Note: The following settings are valid for GPIO which are not assigned a specific function through bits DI08..04 DI03 0 DI02 0 DI01 0 DI00 0 1 GPIO3 pin is configured as general purpose output. Program 1 for QFN packaged devices. 0 GPIO3 pin is configured as general purpose input. Setting not allowed for QFN packaged devices. 1 GPIO2 pin is configured as general purpose output. Program 1 for QFN packaged devices. 0 GPIO2 pin is configured as general purpose input. Setting not allowed for QFN packaged devices. 1 GPIO1 pin is configured as general purpose output. Program 1 for QFN packaged devices. 0 GPIO1 pin is configured as general purpose input. Setting not allowed for QFN packaged devices. 1 GPIO0 pin is configured as general purpose output. Valid setting for QFN packaged devices. 0 GPIO0 pin is configured as general purpose input. Valid setting for QFN packaged devices. 8.5.3 Alarm Thresholds for GPIO Pins Each channel has two alarm program registers, one for setting the high alarm threshold and the other for setting the low alarm threshold. For ease of programming, two alarm programming registers per channel, corresponding to four consecutive channels, are assembled into one group (a total eight registers). There are four such groups for 16 channel devices and 3/2/1 such groups for 12/8/4 channel devices respectively. The grouping of the various channels for each device in the ADS79xx family is listed in Table 12. The details regarding programming the alarm thresholds are illustrated in the flowchart in Figure 59. Table 13 lists the details regarding the Alarm Program Register settings. Table 12. Grouping of Alarm Program Registers GROUP NO. REGISTERS APPLICABLE FOR DEVICE 0 High and low alarm for channel 0, 1, 2, and 3 ADS7953..50, ADS7957..54, ADS7961..58 1 High and low alarm for channel 4, 5, 6, and 7 ADS7953..51, ADS7957..55, ADS7961..59 2 High and low alarm for channel 8, 9, 10, and 11 ADS7953 and 52, ADS7957 and 56, ADS7961 and 60 3 High and low alarm for channel 12, 13, 14, and 15 ADS7953, ADS7957, ADS7961 Each alarm group requires 9 CS frames for programming their respective alarm thresholds. In the first frame the device enters the programming sequence and in each subsequent frame it programs one of the registers from the group. The device offers a feature to program less than eight registers in one programming sequence. The device exits the alarm threshold programming sequence in the next frame after it encounters the first ‘Exit Alarm Program’ bit high. Copyright © 2008–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 43 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605C – JUNE 2008 – REVISED JULY 2018 CS www.ti.com Device in any operation mode No Program alarm thresholds? Yes CS Entry into alarm register programming sequence CS SDI: DI15..12 = 11XX (xx indicates group of four channels; refer table 8) Device enters alarm register programming sequence SDI: DI15..0 as per table 8 (program alarm thresholds) Alarm register programming sequence No Yes DI12 = 1? Yes Program another group of four channels? No End of alarm programing NOTE: The device continues its operation in selected mode during programming. SDO is valid, however it is not possible to change the range or write GPIO data into the device during programming. Figure 59. Alarm Program Register Programming Flowchart 44 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605C – JUNE 2008 – REVISED JULY 2018 Table 13. Alarm Program Register Settings BITS RESET STATE LOGIC STATE FUNCTION FRAME 1 DI15-12 NA 1100 Device enters ‘alarm programming sequence’ for group 0 1101 Device enters ‘alarm programming sequence’ for group 1 1110 Device enters ‘alarm programming sequence’ for group 2 1111 Device enters ‘alarm programming sequence’ for group 3 Note: DI15-12 = 11bb is the alarm programming request for group bb. Here ‘bb’ represents the alarm programming group number in binary format. DI11-14 NA Do not care FRAME 2 AND ONWARDS DI15-14 NA cc Where “cc” represents the lower two bits of the channel number in binary format. The device programs the alarm for the channel represented by the binary number “bbcc”. “bb” is programmed in the first frame. DI13 NA 1 High alarm register selection 0 Low alarm register selection 0 Continue alarm programming sequence in next frame 1 Exit Alarm Programming in the next frame. Note: If the alarm programming sequence is not terminated using this feature then the device will remain in the alarm programming sequence state and all SDI data will be treated as alarm thresholds. Do not care DI12 NA DI11-10 NA xx DI09-00 All ones for high alarm register and all zeros for low alarm register This 10-bit data represents the alarm threshold. The 10-bit alarm threshold is compared with the upper 10-bit word of the 12-bit conversion result. The device sets off an alarm when the conversion result is higher (High Alarm) or lower (Low Alarm) than this number. For 10-bit devices, all 10 bits of the conversion result are compared with the set threshold. For 8-bit devices, all 8 bits of the conversion result are compared with DI09 to DI02 and DI00, 01 are 'do not care'. Copyright © 2008–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 45 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605C – JUNE 2008 – REVISED JULY 2018 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information In general applications, when the internal multiplexer is updated, the previously converted channel charge is stored in the 15-pF internal input capacitance that disturbs the voltage at the newly selected channel. This disturbance is expected to settle to 1 LSB during sampling (acquisition) time to avoid degrading converter performance. The initial absolute disturbance error at the channel input must be less than 0.5 V to prevent source current saturation or slewing that causes significantly long settling times. Fortunately, significantly reducing disturbance error is easy to accomplish by simply placing a large enough capacitor at the input of each channel. Specifically, with a 150-pF capacitor, instantaneous charge distribution keeps disturbance error less than 0.46 V because the internal input capacitance can only hold up to 75 pC (or 5 V × 15 pF). The remaining error must be corrected by the voltage source at each input, with impedance low enough to settle within 1 LSB. The following application examples explain the considerations for the input source impedance (RSOURCE). 9.1.1 Analog Input The ADS79xx device family offers 12/10/8-bit ADCSs with 16/12/8/4 channel multiplexers for analog input. The multiplexer output is available on the MXO pin. AINP is the ADC input pin. The devices offers flexibility for a system designer as both signals are accessible externally. Typically it is convenient to short MXO to the AINP pin so that signal input to each multiplexer channel can be processed independently. In this condition, TI recommends limiting source impedance to 50 Ω or less. Higher source impedance may affect the signal settling time after a multiplexer channel change. This condition can affect linearity and total harmonic distortion. MXO AINP GPIO 0, H Alarm Ch0 Ch1 GPIO 1, L Alarm Ch2 GPIO 2, Range GPIO 3, PD From sensors, INA etc. There is a restriction on source impedance. RSOURCE £ 50 W ADC SDO To Host SDI SCLK CS Chn* REF 10 mF REF5025 o/p GPIO 0,1,2 and 3 are available only in TSSOP packaged devices. QFN device offers 'GPIO 0' only. As a result all references related to 'GPIO 0' only are valid in case of QFN package devices. Figure 60. Typical Application Diagram Showing MXO Shorted to AINP 46 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605C – JUNE 2008 – REVISED JULY 2018 Application Information (continued) Another option is to add a common ADC driver buffer between the MXO and AINP pins. This relaxes the restriction on source impedance to a large extent. Refer to Typical Characteristics (All ADS79xx Family Devices) for the effect of source impedance on device performance. The typical characteristics show that the device has respectable performance with up to 1kΩ source impedance. This topology (including a common ADC driver) is useful when all channel signals are within the acceptable range of the ADC. In this case the user can save on signal conditioning circuit for each channel. High input impedance PGA (or non inverting buffer such as THS4031) PGA Gain Control GPIO1 GPIO2 GPIO3 MXO AINP GPIO0 high-alarm low-alarm Ch0 Ch1 Ch2 See note A. ADC SDO To Host SDI SCLK CS Chn* REF 10 µF REF5025 o/p Figure 61. Typical Application Diagram Showing Common Buffer/PGA for All Channels When the converter samples an input, the voltage difference between AINP and AGND is captured on the internal capacitor array. The (peak) input current through the analog inputs depends upon a number of factors: sample rate, input voltage, and source impedance. The current into the ADS79xx charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. When the converter goes into hold mode, the input impedance is greater than 1 GΩ. Care must be taken regarding the absolute analog input voltage. To maintain linearity of the converter, the Ch0 .. Chn and AINP inputs should be within the limits specified. Outside of these ranges, converter linearity may not meet specifications. Copyright © 2008–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 47 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605C – JUNE 2008 – REVISED JULY 2018 www.ti.com Application Information (continued) MXO Ch0 200 3 pF 80 5 pF AINP 7 pF Chn 20 M 3 pF Ch0 assumed to be on Chn assumed to be off Figure 62. ADC and MUX Equivalent Circuit 9.2 Typical Applications 9.2.1 Unbuffered Multiplexer Output (MXO) This application is the most typical application, but requires the lowest RSOURCE for good performance. In this configuration, the 2xVREF range allows larger source impedance than the 1xVREF range because the 1xVREF range LSB size is smaller, thus making it more sensitive to settling error. MXO RSOURCE AINP GPIO 0 GPIO 1 Ch0 150 pF RSOURCE See Note A GPIO 2 GPIO 3 Ch1 150 pF RSOURCE ADC Chn 150 pF To Host REF REF5025 A. SDO SDI SCLK CS o/p 10 PF A restriction on the source impedance exists. RSOURCE ≤ 100 Ω for the 1xVREF 12-bit settling at 1 MSPS or RSOURCE ≤ 250 Ω for the 2xVREF 12-bit settling at 1 MSPS. Figure 63. Application Diagram for an Unbuffered MXO 9.2.1.1 Design Requirements The design is optimized to show the input source impedance (RSOURCE) from the 100 Ω to 10000 Ω required to meet the 1-LSB settling at 12-bit, 10-bit, and 8-bit resolutions at different throughput in 1xVREF (2.5-V) and 2xVREF (5-V) input ranges. 9.2.1.2 Detailed Design Procedure Although the required input source impedance can be estimated assuming a 0.5-V initial error and exponential recovery during sampling (acquisition) time, this estimation over-simplifies the complex interaction between the converter and source, thus yielding inaccurate estimates. Thus, this design uses an iterative approach with the converter itself to provide reliable impedance values. To determine the actual maximum source impedance for a particular resolution and sampling rate, two subsequent channels are set at least 95% of the full-scale range apart. With a 1xVREF range and 2.5 VREF, the channel difference is at least 2.375 V. With 2xVREF and 2.5 VREF, the difference is at least 4.75 V. With a source impedance from 100 Ω to 10,000 Ω, the conversion runs at a constant rate and a channel update is issued that captures the first couple samples after the update. This process is repeated at least 100 times to remove any noise and to show a clear settling error. The first sample after the channel update is then compared against the second one. If the first and second samples are more than 1 LSB apart, throughput rate is reduced until the settling error becomes 1 LSB, which then sets the maximum throughput for the selected impedance. The whole process is repeated for nine different impedances from 100 Ω to 10000 Ω. 48 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605C – JUNE 2008 – REVISED JULY 2018 Typical Applications (continued) 9.2.1.3 Application Curves These curves show the RSOURCE for an unbuffered MXO. 1000 1000 12-bit 10-bit 8-bit 800 12-bit 10-bit 8-bit 900 MAX Throughput (KSPS) MAX Throughput (KSPS) 900 700 600 500 400 300 200 100 800 700 600 500 400 300 200 100 0 100 1000 Rsource (:) 10000 D100 D101 Figure 64. 2xVREF Input Range Settling Without an MXO Buffer Copyright © 2008–2018, Texas Instruments Incorporated 0 100 1000 Rsource (:) 10000 D101 Figure 65. 1xVREF Input Range Settling Without an MXO Buffer Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 49 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605C – JUNE 2008 – REVISED JULY 2018 www.ti.com Typical Applications (continued) 9.2.2 OPA192 Buffered Multiplexer Output (MXO) The use of a buffer relaxes the RSOURCE requirements to an extent. Charge from the sample-and-hold capacitor no longer dominates as a residual charge from a previous channel. Although having good performance is possible with a larger impedance using the OPA192, the output capacitance of the MXO also holds the previous channel charge and cannot be isolated, which limits how large the input impedance can finally be for good performance. In this configuration, the 1xVREF range allows slightly higher impedance because the OPA192 (20 V/µs) slews approximately 2.5 V in contrast to the 2xVREF range that requires the OPA192 to slew approximately 5 V. 5V + OPA192 - RSOURCE 100 MXO 150pF AINP GPIO 0 GPIO 1 Ch0 150 pF RSOURCE See Note A GPIO 2 GPIO 3 Ch1 150 pF RSOURCE ADC Chn 150 pF To Host REF REF5025 A. SDO SDI SCLK CS o/p 10 PF Restriction on the source impedance exists. R(SOURCE) ≤ 500 Ω for a 12-bit settling at 1 MSPS with both 1xVREF and 2xVREF ranges. Figure 66. Application Diagram for an OPA192 Buffered MXO 9.2.2.1 Design Requirements The design is optimized to show the input source impedance (RSOURCE) from the 100 Ω to 10000 Ω required to meet a 1-LSB settling at 12-bit, 10-bit, and 8-bit resolutions at different throughput in 1xVREF (2.5 V) and 2xVREF (5 V) input ranges. 9.2.2.2 Detailed Design Procedure The design procedure is similar to the unbuffered-MXO application, but includes an operation amplifier in unity gain as a buffer. The most important parameter for multiplexer buffering is slew rate. The amplifier must finish slewing before the start of sampling (acquisition) to keep the buffer operating in small-signal mode during sampling (acquisition) time. Also, between the buffer output and converter input (INP), there must be a capacitor large enough to keep the buffer in small-signal operation during sampling (acquisition) time. Because 150 pF is large enough to protect the buffer form hold charge from internal capacitors, this value selected along with the lowest impedance that allows the op amp to remain stable. The converter allows the MXO to settle approximately 600 ns before sampling. During this time, the buffer slews and then enters small-signal operation. For a 5-V step change, slew rate stays constant during the first 4 V. The last 1 V includes a transition from slewing and non-slewing. Thus, the buffer cannot be assumed to keep a constant slew during the 600 ns available for MXO settling. Assuming that the last 1-V slew is reduced to half is recommended. For this reason, slew is 10 V/µs or (5 Vref + 1 V) / 0.6 µs to account for the 1-V slow slew. The OPA192 has a 20-V/us slew, and is capable of driving 150 pF with more than a 50° phase margin with a 50-Ω or 100-Ω Riso, making the OPA192 an ideal selection for the ADS79xx-Q1 family of converters. 50 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605C – JUNE 2008 – REVISED JULY 2018 Typical Applications (continued) 9.2.2.3 Application Curves These curves show the RSOURCE for an OPA192 buffered MXO. 1000 1000 12-bit 10-bit 8-bit 800 12-bit 10-bit 8-bit 900 MAX Throughput (KSPS) MAX Throughput (KSPS) 900 700 600 500 400 300 200 800 700 600 500 400 300 200 100 100 0 100 1000 Rsource (:) 10000 D102 Figure 67. 2xVREF Input Range Settling with an OPA192 MXO Buffer 0 100 1000 Rsource (:) 10000 D103 Figure 68. 1xVREF Input Range Settling with an OPA192 MXO Buffer 10 Power Supply Recommendations The devices are designed to operate from an analog supply voltage (+VA) range from 2.7 V to 5.25 V and a digital supply voltage (+VBD) range from 1.7 V to 5.25 V. Both supplies must be well regulated. The analog supply is always greater than or equal to the digital supply. A 1-µF ceramic decoupling capacitor is required at each supply pin and must be placed as close as possible to the device. Copyright © 2008–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 51 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605C – JUNE 2008 – REVISED JULY 2018 www.ti.com 11 Layout 11.1 Layout Guidelines • • • • A copper fill area underneath the device ties the AGND, BDGND, AINM, and REFM pins together. This copper fill area must also be connected to the analog ground plane of the PCB using at least four vias. The power sources must be clean and properly decoupled by placing a capacitor close to each of the three supply pins, as shown in Figure 69 and Figure 70. To minimize ground inductance, ensure that each capacitor ground pin is connected to a grounding via by a very short and thick trace. The REFP pin requires a 10-μF ceramic capacitor to meet performance specifications. Place the capacitor directly next to the device. This capacitor ground pin must be routed to the REFM pin by a very short trace, as shown in Figure 69 and Figure 70. Do not place any vias between a capacitor pin and a device pin. NOTE The full-power bandwidth of the converter makes the ADC sensitive to high frequencies in digital lines. Organize components in the PCB by keeping digital lines apart from the analog signal paths. This design configuration is critical to minimize crosstalk. For example, in Figure 69, input drivers are expected to be on the left of the converter and the microcontroller on the right. 1 µF REFP Analog Inputs +VA 11.2 Layout Examples 10 µF Pin 1 GPIO Analog Ground 1 µF +VBD GPIO 1 µF SPI +VA Analog Inputs Figure 69. Recommended Layout for the TSSOP Packaged Device 52 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605C – JUNE 2008 – REVISED JULY 2018 SDI SDO BDGND +VBD GPIO 1 PF REFM REFP 1 PF +VA AGND 1 PF Layout Examples (continued) 25 32 AGND 1 Optional RC filter between MXO and AINP 24 SCLK RFLT AGND MXO CS AINP AGND AINM +VA CFLT 8 17 9 Analog Input Channels 1 PF 16 Analog Input Channels Analog Input Channels Figure 70. Recommended Layout for the VQFN Packaged Device Copyright © 2008–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 53 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605C – JUNE 2008 – REVISED JULY 2018 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: • REF50xx Low-Noise, Very Low Drift, Precision Voltage Reference • OPAx192 36-V, Precision, Rail-to-Rail Input/Output, Low Offset Voltage, Low Input Bias Current Op Amp with e-trim™ 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to order now. Table 14. Related Links PARTS PRODUCT FOLDER ORDER NOW TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY ADS7950 Click here Click here Click here Click here Click here ADS7951 Click here Click here Click here Click here Click here ADS7952 Click here Click here Click here Click here Click here ADS7953 Click here Click here Click here Click here Click here ADS7954 Click here Click here Click here Click here Click here ADS7955 Click here Click here Click here Click here Click here ADS7956 Click here Click here Click here Click here Click here ADS7957 Click here Click here Click here Click here Click here ADS7958 Click here Click here Click here Click here Click here ADS7959 Click here Click here Click here Click here Click here ADS7960 Click here Click here Click here Click here Click here ADS7961 Click here Click here Click here Click here Click here 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.5 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 54 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605C – JUNE 2008 – REVISED JULY 2018 12.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.7 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2008–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 55 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) ADS7950SBDBT ACTIVE TSSOP DBT 30 60 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 125 ADS7950 B Samples ADS7950SBDBTR ACTIVE TSSOP DBT 30 2000 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 125 ADS7950 B Samples ADS7950SBRGER ACTIVE VQFN RGE 24 3000 RoHS & Green Call TI Level-3-260C-168 HR -40 to 125 ADS 7950 B ADS7950SBRGET ACTIVE VQFN RGE 24 250 RoHS & Green Call TI Level-3-260C-168 HR -40 to 125 ADS 7950 B ADS7950SDBT ACTIVE TSSOP DBT 30 60 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 125 ADS7950 Samples ADS7950SDBTR ACTIVE TSSOP DBT 30 2000 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 125 ADS7950 Samples ADS7951SBDBT ACTIVE TSSOP DBT 30 60 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 125 ADS7951 B Samples ADS7951SBDBTR ACTIVE TSSOP DBT 30 2000 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 125 ADS7951 B Samples ADS7951SBRGER ACTIVE VQFN RGE 24 3000 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 125 ADS 7951 B ADS7951SBRGET ACTIVE VQFN RGE 24 250 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 125 ADS 7951 B ADS7951SDBT ACTIVE TSSOP DBT 30 60 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 125 ADS7951 Samples ADS7951SDBTG4 ACTIVE TSSOP DBT 30 60 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 125 ADS7951 Samples ADS7951SDBTR ACTIVE TSSOP DBT 30 2000 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 125 ADS7951 Samples ADS7951SRGER ACTIVE VQFN RGE 24 3000 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 125 ADS 7951 Samples ADS7951SRGET ACTIVE VQFN RGE 24 250 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 125 ADS 7951 Samples ADS7952SBDBT ACTIVE TSSOP DBT 38 50 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 125 ADS7952 B Samples Addendum-Page 1 Samples Samples Samples Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 14-Oct-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) ADS7952SBDBTG4 ACTIVE TSSOP DBT 38 50 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 125 ADS7952 B Samples ADS7952SBDBTR ACTIVE TSSOP DBT 38 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7952 B Samples ADS7952SBRHBR ACTIVE VQFN RHB 32 3000 RoHS & Green Call TI Level-3-260C-168 HR -40 to 125 ADS 7952 B ADS7952SBRHBT ACTIVE VQFN RHB 32 250 RoHS & Green Call TI Level-3-260C-168 HR -40 to 125 ADS 7952 B ADS7952SDBT ACTIVE TSSOP DBT 38 50 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 125 ADS7952 Samples ADS7952SDBTG4 ACTIVE TSSOP DBT 38 50 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 125 ADS7952 Samples ADS7952SDBTR ACTIVE TSSOP DBT 38 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7952 Samples ADS7952SRHBR ACTIVE VQFN RHB 32 3000 RoHS & Green Call TI Level-3-260C-168 HR -40 to 125 ADS 7952 Samples ADS7952SRHBT ACTIVE VQFN RHB 32 250 RoHS & Green Call TI Level-3-260C-168 HR -40 to 125 ADS 7952 Samples ADS7953SBDBT ACTIVE TSSOP DBT 38 50 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 125 ADS7953 B Samples ADS7953SBDBTR ACTIVE TSSOP DBT 38 2000 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 125 ADS7953 B Samples ADS7953SBRHBR ACTIVE VQFN RHB 32 3000 RoHS & Green Call TI Level-3-260C-168 HR -40 to 125 ADS 7953 B ADS7953SBRHBT ACTIVE VQFN RHB 32 250 RoHS & Green Call TI Level-3-260C-168 HR -40 to 125 ADS 7953 B ADS7953SDBT ACTIVE TSSOP DBT 38 50 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 125 ADS7953 Samples ADS7953SDBTR ACTIVE TSSOP DBT 38 2000 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 125 ADS7953 Samples ADS7953SRHBR ACTIVE VQFN RHB 32 3000 RoHS & Green Call TI Level-3-260C-168 HR -40 to 125 ADS 7953 Samples ADS7953SRHBT ACTIVE VQFN RHB 32 250 RoHS & Green Call TI Level-3-260C-168 HR -40 to 125 ADS 7953 Samples Addendum-Page 2 Samples Samples Samples Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 14-Oct-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) ADS7954SDBT ACTIVE TSSOP DBT 30 60 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7954 Samples ADS7954SDBTR ACTIVE TSSOP DBT 30 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7954 Samples ADS7954SRGER ACTIVE VQFN RGE 24 3000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7954 Samples ADS7954SRGET ACTIVE VQFN RGE 24 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7954 Samples ADS7955SDBT ACTIVE TSSOP DBT 30 60 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7955 Samples ADS7955SDBTR ACTIVE TSSOP DBT 30 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7955 Samples ADS7955SRGER ACTIVE VQFN RGE 24 3000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7955 Samples ADS7955SRGET ACTIVE VQFN RGE 24 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7955 Samples ADS7956SDBT ACTIVE TSSOP DBT 38 50 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7956 Samples ADS7956SDBTR ACTIVE TSSOP DBT 38 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7956 Samples ADS7956SRHBR ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7956 Samples ADS7956SRHBT ACTIVE VQFN RHB 32 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7956 Samples ADS7957SDBT ACTIVE TSSOP DBT 38 50 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7957 Samples ADS7957SDBTR ACTIVE TSSOP DBT 38 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7957 Samples ADS7957SRHBR ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7957 Samples ADS7957SRHBT ACTIVE VQFN RHB 32 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7957 Samples ADS7958SDBT ACTIVE TSSOP DBT 30 60 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7958 Samples ADS7958SDBTR ACTIVE TSSOP DBT 30 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7958 Samples ADS7958SRGER ACTIVE VQFN RGE 24 3000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7958 Samples Addendum-Page 3 PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 14-Oct-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) ADS7958SRGET ACTIVE VQFN RGE 24 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7958 Samples ADS7959SDBT ACTIVE TSSOP DBT 30 60 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7959 Samples ADS7959SDBTR ACTIVE TSSOP DBT 30 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7959 Samples ADS7959SRGER ACTIVE VQFN RGE 24 3000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7959 Samples ADS7959SRGET ACTIVE VQFN RGE 24 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7959 Samples ADS7960SDBT ACTIVE TSSOP DBT 38 50 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7960 Samples ADS7960SDBTR ACTIVE TSSOP DBT 38 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7960 Samples ADS7960SRHBR ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7960 Samples ADS7960SRHBT ACTIVE VQFN RHB 32 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7960 Samples ADS7961SDBT ACTIVE TSSOP DBT 38 50 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7961 Samples ADS7961SDBTR ACTIVE TSSOP DBT 38 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7961 Samples ADS7961SRHBR ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7961 Samples ADS7961SRHBT ACTIVE VQFN RHB 32 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7961 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Addendum-Page 4 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of