ADS800E

ADS800 A DS 800 U SBAS035B – FEBRUARY 1995 – REVISED FEBRUARY 2005 12-Bit, 40MHz Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES q q q q LOW POWER: 390mW INTERNAL REFERENCE WIDEBAND TRACK-AND-HOLD: 65MHz SINGLE +5V SUPPLY DESCRIPTION The ADS800 is a low-power, monolithic 12-bit, 40MHz Analog-to-Digital (A/D) converter utilizing a small geometry CMOS process. This complete converter includes a 12-bit quantizer, wideband track-and-hold, reference, and three-state outputs. It operates from a single +5V power supply and can be configured to accept either differential or single-ended input signals. The ADS800 employs digital error correction to provide excellent Nyquist differential linearity performance for demanding imaging applications. Its low distortion, high SNR, and high oversampling capability give it the extra margin needed for telecommunications, test instrumentation, and video applications. This high-performance A/D converter is specified over temperature for AC and DC performance at a 40MHz sampling rate. The ADS800 is available in an SO-28 package. APPLICATIONS q q q q q q IF AND BASEBAND DIGITIZATION DIGITAL COMMUNICATIONS ULTRASOUND IMAGING GAMMA CAMERAS TEST INSTRUMENTATION CCD IMAGING Copiers Scanners Cameras q VIDEO DIGITIZING CLK MSBI OE Timing Circuitry IN T/H IN +3.25V REFT Pipeline A/D Converter Error Correction Logic 3-State Outputs 12-Bit Digital Data CM REFB +1.25V Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1995-2005, Texas Instruments Incorporated www.ti.com ABSOLUTE MAXIMUM RATINGS(1) +VS ....................................................................................................... +6V Analog Input .............................................................. 0V to (+VS + 300mV) Logic Input ................................................................ 0V to (+VS + 300mV) Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature ..................................................................... +125°C External Top Reference Voltage (REFT) .................................. +3.4V Max External Bottom Reference Voltage (REFB) .............................. +1.1V Min NOTE: (1) Stresses above these ratings may permanently damage the device. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION(1) PACKAGE DESIGNATOR DW SPECIFIED TEMPERATURE RANGE –40°C to +85°C PACKAGE MARKING ADS800U ORDERING NUMBER ADS800U TRANSPORT MEDIA, QUANTITY Rails, 28 PRODUCT ADS800U PACKAGE-LEAD SO-28 NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ELECTRICAL CHARACTERISTICS At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. ADS800U PARAMETER Resolution Specified Temperature Range Operating Temperature Range ANALOG INPUT Differential Full-Scale Input Range Common-Mode Voltage Analog Input Bandwidth (–3dB) Small-Signal Full-Power Input Impedance DIGITAL INPUT Logic Family Convert Command ACCURACY(2) Gain Error Gain Drift Power-Supply Rejection of Gain Input Offset Error Power-Supply Rejection of Offset CONVERSION CHARACTERISTICS Sample Rate Data Latency DYNAMIC CHARACTERISTICS Differential Linearity Error f = 500kHz f = 12MHz No Missing Codes Integral Linearity Error at f = 500kHz Spurious-Free Dynamic Range (SFDR) f = 500kHz (–1dBFS input) f = 12MHz (–1dBFS input) tH = 13ns(3) CONDITIONS TAMBIENT TAMBIENT Both Inputs, 180° Out-of-Phase TEMP MIN 0 –40 +1.25 +2.25 –20dBFS(1) Input 0dBFS Input +25°C +25°C 400 65 1.25 || 4 TTL/HCT Compatible CMOS Falling Edge fS = 2.5MHz +25°C Full ∆ +VS = ±5% ∆ +VS = ±5% +25°C Full +25°C 10k 6.5 ±0.4 ±0.6 ±95 0.01 ±2.6 0.02 ±1.5 ±2.5 0.15 ±3.5 0.15 40M % % ppm/°C %FSR/% % %FSR/% Sample/s Convert Cycle TYP 12 +70 +85 +3.25 MAX UNITS Bits °C °C V V MHz MHz MΩ || pF Start Conversion tH = 13ns(3) +25°C Full +25°C Full +25°C Full +25°C Full +25°C Full 65 60 58 55 ±0.6 ±0.8 ±0.4 ±0.5 Tested ±1.9 72 66 61 61 ±1.0 ±1.0 LSB LSB LSB LSB LSB LSB dBFS dBFS dBFS dBFS NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) To assure DNL and no missing code performance, see timing diagram footnote 2. (4) IMD is referred to the larger of the two input signals. If referred to the peak envelope signal (≈0dB), the intermodulation products will be 7dB lower. (5) No “rollover” of bits. 2 ADS800 www.ti.com SBAS035B ELECTRICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. ADS800U PARAMETER CONDITIONS TEMP MIN TYP MAX UNITS DYNAMIC CHARACTERISTICS (Cont.) 2-Tone Intermodulation Distortion (IMD)(4) f = 4.4MHz and 4.5MHz (–7dBFS each tone) Signal-to-Noise Ratio (SNR) f = 500kHz (–1dBFS input) f = 12MHz (–1dBFS input) Signal-to-(Noise + Distortion) (SINAD) f = 500kHz (–1dBFS input) f = 12MHz (–1dBFS input) Differential Gain Error Differential Phase Error Aperture Delay Time Aperture Jitter Over-Voltage Recovery Time(5) OUTPUTS Logic Family Logic Coding Logic Levels NTSC or PAL NTSC or PAL +25°C Full +25°C Full +25°C Full +25°C Full +25°C Full +25°C +25°C +25°C +25°C +25°C 61 57 61 56 59 54 56 51 –63 –62 64 63 62 62 63 64 58 57 0.5 0.1 2 7 2 dBc dBc dB dB dB dB dB dB dB dB % degrees ns ps rms ns 1.5x Full-Scale Input Logic “LO”, CL = 15pF max Logic “HI”, CL = 15pF max Logic Selectable Full Full TTL/HCT Compatible CMOS SOB or BTC 0 0.4 +2.5 20 2 +4.75 +5.0 78 78 390 390 75 +VS 40 10 +5.25 93 97 465 485 V V ns ns V mA mA mW mW °C/W 3-State Enable Time 3-State Disable Time POWER-SUPPLY REQUIREMENTS Supply Voltage: +VS Supply Current: +IS Power Consumption Thermal Resistance, θJA SO-28 Operating Operating Operating Operating Operating Full Full +25°C Full +25°C Full NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) To assure DNL and no missing code performance, see timing diagram footnote 2. (4) IMD is referred to the larger of the two input signals. If referred to the peak envelope signal (≈0dB), the intermodulation products will be 7dB lower. (5) No “rollover” of bits. ADS800 SBAS035B www.ti.com 3 PIN CONFIGURATION Top View SO PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 DESIGNATOR GND B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 GND +VS CLK +VS OE MSBI DESCRIPTION Ground Bit 1, Most Significant Bit Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12, Least Significant Bit Ground +5V Power Supply Convert Clock Input, 50% Duty Cycle +5V Power Supply HI: High Impedance State. LO or Floating: Normal Operation. Internal pull-down resistors. Most Significant Bit Inversion, HI: MSB inverted for complementary output. LO or Floating: Straight output. Internal pull-down resistors. +5V Power Supply Bottom Reference Bypass. For external bypassing of internal +1.25V reference. Common-Mode Voltage. It is derived by (REFT + REFB)/2. Top Reference Bypass. For external bypassing of internal +3.25V reference. +5V Power Supply Ground Input Complementary Input Ground GND B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 GND 1 2 3 4 5 6 7 ADS800 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND IN IN GND +VS REFT CM REFB +VS MSBI OE +VS CLK +VS 20 21 22 23 24 25 26 27 28 +VS REFB CM REFT +VS GND IN IN GND TIMING DIAGRAM tCONV Convert Clock Hold “N” tL tD tH Internal Track-and-Hold Track DATA LATENCY (6.5 Clock Cycles) Hold Hold Hold Hold Hold Hold Track “N + 1” Track “N + 2” Track “N + 3” Track “N + 4” Track “N + 5” Track “N + 6” Track (1) t2 Output Data Data Valid N–8 Data Valid N–7 Data Valid N–6 N–5 N–4 N–3 N–2 N–1 N t1 Data Invalid SYMBOL tCONV tL tH tD t1 t2 DESCRIPTION Convert Clock Period Clock Pulse LOW Clock Pulse HIGH Aperture Delay Data Hold Time, CL = 0pF New Data Delay Time, CL = 15pF max MIN 25 12 12(2) 3.9 TYP MAX 100µs UNITS ns ns ns ns ns ns 12.5 12.5 2 12.5 NOTES: (1) “ ” indicates the portion of the waveform that will stretch out at slower sample rates. (2) tH must be 13ns minimum if no missing codes is desired only for the conditions of tCONV ≤ 28ns and fIN < 2MHz. 4 ADS800 www.ti.com SBAS035B TYPICAL CHARACTERISTICS At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. SPECTRAL PERFORMANCE 0 –20 fIN = 500kHz 0 –20 SPECTRAL PERFORMANCE fIN = 1MHz Amplitude (dB) –60 –80 –100 –120 0 5 10 Frequency (MHz) 15 20 Amplitude (dB) –40 –40 –60 –80 –100 –120 0 5 10 Frequency (MHz) 15 20 SPECTRAL PERFORMANCE 0 fIN = 5MHz –20 Amplitude (dB) SPECTRAL PERFORMANCE 0 fIN = 12MHz –20 Amplitude (dB) –40 –60 –80 –100 –120 0 5 10 Frequency (MHz) 15 20 –40 –60 –80 –100 –120 0 5 10 Frequency (MHz) 15 20 SPECTRAL PERFORMANCE 0 –20 Amplitude (dB) 2-TONE INTERMODULATION 0 –20 Amplitude (dB) fIN = 1MHz fS = 10MHz f1 = 12.5MHz f2 = 12.0MHz –40 –60 –80 –100 –120 0 1 2 3 4 5 Frequency (MHz) –40 –60 –80 –100 –120 0 5 10 Frequency (MHz) 15 20 ADS800 SBAS035B www.ti.com 5 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. DIFFERENTIAL LINEARITY ERROR 2.0 fIN = 500kHz 1.0 1.0 2.0 DIFFERENTIAL LINEARITY ERROR fIN = 12MHz DLE (LSB) 0 DLE (LSB) 0 1024 2048 Code 3072 4096 0 –1.0 –1.0 –2.0 –2.0 0 1024 2048 Code 3072 4096 DYNAMIC PERFORMANCE vs INPUT FREQUENCY 80 75 SFDR SWEPT POWER SFDR 100 fIN = 12MHz 80 SFDR, SNR (dB) SFDR (dBFS) SNR 70 65 60 55 50 0.1 1 10 Frequency (MHz) 100 60 40 20 0 –50 –40 –30 –20 –10 0 10 Input Amplitude (dBm) SWEPT POWER SNR 80 fIN = 12MHz 60 SNR (dB) ILE (LSB) 2.0 4.0 INTEGRAL LINEARITY ERROR fIN = 500kHz 40 0 20 –2.0 0 –50 –40 –30 –20 –10 0 10 Input Amplitude (dBm) –4.0 0 1024 2048 Code 3072 4096 6 ADS800 www.ti.com SBAS035B TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. DYNAMIC PERFORMANCE vs SINGLE-ENDED FULL-SCALE INPUT RANGE 65 fIN = 12MHz SNR 70 75 DYNAMIC PERFORMANCE vs DIFFERENTIAL FULL-SCALE INPUT RANGE SFDR (fIN = 500kHz) Dynamic Range (dB) Dynamic Range (dB) 60 SFDR (fIN = 12MHz) 65 SNR (fIN = 500kHz) 55 SFDR 50 NOTE: REFTEXT varied, REFB is fixed at the internal value of +1.25V. 45 1 2 3 4 Single-Ended Full-Scale Range (Vp-p) 5 60 SNR (fIN = 12MHz) 55 NOTE: REFTEXT varied, REFB is fixed at the internal value of +1.25V. 50 2 3 4 Differential Full-Scale Input Range (Vp-p) SPURIOUS-FREE DYNAMIC RANGE (SFDR) vs TEMPERATURE 90 SIGNAL-TO-NOISE RATIO vs TEMPERATURE 80 80 SFDR (dBFS) 70 fIN = 500kHz SNR (dB) fIN = 500kHz 70 60 fIN = 12MHz 50 60 fIN = 12MHz 50 –25 0 25 Temperature (°C) 50 75 40 –25 0 25 Temperature (°C) 50 75 SIGNAL-TO-(NOISE + DISTORTION) vs TEMPERATURE 70 fIN = 500kHz 65 85 SUPPLY CURRENT vs TEMPERATURE SINAD (dB) 80 60 IQ (mA) fIN = 12MHz 75 70 55 50 –25 0 25 Temperature (°C) 50 75 –25 0 25 Temperature (°C) 50 75 ADS800 SBAS035B www.ti.com 7 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. POWER DISSIPATION vs TEMPERATURE 425 GAIN ERROR vs TEMPERATURE 0.75 0.25 Gain (%FSR) –25 0 25 Temperature (°C) 50 75 Power (mW) 400 –0.25 375 –0.75 350 –1.25 –25 0 25 Temperature (°C) 50 75 OFFSET ERROR vs TEMPERATURE –2.25 Track-Mode Input Response (dB) TRACK-MODE SMALL-SIGNAL INPUT BANDWIDTH 1 0 –1 –2 –3 –4 –5 Offset (%FSR) –2.5 –2.75 –25 0 25 Ambient Temperature (°C) 50 75 10k 100k 1M 10M 100M 1G Frequency (Hz) OUTPUT NOISE HISTOGRAM (NO SIGNAL) 800k 600k Counts 400k 200k 0.0 N–2 N–1 N Code N+1 N+2 8 ADS800 www.ti.com SBAS035B THEORY OF OPERATION The ADS800 is a high-speed, sampling A/D converter with pipelining. It uses a fully differential architecture and digital error correction to ensure 12-bit resolution. The differential track-and-hold circuit is shown in Figure 1. The switches are controlled by an internal clock which has a non-overlapping 2-phase signal, φ1 and φ2. At the sampling time, the input signal is sampled on the bottom plates of the input capacitors. In the next clock phase, φ2, the bottom plates of the input capacitors are connected together and the feedback capacitors are switched to the op amp output. At this time, the charge redistributes between CI and CH, completing one track-and-hold cycle. The differential output is a held DC representation of the analog input at the sample time. The track-and-hold circuit can also convert a single-ended input signal into a fully differential signal for the quantizer. The pipelined quantizer architecture has 11 stages with each stage containing a 2-bit quantizer and a 2-bit Digital-toAnalog Converter (DAC), as shown in Figure 2. Each 2-bit quantizer stage converts on the edge of the sub-clock, which is twice the frequency of the externally applied clock. The output of each quantizer is fed into its own delay line to time- Op Amp Bias φ1 VCM φ1 CH φ2 CI IN IN φ1 φ1 φ2 CI CH φ1 Input Clock (50%) Op Amp Bias Internal Non-Overlapping Clock φ1 φ2 φ1 VCM φ1 φ1 OUT OUT φ2 FIGURE 1. Input Track-and-Hold Configuration with Timing Signals. IN IN Input T/H 2-Bit Flash STAGE 1 2-Bit DAC Digital Delay Σ x2 + – Digital Delay B1 (MSB) B2 Digital Error Correction 2-Bit Flash STAGE 2 2-Bit DAC B3 B4 B5 B6 B7 B8 B9 B10 Digital Delay B11 B12 (LSB) Σ x2 + – 2-Bit Flash STAGE 10 2-Bit DAC Σ x2 + – STAGE 11 2-Bit Flash Digital Delay FIGURE 2. Pipeline A/D Converter Architecture. ADS800 SBAS035B www.ti.com 9 align it with the data created from the following quantizer stages. This aligned data is fed into a digital error correction circuit which can adjust the output data based on the information found on the redundant bits. This technique gives the ADS800 excellent differential linearity and ensures no missing codes at the 12-bit level. Since there are two pipeline stages per external clock cycle, there is a 6.5 clock cycle data latency from the start convert signal to the valid output data. The output data is available in Straight Offset Binary (SOB) or Binary Two’s Complement (BTC) format. • For most applications, the clock duty should be set to 50%. However, for applications requiring no missing codes, a slight skew in the duty cycle will improve DNL performance for conversion rates > 35MHz and input frequencies < 2MHz (see Timing Diagram) in the SO package. For the best performance in the SSOP package, the clock should be skewed under all input frequencies with conversion rates > 35MHz. A possible method for skewing the 50% duty cycle source is shown in Figure 4. VDD RV 2kΩ 0.1µF 0.1µF VDD IC1, IC2 = ACT04 RV = 217Ω, typical THE ANALOG INPUT AND INTERNAL REFERENCE The analog input of the ADS800 can be configured in various ways and driven with different circuits, depending on the nature of the signal and the level of performance desired. The ADS800 has an internal reference that sets the full-scale input range of the A/D converter. The differential input range has each input centered around the common-mode of +2.25V, with each of the two inputs having a full-scale range of +1.25V to +3.25V. Since each input is 2Vp-p and 180° outof-phase with the other, a 4V differential input signal to the quantizer results. As shown in Figure 3, the positive full-scale reference (REFT) and the negative full-scale (REFB) are brought out for external bypassing. In addition, the commonmode voltage (CM) may be used as a reference to provide the appropriate offset for the driving circuitry. However, care must be taken not to appreciably load this reference node. For more information regarding external references, singleended input, and ADS800 drive circuits, refer to the applications section. CLKIN IC1 IC2 CLKOUT FIGURE 4. Clock Skew Circuit. DIGITAL OUTPUT DATA The 12-bit output data is provided at CMOS logic levels. The standard output coding is Straight Offset Binary (SOB) where a full-scale input signal corresponds to all “1’s” at the output, as shown in Table 1. This condition is met with pin 19 “LO” or Floating due to an internal pull-down resistor. By applying a logic “HI” voltage to this pin, a Binary Two’s Complement (BTC) output will be provided where the most significant bit is inverted. The digital outputs of the ADS800 can be set to a high-impedance state by driving OE (pin 18) with a logic “HI”. Normal operation is achieved with pin 18 “LO” or Floating due to internal pull-down resistors. This function is provided for testability purposes and is not meant to drive digital buses directly or be dynamically changed during the conversion process. OUTPUT CODE SOB PIN 19 FLOATING or LO 111111111111 111111111111 111111111110 111000000000 110000000000 101000000000 100000000001 100000000000 011111111111 011000000000 010000000000 001000000000 000000000001 000000000000 BTC PIN 19 HI 011111111111 011111111111 011111111110 011000000000 010000000000 001000000000 000000000001 000000000000 111111111111 111000000000 110000000000 101000000000 100000000001 100000000000 ADS800 +3.25V 23 0.1µF CM 2kΩ 21 0.1µF REFB +1.25V REFT 2kΩ 22 To Internal Comparators +2.25V DIFFERENTIAL INPUT(1) +FS (IN = +3.25V, IN = +1.25V) +FS – 1LSB +FS – 2LSB +3/4 Full-Scale +1/2 Full-Scale +1/4 Full-Scale +1LSB Bipolar Zero (IN = IN = +2.25V) –1LSB –1/4 Full-Scale –1/2 Full-Scale –3/4 Full-Scale –FS + 1LSB –FS (IN = +1.25V, IN = +3.25V) FIGURE 3. Internal Reference Structure. CLOCK REQUIREMENTS The CLK pin accepts a CMOS level clock input. Both the rising and falling edges of the externally applied clock control the various interstage conversions in the pipeline. Therefore, the clock signal’s jitter, rise-and-fall times, and duty cycle can affect conversion performance. • Low clock jitter is critical to SNR performance in frequency-domain signal environments. • Clock rise-and-fall times should be as short as possible (< 2ns for best performance). NOTE: (1) In the single-ended input mode, +FS = +4.25V and –FS = +0.25V. TABLE I. Coding Table for the ADS800. 10 ADS800 www.ti.com SBAS035B APPLICATIONS DRIVING THE ADS800 The ADS800 has a differential input with a common-mode of +2.25V. For AC-coupled applications, the simplest way to create this differential input is to drive the primary winding of a transformer with a single-ended input. A differential output is created on the secondary if the center tap is tied to the common-mode voltage of +2.25V, as per Figure 5. This transformer-coupled input arrangement provides good highfrequency AC performance. It is important to select a transformer that gives low distortion and does not exhibit core saturation at full-scale voltage levels. Since the transformer does not appreciably load the ladder, there is no need to buffer the Common-Mode (CM) output in this instance. In general, it is advisable to keep the current draw from the CM output pin below 0.5µA to avoid nonlinearity in the internal reference ladder. A FET input operational amplifier such as the OPA130 can provide a buffered reference for driving external circuitry. The analog IN and IN inputs should be bypassed with 22pF capacitors to minimize track-and-hold glitches and to improve high input frequency performance. Figure 6 illustrates another possible low-cost interface circuit which utilizes resistors and capacitors in place of a transformer. Depending on the signal bandwidth, the component values should be carefully selected in order to maintain the product performance. The input capacitors, CIN, and the input resistors, RIN, create a high-pass filter with the lower corner frequency at fC = 1/(2pRINCIN). The corner frequency can be reduced by either increasing the value of RIN or CIN. If the circuit operates with a 50Ω or 75Ω impedance level, the resistors are fixed and only the value of the capacitor can be increased. Usually, AC-coupling capacitors are electrolytic or tantalum capacitors with values of 1µF or higher. It should be noted that these large capacitors become inductive with increased input frequency, which could lead to signal amplitude errors or oscillation. To maintain a low AC-coupling impedance throughout the signal band, a small value (e.g. 1µF) ceramic capacitor could be added in parallel with the polarized capacitor. Capacitors CSH1 and CSH2 are used to minimize current glitches resulting from the switching in the input track-andhold stage and to improve signal-to-noise performance. These capacitors can also be used to establish a low-pass filter and effectively reduce the noise bandwidth. In order to create a real pole, resistors RSER1 and RSER2 were added in series with each input. The cutoff frequency of the filter is determined by fC = 1/(2pRSER • (CSH + CADC)) where RSER is the resistor in series with the input, CSH is the external capacitor from the input to ground, and CADC is the internal input capacitance of the A/D converter (typically 4pF). Resistors R1 and R2 are used to derive the necessary common-mode voltage from the buffered top and bottom references. The total load of the resistor string should be selected so that the current does not exceed 1mA. Although the circuit in Figure 6 uses two resistors of equal value so that the common-mode voltage is centered between the top and bottom reference (+2.25V), it is not necessary to do so. In all cases the center point, VCM, should be bypassed to ground in order to provide a low-impedance AC ground. If the signal needs to be DC coupled to the input of the ADS800, an operational amplifier input circuit is required. In the differential input mode, any single-ended signal must be modified to create a differential signal. This can be accomplished by 22 CM 0.1µF 26 IN 22pF AC Input Signal ADS800 Mini-Circuits TT1-6-KK81 or equivalent 27 IN 22pF FIGURE 5. AC-Coupled Single-Ended to Differential Drive Circuit Using a Transformer. C1 0.1µF CIN 0.1µF RIN1 25Ω RSER1(1) 49.9Ω R1 (6kΩ) IN R3 1kΩ C2 0.1µF VCM CSH1 22pF +3.25V Top Reference ADS8xx RIN2 25Ω CIN 0.1µF RSER2(1) 49.9Ω R2 (6kΩ) CSH2 22pF IN +1.25V Bottom Reference NOTE: (1) Indicates optional component. C3 0.1µF FIGURE 6. AC-Coupled Differential Input Circuit. ADS800 SBAS035B www.ti.com 11 using two operational amplifiers, one in the noninverting mode for the input and the other amplifier in the inverting mode for the complementary input. The low distortion circuit in Figure 7 will provide the necessary input shifting required for signals centered around ground. It also employs a diode for output level shifting to ensure a low distortion +3.25V output swing. Other amplifiers can be used in place of the OPA842s if the lowest distortion is not necessary. If output level shifting circuits are not used, care must be taken to select operational amplifiers that give the necessary performance when swinging to +3.25V with a ±5V supply operational amplifier. The ADS800 can also be configured with a single-ended input full-scale range of +0.25V to +4.25V by tying the complementary input to the common-mode reference volt- age, as shown in Figure 8. This configuration will result in increased even-order harmonics, especially at higher input frequencies. However, this tradeoff may be quite acceptable for time-domain applications. The driving amplifier must give adequate performance with a +0.25V to +4.25V output swing in this case. EXTERNAL REFERENCES AND ADJUSTMENT OF FULL-SCALE RANGE The internal reference buffers are limited to approximately 1mA of output current. As a result, these internal +1.25V and +3.25V references may be overridden by external references that have at least 18mA (at room temperature) of output drive capability. In this instance, the common-mode voltage will be +5V 604Ω +5V BAS16(1) Optional High Impedance Input Amplifier 301Ω +5V(2) –5V DC-Coupled Input Signal OPA842 604Ω 604Ω 301Ω OPA842 0.1µF 301Ω 27 IN 2.49kΩ 0.1µF +5V 49.9Ω OPA130 +5V 2.49kΩ +2.25V 22 CM ADS800 22pF –5V 24.9Ω 301Ω +5V BAS16(1) OPA842 0.1µF –5V 604Ω NOTES: (1) A Philips BAS16 diode or equivalent may be used. (2) Supply bypassing not shown. 22pF 301Ω Input Level Shift Buffer 26 IN 301Ω FIGURE 7. A Low Distortion DC-Coupled, Single-Ended to Differential Input Driver Circuit. 22 CM 0.1µF ADS800 Single-Ended Input Signal 22pF 26 IN 27 IN Full Scale = +0.25V to +4.25V with internal references. FIGURE 8. Single-Ended Input Connection. 12 ADS800 www.ti.com SBAS035B set halfway between the two references. This feature can be used to adjust the gain error, improve gain drift, or to change the full-scale input range of the ADS800. Changing the fullscale range to a lower value has the benefit of easing the swing requirements of external input drive amplifiers. The external references can vary as long as the value of the external top reference (REFTEXT) is less than or equal to +3.4V, the value of the external bottom reference (REFBEXT) is greater than or equal to +1.1V, and the difference between the external references are greater than or equal to 1.5V. For the differential configuration, the full-scale input range will be set to the external reference values that are selected. For the single-ended mode, the input range is 2 • (REFTEXT – REFBEXT), with the common-mode being centered at (REFTEXT + REFBEXT)/2. Refer to the typical characteristics for “Expected Performance vs Full-Scale Input Range”. The circuit in Figure 10 works completely on a single +5V supply. As a reference element, it uses the micro-power reference REF1004-2.5, which is set to a quiescent current of 0.1mA. Amplifier A2 is configured as a follower to buffer the +1.25V generated from the resistor divider. To provide the necessary current drive, a pull-down resistor, RP, is added. Amplifier A1 is configured as an adjustable gain stage, with a range of approximately 1 to 1.32. The pull-up resistor again relieves the op amp from providing the full current drive. The value of the pull-up/down resistors is not critical and can be varied to optimize power consumption. The need for pull-up, pull-down resistors depends only on the drive capability of the selected drive amplifiers and thus can be omitted. –541 11 12 13 14 15 16 +5V 0.1µF Ext Clk R1 50Ω +VS CLK 0.1µF +VS OE MSBI 0.1µF +VS REFB CM REFT 0.1µF AC Input Signal R2 50Ω 22pF Mini-Circuits TT1-6-KK81 or equivalent (1) 9 8 7 6 5 4 3 2 17 15 16 17 18 19 20 21 ADS800 22 23 24 25 26 27 28 7 6 5 4 3 2 1 MSB GND 1 19 Dir G+ 14 13 12 19 11 10 9 8 11 12 13 14 15 16 17 18 GND LSB 1 Dir G+ –541 18 9 8 7 6 5 4 3 2 0.1µF 0.1µF 0.1µF +VS GND IN IN GND 22pF NOTE: (1) All capacitors should be located as close to the pins as the manufacturing process will allow. Ceramic X7R surface-mount capacitors or equivalent are recommended. FIGURE 9. ADS800 Interface Schematic with AC-Coupling and External Buffers. ADS800 SBAS035B www.ti.com 13 +5V A1 RP 220Ω +5V 10kΩ 1/2 OPA2234 Top Reference +2.5V to +3.25V 2kΩ 6.2kΩ 10kΩ 0.1µF 10kΩ(1) A2 1/2 OPA2234 REF1004 +2.5V +1.25V RP 220Ω 10kΩ 10kΩ(1) Bottom Reference NOTE: (1) Use parts alternatively for adjustment capability. FIGURE 10. Optional External Reference to Set the Full-Scale Range Utilizing a Dual, Single-Supply Op Amp. HP8022A pulse generator for the A/D converter clock, gives excellent results. Low-pass filtering (or bandpass filtering) of test signals is absolutely necessary to test the low distortion of the ADS800. Using a signal amplitude slightly lower than fullscale will allow a small amount of “headroom” so that noise or DC offset voltage will not over-range the A/D converter and cause clipping on signal peaks. PC BOARD LAYOUT AND BYPASSING A well-designed, clean PC board layout will assure proper operation and clean spectral response. Proper grounding and bypassing, short lead lengths, and the use of ground planes are particularly important for high-frequency circuits. Multilayer PC boards are recommended for best performance but if carefully designed, a two-sided PC board with large, heavy ground planes can give excellent results. It is recommended that the analog and digital ground pins of the ADS800 be connected directly to the analog ground plane. In our experience, this gives the most consistent results. The A/D converter power-supply commons should be tied together at the analog ground plane. Power supplies should be bypassed with 0.1µF ceramic capacitors as close to the pin as possible. DYNAMIC PERFORMANCE DEFINITIONS 1. Signal-to-Noise-and-Distortion Ratio (SINAD): 10 log Sinewave Signal Power Noise + Harmonic Power (first 15 harmonics) 2. Signal-to-Noise Ratio (SNR): 10 log Sinewave Signal Power Noise Power DYNAMIC PERFORMANCE TESTING The ADS800 is a high performance converter and careful attention to test techniques is necessary to achieve accurate results. Highly accurate phase-locked signal sources allow high resolution FFT measurements to be made without using data windowing functions. A low jitter signal generator such as the HP8644A for the test signal, phase-locked with a low jitter 3. Intermodulation Distortion (IMD): 10 log Highest IMD Pr oduct Power ( to 5th − order ) Sinewave Signal Power IMD is referenced to the larger of the test signals, f1 or f2. Five “bins” either side of peak are used for calculation of fundamental and harmonic power. The “0” frequency bin (DC) is not included in these calculations as it is of little importance in dynamic signal processing applications. 14 ADS800 www.ti.com SBAS035B PACKAGE OPTION ADDENDUM www.ti.com 14-Feb-2005 PACKAGING INFORMATION Orderable Device ADS800E ADS800E/1K ADS800U ADS800U/1K (1) Status (1) OBSOLETE OBSOLETE ACTIVE ACTIVE Package Type SSOP SSOP SOIC SOIC Package Drawing DB DB DW DW Pins Package Eco Plan (2) Qty 28 28 28 28 28 1000 None None None None Lead/Ball Finish Call TI Call TI CU SNPB CU SNPB MSL Peak Temp (3) Call TI Call TI Level-3-220C-168 HR Level-3-220C-168 HR The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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