ADS801

® ADS ADS 801 E 801 ADS801 U 12-Bit, 25MHz Sampling ANALOG-TO-DIGITAL CONVERTER TM FEATURES q NO MISSING CODES q LOW POWER: 270mW q INTERNAL REFERENCE q WIDEBAND TRACK/HOLD: 65MHz q SINGLE +5V SUPPLY q PACKAGE: 28-Lead SOIC and 28-Lead SSOP DESCRIPTION The ADS801 is a low power, monolithic 12-bit, 25MHz analog-to-digital converter utilizing a small geometry CMOS process. This COMPLETE converter includes a 12-bit quantizer, wideband track/hold, reference, and three-state outputs. It operates from a single +5V power supply and can be configured to accept either single-ended or differential input signals. The ADS801 employs digital error correction to provide excellent Nyquist differential linearity performance for demanding imaging applications. Its low distortion, high SNR and high oversampling capability give it the extra margin needed for telecommunications, instrumentation and video applications. This high performance A/D converter is specified over temperature for AC and DC performance at a 25MHz sampling rate. The ADS820 is available in 28-lead SOIC and 28-lead SSOP packages. APPLICATIONS q IF AND BASEBAND DIGITIZATION q DIGITAL COMMUNICATIONS q TEST INSTRUMENTATION q CCD IMAGING Copiers Scanners Cameras q VIDEO DIGITIZING q GAMMA CAMERAS CLK MSBI OE Timing Circuitry IN T/H IN +3.25V REFT Pipeline A/D Error Correction Logic 3-State Outputs 12-Bit Digital Data CM REFB +1.25V International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1995 Burr-Brown Corporation PDS-1287E Printed in U.S.A. September, 1996 SPECIFICATIONS At TA = +25 °C, VS = +5V, Sampling Rate = 25MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted. ADS801U PARAMETER Resolution Specified Temperature Range ANALOG INPUT Differential Full Scale Input Range Common-Mode Voltage Analog Input Bandwidth (–3dB) Small Signal Full Power Input Impedance DIGITAL INPUT Logic Family Convert Command ACCURACY(3) Gain Error Gain Tempco Power Supply Rejection of Gain Input Offset Error Power Supply Rejection of Offset CONVERSION CHARACTERISTICS Sample Rate Data Latency DYNAMIC CHARACTERISTICS Differential Linearity Error f = 500kHz f = 10MHz No Missing Codes Integral Linearity Error at f = 500kHz Spurious-Free Dynamic Range (SFDR) f = 500kHz (–1dBFS input) f = 10MHz (–1dBFS input) Two-Tone Intermodulation Distortion (IMD)(4) f = 4.4MHz and 4.5MHz (–7dBFS each tone) Signal-to-Noise Ratio (SNR) f = 500kHz (–1dBFS input) f = 10MHz (–1dBFS input) Signal-to-(Noise + Distortion) (SINAD) f = 500kHz (–1dBFS input) f = 10MHz (–1dBFS input) Differential Gain Error Differential Phase Error NTSC or PAL Aperture Delay Time Aperture Jitter Overvoltage Recovery Time(5) NTSC or PAL CONDITIONS TAMBIENT Both Inputs, 180° Out of Phase TEMP MIN –40 +1.25 +2.25 –20dBFS(2) Input 0dBFS Input +25°C +25°C 400 65 1.25 || 4 TTL/HCT Compatible CMOS Falling Edge +25°C Full Delta +VS = ±5% Delta +VS = ±5% +25°C Full +25°C 10k 6.5 ±0.6 ±1.0 ±85 0.03 ±2.1 0.05 ±1.5 ±2.5 0.15 ±3.0 0.15 25M T T TYP 12 +85 +3.25 T(1) T T T T T TTL/HCT Compatible CMOS Falling Edge T T T T T T T T T T T T % % ppm/°C %FSR/% % %FSR/% Sample/s Convert Cycle MAX MIN ADS801E TYP 12 T T MAX UNITS Bits °C V V MHz MHz MΩ || pF Start Conversion +25°C 0°C to +85°C +25°C 0°C to +85°C 0°C to +85°C Full +25°C Full +25°C Full +25°C Full +25°C Full +25°C Full +25°C Full +25°C Full +25°C +25°C +25°C +25°C +25°C 64 61 62 58 63 60 56 54 63 62 57 55 ±0.3 ±0.4 ±0.3 ±0.4 Guaranteed ±1.7 77 73 61 61 –64 –63 66 64 65 64 66 63 59 58 0.5 0.1 2 7 2 ±1.0 ±1.0 ±1.0 ±1.0 ±0.4 ±0.5 ±0.4 ±0.5 Guaranteed T T T T T T T 62 59 T T 61 58 T T 64 T T T 64 T T T T T T T T T T T T LSB LSB LSB LSB LSB LSB dBFS dBFS dBFS dBFS dBc dBc dB dB dB dB dB dB dB dB % degrees ns ps rms ns T T T T 1.5x Full Scale Input NOTE: (1) An asterisk (T) indicates same specifications as the ADS801U. (2) dBFS refers to dB below Full Scale. (3) Percentage accuracies are referred to the internal A/D Full Scale Range of 4Vp-p. (4) IMD is referred to the larger of the two input signals. If referred to the peak envelope signal (≈0dB), the intermodulation products will be 7dB lower. (5) No “rollover” of bits. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® ADS801 2 SPECIFICATIONS PARAMETER OUTPUTS Logic Family Logic Coding Logic Levels (CONT) ADS801U CONDITIONS TEMP MIN TYP MAX MIN ADS801E TYP MAX UNITS At TA = +25°C, VS = +5V, Sampling Rate = 25MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted. Logic Selectable Logic “LO”, CL = 15pF max Logic “HI”, CL = 15pF max Full Full TTL/HCT Compatible CMOS Falling Edge 0 0.4 +2.5 20 2 +4.75 +5.0 54 54 270 270 75 50 +VS 40 10 +5.25 65 68 325 340 TTL/HCT Compatible CMOS Falling Edge T T T T T T T T T T T T T T T T T T T T T V V ns ns V mA mA mW mW °C/W °C/W 3-State Enable Time 3-State Disable Time POWER SUPPLY REQUIREMENTS Supply Voltage: +VS Supply Current: +IS Power Consumption Thermal Resistance, θJA 28-Lead SOIC 28-Lead SSOP T Specifications same as ADS801U. Operating Operating Operating Operating Operating Full Full +25°C Full +25°C Full ABSOLUTE MAXIMUM RATINGS +VS ....................................................................................................... +6V Analog Input ............................................................. 0V to (+VS + 300mV) Logic Input ................................................................ 0V to (+VS + 300mV) Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature ..................................................................... +125°C External Top Reference Voltage (REFT) .................................. +3.4V Max External Bottom Reference Voltage (REFB) .............................. +1.1V Min NOTE: Stresses above these ratings may permanently damage the device. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. BurrBrown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. PACKAGE/ORDERING INFORMATION PACKAGE DRAWING NUMBER(1) 217 324 TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C PRODUCT ADS801U ADS801E PACKAGE 28-Lead SOIC 28-Lead SSOP NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ® 3 ADS801 PIN CONFIGURATION TOP VIEW SOIC/SSOP PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 DESIGNATOR GND B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 GND +VS CLK +VS OE MSBI DESCRIPTION Ground Bit 1, Most Significant Bit Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12, Least Significant Bit Ground +5V Power Supply Convert Clock Input, 50% Duty Cycle +5V Power Supply HI: High Impedance State. LO or Floating: Normal Operation. Internal pull-down resistors. Most Significant Bit Inversion, HI: MSB inverted for complementary output. LO or Floating: Straight output. Internal pull-down resistors. +5V Power Supply Bottom Reference Bypass. For external bypassing of internal +1.25V reference. Common-Mode Voltage. It is derived by (REFT + REFB)/2. Top Reference Bypass. For external bypassing of internal +3.25V reference. +5V Power Supply Ground Input Complementary Input Ground GND B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 GND 1 2 3 4 5 6 7 ADS801 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND IN IN GND +VS REFT CM REFB +VS MSBI OE +VS CLK +VS 20 21 22 23 24 25 26 27 28 +VS REFB CM REFT +VS GND IN IN GND TIMING DIAGRAM tCONV CONVERT CLOCK tL tD Hold "N" tH INTERNAL TRACK/HOLD Track DATA LATENCY (6.5 Clock Cycles) Hold Hold Hold Hold Hold Hold Track "N + 1" Track "N + 2" Track "N + 3" Track "N + 4" Track "N + 5" Track "N + 6" Track (1) t2 OUTPUT DATA Data Valid N-8 Data Valid N-7 Data Valid N-6 N-5 N-4 N-3 N-2 N-1 N Data Invalid t1 SYMBOL tCONV tL tH tD t1 t2 NOTE: (1) “ DESCRIPTION Convert Clock Period Clock Pulse Low Clock Pulse High Aperture Delay Data Hold Time, CL = 0pF New Data Delay Time, CL = 15pF max MIN 40 19 19 3.9 TYP MAX 100µs UNITS ns ns ns ns ns ns 20 20 2 12.5 ” indicates the portion of the waveform that will stretch out at slower sample rates. ® ADS801 4 TYPICAL PERFORMANCE CURVES At TA = +25°C, VS = +5V, Sampling Rate = 25MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted. SPECTRAL PERFORMANCE 0 fIN = 500kHz –20 Amplitude (dB) Amplitude (dB) SPECTRAL PERFORMANCE 0 fIN = 10MHz –20 –40 –60 –80 –100 –120 –40 –60 –80 –100 –120 0 2.5 5.0 7.5 10.0 12.5 Frequency (MHz) 0 2.5 5.0 7.5 10.0 12.5 Frequency (MHz) DIFFERENTIAL LINEARITY ERROR 2.0 fIN = 500kHz 1.0 DLE (LSB) DIFFERENTIAL LINEARITY ERROR 2.0 fIN = 10MHz 1.0 0 DLE (LSB) 0 1024 2048 Code 3072 4096 0 –1.0 –1.0 –2.0 –2.0 0 1024 2048 Code 3072 4096 TWO-TONE INTERMODULATION 0 f1 = 4.5MHz –20 Amplitude (dB) INPUT FREQUENCY vs DYNAMIC PERFORMANCE 80 75 SFDR f2 = 4.4MHz SFDR, SNR (dB) –40 –60 –80 –100 –120 0.0 3.13 6.25 Frequency (MHz) 9.38 12.50 70 65 60 55 50 0.1 1 10 Frequency (MHz) 100 SNR ® 5 ADS801 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25 °C, VS = +5V, Sampling Rate = 25MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted. OUTPUT NOISE HISTOGRAM (NO SIGNAL) 800k SWEPT POWER SFDR 100 fIN = 10MHz 600k 80 SFDR (dBFS) N–2 N–1 N Code N+1 N+2 Counts 60 400k 40 200k 20 0.0 0 –50 –40 –30 –20 –10 0 10 Input Amplitude (dBm) SWEPT POWER SNR 80 fIN = 10MHz 60 INTEGRAL LINEARITY ERROR 4.0 fIN = 500kHz 2.0 ILE (LSB) SNR (dB) 40 0 20 –2.0 0 –50 –40 –30 –20 –10 0 10 Input Amplitude (dBm) –4.0 0 1024 2048 Code 3072 4096 DYNAMIC PERFORMANCE vs SINGLE-ENDED FULL-SCALE INPUT RANGE 65 SNR (fIN = 10MHz) 70 DYNAMIC PERFORMANCE vs DIFFERENTIAL FULL-SCALE INPUT RANGE SFDR (fIN = 10MHz) Dynamic Range (dB) Dynamic Range (dB) 60 65 SFDR (fIN = 10MHz) 55 SNR (fIN = 10MHz) 60 50 1 2 3 4 5 Single-Ended Full-Scale Input Range (Vp-p) 55 1 2 3 4 5 Differential Full-Scale Input Range (Vp-p) ® ADS801 6 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = +5V, Sampling Rate = 25MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted. DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 0.5 fIN = 500kHz 0.4 SPURIOUS FREE DYNAMIC RANGE (SFDR) vs TEMPERATURE 80 75 fIN = 500kHz SFDR (dBFS) DLE (LSBs) 70 0.3 fIN = 10MHz 0.2 65 fIN = 10MHz 60 0.1 –50 –25 0 25 50 75 100 Ambient Temperature (°C) 55 –50 –25 0 25 50 75 100 Ambient Temperature (°C) SIGNAL-TO-NOISE RATIO vs TEMPERATURE 70 70 SIGNAL-TO-(NOISE + DISTORTION) vs TEMPERATURE 65 68 SNR (dB) fIN = 500kHz fIN = 500kHz SINAD (dB) 60 fIN = 10MHz 66 55 64 fIN = 10MHz 50 62 –50 –25 0 25 50 75 100 Ambient Temperature (°C) 45 –50 –25 0 25 50 75 100 Ambient Temperature (°C) SUPPLY CURRENT vs TEMPERATURE 52 265 POWER DISSIPATION vs TEMPERATURE 260 Power (mW) –50 –25 0 25 50 75 100 51 IQ (mA) 255 50 250 49 Ambient Temperature (°C) 245 –50 –25 0 25 50 75 100 Ambient Temperature (°C) ® 7 ADS801 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25 °C, VS = +5V, Sampling Rate = 25MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted. GAIN ERROR vs TEMPERATURE –0.05 –1.50 OFFSET ERROR vs TEMPERATURE Gain (% FSR) –0.55 Offset (% FSR) –50 –25 0 25 50 75 100 –1.75 –1.05 –2.0 –1.55 Ambient Temperature (°C) –2.25 –50 –25 0 25 50 75 100 Ambient Temperature (°C) TRACK-MODE SMALL-SIGNAL INPUT BANDWIDTH 1 Track-Mode Input Response (dB) 0 –1 –2 –3 –4 –5 10k 100k 1M 10M 100M 1G Frequency (Hz) ® ADS801 8 THEORY OF OPERATION The ADS801 is a high speed sampling analog-to-digital converter with pipelining. It uses a fully differential architecture and digital error correction to guarantee 12-bit resolution. The differential track/hold circuit is shown in Figure 1. The switches are controlled by an internal clock which is a non-overlapping two phase signal, φ1 and φ2. At the sampling time the input signal is sampled on the bottom plates of the input capacitors. In the next clock phase, φ2, the bottom plates of the input capacitors are connected together and the feedback capacitors are switched to the op amp output. At this time the charge redistributes between CI and CH, completing one track/hold cycle. The differential output is a held DC representation of the analog input at the sample time. The track/hold circuit can also convert a single-ended input signal into a fully differential signal for the quantizer. The pipelined quantizer architecture has 11 stages with each stage containing a two-bit quantizer and a two bit digital-toanalog converter, as shown in Figure 2. Each two-bit quantizer stage converts on the edge of the sub-clock, which is twice the frequency of the externally applied clock. The output of each quantizer is fed into its own delay line to Op Amp Bias φ1 VCM φ1 CH φ2 CI IN IN φ1 φ1 φ2 CI CH φ1 Input Clock (50%) Op Amp Bias Internal Non-overlapping Clock φ1 φ2 φ1 VCM φ1 φ1 OUT OUT φ2 FIGURE 1. Input Track/Hold Configuration with Timing Signals. IN IN Input T/H 2-Bit Flash STAGE 1 2-Bit DAC Digital Delay Σ x2 + – Digital Delay B1 (MSB) B2 Digital Error Correction 2-Bit Flash STAGE 2 2-Bit DAC B3 B4 B5 B6 B7 B8 B9 B10 Digital Delay B11 B12 (LSB) Σ x2 + – 2-Bit Flash STAGE 10 2-Bit DAC Σ x2 + – STAGE 11 2-Bit Flash Digital Delay FIGURE 2. Pipeline A/D Architecture. ® 9 ADS801 time-align it with the data created from the following quantizer stages. This aligned data is fed into a digital error correction circuit which can adjust the output data based on the information found on the redundant bits. This technique gives the ADS801 excellent differential linearity and guarantees no missing codes at the 12-bit level. Since there are two pipeline stages per external clock cycle, there is a 6.5 clock cycle data latency from the start convert signal to the valid output data. The output data is available in Straight Offset Binary (SOB) or Binary Two’s Complement (BTC) format. THE ANALOG INPUT AND INTERNAL REFERENCE The analog input of the ADS801 can be configured in various ways and driven with different circuits, depending on the nature of the signal and the level of performance desired. The ADS801 has an internal reference that sets the full scale input range of the A/D. The differential input range has each input centered around the common-mode of +2.25V, with each of the two inputs having a full scale range of +1.25V to +3.25V. Since each input is 2V peak-to-peak and 180° out of phase with the other, a 4V differential input signal to the quantizer results. As shown in Figure 3, the positive full scale reference (REFT) and the negative full scale (REFB) are brought out for external bypassing. In addition, the common-mode voltage (CM) may be used as a reference to provide the appropriate offset for the driving circuitry. However, care must be taken not to appreciably load this reference node. For more information regarding external references, single-ended input, and ADS801 drive circuits, refer to the applications section. ADS801 +3.25V 23 0.1µF 2kΩ 22 CM 2kΩ 21 0.1µF REFB +1.25V To Internal Comparators REFT DIGITAL OUTPUT DATA The 12-bit output data is provided at CMOS logic levels. The standard output coding is Straight Offset Binary where a full scale input signal corresponds to all “1’s” at the output. This condition is met with pin 19 “LO” or Floating due to an internal pull-down resistor. By applying a logic “HI” voltage to this pin, a Binary Two’s Complement output will be provided where the most significant bit is inverted. The digital outputs of the ADS801 can be set to a high impedance state by driving OE (pin 18) with a logic “HI”. Normal operation is achieved with pin 18 “LO” or Floating due to internal pull-down resistors. This function is provided for testability purposes and is not meant to drive digital buses directly or be dynamically changed during the conversion process. OUTPUT CODE SOB PIN 19 FLOATING or LO 111111111111 111111111111 111111111110 111000000000 110000000000 101000000000 100000000001 100000000000 011111111111 011000000000 010000000000 001000000000 000000000001 000000000000 BTC PIN 19 HI 011111111111 011111111111 011111111110 011000000000 010000000000 001000000000 000000000001 000000000000 111111111111 111000000000 110000000000 101000000000 100000000001 100000000000 DIFFERENTIAL INPUT(1) +FS (IN = +3.25V, IN = +1.25V) +FS –1LSB +FS –2LSB +3/4 Full Scale +1/2 Full Scale +1/4 Full Scale +1LSB Bipolar Zero (IN = IN = +2.25V) –1LSB –1/4 Full Scale –1/2 Full Scale –3/4 Full Scale –FS +1LSB –FS (IN = +1.25V, IN = +3.25V) Note: In the single-ended input mode, +FS = +4.25V and –FS = +0.25V. TABLE I. Coding Table for the ADS801. APPLICATIONS DRIVING THE ADS801 The ADS801 has a differential input with a common-mode of +2.25V. For AC-coupled applications, the simplest way to create this differential input is to drive the primary winding of a transformer with a single-ended input. A differential output is created on the secondary if the center tap is tied to the common-mode voltage of +2.25V per Figure 4. This transformer-coupled input arrangement pro- +2.25V FIGURE 3. Internal Reference Structure. CLOCK REQUIREMENTS The CLK pin accepts a CMOS level clock input. The rising and falling edges of the externally applied convert command clock control the various interstage conversions in the pipeline. Therefore, the duty cycle of the clock should be held at 50% with low jitter and fast rise/fall times of 2ns or less. This is particularly important when digitizing a high frequency input and operating at the maximum sample rate. Deviation from a 50% duty cycle will effectively shorten some of the interstage settling times, thus degrading the SNR and DNL performance. ® 22 CM 0.1µF AC Input Signal 26 IN 22pF ADS801 Mini-Circuits T T1-6-KK81 or equivalent 27 IN 22pF FIGURE 4. AC-Coupled Single-Ended to Differential Drive Circuit Using a Transformer. 10 ADS801 vides good high frequency AC performance. It is important to select a transformer that gives low distortion and does not exhibit core saturation at full scale voltage levels. Since the transformer does not appreciably load the ladder, there is no need to buffer the common-mode (CM) output in this instance. In general, it is advisable to keep the current draw from the CM output pin below 0.5µA to avoid nonlinearity in the internal reference ladder. A FET input operational amplifier such as the OPA130 can provide a buffered reference for driving external circuitry. The analog IN and IN inputs should be bypassed with 22pF capacitors to minimize track/hold glitches and to improve high input frequency performance. Figure 5 illustrates another possible low cost interface circuit which utilizes resistors and capacitors in place of a transformer. Depending on the signal bandwidth, the component values should be carefully selected in order to maintain the performance outlined in the data sheet. The input capacitors, CIN, and the input resistors, RIN, create a high-pass filter with the lower corner frequency at fC = 1/(2πRINCIN). The corner frequency can be reduced by either increasing the value of RIN or CIN. If the circuit operates with a 50Ω or 75Ω impedance level, the resistors are fixed and only the value of the capacitor can be increased. Usually AC-coupling capacitors are electrolytic or tantalum capacitors with values of 1µF or higher. It should be noted that these large capacitors become inductive with increased input frequency, which could lead to signal amplitude errors or oscillation. To maintain a low AC-coupling impedance throughout the signal band, a small value (e.g. 1µF) ceramic capacitor could be added in parallel with the polarized capacitor. Capacitors CSH1 and CSH2 are used to minimize current glitches resulting from the switching in the input track and hold stage and to improve signal-to-noise performance. These capacitors can also be used to establish a low-pass filter and effectively reduce the noise bandwidth. In order to create a real pole, resistors RSER1 and RSER2 were added in series with each input. The cut-off frequency of the filter is determined by fC = 1/(2πRSER•(CSH+CADC)) where RSER is the resistor in series with the input, CSH is the external capacitor from the input to ground, and CADC is the internal input capacitance of the A/D converter (typically 4pF). Resistors R1 and R2 are used to derive the necessary common mode voltage from the buffered top and bottom references. The total load of the resistor string should be selected so that the current does not exceed 1mA. Although the circuit in Figure 5 uses two resistors of equal value so that the common mode voltage is centered between the top and bottom reference (+2.25V), it is not necessary to do so. In all cases the center point, VCM, should be bypassed to ground in order to provide a low impedance AC ground. If the signal needs to be DC coupled to the input of the ADS801, an operational amplifier input circuit is required. In the differential input mode, any single-ended signal must be modified to create a differential signal. This can be accomplished by using two operational amplifiers, one in the noninverting mode for the input and the other amplifier in the inverting mode for the complementary input. The low distortion circuit in Figure 6 will provide the necessary input shifting required for signals centered around ground. It also employs a diode for output level shifting to guarantee a low distortion +3.25V output swing. Other amplifiers can be used in place of the OPA642s if the lowest distortion is not necessary. If output level shifting circuits are not used, care must be taken to select operational amplifiers that give the necessary performance when swinging to +3.25V with a ±5V supply operational amplifier. The ADS801 can also be configured with a single-ended input full scale range of +0.25V to +4.25V by tying the complementary input to the common-mode reference voltage as shown in Figure 7 . This configuration will result in increased even-order harmonics, especially at higher input frequencies. However, this tradeoff may be quite acceptable for time-domain applications. The driving amplifier must give adequate performance with a +0.25V to +4.25V output swing in this case. C1 0.1µF CIN 0.1µF RIN1 25Ω *RSER1 49.9Ω R1 (6kΩ) IN R3 1kΩ C2 0.1µF VCM CSH1 22pF +3.25V Top Reference ADS8xx RIN2 25Ω CIN 0.1µF *RSER2 49.9Ω R2 (6kΩ) CSH2 22pF IN +1.25V Bottom Reference NOTE: * indicates optional component. C3 0.1µF FIGURE 5. AC-Coupled Differential Input Circuit. ® 11 ADS801 604Ω +5V BAS16(1) Optional High Impedance Input Amplifier 301Ω +5V(2) –5V DC-Coupled Input Signal OPA642 604Ω 301Ω OPA642 +5V 301Ω 27 IN 2.49kΩ 0.1µF 0.1µF +5V 604Ω 49.9Ω OPA130 +5V 2.49kΩ +2.25V 22 CM ADS801 22pF –5V 301Ω 24.9Ω +5V BAS16(1) OPA642 22pF 0.1µF –5V 301Ω 604Ω NOTES: (1) A Philips BAS16 diode or equivalent may be used. (2) Supply bypassing not shown. 301Ω Input Level Shift Buffer 26 IN FIGURE 6. A Low Distortion DC-Coupled, Single-Ended to Differential Input Driver Circuit. REFBEXT), with the common-mode being centered at (REFTEXT + REFBEXT)/2. Refer to the typical performance curves for expected performance vs full scale input range. The circuit in Figure 8 works completely on a single +5V supply. As a reference element, it uses the micro-power reference REF1004-2.5, which is set to a quiescent current of 0.1mA. Amplifier A2 is configured as a follower to buffer the +1.25V generated from the resistor divider. To provide the necessary current drive, a pull-down resistor, RP is added. Amplifier A1 is configured as an adjustable gain stage, with a range of approximately 1 to 1.32. The pull-up resistor again relieves the op amp from providing the full current drive. The value of the pull-up/down resistors is not critical and can be varied to optimize power consumption. The need for pull-up/down resistors depends only on the drive capability of the selected drive amplifier and thus can be omitted. PC BOARD LAYOUT AND BYPASSING A well-designed, clean PC board layout will assure proper operation and clean spectral response. Proper grounding and bypassing, short lead lengths, and the use of ground planes are particularly important for high frequency circuits. Multilayer PC boards are recommended for best performance but if carefully designed, a two-sided PC board with large, heavy ground planes can give excellent results. It is recommended that the analog and digital ground pins of the ADS801 be connected directly to the analog ground plane. In our experience, this gives the most consistent results. The A/D power supply commons should be tied together at the analog ground plane. Power supplies should be bypassed with 0.1µF ceramic capacitors as close to the pin as possible. 22 CM 0.1µF Single-Ended Input Signal 26 IN 27 IN 22pF ADS801 Full Scale = +0.25V to +4.25V with internal references. FIGURE 7. Single-Ended Input Connection. EXTERNAL REFERENCES AND ADJUSTMENT OF FULL SCALE RANGE The internal reference buffers are limited to approximately 1mA of output current. As a result, these internal +1.25V and +3.25V references may be overridden by external references that have at least 18mA (at room temperature) of output drive capability. In this instance, the common-mode voltage will be set halfway between the two references. This feature can be used to adjust the gain error, improve gain drift, or to change the full scale input range of the ADS801. Changing the full scale range to a lower value has the benefit of easing the swing requirements of external input amplifiers. The external references can vary as long as the value of the external top reference (REFTEXT) is less than or equal to +3.4V and the value of the external bottom reference (REFBEXT) is greater than or equal to +1.1V and the difference between the external references are greater than or equal to 1.5V. For the differential configuration, the full scale input range will be set to the external reference values that are selected. For the single-ended mode, the input range is 2•(REFTEXT – ® ADS801 12 DYNAMIC PERFORMANCE TESTING The ADS801 is a high performance converter and careful attention to test techniques is necessary to achieve accurate results. Highly accurate phase-locked signal sources allow high resolution FFT measurements to be made without using data windowing functions. A low jitter signal generator such as the HP8644A for the test signal, phase-locked with a low jitter HP8022A pulse generator for the A/D clock, gives excellent results. Low pass filtering (or bandpass filtering) of test signals is absolutely necessary to test the low distortion of the ADS801. Using a signal amplitude slightly lower than full scale will allow a small amount of “headroom” so that noise or DC offset voltage will not overrange the A/D and cause clipping on signal peaks. DYNAMIC PERFORMANCE DEFINITIONS 1. Signal-to-Noise-and-Distortion Ratio (SINAD): Sinewave Signal Power 10 log Noise + Harmonic Power (first 15 harmonics) 2. Signal-to-Noise Ratio (SNR): Sinewave Signal Power 10 log Noise Power 3. Intermodulation Distortion (IMD): Highest IMD Product Power (to 5th-order) 10 log Sinewave Signal Power IMD is referenced to the larger of the test signals f1 or f2. Five “bins” either side of peak are used for calculation of fundamental and harmonic power. The “0” frequency bin (DC) is not included in these calculations as it is of little importance in dynamic signal processing applications. +5V +5V 10kΩ 6.2kΩ 10kΩ 0.1µF 10kΩ* 10kΩ* 10kΩ A1 1/2 OPA2234 RP 220Ω Top Reference +2.5V to +3.25V 2kΩ REF1004 +2.5V A2 1/2 OPA2234 +1.25V RP 220Ω Bottom Reference NOTE: (*) Use parts alternatively for adjustment capability. FIGURE 8. Optional External Reference to Set the Full-Scale Range Utilizing a Dual, Single-Supply Op Amp. IDT74FCT2245 11 12 13 14 15 16 +5V 0.1µF Ext Clk R1 50Ω +VS CLK 0.1µF +VS OE MSBI 0.1µF +VS REFB CM REFT 0.1µF AC Input Signal R2 50Ω 22pF Mini-Circuits T T1-6-KK81 or equivalent (1) 9 8 7 6 5 4 3 2 17 15 16 17 18 19 20 21 ADS800 22 23 24 25 26 27 28 7 6 5 4 3 2 1 MSB GND 1 19 Dir G+ 14 13 12 19 11 10 9 8 11 12 13 14 15 16 17 18 GND LSB 1 Dir G+ IDT74FCT2245 18 9 8 7 6 5 4 3 2 0.1µF 0.1µF 0.1µF +VS GND IN IN GND 22pF NOTE: (1) All capacitors should be located as close to the pins as the manufacturing process will allow. Ceramic X7R surface-mount capacitors or equivalent are recommended. FIGURE 9. ADS801 Interface Schematic with AC-Coupling and External Buffers. 13 ® ADS801