ADS805U

® ADS 805 U ADS805 ADS 805 E 12-Bit, 20MHz Sampling ANALOG-TO-DIGITAL CONVERTER TM FEATURES q q q q q HIGH SFDR: 74dB at 9.8MHz fIN HIGH SNR: 68dB LOW POWER: 300mW LOW DLE: 0.25LSB SMALL 28-LEAD SSOP AND SOIC PACKAGES q FLEXIBLE INPUT RANGE q OVER-RANGE INDICATOR APPLICATIONS q q q q STUDIO CAMERAS IF AND BASEBAND DIGITIZATION COPIERS TEST INSTRUMENTATION DESCRIPTION The ADS805 is a 20MHz, high dynamic range, 12-bit pipelined analog-to-digital converter. This converter includes a high-bandwidth track/hold that gives excellent spurious performance up to and beyond the Nyquist rate. This high-bandwidth, linear track/hold minimizes harmonics and has low jitter, leading to excellent SNR performance. The ADS805 is also pin-compatible with the 10MHz ADS804 and the 5MHz ADS803. The ADS805 provides an internal reference or an external reference can be used. ADS805 can be programmed for a 2Vp-p input range which is the easiest to drive with a single op amp and provides the best spurious performance. Alternatively, the 5Vp-p input range can be used for the lowest input-referred noise of 0.09 LSBs rms giving +VS superior imaging performance. There is also the capability to set the input range between 2Vp-p and 5Vp-p, either single-ended or differential. The ADS805 also provides an overrange flag that indicates when the input signal has exceeded the converter’s full scale range. This flag can also be used to reduce the gain of the front end signal conditioning circuitry. The ADS805 employs digital error techniques to provide excellent differential linearity for demanding imaging applications. Its low distortion and high SNR give the extra margin needed for communications, medical imaging, video and test instrumentation applications. The ADS805 is available in 28-lead SSOP and SOIC packages. CLK VDRV ADS805 Timing Circuitry VIN IN T/H IN 12-Bit Pipelined A/D Core Error Correction Logic 3-State Outputs D0 • • • D11 CM Reference Ladder and Driver Reference and Mode Select OVR REFT VREF SEL REFB OE International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1997 Burr-Brown Corporation PDS-1397C Printed in U.S.A. October, 1998 SPECIFICATIONS At TA = full specified temperature range, VS = +5V, specified input range = 1.5V to 3.5V, single-ended input and sampling rate = 20MHz, unless otherwise specified. ADS805U PARAMETER RESOLUTION SPECIFIED TEMPERATURE RANGE CONVERSION CHARACTERISTICS Sample Rate Data Latency ANALOG INPUT Standard Single-Ended Input Range Optional Single-Ended Input Range Standard Common-Mode Voltage Standard Optional Common-Mode Voltage Input Capacitance Track-Mode Input Bandwidth DYNAMIC CHARACTERISTICS Differential Linearity Error (Largest Code Error) f = 500kHz No Missing Codes Spurious Free Dynamic Range(2) f = 9.8MHz Two-Tone Intermodulation Distortion(4) f = 7.7MHz and 7.9MHz (–7dB each tone) Signal-to-Noise Ratio (SNR) f = 9.8MHz Signal-to-(Noise + Distortion) (SINAD) f = 9.8MHz Effective Number of Bits at 9.8MHz(5) Input Referred Noise Integral Nonlinearity Error f = 500kHz Aperture Delay Time Aperture Jitter Overvoltage Recovery Time Full-Scale Step Acquisition Time DIGITAL INPUTS Logic Family Convert Command High Level Input Current (VIN = 5V)(6) Low Level Input Current (VIN = 0V) High Level Input Voltage Low Level Input Voltage Input Capacitance DIGITAL OUTPUTS Logic Family Logic Coding Low Output Voltage Low Output Voltage High Output Voltage High Output Voltage 3-State Enable Time 3-State Disable Time Output Capacitance ACCURACY (5Vp-p Input Range) Zero Error (Referred to –FS) Zero Error Drift (Referred to –FS) Gain Error(7) Gain Error Drift(7) Gain Error(8) Gain Error Drift(8) Power Supply Rejection of Gain Reference Input Resistance Internal Voltage Reference Tolerance (VREF = 2.5V) Internal Voltage Reference Tolerance (VREF = 1.0V) 10k 6 1.5 0 2.5 1 20 270 3.5 5 T T T T T T CONDITIONS MIN TYP MAX MIN ADS805E TYP T(1) –40 to +85 20M T T T T T MAX UNITS Bits °C Samples/s Clk Cycles V V V V pF MHz 12 Bits Guaranteed –40 to +85 –3dBFS Input ±0.25 ±0.75 Guaranteed 65 74 –70 63 62 0V to 5V Input 1.5V to 3.5V Input 68 66 10.7 0.09 0.23 ±1 3 4 2 20 ±2 T T T T Guaranteed T T T T T T T T T T T 20 T LSB dBFS dBc dBFS dBFS Bits LSBs rms LSBs rms T LSB ns ps rms ns ns 1.5X FS Input Start Conversion CMOS Compatible CMOS Rising Edge of Convert Clock Rising Edge ±100 10 +3.5 T +1.0 5 CMOS/TTL Compatible Straight Offset Binary 0.1 0.4 +4.5 +2.4 20 40 2 10 5 0.3 ±5 0.7 ±18 0.2 ±10 70 1.6 ±1.5 ±2.0 Compatible of Convert Clock T T T T µA µA V V pF (IOL = 50µA) (IOL = 1.6mA) (IOH = 50µA) (IOH = 0.5mA) OE = L OE = H CMOS/TTL Compatible Straight Offset Binary T T T T T T T T T T T T T T T T T T T T T V V V V ns ns pF %FS ppm/°C %FS ppm/°C %FS ppm/°C dB kΩ mV mV At 25°C At 25°C At 25°C ∆ VS = ±5% At 25°C At 25°C 60 ±1.5 ±35 ±14 ® ADS805 2 SPECIFICATIONS (CONT) At TA = full specified temperature range, VS = +5V, specified input range = 1.5V to 3.5V, single-ended input and sampling rate = 20MHz, unless otherwise specified. ADS805U PARAMETER POWER SUPPLY REQUIREMENTS Supply Voltage: +VS Supply Current: +IS Power Dissipation Thermal Resistance, θJA 28-Lead SOIC 28-Lead SSOP CONDITIONS MIN TYP MAX MIN T ADS805E TYP T T T MAX T T T UNITS Operating Operating Operating +4.75 +5.0 60 300 75 +5.25 69 345 V mA mW °C/W °C/W 50 NOTES: (1) An asterisk (T) indicates same specifications as the ADS805U. (2) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (3) dBFS means dB relative to full scale. (4) Two-tone intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental envelope. (5) Effective number of bits (ENOB) is defined by (SINAD – 1.76)/6.02. (6) Internal 50kΩ pull down resistor. (7) Includes internal reference. (8) Excludes internal reference. ABSOLUTE MAXIMUM RATINGS +VS ....................................................................................................... +6V Analog Input ........................................................... (–0.3V) to (+VS +0.3V) Logic Input ............................................................. (–0.3V) to (+VS +0.3V) Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature ..................................................................... +150°C ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DEMO BOARD ORDERING INFORMATION PRODUCT ADS805U DEMO BOARD DEM-ADS80xU PACKAGE/ORDERING INFORMATION PACKAGE DRAWING NUMBER(1) 217 324 " SPECIFIED TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C " PACKAGE MARKING ADS805U ADS805E " ORDERING NUMBER ADS805U ADS805E ADS805E/1K TRANSPORT MEDIA Rails Rails Tape and Reel PRODUCT ADS805U ADS805E " PACKAGE SO-28 Surface Mount SSOP-28 Surface Mount " NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. For detailed Tape and Reel mechanical information refer to Appendix B of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 ADS805 PIN CONFIGURATION Top View SOIC/SSOP PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DESIGNATOR OVR B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 CLK OE DESCRIPTION Over Range Indicator Data Bit 1 (D11) (MSB) Data Bit 2 (D10) Data Bit 3 (D9) Data Bit 4 (D8) Data Bit 5 (D7) Data Bit 6 (D6) Data Bit 7 (D5) Data Bit 8 (D4) Data Bit 9 (D3) Data Bit 10 (D2) Data Bit 11 (D1) Data Bit 12 (D0) (LSB) Convert Clock Input Output Enable. H = High Impedance State. L = LOW or floating, normal operation (internal pull-down resistor). +5V Supply Ground Input Range Select Reference Voltage Select Bottom Reference Common-Mode Voltage Top Reference Complementary Analog Input Ground Analog Input (+) Ground +5V Supply Output Driver Voltage OVR B1 B2 B3 B4 B5 B6 B7 B8 1 2 3 4 5 6 7 ADS805 8 9 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDRV +VS GND IN GND IN REFT CM REFB VREF SEL GND +VS OE B9 10 B10 11 B11 12 B12 13 CLK 14 16 17 18 19 20 21 22 23 24 25 26 27 28 +VS GND SEL VREF REFB CM REFT IN GND IN GND +VS VDRV TIMING DIAGRAM N+1 Analog In N tD Clock tCONV N+2 N+3 N+4 N+5 tL tH N+6 N+7 6 Clock Cycles t2 Data Out N–6 N–5 N–4 N–3 N–2 N-1 t1 N N+1 Data Invalid SYMBOL tCONV tL tH tD t1 t2 DESCRIPTION Convert Clock Period Clock Pulse Low Clock Pulse High Aperture Delay Data Hold Time, CL = 0pF New Data Delay Time, CL = 15pF max MIN 50 24 24 3.9 TYP MAX 100µs UNITS ns ns ns ns ns ns 25 25 3 12 ® ADS805 4 TYPICAL PERFORMANCE CURVES At TA = full specified temperature range, VS = +5V, specified single-ended input range = 1.5V to 3.5V, sampling rate = 20MHz, unless otherwise specified. SPECTRAL PERFORMANCE 0 fIN = 500kHz –20 –20 0 SPECTRAL PERFORMANCE fIN = 9.8MHz Amplitude (dB) –60 –80 –100 –120 0 2.0 4.0 6.0 8.0 10.0 Frequency (MHz) Amplitude (dB) –40 –40 –60 –80 –100 –120 0 2.0 4.0 6.0 8.0 10.0 Frequency (MHz) FREQUENCY SPECTRUM 0 –20 f7 = 7.7MHz at –7dBFS f2 = 7.9MHz at –7dBFS IMD (3) = –70dBc 1.0 DIFFERENTIAL LINEARITY ERROR fIN = 9.8MHz Code Width Error (LSB) Magnitude (dBFSR) 0.5 –40 –60 –80 –100 –120 0 2.5 5.0 Frequency (MHz) 7.5 10.0 0 –0.5 –1.0 0 1024 2048 Output Code 3072 4096 INTEGRAL LINEARITY ERROR 4.0 fIN = 500kHz 2.0 SWEPT POWER SFDR 100 fIN = 9.8MHz 80 SFDR (dBFS, dBc) dBFS 60 dBc ILE (LSB) 0 40 –2.0 20 –4.0 0 1024 2048 Output Code 3072 4096 0 –60 –50 –40 –30 –20 –10 0 Input Amplitude (dBFS) ® 5 ADS805 TYPICAL PERFORMANCE CURVES (CONT) At TA = full specified temperature range, VS = +5V, specified single-ended input range = 1.5V to 3.5V, sampling rate = 20MHz, unless otherwise specified. DYNAMIC PERFORMANCE vs INPUT FREQUENCY 85 SFDR 0.6 DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 80 SFDR, SNR (dBFS) fIN = 9.8MHz DLE (LSB) 75 0.4 70 SNR 0.2 65 fIN = 500kHz 60 0.1 1 Frequency (MHz) 10 0 –50 –25 0 25 Temperature (°C) 50 75 100 85 SPURIOUS FREE DYNAMIC RANGE vs TEMPERATURE SIGNAL-TO-NOISE RATIO vs TEMPERATURE 72 fIN = 500kHz fIN = 500kHz 70 SFDR (dBFS) SNR (dBFS) 80 68 fIN = 9.8MHz 66 75 fIN = 9.8MHz 70 –50 –25 0 25 50 75 100 Temperature (°C) 64 –50 –25 0 25 50 75 100 Temperature (°C) SIGNAL-TO-(NOISE+DISTORTION) vs TEMPERATURE 72 305 POWER DISSIPATION vs TEMPERATURE 70 SINAD (dBFS) 68 Power (mW) fIN = 500kHz 300 295 66 fIN = 9.8MHz 64 –50 –25 0 25 50 75 100 Temperature (°C) 290 –50 –25 0 25 50 75 100 Temperature (°C) ® ADS805 6 TYPICAL PERFORMANCE CURVES (CONT) At TA = full specified temperature range, VS = +5V, specified single-ended input range = 1.5V to 3.5V, sampling rate = 20MHz, unless otherwise specified. OUTPUT NOISE HISTOGRAM (DC INPUT) 800k 800k OUTPUT NOISE HISTOGRAM (DC Input, VIN = 5Vp-p Range) 600k 600k Counts N-2 N-1 N Code N+1 N+2 Counts 400k 400k 200k 200k 0 0 N-2 N-1 N Code N+1 N+2 UNDERSAMPLING (Differential Input, 2Vp-p) 0 –20 fS = 20MHz fIN = 41MHz SNR = 63.2dBFS SFDR = 76.3dBFS Magnitude (dB) –40 –60 –80 –100 –120 0 2.0 4.0 6.0 8.0 10.0 Frequency (MHz) ® 7 ADS805 APPLICATION INFORMATION DRIVING THE ANALOG INPUT The ADS805 allows its analog inputs to be driven either single-ended or differentially. The focus of the following discussion is on the single-ended configuration. Typically, its implementation is easier to achieve and the rated specifications for the ADS805 are characterized using the singleended mode of operation. AC-COUPLED INPUT CONFIGURATION Given in Figure 1 is the circuit example of the most common interface configuration for the ADS805. With the VREF pin connected to the SEL pin, the full-scale input range is defined to be 2Vp-p. This signal is ac-coupled in singleended form to the ADS805 using the low distortion voltagefeedback amplifier OPA642. As is generally necessary for single-supply components, operating the ADS805 with a full-scale input signal swing requires a level-shift of the amplifier’s zero centered analog signal to comply with the A/D converter’s input range requirements. Using a DC blocking capacitor between the output of the driving amplifier and the converter’s input, a simple level-shifting scheme can be implemented. In this configuration, the top and bottom references (REFT, REFB) provide an output voltage of +3V and +2V, respectively. Here, two resistor pairs (2 x 2kΩ) are used to create a common-mode voltage of approximately +2.5V to bias the inputs of the ADS805 (IN, IN) to the required DC voltage. An advantage of ac-coupling is that the driving amplifier still operates with a ground-based signal swing. This will keep the distortion performance at its optimum since the signal swing stays within the linear region of the op amp and sufficient headroom to the supply rails can be maintained. Consider using the inverting gain configuration to eliminate CMR induced errors of the amplifier. The addition of a small series resistor (RS) between the output of the op amp and the input of the ADS805 will be beneficial in almost all interface configurations. This will decouple the op amp’s output from the capacitive load and avoid gain peaking, which can result in increased noise. For best spurious and distortion performance, the resistor value should be kept below 100Ω. Furthermore, the series resistor, together with the 100pF capacitor, establish a passive low-pass filter, limiting the bandwidth for the wideband noise, thus help improving the signal-to-noise performance. DC-COUPLED WITHOUT LEVEL SHIFT In some applications the analog input signal may already be biased at a level which complies with the selected input range and reference level of the ADS805. In this case, it is only necessary to provide an adequately low source impedance to the selected input, IN or IN. Always consider wideband op amps since their output impedance will stay low over a wide range of frequencies. DC-COUPLED WITH LEVEL SHIFT Several applications may require that the bandwidth of the signal path includes DC, in which case the signal has to be DC-coupled to the A/D converter. In order to accomplish this, the interface circuit has to provide a DC-level shift. The circuit shown in Figure 2 utilizes the single-supply, current feedback op amp OPA681 (A1), to sum the ground centered input signal with a required DC offset. The ADS805 typically operates with a +2.5V common-mode voltage, which is established with resistors R3 and R4 and connected to the IN input of the converter. Amplifier A1 operates in inverting configuration. Here, resistors R1 and R2 set the DC-bias level for A1. Because of the op amp’s noise gain of +2V/V, assuming RF = RIN, the DC offset voltage applied to its noninverting input has to be divided down to +1.25V, resulting in a DC output voltage of +2.5V. DC voltage differences between the IN and IN inputs of the ADS805 effectively will produce an offset, which can be corrected for by adjusting +5V –5V RS 24.9Ω 2kΩ 2kΩ IN 100pF RF 402Ω 2kΩ REFT (+3V) +VIN –VIN VIN OPA642 0V 2Vp-p 0.1µF ADS805 +2.5V 0.1µF 2kΩ RG 402Ω IN (+2V) REFB (+1V) VREF SEL FIGURE 1. AC-Coupled Input Configuration for 2Vp-p Input Swing and Common-Mode Voltage at +2.5V Derived from Internal Top and Bottom Reference. ® ADS805 8 RF +1V 0 –1V 2Vp-p VIN OPA681 22pF RIN +VS R3 2kΩ IN REFT RS 50Ω R1 +VS R2 ADS805 +2.5V 0.1µF + IN 0.1µF R4 2kΩ REFB (+1V) VREF 10µF SEL NOTE: RF = RIN, G = –1 FIGURE 2. DC-Coupled, Single-Ended Input Configuration with DC-level Shift. the values of resistors R1 and R2. The bias current of the op amp may also result in an undesired offset. The selection criteria for an appropriate op amp should include the input bias current, output voltage swing, distortion and noise specification. Note that in this example the overall signal phase is inverted. To re-establish the original signal polarity it is always possible to interchange the IN and IN connections. SINGLE-ENDED-TO-DIFFERENTIAL CONFIGURATION (TRANSFORMER COUPLED) In order to select the best suited interface circuit for the ADS805, the performance requirements must be known. If an ac-coupled input is needed for a particular application, the next step is to determine the method of applying the signal; either single-ended or differentially. The differential input configuration may provide a noticeable advantage of achieving good SFDR performance based on the fact that in the differential mode the signal swing can be reduced to half of the swing required for single-ended drive. Secondly, by driving the ADS805 differentially, the even-order harmonics will be reduced. Figure 3 shows the schematic for the suggested transformer coupled interface circuit. The resistor across the secondary side (RT) should be set to get an input impedance match (e.g., RT = n2 • RG). One application example that will benefit from the differential input configuration is the digitization of IF signals. The wide track-and-hold input bandwidth makes the ADS805 well suited for IF down conversion in both narrow and wideband applications. The ADS805 maintains excellent dynamic performance in multiple Nyquist regions covering a variety of IF frequencies (see Typical Performance Curves). Using the ADS805 for direct IF conversion eliminates the need of an analog mixer along with subsequent functions like amplifiers and filters thus reducing system cost and complexity. RG 0.1µF VIN 100pF RT ADS805 22Ω IN 100pF + CM 1:n 22Ω IN 4.7µF 0.1µF FIGURE 3. Transformer Coupled Input. REFERENCE OPERATION Integrated into the ADS805 is a bandgap reference circuit including logic that provides either a +1V or +2.5V reference output, by simply selecting the corresponding pin-strap configuration. Different reference voltages can be generated by the use of two external resistors, which will set a different gain for the internal reference buffer. For more design flexibility, the internal reference can be shut off and an external reference voltage used. Table I provides an overview of the possible reference options and pin configurations. INPUT FULL-SCALE RANGE 2Vp-p 5Vp-p 2V≤ FSR < 5V FSR = 2 x VREF External 1V < FSR < 5V MODE Internal Internal Internal REQUIRED VREF +1V +2.5V 1V < VREF < 2.5V VREF = 1 + (R1/R2) 0.5V < VREF < 2.5V CONNECT SEL SEL R1 R2 SEL VREF TO VREF GND VREF and SEL SEL and Gnd +VS Ext. VREF TABLE I. Selected Reference Configuration Examples. ® 9 ADS805 Disable Switch 1VDC to A/D SEL VREF Resistor Network and Switches REFT 800Ω Bandgap and Logic Reference Driver CM 800Ω REFB to A/D ADS805 FIGURE 4. Equivalent Reference Circuit. A simple model of the internal reference circuit is shown in Figure 4. The internal blocks are a 1V-bandgap voltage reference, buffer, the resistive reference ladder and the drivers for the top and bottom reference which supply the necessary current to the internal nodes. As shown, the output of the buffer appears at the VREF pin. The full-scale input span of the ADS805 is determined by the voltage at VREF, according to the Equation 1: Full-Scale Input Span = 2 x VREF (1) IN REFT 0.1µF ADS805 R2 IN REFB 0.1µF R1 CMV operation with all reference configurations, it is necessary to provide solid bypassing to the reference pins in order to keep the clock feedthrough to a minimum. Figure 5 shows the recommended decoupling network. Note that the current drive capability of this amplifier is limited to approximately 1mA and should not be used to drive low loads. The programmable reference circuit is controlled by the voltage applied to the select pin (SEL). Refer to Table I for an overview. The top reference (REFT) and the bottom reference (REFB) are brought out mainly for external bypassing. For proper ADS805 REFT 0.1µF 10µF + 0.1µF 0.1µF 0.1µF 0.1µF + REFB CM VREF FIGURE 6. Alternative Circuit to Generate Common-Mode Voltage. In addition, the common-mode voltage (CMV) may be used as a reference level to provide the appropriate offset for the driving circuitry. However, care must be taken not to appreciably load this node, which is not buffered and has a high impedance. An alternate method of generating a commonmode voltage is given in Figure 6. Here, two external precision resistors (tolerance 1% or better) are located between the top and bottom reference pins. The commonmode level will appear at the midpoint. The output buffers of the top and bottom reference are designed to supply approximately 2mA of output current. 10µF FIGURE 5. Recommended Reference Bypassing Scheme. ® ADS805 10 SELECTING THE INPUT RANGE AND REFERENCE Figures 7 through 9 show a selection of circuits for the most common input ranges when using the internal reference of the ADS805. All examples are for single-ended input and operate with a nominal common-mode voltage of +2.5V. 5V VIN 0V ADS805 IN EXTERNAL REFERENCE OPERATION Depending on the application requirements, it might be advantageous to operate the ADS805 with an external reference. This may improve the DC accuracy if the external reference circuitry is superior in its drift and accuracy. To use the ADS805 with an external reference, the user must disable the internal reference (see Figure 10). By connecting the SEL pin to +VS, the internal logic will shut down the internal reference. At the same time, the output of the internal reference buffer is disconnected from the VREF pin, which now must be driven with the external reference. Note that a similar bypassing scheme should be maintained as described for the internal reference operation. IN VREF SEL 4.5V VIN 0.5V ADS805 IN +2.5V FIGURE 7. Internal Reference with 0V to 5V Input Range. REF1004 +2.5V +2.5V ext. IN + 10µF 1.24kΩ +2VDC +5V 0.1µF VREF SEL 3.5V VIN 1.5V ADS805 IN 4.99kΩ +2.5V ext. IN VREF +1V SEL FIGURE 10. External Reference, Input Range 0.5V to 4.5V (4Vp-p), with +2.5V Common-Mode Voltage. DIGITAL INPUTS AND OUTPUTS Over Range (OVR) One feature of the ADS805 is its ‘Over Range’ digital output (OVR). This pin can be used to monitor any out-of-range condition, which occurs every time the applied analog input voltage exceeds the input range (set by VREF). The OVR output is LOW when the input voltage is within the defined input range. It becomes HIGH when the input voltage is beyond the input range. This is the case when the input voltage is either below the bottom reference voltage or above the top reference voltage. OVR will remain active until the analog input returns to its normal signal range and another conversion is completed. Using the MSB and its complement in conjunction with OVR, a simple decode logic can be built that detects the overrange and underrange conditions, (see Figure 11). It should be noted that OVR is a digital output which is updated along with the bit information corresponding to the particular sampling incidence of the analog signal. Therefore, the OVR data is subject to the same pipeline delay (latency) as the digital data. FIGURE 8. Internal Reference with 1.5V to 3.5V Input Range. 4V VIN 1V ADS805 IN +2.5V ext. IN VREF R1 5kΩ SEL VREF = 1V 1 + R1 R2 +1.5V R2 10kΩ FSR = 2 x VREF FIGURE 9. Internal Reference with 1V to 4V Input Range. ® 11 ADS805 MSB Over = H OVR Under = H necessary, external buffers or latches may be used which provide the added benefit of isolating the ADS805 from any digital noise activities on the bus coupling back high frequency noise. In addition, resistors in series with each data line may help maintain the ac performance of the ADS805. Their use depends on the capacitive loading seen by the converter. Values in the range of 100Ω to 200Ω will limit the instantaneous current the output stage has to provide for recharging the parasitic capacitances, as the output levels change from L to H or H to L. GROUNDING AND DECOUPLING Proper grounding and bypassing, short lead length, and the use of ground planes are particularly important for high frequency designs. Multi-layer PC boards are recommended for best performance since they offer distinct advantages like minimizing ground impedance, separation of signal layers by ground layers, etc. It is recommended that the analog and digital ground pins of the ADS805 be joined together at the IC and be connected only to the analog ground of the system. The ADS805 has analog and digital supply pins, however the converter should be treated as an analog component and all supply pins should be powered by the analog supply. This will ensure the most consistent results, since digital supply lines often carry high levels of noise that would otherwise be coupled into the converter and degrade the achievable performance. Because of the pipeline architecture, the converter also generates high frequency current transients and noise that are fed back into the supply and reference lines. This requires that the supply and reference pins be sufficiently bypassed. Figure 12 shows the recommended decoupling scheme for the analog supplies. In most cases, 0.1µF ceramic chip capacitors are adequate to keep the impedance low over a wide frequency range. Their effectiveness largely depends on the proximity to the individual supply pin. Therefore, they should be located as close to the supply pins as possible. In addition, a larger size bipolar capacitor (1µF to 22µF) should be placed on the PC board in close proximity to the converter circuit. FIGURE 11. External Logic for Decoding Underrange and Overrange Condition. CLOCK INPUT REQUIREMENTS Clock jitter is critical to the SNR performance of high speed, high resolution analog-to-digital converters. It leads to aperture jitter (tA) which adds noise to the signal being converted. The ADS805 samples the input signal on the rising edge of the CLK input. Therefore, this edge should have the lowest possible jitter. The jitter noise contribution to total SNR is given by the following equation. If this value is near your system requirements, input clock jitter must be reduced. JitterSNR = 20 log 1 rms signal to rms noise 2 π ƒ IN t A Where: ƒIN is Input Signal Frequency tA is rms Clock Jitter Particularly in undersampling applications, special consideration should be given to clock jitter. The clock input should be treated as an analog input in order to achieve the highest level of performance. Any overshoot or undershoot of the clock signal may cause degradation of the performance. When digitizing at high sampling rates, the clock should have a 50% duty cycle (tH = tL), along with fast rise and fall times of 2ns or less. DIGITAL OUTPUTS The digital outputs of the ADS805 are designed to be compatible with both high speed TTL and CMOS logic families. The driver stage for the digital outputs is supplied through a separate supply pin, VDRV, which is not connected to the analog supply pins. By adjusting the voltage on VDRV, the digital output levels will vary respectively. Therefore, it is possible to operate the ADS805 on a +5V analog supply while interfacing the digital outputs to 3V-logic with the VDRV pin tied to the +3V digital supply. It is recommended to keep the capacitive loading on the data lines as low as possible (≤ 15pF). Larger capacitive loads demand higher charging currents as the output are changing. Those high current surges can feed back to the analog portion of the ADS805 and influence the performance. If ADS805 +VS 27 0.1µF GND 26 +VS 16 0.1µF GND 17 VDRV 28 0.1µF 2.2µF + +5V +5V/+3V FIGURE 12. Recommended Bypassing for Analog Supply Pins. ® ADS805 12