®
ADS ADS 825
822
ADS822 ADS825
For most current data sheet and other product information, visit www.burr-brown.com
10-Bit, 40MHz Sampling ANALOG-TO-DIGITAL CONVERTERS
TM
FEATURES
q q q q q HIGH SNR: 60dB HIGH SFDR: 72dBFS LOW POWER: 190mW INTERNAL/EXTERNAL REFERENCE OPTION SINGLE-ENDED OR FULLY DIFFERENTIAL ANALOG INPUT q PROGRAMMABLE INPUT RANGE q LOW DNL: 0.5LSB q SINGLE +5V SUPPLY OPERATION
q +3V OR +5V LOGIC I/O COMPATIBLE (ADS825) q POWER DOWN: 20mW q 28-LEAD SSOP PACKAGE
APPLICATIONS
q MEDICAL IMAGING q TEST EQUIPMENT q COMPUTER SCANNERS q COMMUNICATIONS q VIDEO DIGITIZING
The ADS822 and ADS825 employ digital error correction techniques to provide excellent differential linearity for demanding imaging applications. Its low distortion and high SNR give the extra margin needed for medical imaging, communications, video, and test instrumentation. The ADS822 and ADS825 offer power dissipation of 190mW and also provide a power-down mode, thus reducing power dissipation to only 20mW. The ADS825 is +3V or +5V Logic I/O compatible. The ADS822 and ADS825 are specified at a maximum sampling frequency of 40MHz and a single-ended input range of 1.5V to 3.5V. The ADS822 and ADS825 are available in a 28-lead SSOP package and are pin-for-pin compatible with the 10-bit, 60MHz ADS823 and ADS826, and the 10-bit, 70MHz ADS824, providing an upgrade path to higher sampling frequencies.
CLK VDRV
DESCRIPTION
The ADS822 and ADS825 are pipeline, CMOS analog-to-digital converters that operate from a single +5V power supply. These converters provide excellent performance with a single-ended input and can be operated with a differential input for added spurious performance. These high-performance converters include a 10-bit quantizer, high-bandwidth track-and-hold, and a high-accuracy internal reference. They also allow for the user to disable the internal reference and utilize external references. This external reference option provides excellent gain and offset matching when used in multi-channel applications or in applications where full-scale range adjustment is required.
+VS ADS822 ADS825
Timing Circuitry
VIN
IN IN T/H
10-Bit Pipelined A/D Core
Error Correction Logic
3-State Outputs
D0 • • • D9
CM
Internal Reference
Optional External Reference
Int/Ext
PD
OE
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©
1997 Burr-Brown Corporation
PDS-1385E
Printed in U.S.A. October, 1999
SPECIFICATIONS
At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, and sampling rate = 40MHz, external reference, unless otherwise noted. ADS822E PARAMETER RESOLUTION SPECIFIED TEMPERATURE RANGE ANALOG INPUT Standard Single-Ended Input Range Optional Single-Ended Input Range Common-Mode Range Optional Differential Input Range Analog Input Bias Current Input Impedance Track-Mode Input Bandwidth CONVERSION CHARACTERISTICS Sample Rate Data Latency DYNAMIC CHARACTERISTICS Differential Linearity Error (largest code error) f = 1MHz f = 10MHz No Missing Codes Integral Nonlinearity Error, f = 1MHz Spurious Free Dynamic Range(2) f = 1MHz f = 10MHz Two-Tone Intermodulation Distortion(4) f = 9.5MHz and 9.9MHz (–7dB each tone) Signal-to-Noise Ratio (SNR) f = 1MHz f = 10MHz Signal-to-(Noise + Distortion) (SINAD) f = 1MHz f = 10MHz Effective Number of Bits(5), f = 1MHz Output Noise Aperture Delay Time Aperture Jitter Overvoltage Recovery Time Full-Scale Step Acquisition Time DIGITAL INPUTS Logic Family Convert Command High Level Input Current(6) (VIN = 5VDD) Low Level Input Current (VIN = 0V) High Level Input Voltage Low Level Input Voltage Input Capacitance DIGITAL OUTPUTS Logic Family Logic Coding Low Output Voltage (IOL = 50µA to 1.6mA) High Output Voltage, (IOH = 50µA to 0.5mA) Low Output Voltage, (IOL = 50µA to 1.6mA) High Output Voltage, (IOH = 50µA to 0.5mA) 3-State Enable Time 3-State Disable Time Output Capacitance Ambient Air 2Vp-p 1Vp-p 2Vp-p 1.5 2 2.5 2 1 1.25 || 5 300 10k 5 40M T T 3 T T T T T CONDITIONS MIN TYP 10 Guaranteed –40 to +85 3.5 3 T T T T MAX MIN ADS825E(1) TYP 10 Guaranteed –40 to +85 T T MAX UNITS Bits °C V V V V µA MΩ || pF MHz Samples/s Clk Cyc
–3dBFS Input
±0.25 ±0.5 Guaranteed ±0.5 Referred to Full Scale 63 72 66 –67 Referred to Full Scale 57 Referred to Full Scale 56 Input Tied to Common-Mode 59 58 9.5 0.2 3 1.2 2 5 60 60
±1.0
±2.0
T T Guaranteed T 71 65 T T T T T T T T T T T
T
LSB LSB LSBs dBFS(3) dBFS dBc dB dB dB dB Bits LSBs rms ns ps rms ns ns
T
60
T
T
Start Conversion
CMOS-Compatible Rising Edge of Convert Clock 100 10 +3.5 +1.0 5 CMOS-Compatible Straight Offset Binary +0.1 +4.9 +0.1 +2.8 2 40 2 10 5 ±1.0 5 ±1.5 38 ±0.75 25 70 ±10 ±10 3.5 1.5 1.6 ±3.0
TTL, +3V/+5V CMOS-Compatible Rising Edge of Convert Clock T T +2.0 +0.8 T CMOS-Compatible Straight Offset Binary T T T T T T T T T ±0.29 T T T T T T T T T T T T
µA µA V V pF
VDRV = 5V VDRV = 3V OE = H to L OE = L to H
V V V V ns ns pF % FS ppm/°C % FS % FS ppm/°C % FS ppm/°C dB mV mV V V kΩ
ACCURACY (Internal Reference, 2Vp-p, Unless Otherwise Noted) Zero Error (referred to –FS) at 25°C Zero Error Drift (referred to –FS) Midscale Offset Error at 25°C Gain Error(7) at 25°C Gain Error Drift(7) Gain Error(8) at 25°C Gain Error Drift(8) Power Supply Rejection of Gain ∆ VS = ±5% REFT Tolerance Deviation From Ideal 3.5V REFB Tolerance Deviation From Ideal 1.5V External REFT Voltage Range External REFB Voltage Range Reference Input Resistance REFT to REFB
T
±2.5 ±1.5
T T
REFB + 0.8 1.25
±25 ±25 VS – 1.25 REFT – 0.8
T T
T T T T
®
ADS822, ADS825
2
SPECIFICATIONS (Cont.)
At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, and sampling rate = 40MHz, external reference, unless otherwise noted. ADS822E PARAMETER POWER SUPPLY REQUIREMENTS Supply Voltage: +VS Supply Current: +IS Power Dissipation: VDRV = 5V VDRV = 3V VDRV = 5V VDRV = 3V Power Down Thermal Resistance, θJA 28-Lead SSOP T Indicates the same specifications as the ADS822E. NOTES: (1) ADS825E accepts a +3V clock input. (2) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (3) dBFS means dB relative to Full Scale. (4) Two-tone intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental envelope. (5) Effective number of bits (ENOB) is defined by (SINAD – 1.76)/6.02. (6) A 50kΩ pull-down resistor is inserted internally on OE pin. (7) Includes internal reference. (8) Excludes internal reference. CONDITIONS MIN TYP MAX MIN ADS825E(1) TYP MAX UNITS
Operating Operating (External Reference) External Reference External Reference Internal Reference Internal Reference Operating
+4.75
+5.0 40 200 190 250 240 20 89
+5.25 230
T
T T T T T T T T
T T
V mA mW mW mW mW mW °C/W
PIN CONFIGURATION
Top View SSOP
PIN DESCRIPTIONS
PIN 1 2 3 4 5 6 7 8 9 10 11 12 DESIGNATOR GND Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 OE DESCRIPTION Ground Data Bit 1 (D9) (MSB) Data Bit 2 (D8) Data Bit 3 (D7) Data Bit 4 (D6) Data Bit 5 (D5) Data Bit 6 (D4) Data Bit 7 (D3) Data Bit 8 (D2) Data Bit 9 (D1) Data Bit 10 (D0) (LSB) Output Enable. HI = high impedance state LO = normal operation (internal pull-down resistor) Power Down. HI = enable; LO = disable Convert Clock Input +5V Supply Ground Input Range Select. HI = 2V; LO = 1V Reference Select. HI = external, LO = internal Bottom Reference Bottom Ladder Bypass Top Ladder Bypass Top Reference Common-Mode Voltage Output Complementary Input (–) Analog Input (+) Analog Ground +5V Supply Output Logic Driver Supply Voltage
GND Bit 1 (MSB) Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8
1 2 3 4 5 6 7 8 9 ADS822 ADS825
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDRV +VS GND IN IN CM REFT ByT ByB REFB INT/EXT RSEL GND +VS
Bit 9 10 Bit 10 (LSB) 11 OE 12 PD 13 CLK 14
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
PD CLK +VS GND RSEL INT/EXT REFB ByB ByT REFT CM IN IN GND +VS VDRV
®
3
ADS822, ADS825
TIMING DIAGRAM
N+1 Analog In N tD Clock 5 Clock Cycles t2 Data Out N–5 N–4 N–3 N–2 N–1 N t1 N+1 N+2 tCONV N+2 N+3 N+4 N+5 tL tH N+6
N+7
Data Invalid
SYMBOL tCONV tL tH tD t1 t2
DESCRIPTION Convert Clock Period Clock Pulse Low Clock Pulse High Aperture Delay Data Hold Time, CL = 0pF New Data Delay Time, CL = 15pF max
MIN 25 11.5 11.5 3.9
TYP
MAX 100µs
UNITS ns ns ns ns ns ns
12.5 12.5 3 12
PACKAGE/ORDERING INFORMATION
PACKAGE DRAWING NUMBER 324 " 324 " SPECIFIED TEMPERATURE RANGE –40°C to +85°C " –40°C to +85°C " PACKAGE MARKING ADS822E " ADS825E " ORDERING NUMBER(1) ADS822E ADS822E/1K ADS825E ADS825E/1K TRANSPORT MEDIA Rails Tape and Reel Rails Tape and Reel
PRODUCT ADS822E " ADS825E "
PACKAGE SSOP-28 " SSOP-28 "
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of ADS822E/1K” will get a single 1000-piece Tape and Reel.
DEMO BOARD ORDERING INFORMATION
PRODUCT ADS822E DEMO BOARD DEM-ADS822E
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
+VS ....................................................................................................... +6V Analog Input ............................................................. –0.3V to (+VS + 0.3V) Logic Input ............................................................... –0.3V to (+VS + 0.3V) Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature ..................................................................... +150°C
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
ADS822, ADS825
4
TYPICAL PERFORMANCE CURVES
At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, and sampling rate = 40MHz, external reference, unless otherwise noted.
SPECTRAL PERFORMANCE 0 fIN = 1MHz –20
Magnitude (dB) Magnitude (dB)
SPECTRAL PERFORMANCE 0 fIN = 10MHz –20
–40
–40
–60
–60
–80
–80
–100 0 5 10 Frequency (MHz) 15 20
–100 0 5 10 Frequency (MHz) 15 20
SPECTRAL PERFORMANCE (Differential Input, 1Vp-p) 0 fIN = 10MHz SNR = 58dBFS SFDR = 74dBFS Magnitude (dB) 0
SPECTRAL PERFORMANCE (Single-Ended, 1Vp-p) fIN = 10MHz SNR = 57dBFS SFDR = 71dBFS
–20 Magnitude (dB)
–20
–40
–40
–60
–60
–80
–80
–100 0 5 10 Frequency (MHz) 15 20
–100 0 5 10 Frequency (MHz) 15 20
SPECTRAL PERFORMANCE (Single-Ended, 1Vp-p) 0 fIN = 20MHz SNR = 57dBFS SFDR = 70dBFS Magnitude (dB) 0
UNDERSAMPLING (Differential Input, 2Vp-p) fS = 40MHz fIN = 45MHz SNR = 60dBFS SFDR = 74dBFS
–20 Magnitude (dB)
–20
–40
–40
–60
–60
–80
–80
–100 0 5 10 Frequency (MHz) 15 20
–100 0 5 10 Frequency (MHz) 15 20
®
5
ADS822, ADS825
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, and sampling rate = 40MHz, external reference, unless otherwise noted.
UNDERSAMPLING (Differential Input, 2Vp-p) 0 fS = 40MHz fIN = 75MHz SNR = 59dBFS SFDR = 66dBFS
TWO-TONE INTERMODULATION DISTORTION 0 f1 = 9.5MHz at –7dBFS f2 = 9.9MHz at –7dBFS IMD (3) = –67dB
–20 Magnitude (dB)
–20
Magnitude (dB)
–40
–40
–60
–60
–80
–80
–100 0 5 10 Frequency (MHz) 15 20
–100 0 5 10 Frequency (MHz) 15 20
DIFFERENTIAL LINEARITY ERROR 1.0 fIN = 1MHz 1.0
DIFFERENTIAL LINEARITY ERROR fIN = 10MHz
0.5
0.5
DLE (LSB)
0
DLE (LSB)
0 20 40 60 80 1024
0
–0.5
–0.5
–1.0 Output Code
–1.0 0 20 40 60 80 1024 Output Code
INTEGRAL LINEARITY ERROR 2.0
100
SWEPT POWER SFDR
SFDR (dBFS, dBc)
1.0
ILE (LSB)
80 dBFS
60
0
40 dBc 20
–1.0
–2.0 0 256 512 Output Code 768 1024
0 –60 –50 –40 –30 –20 –10 0 Input Amplitude (dBFS)
®
ADS822, ADS825
6
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, and sampling rate = 40MHz, external reference, unless otherwise noted.
DYNAMIC PERFORMANCE vs INPUT FREQUENCY 75 75
DYNAMIC PERFORMANCE vs TEMPERATURE
70
SFDR, SNR (dBFS)
SFDR, SNR (dBFS)
SFDR
70
SFDR (fIN = 10MHz)
65
65 SFDR (fIN = 20MHz) 60 SNR (fIN = 20MHz) SNR (fIN = 10MHz)
60 SNR 55
50 0.1 1 10 Frequency (MHz) 100
55 –50 –25 0 25 50 75 100 Temperature (°C)
SIGNAL-TO-(NOISE + DISTORTION) vs TEMPERATURE 60 fIN = 1MHz .60
DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE
fIN = 20MHz
Sinad (dBFS)
fIN = 10MHz
DLE (LSB)
59
.50 fIN = 10MHz .40
58 fIN = 20MHz
57 –50 –25 0 25 50 75 100 Temperature (°C)
.30 –50 –25 0 25 Temperature (°C) 50 75 100
POWER DISSIPATION vs TEMPERATURE 205
800k
OUTPUT NOISE (DC Input)
600k
Power (mW)
200
Counts
400k
195
200k
190 –50 –25 0 25 50 75 100 Temperature (°C)
0 N-2 N-1 N Code N+1 N+2
®
7
ADS822, ADS825
APPLICATION INFORMATION
THEORY OF OPERATION The ADS822 and ADS825 are high-speed CMOS analog-todigital converters which employ a pipelined converter architecture consisting of 9 internal stages. Each stage feeds its data into the digital error correction logic ensuring excellent differential linearity and no missing codes at the 10-bit level. The output data becomes valid on the rising clock edge (see Timing Diagram). The pipeline architecture results in a data latency of 5 clock cycles. The analog inputs of the ADS822 and ADS825 are differential track-and-hold (see Figure 1). The differential topology, along with tightly matched capacitors, produce a high level of AC performance while sampling at very high rates. The ADS822 and ADS825 allow their analog inputs to be driven either single-ended or differentially. The typical configuration for the ADS822 and ADS825 is the single-ended mode in which the input track-and-hold performs a singleended-to-differential conversion of the analog input signal. Both inputs (IN, IN) require external biasing using a common-mode voltage that is typically at the mid-supply level (+VS/2). The following application discussion focuses on the singleended configuration. Typically, its implementation is easier to achieve and the rated specifications for the ADS822 and ADS825 are characterized using the single-ended mode of operation. DRIVING THE ANALOG INPUT The ADS822 and ADS825 achieve excellent AC performance either in the single-ended or differential mode of operation.
Op Amp Bias φ1
The selection for the optimum interface configuration will depend on the individual application requirements and system structure. For example, communications applications often process a band of frequencies that do not include DC, whereas in imaging applications, the previously restored DC level must be maintained correctly up to the A/D converter. Features on the ADS822 and ADS825, such as the input range select (RSEL pin) or the option for an external reference, provide the needed flexibility to accommodate a wide range of applications. In any case, the ADS822 and ADS825 should be configured such that the application objectives are met while observing the headroom requirements of the driving amplifier in order to yield the best overall performance. INPUT CONFIGURATIONS AC-Coupled, Single-Supply Interface Figure 2 shows the typical circuit for an AC-coupled analog input configuration of the ADS822 and ADS825 while all components are powered from a single +5V supply. With the RSEL pin connected high, the full-scale input range is set to 2Vp-p. In this configuration, the top and bottom references (REFT, REFB) provide an output voltage of +3.5V and +1.5V, respectively. Two resistors ( 2x 1.62kΩ) are used to create a common-mode voltage (VCM) of approximately +2.5V to bias the inputs of the driving amplifier A1. Using the OPA680 on a single +5V supply, its ideal common-mode point is at +2.5V which coincides with the recommended common-mode input level for the ADS822 and ADS825. This obviates the need of a coupling capacitor between the amplifier and the converter. Even though the OPA680 has an AC gain of +2, the DC gain is only +1 due to the blocking capacitor at resistor RG. The addition of a small series resistor (RS) between the output of the op amp and the input of the ADS822 and ADS825 will be beneficial in almost all interface configurations. This will decouple the op amp’s output from the capacitive load and avoid gain peaking, which can result in increased noise. For best spurious and distortion performance, the resistor value should be kept below 100Ω. Furthermore, the series resistor in combination with the 10pF capacitor establishes a passive low-pass filter limiting the bandwidth for the wideband noise, thus helping improve the SNR performance. AC-Coupled, Dual Supply Interface The circuit provided in Figure 3 shows typical connections for the analog input in case the selected amplifier operates on dual supplies. This might be necessary to take full advantage of very low distortion operational amplifiers, like the OPA642. The advantage is that the driving amplifier can be operated with a ground referenced bipolar signal swing. This will keep the distortion performance at its lowest since the signal range stays within the linear region of the op amp and sufficient headroom to the supply rails can be maintained. By capacitively coupling the single-ended signal to the input of the ADS822 and ADS825, its common-mode requirements can easily be satisfied with two resistors connected between the top and bottom reference. 8
VCM φ1 CH φ2
CI IN IN φ1 φ1 φ2 CI CH φ1 Input Clock (50%) Op Amp Bias Internal Non-overlapping Clock φ1 φ2 φ1 VCM φ1 φ1
OUT OUT
φ2
FIGURE 1. Simplified Circuit of Input Track-and-Hold with Timing Diagram.
®
ADS822, ADS825
1.62kΩ +5V VCM +2.5V +5V 0.1µF VIN OPA680 10pF +VIN 0V –VIN RF 402Ω CM RG 402Ω 0.1µF IN 0.1µF INT/EXT GND ADS822 ADS825 50Ω RS 50Ω IN REFB +1.5V REFT +3.5V RSEL +VS 1.62kΩ
FIGURE 2. AC-Coupled Input Configuration for a 2Vp-p Full-Scale Range and a Common-Mode Voltage, VCM, at +2.5V Derived From the Internal Top (REFT) and Bottom Reference (REFB).
+5V 1.62kΩ +5V VIN OPA642 100pF –5V RF 402Ω 1.62kΩ CM IN RG 402Ω 0.1µF REFB +1.5V ADS822 ADS825 RS 24.9Ω 0.1µF IN REFT +3.5V RSEL +VS
INT/EXT
GND
FIGURE 3. AC-Coupling the Dual Supply Amplifier OPA642 to the ADS822 for a 2Vp-p Full-Scale Input Range. For applications requiring the driving amplifier to provide a signal amplification, with a gain ≥ 5, consider using decompensated voltage-feedback op amps, like the OPA643, or current-feedback op amps like the OPA681 and OPA658. DC-coupled with Level Shift Several applications may require that the bandwidth of the signal path include DC, in which case, the signal has to be DC-coupled to the A/D converter. In order to accomplish this, the interface circuit has to provide a DC level shift to the analog input signal. The circuit shown in Figure 4 employs a dual op amp, A1, to drive the input of the ADS822 and ADS825, and level shifts the signal to be compatible with the selected input range. With the RSEL pin tied to the supply and the INT/EXT pin to ground, the ADS822 and ADS825 are configured for a 2Vp-p input range and use the internal references. The complementary input (IN) may be appropriately biased using the +2.5V common-mode voltage available at the CM pin. One half of amplifier A1 buffers the REFB pin and drives the voltage divider R1, R2. Due to the op amp’s noise gain of +2V/V, assuming RF = RIN , the common-mode voltage (VCM) has to be re-scaled to +1.25V. This results in the correct DC level of +2.5V for the signal input (IN). Any DC voltage differences between the IN and IN inputs of the ADS822 and ADS825 effectively produces an offset, which can be corrected for by adjusting the resistor values of the divider, R1and R2. The selection criteria for a suitable op amp should include the supply voltage, input bias current, output voltage swing, distortion, and noise specification. Note that in this example, the overall signal phase is inverted. To re-establish the original signal polarity, it is always possible to interchange the IN and IN connections.
®
9
ADS822, ADS825
+5V RF 499Ω RIN 499Ω VIN 2Vp-p
1/2 OPA2681
RS 50Ω IN 10pF
RSEL
+VS
ADS822 ADS825 NOTE: RF = RIN, G = –1 CM (+2.5) IN +5V R2 200Ω VCM = +1.25V R1 1kΩ 0.1µF 50Ω
1/2 OPA2681
REFB (+1.5V)
REFT (+3.5V) 0.1µF
INT/EXT
0.1µF
RF 1kΩ
FIGURE 4. DC-Coupled Interface Circuit with Dual Current-Feedback Amplifier OPA2681. SINGLE-ENDED-TO-DIFFERENTIAL CONFIGURATION (Transformer Coupled) If the application requires a signal conversion from a singleended source to feed the ADS822 and ADS825 differentially, a RF transformer might be a good solution. The selected transformer must have a center tap in order to apply the common-mode DC voltage necessary to bias the converter inputs. AC-grounding the center tap will generate the differential signal swing across the secondary winding. Consider a step-up transformer to take advantage of a signal amplification without the introduction of another noise source. Furthermore, the reduced signal swing from the source may lead to an improved distortion performance. The differential input configuration may provide a noticeable advantage of achieving good SFDR performance over a wide range of input frequencies. In this mode, both inputs of the ADS822 and ADS825 see matched impedances, and the differential signal swing can be reduced to half of the swing required for single-ended drive. Figure 5 shows the schematic for the suggested transformer-coupled interface
RG 0.1µF 1:n VIN 47pF RT 22Ω IN 47pF +5V + 10µF 0.1µF Bypass Capacitors: 0.1µF || 2.2µF each CM RSEL INT/EXT REFT ByT CM ByB REFB ADS822 ADS825 400Ω 400Ω 400Ω 400Ω 22Ω IN +1 +1
circuit. The component values of the R-C low-pass may be optimized depending on the desired roll-off frequency. The resistor across the secondary side (RT) should be calculated using the equation RT = n2 • RG to match the source impedance (RG) for good power transfer and Voltage Standing Wave Ratio (VSWR). REFERENCE OPERATION Figure 6 depicts the simplified model of the internal reference circuit. The internal blocks are the bandgap voltage reference, the drivers for the top and bottom reference, and
RSEL ADS822 50kΩ
+VS
INT/EXT 50kΩ
Bandgap Reference and Logic VREF
FIGURE 5. Transformer Coupled Input.
®
FIGURE 6. Equivalent Reference Circuit with Recommended Reference Bypassing. 10
ADS822, ADS825
the resistive reference ladder. The bandgap reference circuit includes logic functions that allows setting the analog input swing of the ADS822 and ADS825 to either a 1Vp-p or 2Vp-p full-scale range simply by tying the RSEL pin to a Low or High potential, respectively. While operating the ADS822 in the external reference mode, the buffer amplifiers for the REFT and REFB are disconnected from the reference ladder. As shown, the ADS822 and ADS825 have internal 50kΩ pull-up resistors at the range select pin (RSEL) and reference select pin (INT/EXT). Leaving these pins open configures the ADS822 and ADS825 for a 2Vp-p input range and external reference operation. Setting the ADS822 and ADS825 up for internal reference mode requires bringing the INT/EXT pin Low. The reference buffers can be utilized to supply up to 1mA (sink and source) to external circuitry. The resistor ladders of the ADS822 and ADS825 are divided into several segments and have two additional nodes, ByT and ByB, which are brought out for external bypassing only (see Figure 6). To ensure proper operation with any reference configurations, it is necessary to provide solid bypassing at all reference pins in order to keep the clock feedthrough to a minimum. All bypassing capacitors should be located as close to their respective pins as possible.
The common-mode voltage available at the CM pin may be used as a bias voltage to provide the appropriate offset for the driving circuitry. However, care must be taken not to appreciably load this node, which is not buffered and has a high impedance. An alternative way of generating a common-mode voltage is given in Figure 7. Here, two external precision resistors (tolerance 1% or better) are located between the top and bottom reference pins. The commonmode voltage, CMV, will appear at the midpoint. EXTERNAL REFERENCE OPERATION For even more design flexibility, the internal reference can be disabled and an external reference voltage be used. The utilization of an external reference may be considered for applications requiring higher accuracy, improved temperature performance, or a wide adjustment range of the converter’s full-scale range. Especially in multichannel applications, the use of a common external reference has the benefit of obtaining better matching of the full-scale range between converters. The external references can vary as long as the value of the external top reference REFTEXT stays within the range of (VS – 1.25V) and (REFB + 0.8V), and the external bottom reference REFBEXT stays within 1.25V and (REFT – 0.8V) (See Figure 8). DIGITAL INPUTS AND OUTPUTS
REFT +3.5V R1 1.6kΩ 0.1µF
ADS822 ADS825
REFB +1.5V R2 1.6kΩ 0.1µF
Clock Input Requirements Clock jitter is critical to the SNR performance of high-speed, high-resolution A/D converters. Clock jitter leads to aperture jitter (tA), which adds noise to the signal being converted. The ADS822 and ADS825 samples the input signal on the rising edge of the CLK input. Therefore, this edge should have the lowest possible jitter. The jitter noise contribution to total
CMV +2.5V
FIGURE 7. Alternative Circuit to Generate CM Voltage.
+5V A - Short for 1Vp-p Input Range B - Short for 2Vp-p Input Range (Default) +VS VIN IN ADS822 ADS825 CMV +2.5VDC IN REFT ByT GND ByB REFB INT/EXT B A
RSEL
GND
External Top Reference REFT = REFB +0.8V to +3.75V
4 x 0.1µF || 2.2µF
External Bottom Reference REFB = REFT –0.8V to +1.25V
FIGURE 8. Configuration Example for External Reference Operation.
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ADS822, ADS825
SNR is given by the following equation. If this value is near your system requirements, input clock jitter must be reduced. Jitter SNR = 20 log 1 rms signal to rms noise 2 π ƒ IN t A
where: ƒIN is input signal frequency tA is rms clock jitter Particularly in undersampling applications, special consideration should be given to clock jitter. The clock input should be treated as an analog input in order to achieve the highest level of performance. Any overshoot or undershoot of the clock signal may cause degradation of the performance. When digitizing at high sampling rates, the clock should have 50% duty cycle (tH = tL), along with fast rise and fall times of 2ns or less. The clock input of the ADS825 can be driven with either 3V or 5V logic levels. Using low-voltage logic (3V) may lead to improved AC performance of the converter. Digital Outputs The output data format of the ADS822 and ADS825 are in positive Straight Offset Binary code (see Tables I and II). This format can easily be converted into the Binary Two’s Complement code by inverting the MSB. It is recommended to keep the capacitive loading on the data lines as low as possible (≤ 15pF). Higher capacitive loading will cause larger dynamic currents as the digital outputs are changing. Those high current surges can feed back to the analog portion of the ADS822 and ADS825 and affect the performance. If necessary, external buffers or latches close to the converter’s output pins may be used to minimize the capacitive loading. They also provide the added benefit of isolating the ADS822 and ADS825 from any digital noise activities on the bus coupling back high frequency noise.
SINGLE-ENDED INPUT (IN = CMV) +FS –1LSB (IN = REFT) +1/2 Full Scale Bipolar Zero (IN = CMV) –1/2 Full Scale –FS (IN = REFB) STRAIGHT OFFSET BINARY (SOB) 11 11 10 01 00 1111 0000 0000 0000 0000 1111 0000 0000 0000 0000
Digital Output Driver (VDRV) The ADS822 features a dedicated supply pin for the output logic drivers, VDRV, which is not internally connected to the other supply pins. Setting the voltage at VDRV to +5V or +3V, the ADS822 and ADS825 produce corresponding logic levels and can directly interface to the selected logic family. The output stages are designed to supply sufficient current to drive a variety of logic families. However, it is recommended to use the ADS822 and ADS825 with +3V logic supply. This will lower the power dissipation in the output stages due to the lower output swing and reduce current glitches on the supply line which may affect the ACperformance of the converter. In some applications, it might be advantageous to decouple the VDRV pin with additional capacitors or a pi-filter. GROUNDING AND DECOUPLING Proper grounding and bypassing, short lead length, and the use of ground planes are particularly important for high frequency designs. Multilayer PC boards are recommended for best performance since they offer distinct advantages like minimizing ground impedance, separation of signal layers by ground layers, etc. The ADS822 and ADS825 should be treated as analog components. Whenever possible, the supply pins should be powered by the analog supply. This will ensure the most consistent results since digital supply lines often carry high levels of noise which otherwise would be coupled into the converter and degrade the achievable performance. All ground connections on the ADS822 and ADS825 are internally joined together obviating the design of split ground planes. The ground pins (1, 16, 26) should directly connect to an analog ground plane which covers the PC board area around the converter. While designing the layout, it is important to keep the analog signal traces separated from any digital lines to prevent noise coupling onto the analog signal path. Due to their high sampling rates, the ADS822 and ADS825 generate high frequency current transients, and noise (clock feedthrough) that are fed back into the supply and reference lines. This requires that all supply and reference pins are sufficiently bypassed. Figure 9 shows the recommended decoupling scheme for the ADS822 and ADS825. In most cases, 0.1µF ceramic chip capacitors at each pin are adequate to keep the impedance low over a wide frequency range. Their effectiveness largely depends on the proximity to the individual supply pin. Therefore, they should be located as close to the supply pins as possible. In addition, a larger bipolar capacitor (1µF to 22µF) should be placed on the PC board in proximity of the converter circuit.
TABLE I. Coding Table for Single-Ended Input Configuration with IN Tied to the Common-Mode Voltage (CMV).
STRAIGHT OFFSET BINARY (SOB) 11 11 10 01 00 1111 0000 0000 0000 0000 1111 0000 0000 0000 0000
DIFFERENTIAL INPUT +FS –1LSB (IN = +3V, IN = +2V) +1/2 Full Scale Bipolar Zero (IN = IN = CMV) –1/2 Full Scale –FS (IN = +2V, IN = +3V)
+VS 27 0.1µF
GND 26
ADS822 ADS825 +VS 15 0.1µF 10µF +
GND 16
VDRV 28 0.1µF
TABLE II. Coding Table for Differential Input Configuration and 2Vp-p Full-Scale Range.
+5V
+3/+5V
Figure 9. Recommended Bypassing for the Supply Pins.
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ADS822, ADS825
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