ADS831

® AD S83 ¤ 1 ADS831 8-Bit, 80MHz Sampling ANALOG-TO-DIGITAL CONVERTER TM FEATURES q HIGH SNR: 49dB q INTERNAL / EXTERNAL REFERENCE OPTION q SINGLE-ENDED OR DIFFERENTIAL ANALOG INPUT q PROGRAMMABLE INPUT RANGE: 1Vp-p /2Vp-p q LOW POWER: 275mW q LOW DNL: 0.35LSB q SINGLE +5V SUPPLY OPERATION q 20-PIN SSOP PACKAGE DESCRIPTION The ADS831 is a pipeline, CMOS analog-to-digital converter that operates from a single +5V power supply. This converter provides excellent performance with a singleended input and can be operated with a differential input for added spurious performance. This high performance converter includes an 8-bit quantizer, high bandwidth track/hold, and a high accuracy internal reference. It also allows for the user to disable the internal reference and utilize external references. This external reference option provides excellent gain and offset matching when used in multi-channel applications or in applications where DC full scale range adjustment is required. The ADS831 employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications. Its low distortion and high SNR give the extra margin needed for medical imaging, communications, video, and test instrumentation. The ADS831 is specified at a maximum sampling frequency of 80MHz and a single-ended input range of 1.5V to 3.5V. The ADS831 is available in a 20-lead SSOP package and is pin-for-pin compatible with the 8-bit, 60MHz ADS830. APPLICATIONS q q q q q MEDICAL IMAGING VIDEO DIGITIZING COMPUTER SCANNERS COMMUNICATIONS DISK-DRIVE CONTROL +VS ADS831 CLK VDRV Timing Circuitry VIN IN T/H IN (Opt) 8-Bit Pipelined A/D Core Error Correction Logic 3-State Outputs D0 • • • D7 Internal Reference Optional External Reference Int/Ext International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1998 Burr-Brown Corporation PDS-1430B Printed in U.S.A. October, 1998 SPECIFICATIONS At TA = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 80MHz, and external reference, unless otherwise noted. ADS831E PARAMETER RESOLUTION SPECIFIED TEMPERATURE RANGE ANALOG INPUT Standard Single-Ended Input Range Optional Single-Ended Input Range Common-Mode Voltage Optional Differential Input Range Analog Input Bias Current Input Impedance Track-Mode Input Bandwidth CONVERSION CHARACTERISTICS Sample Rate Data Latency DYNAMIC CHARACTERISTICS Differential Linearity Error (largest code error) f = 1MHz f = 10MHz No Missing Codes Integral Nonlinearity Error, f = 1MHz Spurious Free Dynamic Range(1) f = 1MHz (–1dB input) f = 10MHz (–1dB input) Two-Tone Intermodulation Distortion(3) f = 9.5MHz and 9.9MHz (–7dB each tone) Signal-to-Noise Ratio (SNR) f = 1MHz f = 10MHz Signal-to-(Noise + Distortion) (SINAD) f = 1MHz f = 10MHz Effective Number of Bits(4), f = 1MHz Output Noise Aperture Delay Time Aperture Jitter Overvoltage Recovery Time Full-Scale Step Acquisition Time DIGITAL INPUTS Logic Family Convert Command High Level Input Current(5) (VIN = 5V) Low Level Input Current (VIN = 0V) High Level Input Voltage Low Level Input Voltage Input Capacitance DIGITAL OUTPUTS Logic Family Logic Coding Low Output Voltage (IOL = 50µA) Low Output Voltage, (IOL = 1.6mA) High Output Voltage, (IOH = 50µA) High Output Voltage, (IOH = 0.5mA) Low Output Voltage, (IOL = 50µA) High Output Voltage, (IOH = 50µA) Output Capacitance Ambient Air 2Vp-p 1Vp-p 2Vp-p 1.5 2 2.5 2 1 1.25 || 5 300 10k 4 80M 3 CONDITIONS MIN TYP 8 Guaranteed –40 to +85 3.5 3 MAX UNITS Bits °C V V V V µA MΩ || pF MHz Samples/s Clk Cyc –3dBFS ±0.25 ±0.35 Guaranteed ±0.5 67 65 –57 Referred to Full Scale 46 Referred to Full Scale 44 Input Tied to Common-Mode 48.5 48.5 7.8 0.2 3 1.2 2 2.5 CMOS Compatible Rising Edge of Convert Clock 49 49 ±1.0 ±2.0 LSB LSB LSBs dBFS(2) dBFS dBc dB dB dB dB Bits LSBs rms ns ps rms ns ns 50 Start Conversion 100 10 +3.5 +1.0 5 CMOS/TTL Compatible Straight Offset Binary VDRV = 5V +4.9 +4.8 VDRV = 3V +2.8 5 –2.5 –2.5 ±0.5 ±53 ±0.5 ±75 55 ±10 ±10 3.0 2.0 800 +2.5 +2.5 ±100 ±100 VS – 1.25 REFT – 0.8 +0.1 +0.1 +0.2 µA µA V V pF V V V V V V pF %FS ppm/°C %FS ppm/°C dB mV mV V V Ω ACCURACY (Internal Reference, 2Vp-p, Unless Otherwise Noted) Zero Error (Referred to –FS) at 25°C Zero Error Drift (Referred to –FS) Gain Error(6) at 25°C Gain Error Drift(6) Power Supply Rejection of Gain ∆ VS = ±5% Internal REFT Tolerance Deviation from Ideal 3.0V Internal REFB Tolerance Deviation from Ideal 2.0V External REFT Voltage Range External REFB Voltage Range Reference Input Resistance REFT to REFB REFB + 0.8 1.25 ® ADS831 2 SPECIFICATIONS At TA = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 80MHz, and external reference, unless otherwise noted. ADS831E PARAMETER POWER SUPPLY REQUIREMENTS Supply Voltage: +VS Supply Current: +IS Power Dissipation: VDRV = 5V VDRV = 3V VDRV = 5V VDRV = 3V Thermal Resistance, θJA 20-Lead SSOP CONDITIONS Operating Operating External Reference External Reference Internal Reference Internal Reference MIN +4.75 TYP +5.0 58 290 275 310 285 115 MAX +5.25 70 350 UNITS V mA mW mW mW mW °C/W NOTES: (1) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full Scale. (3) Two-tone intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental envelope. (4) Effective number of bits (ENOB) is defined by (SINAD – 1.76)/6.02. (5) A 50k Ω pull-down resistor is inserted internally. (6) Excludes internal reference. PIN CONFIGURATION Top View SSOP PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DESIGNATOR GND Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 CLK RSEL INT/EXT REFB REFT CM IN IN GND +VS VDRV DESCRIPTION Ground Data Bit 1 (D7) (MSB) Data Bit 2 (D6) Data Bit 3 (D5) Data Bit 4 (D4) Data Bit 5 (D3) Data Bit 6 (D2) Data Bit 7 (D1) Data Bit 8 (D0) (LSB) Convert Clock Input Range Select: HI = 2V; LO = 1V Reference Select: HI = External; LO = Internal Bottom Reference Top Reference Common-Mode Voltage Output Complementary Input Analog Input Ground +5V Supply Output Logic Driver Supply Voltage GND Bit 1 (MSB) Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 (LSB) 1 2 3 4 5 6 7 8 9 ADS831 20 19 18 17 16 15 14 13 12 11 VDRV +VS GND IN IN CM REFT REFB INT/EXT RSEL CLK 10 PACKAGE/ORDERING INFORMATION PACKAGE DRAWING NUMBER(1) 349 " SPECIFIED TEMPERATURE RANGE –40°C to +85°C " PACKAGE MARKING ADS831E " ORDERING NUMBER ADS831E ADS831E/1K TRANSPORT MEDIA Rails Tape and Reel PRODUCT ADS831E " PACKAGE 20-Lead SSOP (QSOP) " NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book. ABSOLUTE MAXIMUM RATINGS +VS ....................................................................................................... +6V Analog Input ............................................................. –0.3V to (+VS + 0.3V) Logic Input ............................................................... –0.3V to (+VS + 0.3V) Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature ..................................................................... +150°C ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ® DEMO BOARD ORDERING INFORMATION PRODUCT ADS831 DEMO BOARD DEM-ADS831E 3 ADS831 TIMING DIAGRAM N+1 Analog In N tD Clock tCONV N+2 N+3 tL tH N+4 N+5 N+6 N+7 4 Clock Cycles t2 Data Out N–4 N–3 N–2 N–1 N t1 N+1 N+2 N+3 Data Invalid SYMBOL tCONV tL tH tD t1 t2 DESCRIPTION Convert Clock Period Clock Pulse Low Clock Pulse High Aperture Delay Data Hold Time, CL = 0pF New Data Delay Time, CL = 15pF max MIN 12.5 5.8 5.8 3.9 TYP MAX 100µs UNITS ns ns ns ns ns ns 6.25 6.25 3 5.9 12 The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® ADS831 4 TYPICAL PERFORMANCE CURVES At TA = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 80MHz, and external reference, unless otherwise noted. SPECTRAL PERFORMANCE 0 –10 –20 Magnitude (dB) 0 SPECTRAL PERFORMANCE fIN = 10MHz SNR = 49dBFS SFDR = 67dBFS fIN = 1MHz SNR = 49dBFS SFDR = 68dBFS Magnitude (dB) –10 –20 –30 –40 –50 –60 –70 –80 –90 –30 –40 –50 –60 –70 –80 –90 0 10 20 Frequency (MHz) 30 40 0 10 20 Frequency (MHz) 30 40 SPECTRAL PERFORMANCE 0 –10 –20 fIN = 20MHz SNR = 49dBFS SFDR = 66dBFS SPECTRAL PERFORMANCE (Single-Ended, 1Vp-p) 0 –10 –20 Magnitude (dB) fIN = 10MHz SNR = 49dBFS SFDR = 66dBFS Magnitude (dB) –30 –40 –50 –60 –70 –80 –90 0 10 20 Frequency (MHz) 30 40 –30 –40 –50 –60 –70 –80 –90 0 10 20 Frequency (MHz) 30 40 TWO-TONE INTERMODULATION DISTORTION 0 –10 f1 = 9.5MHz at –7dBFS f2 = 9.9MHz at –7dBFS IMD(3) = –57dBc 0.25 DLE (LSB) 0.5 DIFFERENTIAL LINEARITY ERROR fIN = 10MHz Magnitude (dBFSR) –20 –30 –40 –50 –60 –70 –80 –90 0 10 20 0 –0.25 –0.5 30 40 0 64 128 Output Code 192 256 Frequency (MHz) ® 5 ADS831 TYPICAL PERFORMANCE CURVES (CONT) At TA = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 80MHz, and external reference, unless otherwise noted. DIFFERENTIAL LINEARITY ERROR 1.0 fIN = 20MHz 0.5 0.5 1.0 INTEGRAL LINEARITY ERROR fIN = 1MHz DLE (LSB) 0.25 0 –0.25 –0.5 ILE (LSB) 0 –0.5 –1.0 0 64 128 Output Code 192 256 –1.0 0 64 128 Output Code 192 256 DYNAMIC PERFORMANCE vs INPUT FREQUENCY POWER DISSIPATION vs TEMPERATURE 350 VDRV = +5V 80 SFDR SFDR, SNR (dBFS) 70 Power Dissipation (mW) 330 Internal Reference 310 60 SNR 50 290 External Reference 270 40 0.1 1 10 100 Input Frequency (MHz) 250 –50 –25 0 25 50 75 100 Temperature (°C) OUTPUT NOISE HISTOGRAM (DC Input) 800k 600k Counts 400k 200k 0 N–2 N–1 N Output Code N+1 N+2 ® ADS831 6 APPLICATION INFORMATION THEORY OF OPERATION The ADS831 is a high-speed CMOS analog-to-digital converter which employs a pipelined converter architecture consisting of 6 internal stages. Each stage feeds its data into the digital error correction logic ensuring excellent differential linearity and no missing codes at the 8-bit level. The output data becomes valid on the rising clock edge (see Timing Diagram). The pipeline architecture results in a data latency of 4 clock cycles. The analog input of the ADS831 is a differential track and hold, see Figure 1. The differential topology along with tightly matched capacitors produce a high level of ac performance while sampling at very high rates. The ADS831 allows its analog inputs to be driven either single-ended or differentially. The typical configuration for the ADS831 is for the single-ended mode in which the input track and hold performs a single-ended to differential conversion of the analog input signal. Both inputs (IN, IN) require external biasing using a common-mode voltage that is typically at the mid-supply level (+VS /2). The following application discussion focuses on the singleended configuration. Typically, its implementation is easier to achieve and the rated specifications for the ADS831 are characterized using the single-ended mode of operation. DRIVING THE ANALOG INPUT The ADS831 achieves excellent ac performance either in the single-ended or differential mode of operation. The selection for the optimum interface configuration will depend on the individual application requirements and system structure. For example, communication applications often process a band of frequencies that does not include DC, whereas in imaging applications, the previously restored DC level must be maintained correctly up to the A/D converter. Features on the ADS831, such as the input range select (RSEL pin) or the option for an external reference, provide the needed flexibility to accommodate a wide range of applications. In any case, the ADS831 should be configured such that the application objectives are met while observing the headroom requirements of the driving amplifier in order to yield the best overall performance. INPUT CONFIGURATIONS AC-Coupled, Single-Supply Interface Figure 2 shows the typical circuit for an ac-coupled analog input configuration of the ADS831 where all components are powered from a single +5V supply. With the RSEL pin connected HIGH, the full scale input range is set to 2Vp-p. In this configuration, the top and bottom references (REFT, REFB) provide an output voltage of +3.0V and +2.0V, respectively. Two resistors ( 2 x 1kΩ) are used to create a common-mode voltage (VCM) of approximately +2.5V to bias the inputs of the driving amplifier. Using the OPA681 on a single +5V supply, its ideal common-mode point is +2.5V. This coincides with the recommended common-mode input level for the ADS831 thus, obviating the need for a coupling capacitor between the amplifier and the converter. Even though the OPA681 has an ac gain of +2, the dc gain is only +1 due to the blocking capacitor at resistor RG. The addition of a small series resistor (RS) between the output of the op amp and the input of the ADS831 will be beneficial in almost all interface configurations. This will de-couple the op amp’s output from the capacitive load and avoid gain peaking, which can result in increased noise. For best spurious and distortion performance, the resistor value should be kept below 75Ω. The series resistor in combination with the 47pF capacitor establishes a passive low-pass filter limiting the bandwidth for the wideband noise thus help improving the SNR performance. AC-Coupled, Dual Supply Interface The circuit provided in Figure 3 shows typical connections for the analog input in case the selected amplifier operates on dual supplies. This might be necessary to take full advantage of very low distortion operational amplifiers, like the OPA642. The advantage is that the driving amplifier can be operated with a ground referenced bipolar signal swing. This will keep the distortion performance at its lowest since the signal range stays within the linear region of the op amp and sufficient headroom to the supply rails can be maintained. By capacitively coupling the single-ended signal to the input of the ADS831, its common-mode requirements can easily be satisfied with two resistors connected between the top and bottom reference. Op Amp Bias φ1 VCM φ1 CH φ2 CI IN IN φ1 φ1 φ2 CI CH φ1 Input Clock (50%) Op Amp Bias Internal Non-overlapping Clock φ1 φ2 φ1 VCM φ1 φ1 OUT OUT φ2 FIGURE 1. Simplified Circuit of Input Track and Hold with Timing Diagram. ® 7 ADS831 1kΩ +5V VCM = +2.5VDC +5V 0.1µF VIN OPA681 47pF +VIN 0V –VIN RF 402Ω CM RG 402Ω 0.1µF IN 0.1µF INT/EXT GND ADS831 RS 39Ω IN REFB +2.0V REFT +3.0V RSEL +VS 1kΩ FIGURE 2. AC-Coupled Input Configuration for a 2Vp-p Full-Scale Range and a Common-Mode Voltage, VCM, at +2.5V Derived From the Internal Top (REFT) and Bottom Reference (REFB). The OPA680 can be used in place of the OPA681 if a voltage feedback amplifier is preferred. +5V 1kΩ +5V VIN OPA642 47pF –5V RF 402Ω 1kΩ CM IN RG 402Ω 0.1µF REFB +2.0V ADS831 RS 24.9Ω 0.1µF IN REFT +3.0V RSEL +VS INT/EXT GND FIGURE 3. AC-Coupling the Dual Supply Amplifier OPA642 to the ADS831 for a 2Vp-p Full-Scale Input Range. For applications requiring the driving amplifier to provide a signal amplification with a gain ≥ 5, consider using decompensated voltage feedback op amps, such as the OPA643, or current feedback op amps OPA681 and OPA658. DC-Coupled with Level Shift Several applications may require that the bandwidth of the signal path includes DC, in which case the signal has to be DC-coupled to the A/D converter. In order to accomplish this, the interface circuit has to provide a DC level shift to the analog input signal. The circuit shown in Figure 4 employs a dual op amp, A1, to drive the input of the ADS831 and level shift the signal to be compatible with the selected input range. With the RSEL pin tied to the supply and the INT/EXT pin to ground, the ADS831 is configured for a 2Vp-p input range and uses the internal references. The complementary input (IN) may be appropri® ately biased using the +2.5V common-mode voltage available at the CM pin. One-half of the amplifier (OPA2681) buffers the REFB pin and drives the voltage divider R1, R2. Because of the op amp’s noise gain of +2V/V, assuming RF = RIN , the common-mode voltage (VCM) has to be rescaled to +1.25V, resulting in the correct DC level of +2.5V for the signal input (IN). Any DC voltage differences between the IN and IN inputs of the ADS831 effectively produce an offset, which can be corrected for by adjusting the resistor values of the divider, R1 and R2. The selection criteria for a suitable op amp should include the supply voltage, input bias current, output voltage swing, distortion, and noise specification. Note that in this example the overall signal phase is inverted. To re-establish the original signal polarity, it is always possible to interchange the IN and IN connections. ADS831 8 +5V RF 499Ω RIN 499Ω VIN 2Vp-p 1/2 OPA2681 RS 39Ω IN 47pF RSEL +VS ADS831 NOTE: RF = RIN, G = –1 CM (+2.5V) IN +5V R2 301Ω VCM = +1.25V R1 499Ω 0.1µF REFB (+2.0V) REFT (+3.0V) 0.1µF 1/2 OPA2681 INT/EXT 50Ω 0.1µF RF 1kΩ FIGURE 4. DC-Coupled Interface Circuit with Dual Current-Feedback Amplifier OPA2681. The OPA2680 can be used in place of the OPA2681 if a voltage feedback amplifier is preferred. SINGLE ENDED-TO-DIFFERENTIAL CONFIGURATION (Transformer Coupled) If the application requires a signal conversion from a singleended source to feed the ADS831 differentially, a RF transformer might be a good solution. The selected transformer must have a center tap in order to apply the common-mode DC voltage necessary to bias the converter inputs. AC grounding the center tap will generate the differential signal swing across the secondary winding. Consider a stepup transformer to take advantage of a signal amplification without the introduction of another noise source. Furthermore, the reduced signal swing from the source may lead to an improved distortion performance. The differential input configuration may provide a noticeable advantage of achieving good SFDR performance over a wide range of input frequencies. In this mode both inputs of the ADS831 see closely matched impedances, and the differential signal swing is reduced to half of the swing required for single-ended drive. Figure 5 shows the schematic for the suggested transformer coupled interface cirRG 0.1µF 1:n VIN 47pF RT 22Ω IN 47pF +5V + 10µF 0.1µF CM RSEL INT/EXT ADS831 22Ω IN cuit. The component values of the R-C lowpass may be optimized depending on the desired roll-off frequency. The resistor across the secondary side (RT) should be calculated using the equation RT = n2 x RG to match the source impedance (RG) for good power transfer and VSWR. REFERENCE OPERATION Figure 6 depicts the simplified model of the internal reference circuit. The internal blocks are the bandgap voltage reference, the drivers for the top and bottom reference, and RSEL ADS831 50kΩ +VS INT/EXT 50kΩ Bandgap Reference and Logic VREF +1 +1 400Ω 400Ω REFT CM REFB Bypass Capacitors: 0.1µF || 2.2µF each FIGURE 5. Transformer Coupled Input. 9 FIGURE 6. Equivalent Reference Circuit with Recommended Reference Bypassing. ® ADS831 the resistive reference ladder. The bandgap reference circuit includes logic functions that allow to set the analog input swing of the ADS831 to either a 1Vp-p or 2Vp-p full-scale range simply by tying the RSEL pin to a LOW or HIGH potential, respectively. While operating the ADS831 in the external reference mode, the buffer amplifiers for REFT and REFB are disconnected from the reference ladder. As shown, the ADS831 has internal 50kΩ pull-up resistors at the Range Select pin (RSEL) and Reference Select pin (INT/EXT). Leaving those pins open configures the ADS831 for a 2Vp-p input range and external reference operation. Setting the ADS831 up for internal reference mode requires to bring the INT/EXT pin LOW. The reference buffers can be utilized to supply up to 1mA (sink and source) to external circuitry. To ensure proper operation with any reference configurations, it is necessary to provide solid bypassing at the reference pins in order to keep the clock feedthrough to a minimum (Figure 6). All bypassing capacitors should be located as close to their respective pins as possible. The common-mode voltage available at the CM pin may be used as a bias voltage to provide the appropriate offset for the driving circuitry. However, care must be taken not to appreciably load this node, which is not buffered and has a high impedance. An alternative way of generating a common-mode voltage is given in Figure 7. Here, two external precision resistors (1% tolerance or better) are located between the top and bottom reference pins. The commonmode voltage, CMV, will appear at the midpoint. EXTERNAL REFERENCE OPERATION For even more design flexibility, the internal reference can be disabled and an external reference voltage be used. The utilization of an external reference may be considered for applications requiring higher accuracy, improved temperature performance, or a wide adjustment range of the converter’s full-scale range. Especially in multichannel applications, the use of a common external reference has the benefit of obtaining better matching of the full-scale range between converters. The external references can vary as long as the value of the external top reference REFTEXT stays within the range of (VS – 1.25V) and (REFB + 0.8V), and the external bottom reference REFBEXT stays within 1.25V and (REFT – 0.8V), see Figure 8. REFT +3.0V R1 1kΩ 2.2µF + 0.1µF ADS831 REFB +2.0V R2 1kΩ 0.1µF + 2.2µF CMV +2.5V FIGURE 7. Alternative Circuit to Generate Common-Mode Voltage. The full-scale input signal range (FSR) of the ADS831 is determined by the voltage difference across the reference pins REFT and REFB (FSR = REFT – REFB), while the common-mode voltage is defined by CMV = (REFT + REFB)/2. In order to maintain good ac performance, it is recommended that the typical common-mode voltage be kept at +2.5V while setting the external reference voltages. It is possible, however, to deviate from this common-mode level without significantly impacting the performance. In particular, DC-coupled applications may benefit from a lower CMV as it increases the signal headroom of the +5V A - Short for 1Vp-p Input Range B - Short for 2Vp-p Input Range (Default) +VS VIN IN ADS831 CMV IN REFT GND REFB INT/EXT B A RSEL GND External Top Reference REFT = REFB +0.8V to +3.75V External Bottom Reference REFB = REFT –0.8V to +1.25V FIGURE 8. Configuration Example for External Reference Operation. ® ADS831 10 driving amplifier. The internal reference ladder has a nominal impedance of 800Ω. Depending on the selected reference voltages, the required drive current will vary accordingly and the external reference circuitry should be designed to supply the maximum required current. DIGITAL INPUTS AND OUTPUTS Clock Input Requirements Clock jitter is critical to the SNR performance of high speed, high resolution Analog to Digital Converters. It leads to aperture jitter (tA) which adds noise to the signal being converted. The ADS831 samples the input signal on the rising edge of the CLK input. Therefore, this edge should have the lowest possible jitter. The jitter noise contribution to total SNR is given by the following equation. If this value is near your system requirements, input clock jitter must be reduced. Jitter SNR = 20 log 1 2 π ƒ IN t A rms signal to rms noise Digital Output Driver (VDRV) The ADS831 features a dedicated supply pin for the output logic drivers, VDRV, which is not internally connected to the other supply pins. Setting the voltage at VDRV to +5V or +3V the ADS831 produces corresponding logic levels and can directly interface to the selected logic family. The output stages are designed to supply sufficient current to drive a variety of logic families. However, it is recommended to use the ADS831 with +3V logic supply. This will lower the power dissipation in the output stages due to the lower output swing and reduce current glitches on the supply line which may affect the ac performance of the converter. In some applications, it might be advantageous to decouple the VDRV pin with additional capacitors or a pi-filter. GROUNDING AND DECOUPLING Proper grounding and bypassing, short lead length, and the use of ground planes are particularly important for high frequency designs. Multilayer PC boards are recommended for best performance since they offer distinct advantages like minimizing ground impedance, separation of signal layers by ground layers, etc. The ADS831 should be treated as an analog component. Whenever possible, the supply pins should be powered by the analog supply. This will ensure the most consistent results since digital supply lines often carry high levels of noise which otherwise would be coupled into the converter and degrade the achievable performance. All ground connections on the ADS831 are internally joined together, obviating the design of split ground planes. The ground pins (1, 18) should directly connect to an analog ground plane which covers the PC board area around the converter. While designing the layout, it is important to keep the analog signal traces separated from any digital lines to prevent noise coupling onto the analog signal path. Because of its high sampling rate, the ADS831 generates high frequency current transients and noise (clock feedthrough) that are fed back into the supply and reference lines. This requires that all supply and reference pins are sufficiently bypassed. Figure 9 shows the recommended decoupling scheme for the ADS831. In most cases, 0.1µF ceramic chip capacitors at each pin are adequate to keep the impedance low over a wide frequency range. Their effectiveness largely depends on the proximity to the individual supply pin. Therefore, they should be located as close to the supply pins as possible. In addition, a larger bipolar capacitor (1µF to 22µF) should be placed on the PC board in proximity of the converter circuit. Where: ƒIN is Input Signal Frequency tA is rms Clock Jitter Particularly in udersampling applications, special consideration should be given to clock jitter. The clock input should be treated as an analog input in order to achieve the highest level of performance. Any overshoot or undershoot of the clock signal may cause degradation of the performance. When digitizing at high sampling rates, the clock should have a 50% duty cycle (tH = tL), along with fast rise and fall times of 2ns or less. Digital Outputs The output data format of the ADS831 is in positive Straight Offset Binary code, see Table I. This format can easily converted into the Two’s Binary Complement code by inverting the MSB. SINGLE-ENDED INPUT (2Vp-p) (IN = CMV) +FS (IN = +3.5V) +1/2 FS +1LSB Bipolar Zero (IN = 2.5V) –1LSB –1/2 FS –FS (IN = +1.5V) STRAIGHT OFFSET BINARY (SOB) 1111 1100 1000 1000 0111 0100 0000 1111 0000 0001 0000 1111 0000 0000 TABLE I. Coding Table for the ADS831. It is recommended to keep the capacitive loading on the data lines as low as possible (≤ 15pF). Higher capacitive loading will cause larger dynamic currents as the digital outputs are changing. Those high current surges can feed back to the analog portion of the ADS831 and affect the performance. If necessary, external buffers or latches close to the converter’s output pins may be used to minimize the capacitive loading. They also provide the added benefit of isolating the ADS831 from any digital noise activities on the bus coupling back high frequency noise. 11 ADS831 GND 1 +VS 19 0.1µF GND 18 VDRV 20 0.1µF 10µF + +5V +3/+5V FIGURE 9. Recommended Bypassing for the Supply Pins. ® ADS831