ADS8319IDGST

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents ADS8319 SLAS600C – MAY 2008 – REVISED DECEMBER 2016 ADS8319 16-Bit, 500-kSPS, Serial Interface, Micropower, Miniature, SAR Analog-to-Digital Converter 1 Features 3 Description • • • • • The ADS8319 device is a 16-bit, 500-kSPS, analogto-digital converter (ADC) that operates with a 2.25-V to 5.5-V external reference. The device includes a capacitor-based, successive-approximation register (SAR) ADC with inherent sample and hold. 1 • • • • • 500-kHz Sample Rate 16-Bit Resolution Zero Latency at Full Speed Unipolar, Single-Ended Input Range: 0 V to VREF SPI-Compatible Serial Interface With Daisy-Chain Option Excellent Performance: – 93.6-dB SNR (Typical) at 10-kHz Input – –106-dB THD (Typical) at 10-kHz Input – ±1.5-LSB (Maximum) INL – ±1-LSB (Maximum) DNL Low Power Dissipation: 18 mW (Typical) at 500 kSPS Power Scales Linearly with Speed: 3.6 mW / 100 kSPS Power Dissipation During Power-Down State: 0.25 µW (Typical) 10-Pin VSSOP and VSON Packages The device includes a 50-MHz, SPI-compatible serial interface. The interface is designed to support daisychaining or cascading of multiple devices. Furthermore, a Busy Indicator makes synchronizing with the digital host easy. The device unipolar, single-ended input supports an input swing of 0 V to +VREF. Device operation is optimized for very-low power operation and the power consumption directly scales with speed. This feature makes the device attractive for lower-speed applications. The device is available in 10-pin VSSOP and VSON packages. Device Information(1) PART NUMBER ADS8319 2 Applications • • • • • range PACKAGE BODY SIZE (NOM) VSSOP (10) 3.00 mm × 3.00 mm VSON (10) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Battery-Powered Equipment Data Acquisition Systems Instrumentation and Process Controls Medical Electronics Optical Networking Simplified Schematic +VA SAR O/P Drive COMP I/P Shift Reg IN+ CDAC +VBD IN- REFIN Conversion and I/O Control Logic ADS8319 GND SDO SDI SCLK CONVST Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADS8319 SLAS600C – MAY 2008 – REVISED DECEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 4 4 4 4 5 7 7 9 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements: +VBD ≥ 4.5 V........................ Timing Requirements: 4.5 V > +VBD ≥ 2.375 V ...... Typical Characteristics .............................................. Detailed Description ............................................ 16 8.1 Overview ................................................................. 16 8.2 Functional Block Diagram ....................................... 16 8.3 Feature Description................................................. 17 8.4 Device Functional Modes........................................ 19 9 Application and Implementation ........................ 27 9.1 Application Information............................................ 27 9.2 Typical Application .................................................. 27 10 Power Supply Recommendations ..................... 29 11 Layout................................................................... 29 11.1 Layout Guidelines ................................................. 29 11.2 Layout Example .................................................... 30 12 Device and Documentation Support ................. 31 12.1 12.2 12.3 12.4 12.5 12.6 Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 31 31 31 31 31 31 13 Mechanical, Packaging, and Orderable Information ........................................................... 31 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (December 2015) to Revision C Page • Added ESD Ratings table, Recommended Operating Conditions table, Thermal Information table, Functional Block Diagram, Application and Implementation section, Power Supply Recommendations section, and Layout section ............. 1 • Changed all references of MSOP to VSSOP ........................................................................................................................ 1 • Changed all references of SON to VSON ............................................................................................................................. 1 • Moved Operation temperature From: Electrical Characteristics table To: Recommended Operating Conditions table ....... 4 • Changed Thermal impedance, RθJA, values in Thermal Information table From: 180°C/W To: 107.5°C/W (VSSOP) and From: 70°C/W To: 87.2°C/W (VSON) ............................................................................................................................. 4 Changes from Revision A (September 2013) to Revision B Page • Deleted data from the Device Comparison Table this is repeated in the POA ...................................................................... 3 • Changed External Reference Input, VREF parameter maximum specification ........................................................................ 6 • Changed VDD to +VA in first sentence fo the Reference section .......................................................................................... 18 • Changed Figure 51: added +VBD to device SDI connection ............................................................................................... 21 • Changed Figure 57: changed device number for device blocks .......................................................................................... 24 • Changed Figure 58: changed SDO #2 trace ........................................................................................................................ 25 • Changed Figure 59: changed device number for device blocks .......................................................................................... 25 • Changed Figure 60: changed SDO #2 trace ........................................................................................................................ 26 Changes from Original (May 2008) to Revision A Page • Changed CBC to CEN in Ordering Information...................................................................................................................... 3 • Changed CBE to CEP in Ordering Information ...................................................................................................................... 3 2 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 ADS8319 www.ti.com SLAS600C – MAY 2008 – REVISED DECEMBER 2016 5 Device Comparison Table DEVICE MAXIMUM INTEGRAL LINEARITY (LSB) MAXIMUM DIFFERENTIAL LINEARITY (LSB) NO MISSING CODES AT RESOLUTION (Bits) ADS8319I ±2.5 1.5, –1 16 ADS8319IB ±1.5 ±1 16 6 Pin Configuration and Functions DGS Package 10-Pin VSSOP Top View DRC Package 10-Pin VSON With Exposed Thermal Pad Top View REFIN 1 10 +VBD +VA 2 9 SDI +IN 3 8 SCLK –IN 4 7 SDO GND 5 6 CONVST REFIN 1 10 +VA 2 9 SDI +IN 3 8 SCLK –IN 4 7 SDO GND 5 6 CONVST PAD +VBD Not to scale Not to scale Pin Functions PIN NAME NO. I/O DESCRIPTION CONVST 6 Input Convert input. CONVST also functions as the CS input in 3-wire interface mode. See CS Mode for more details. GND 5 Power Device ground. This pin is a common ground for both analog power supply (+VA) and digital I/O supply (+VBD). +IN 3 Analog Input Noninverting analog signal input –IN 4 Analog Input Inverting analog signal input. This input is limited to ±0.1 V and is typically grounded at the input decoupling capacitor. REFIN 1 Analog Input Reference (positive) input. Decouple to GND with a 0.1-µF bypass capacitor and a 10-µF storage capacitor. SCLK 8 Input SDO 7 Output SDI 9 Input Serial data input. The SDI level at the start of a conversion selects the mode of operation (such as CS or daisy-chain mode). This pin also serves as the CS input in 4-wire interface mode. See CS Mode for more details. +VA 2 Power Analog power supply. Decouple to GND. +VBD 10 Power Digital I/O power supply. Decouple to GND. Serial I/O clock input. Data (on the SDO output are synchronized with this clock. Serial data output Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 3 ADS8319 SLAS600C – MAY 2008 – REVISED DECEMBER 2016 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) +IN pin voltage MIN MAX UNIT –0.3 +VA + 0.3 V ±130 mA +IN pin current –IN pin voltage –0.3 –IN pin current 0.3 V ±130 mA +VA to AGND –0.3 7 V +VBD to BDGND –0.3 7 V Digital input voltage to GND –0.3 +VBD + 0.3 V Digital output to GND –0.3 +VBD + 0.3 V 260 °C 260 °C 85 °C 150 °C 150 °C Maximum VSSOP reflow temperature (2) Maximum VSON reflow temperature (2) Operating free-air temperature, TA –40 Junction temperature, TJ(MAX) Storage temperature, Tstg (1) (2) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The device is rated to MSL2 260°C, as per the JSTD-020 specification. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX 4.5 5 5.5 V 2.375 3.3 5.5 V Reference voltage 2.25 4.096 +VA + 0.1 V Operating temperature –40 85 °C +VA Analog power-supply voltage +VBD Digital I/O-supply voltage VREF TA UNIT 7.4 Thermal Information ADS8319 THERMAL METRIC (1) DGS (VSSOP) DRC (VSON) 10 PINS 10 PINS UNIT RθJA Junction-to-ambient thermal resistance 107.5 87.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 21.8 31.1 °C/W RθJB Junction-to-board thermal resistance 24.2 25.5 °C/W ψJT Junction-to-top characterization parameter 0.6 1 °C/W ψJB Junction-to-board characterization parameter 24.4 29.2 °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 ADS8319 www.ti.com SLAS600C – MAY 2008 – REVISED DECEMBER 2016 7.5 Electrical Characteristics TA = –40°C to 85°C, +VA = 5 V, +VBD = 5 V to 2.375 V, VREF = 4 V, and fSAMPLE = 500 kHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V ANALOG INPUT Full-scale input span (1) Operating input +IN – (–IN) 0 VREF +IN –0.1 VREF + 0.1 –IN –0.1 0.1 Input capacitance Input leakage current During acquisition V 59 pF 1000 pA 16 Bits SYSTEM PERFORMANCE Resolution No missing codes INL Integral linearity (2) DNL Differential linearity EO Offset error (4) EG Gain error 16 Bits ADS8319I –2.5 ±1.2 2.5 ADS8319IB –1.5 ±1 1.5 ADS8319I –1 ±0.65 1.5 ADS8319IB –1 ±0.5 1 –1.5 ±0.3 1.5 –0.03 ±0.0045 At 16-bit level CMRR Common-mode rejection ratio With common-mode input signal = 200 mVPP at 500 kHz PSRR Power-supply rejection ratio At FFF0h output code LSB mV 0.03 %FSR 78 Transition noise LSB (3) dB 80 dB 0.5 LSB SAMPLING DYNAMICS tCONV Conversion time Acquisition time +VBD = 5 V 1400 +VBD = 3 V 1400 +VBD = 5 V 600 +VBD = 3 V 600 ns Maximum throughput rate with or without latency 0.5 Aperture delay Aperture jitter, RMS ns MHz 2.5 ns 6 ps Step response Settling to 16-bit accuracy 600 ns Overvoltage recovery Settling to 16-bit accuracy 600 ns DYNAMIC CHARACTERISTICS THD Total harmonic distortion (5) VIN 0.4 dB below FS at 1 kHz, VREF = 5 V –111 VIN 0.4 dB below FS at 10 kHz, VREF = 5 V –106 VIN 0.4 dB below FS at 100 kHz, VREF = 5 V –89 ADS8319IB, VIN 0.4 dB below FS at 1 kHz, VREF = 5 V SNR SINAD (1) (2) (3) (4) (5) Signal-to-noise ratio Signal-to-noise + distortion dB 92 VIN 0.4 dB below FS at 1 kHz, VREF = 5 V 93.9 VIN 0.4 dB below FS at 10 kHz, VREF = 5 V 93.6 VIN 0.4 dB below FS at 100 kHz, VREF = 5 V 92.2 VIN 0.4 dB below FS at 1 kHz, VREF = 5 V 93.8 VIN 0.4 dB below FS at 10 kHz, VREF = 5 V 93.4 VIN 0.4 dB below FS at 100 kHz, VREF = 5 V 87.4 dB dB Ideal input span, does not include gain or offset error. This parameter is endpoint INL, not best fit. LSB means least significant bit. Measured relative to actual measured reference. Calculated on the first nine harmonics of the input frequency. Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 5 ADS8319 SLAS600C – MAY 2008 – REVISED DECEMBER 2016 www.ti.com Electrical Characteristics (continued) TA = –40°C to 85°C, +VA = 5 V, +VBD = 5 V to 2.375 V, VREF = 4 V, and fSAMPLE = 500 kHz, unless otherwise noted. PARAMETER SFDR Spurious-free dynamic range TEST CONDITIONS MIN TYP VIN 0.4 dB below FS at 1 kHz, VREF = 5 V 113 VIN 0.4 dB below FS at 10 kHz, VREF = 5 V 107 VIN 0.4 dB below FS at 100 kHz, VREF = 5 V 90 –3-dB small-signal bandwidth MAX UNIT dB 15 MHz EXTERNAL REFERENCE INPUT VREF Reference input Reference input current (6) 2.25 During conversion 4.096 +VA + 0.1 250 V µA POWER SUPPLY REQUIREMENTS Power-supply voltage +VBD +VA 2.375 3.3 5.5 4.5 5 5.5 V Supply current +VA, 500-kHz sample rate 3.6 4.5 mA PVA Power dissipation +VA = 5 V, 500-kHz sample rate 18 22.5 mW IVApd Device power-down current (7) +VA = 5 V 50 300 nA LOGIC FAMILY CMOS VIH Input HIGH logic level IIH = 5 µA +(0.7 × VBD) +VBD + 0.3 VIL Input LOW logic level IIL = 5 µA –0.3 +(0.3 × VBD) VOH Output HIGH logic level IOH = 2 TTL loads +VBD – 0.3 +VBD VOL Output LOW logic level IOL = 2 TTL loads 0 0.4 (6) (7) 6 V Can vary by ±20%. The device automatically enters a power-down state at the end of every conversion and remains in a power-down state during the acquisition phase. Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 ADS8319 www.ti.com SLAS600C – MAY 2008 – REVISED DECEMBER 2016 7.6 Timing Requirements: +VBD ≥ 4.5 V All specifications are typical at –40°C to 85°C, +VA = 5 V, and +VBD ≥ 4.5 V, unless otherwise noted. REFERENCE FIGURE MIN MAX UNIT SAMPLING AND CONVERSION RELATED tACQ Acquisition time tcnv Conversion time tcyc Time between conversions t1 Pulse duration, CONVST high t6 Pulse duration, CONVST low 600 Figure 50, Figure 52, Figure 53, Figure 55 ns 1400 ns 2000 ns Figure 50, Figure 52 10 ns Figure 53, Figure 55, Figure 58 20 ns 20 ns 9 ns 9 ns I/O RELATED tclk SCLK period tclkl SCLK low time tclkh SCLK high time t2 SCLK falling edge to data remains valid t3 SCLK falling edge to next data valid delay ten Enable time, CONVST or SDI low to MSB valid tdis Disable time, CONVST or SDI high or last SCLK falling edge to SDO 3-state (CS mode) t4 Setup time, SDI valid to CONVST rising edge t5 Hold time, SDI valid from CONVST rising edge t7 Setup time, SCLK valid to CONVST rising edge t8 Hold time, SCLK valid from CONVST rising edge Figure 50, Figure 52, Figure 53, Figure 55, Figure 58, Figure 60 5 ns 16 ns Figure 50, Figure 53 15 ns Figure 50, Figure 52, Figure 53, Figure 55 12 ns Figure 53, Figure 55 Figure 58 5 ns 5 ns 5 ns 5 ns 7.7 Timing Requirements: 4.5 V > +VBD ≥ 2.375 V All specifications are typical at –40°C to 85°C, +VA = 5 V, and +4.5 V > +VBD ≥ 2.375 V, unless otherwise noted. REFERENCE FIGURE MIN MAX UNIT SAMPLING AND CONVERSION RELATED tACQ Acquisition time tcnv Conversion time 600 tcyc Time between conversions 2000 ns t1 Pulse width CONVST high Figure 50, Figure 52 10 ns t6 Pulse width CONVST low Figure 53, Figure 55, Figure 58 20 ns Figure 50, Figure 52, Figure 53, Figure 55 ns 1400 ns I/O RELATED tclk SCLK period 30 ns tclkl SCLK low time 13 ns tclkh SCLK high time 13 ns t2 SCLK falling edge to data remains valid t3 SCLK falling edge to next data valid delay ten CONVST or SDI low to MSB valid tdis CONVST or SDI high or last SCLK falling edge to Figure 50, Figure 52, Figure 53, Figure 55 SDO 3-state (CS mode) t4 SDI valid setup time to CONVST rising edge t5 SDI valid hold time from CONVST rising edge t7 SCLK valid setup time to CONVST rising edge t8 SCLK valid hold time from CONVST rising edge Figure 50, Figure 52, Figure 53, Figure 55, Figure 58, Figure 60 5 Figure 50, Figure 53 Figure 53, Figure 55 Figure 58 ns 24 ns 22 ns 15 ns 5 ns 5 ns 5 ns 5 ns Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 7 ADS8319 SLAS600C – MAY 2008 – REVISED DECEMBER 2016 www.ti.com 500µA I ol From SDO 1.4V 20pF 500µA I oh Figure 1. Load Circuit for Digital Interface Timing 0.7 VBD 0.3 VBD t DELAY tDELAY 2V 2V 0.8V 0.8V Figure 2. Voltage Levels for Timing 8 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 ADS8319 www.ti.com SLAS600C – MAY 2008 – REVISED DECEMBER 2016 7.8 Typical Characteristics 0.005 -0.2 0.0045 -0.25 0.004 -0.35 -0.4 +VBD = 2.7 V, Vref = 4.096 V, fs = 500 KSPS, TA = 30°C -0.45 -0.5 4.5 4.75 5 5.25 0.0035 Gain Error - %FSR Offset Error - mV -0.3 0.003 0.0025 0.002 0.0015 0.0005 0 4.5 5.5 +VA - Supply Voltage - V 4.75 5.25 5.5 Figure 4. Gain Error vs Supply Voltage 0.0045 0 +VBD = 2.7 V, +VA = 5 V, fs = 500 KSPS, TA = 30°C -0.05 0.004 0.0035 Gain Error - %FSR -0.1 -0.15 -0.2 -0.25 0.003 0.0025 0.002 0.0015 +VBD = 2.7 V, +VA = 5 V, fs = 500 KSPS, TA = 30°C 0.001 -0.3 0.0005 -0.35 2 2.5 3 3.5 4 4.5 Vref - Reference Voltage - V 0 5 2 Figure 5. Offset Error vs Reference Voltage -0.2 5 0.01 +VA = 5 V, +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS 0.009 0.008 Gain Error - %FSR -0.3 -0.4 -0.5 -0.6 -0.7 0.007 0.005 0.004 0.003 0.002 -0.9 0.001 -25 -10 5 20 35 50 65 0 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 80 TA - Free-Air Temperature - °C Figure 7. Offset Error vs Free-Air Temperature +VA = 5 V, +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS 0.006 -0.8 -1 -40 2.5 3 3.5 4 4.5 Vref - Reference Voltage - V Figure 6. Gain Error vs Reference Voltage 0 -0.1 Offset Error - mV 5 +VA - Supply Voltage - V Figure 3. Offset Error vs Supply Voltage Offset Error - mV +VBD = 2.7 V, Vref = 4.096 V, fs = 500 KSPS, TA = 30°C 0.001 80 Figure 8. Gain Error vs Free-Air Temperature Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 9 ADS8319 SLAS600C – MAY 2008 – REVISED DECEMBER 2016 www.ti.com Typical Characteristics (continued) 25 14 +VA = 5 V, +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS 10 20 8 6 4 3 10 5 5 5 1 0 0 0 0 0 0 1 0 0 0 -0.5 -0.4-0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 ppm/°C 0.6 0 0 0 0 0 Figure 10. Offset Error Drift Histogram 1.5 INL - Integral Nonlinearity LSBs +VBD = 2.7 V, Vref = 4.096 V, fs = 500 KSPS, TA = 30°C 0.8 0 -0.5 -0.4 -0.3-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 ppm/°C Figure 9. Gain Error Drift Histogram 1 DNL - Differential Nonlinearity - LSBs 20 15 3 2 DNLMAX 0.4 0.2 0 -0.2 DNLMIN -0.4 -0.6 INLMAX 1 0.5 +VBD = 2.7 V, Vref = 4.096 V, fs = 500 KSPS, TA = 30°C 0 -0.5 INLMIN -1 -0.8 -1 4.5 4.75 5 5.25 +VA - Supply Voltage - V -1.5 4.5 5.5 5 5.25 5.5 Figure 12. Integral Nonlinearity vs Supply Voltage 1.5 1 0.8 INL - Integral Nonlinearity LSBs DNL - Differential Nonlinearity LSBs 4.75 +VA - Supply Voltage - V Figure 11. Differential Nonlinearity vs Supply Voltage DNLMAX 0.6 0.4 +VA = 5 V, +VBD = 2.7 V, fs = 500 KSPS, TA = 30°C 0.2 0 -0.2 DNLMIN -0.4 -0.6 INLMAX 1 0.5 +VA = 5 V, +VBD = 2.7 V, fs = 500 KSPS, TA = 30°C 0 -0.5 INLMIN -1 -0.8 -1.5 -1 2 2.5 3 3.5 4 4.5 Vref - Reference Voltage - V 2 5 Figure 13. Differential Nonlinearity vs Reference Voltage 10 +VA = 5 V +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS 12 12 Number of Devices Number of Devices 12 2.5 3 3.5 4 4.5 Vref - Reference Voltage - V 5 Figure 14. Integral Nonlinearity vs Reference Voltage Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 ADS8319 www.ti.com SLAS600C – MAY 2008 – REVISED DECEMBER 2016 1 1 0.8 0.8 0.6 INL - Integral Nonlinearity - LSBs INL - Integral Nonlinearity LSBs Typical Characteristics (continued) DNLMAX 0.4 0.2 0 -0.2 DNLMIN -0.4 +VA = 5 V +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS -0.6 -0.8 -1 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 0.6 0.4 0 -0.2 -0.4 -0.6 -0.8 15.7 15.5 15.4 15.3 15.2 15.1 4.75 5 5.25 +VA - Supply Voltage - V 15.6 15.4 15.2 15 14.8 14.6 14.4 14.2 15.6 15.5 15.4 15.3 15.2 15.1 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 2.5 3 3.5 4 4.5 5 Figure 18. Effective Number of Bits vs Reference Voltage SFDR - Spurious Free Dynamic Range - dB +VA = 5 V, +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS, fi = 1.9 kHz 15 -40 -25 2 Vref - Reference Voltage - V 16 ENOB - Effective Number Of Bits - LSBs +VA = 5 V, +VBD = 2.7 V, fs = 500 KSPS, fi = 1.9 kHz, TA = 30°C 15.8 5.5 Figure 17. Effective Number of Bits vs Supply Voltage 15.7 80 14 15 4.5 15.8 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 16 +VBD = 2.7 V, Vref = 4.096 V, fs = 500 KSPS, fi = 1.9 kHz, TA = 30°C 15.6 15.9 -25 Figure 16. Integral Nonlinearity vs Free-Air Temperature ENOB - Effective Number Of Bits - LSBs ENOB - Effective Number Of Bits - LSBs 15.8 INLMIN -1 -40 16 15.9 +VA = 5 V +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS 0.2 80 Figure 15. Differential Nonlinearity vs Free-Air Temperature INLMAX 80 Figure 19. Effective Number of Bits vs Free-Air Temperature 119 117 115 +VBD = 2.7 V, Vref = 4.096 V, fs = 500 KSPS, fi = 1.9 kHz, TA = 30°C 113 111 109 107 105 4.5 4.75 5 5.25 +VA - Supply Voltage - V 5.5 Figure 20. Spurious-Free Dynamic Range vs Supply Voltage Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 11 ADS8319 SLAS600C – MAY 2008 – REVISED DECEMBER 2016 www.ti.com Typical Characteristics (continued) 94.5 +VBD = 2.7 V, Vref = 4.096 V, fs = 500 KSPS, fi = 1.9 kHz, TA = 30°C 94 SNR - Signal-to-Noise Ratio - dB SINAD - Signal-to-Noise and Distortion - dB 94.5 93.5 93 92.5 92 4.5 4.75 5 5.25 +VA - Supply Voltage - V 111 109 107 4.75 5 5.25 +VA - Supply Voltage - V 117 113 111 109 107 105 2 5.5 95 94.5 93 92.5 92 91.5 91 90.5 3 3.5 4 4.5 Vref - Reference Voltage - V 5 94 93.5 93 +VA = 5 V, +VBD = 2.7 V, fs = 500 KSPS, fi = 1.9 kHz, TA = 30°C 92.5 92 91.5 91 90.5 90 2 12 SNR - Signal-to-Noise Ratio - dB SINAD - Signal-to-Noise + Distortion - dB 95 93.5 2.5 Figure 24. Spurious-Free Dynamic Range vs Reference Voltage 94.5 +VA = 5 V, +VBD = 2.7 V, fs = 500 KSPS, fi = 1.9 kHz, TA = 30°C 5.5 +VA = 5 V, +VBD = 2.7 V, fs = 500 KSPS, fi = 1.9 kHz, TA = 30°C 115 Figure 23. Total Harmonic Distortion vs Supply Voltage 94 4.75 5 5.25 +VA - Supply Voltage - V Figure 22. Signal-to-Noise Ratio vs Supply Voltage 113 105 4.5 +VBD = 2.7 V, Vref = 4.096 V, fs = 500 KSPS, fi = 1.9 kHz, TA = 30°C 92.5 SFDR - Spurious Free Dynamic Range - dB THD - Total Harmonic Distortion - dB 115 93 92 4.5 +VBD = 2.7 V, Vref = 4.096 V, fs = 500 KSPS, fi = 1.9 kHz, TA = 30°C 117 93.5 5.5 Figure 21. Signal-to-Noise + Distortion vs Supply Voltage 119 94 2.5 3 3.5 4 4.5 5 90 2 Vref - Reference Voltage - V 2.5 3 3.5 4 4.5 Vref - Reference Voltage - V Figure 25. Signal-to-Noise + Distortion vs Reference Voltage Figure 26. Signal-to-Noise Ratio vs Reference Voltage Submit Documentation Feedback 5 Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 ADS8319 www.ti.com SLAS600C – MAY 2008 – REVISED DECEMBER 2016 THD - Total Harmonic Distortion - dB 117 SFDR - Spurious Free Dynamic Range - dB Typical Characteristics (continued) +VA = 5 V, +VBD = 2.7 V, fs = 500 KSPS, fi = 1.9 kHz, TA = 30°C 115 113 111 109 107 105 2 2.5 3 3.5 4 4.5 Vref - Reference Voltage - V 117 115 113 SFDR 111 5 109 107 105 103 -40 96 80 96 95 SINAD 94 93 +VA = 5 V, +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS, fi = 1.9 kHz 92 91 90 -40 -25 -10 5 20 35 50 65 SNR - Signal-to-Noise Ratio - dB SINAD - Signal-to-noise + Distortion - dB -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C Figure 28. Spurious-Free Dynamic Range vs Free-Air Temperature Figure 27. Total Harmonic Distortion vs Reference Voltage 95 93 92 +VA = 5 V, +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS, fi = 1.9 kHz 91 90 -40 80 Figure 29. Signal-to-Noise + Distortion vs Free-Air Temperature SNR 94 TA - Free-Air Temperature - °C -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 80 Figure 30. Signal-to-Noise Ratio vs Free-Air Temperature 117 SINAD - Signal-To-Noise + Distortion - dB 95 +VA = 5 V, +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS, fi = 1.9 kHz 115 THD - Total Harmonic Distortion +VA = 5 V, +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS, fi = 1.9 kHz 113 111 THD 109 107 105 103 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 80 94 SINAD @ -10 dB 93 92 SINAD @ -0.5 dB 91 90 +VA = 5 V +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS, TA = 30°C 89 88 87 1 Figure 31. Total Harmonic Distortion vs Free-Air Temperature 10 fi - Signal Input Frequency - kHz 100 Figure 32. Signal-to-Noise + Distortion vs Signal Input Frequency Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 13 ADS8319 SLAS600C – MAY 2008 – REVISED DECEMBER 2016 www.ti.com Typical Characteristics (continued) 300000 +VA = 5 V, +VBD = 2.7 V, 250000 Vref = 5 V, fs = 500 KSPS, T = 30°C 200000 A +VA = 5 V +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS, TA = 30°C 125 115 Hits THD - Total Harmonic Distortion - dB 135 THD @ -0.5 dB 105 95 150000 100000 THD @ -10 dB 85 50000 75 1 10 fi - Signal Input Frequency - kHz 0 100 Figure 33. Total Harmonic Distortion vs Signal Input Frequency 0 32766 Codes 32767 Figure 34. DC Histogram of ADC Close to Center Code 3.85 0 pF 3.8 112 110 Iavdd - Supply Current - mA THD - Total Harmonic Distortion - dB 101 32765 114 680 pF 100 pF 108 +VA = 5V, +VBD = 2.7 V, Vref = 5 V, fi = 1.9 kHz, fs = 500 KSPS, TA = 30°C 106 104 3.75 3.7 +VBD = 2.7 V, Vref = 4.096 V, fs = 500 KSPS, TA = 30°C 3.65 3.6 3.55 3.5 3.45 102 3.4 100 0 100 200 300 400 500 3.35 4.5 600 Source Resistance - W 4.75 5 5.25 +VA - Supply Voltage - V Figure 35. Total Harmonic Distortion vs Source Resistance Figure 36. Supply Current vs Supply Voltage 3.9 3.7 3500 +VA = 5 V +VBD = 2.7 V, fs = 500 KSPS 3.6 3.5 3.4 3.3 3.2 3000 +VA = 5 V, +VBD = 2.7 V, TA = 30°C 2500 2000 1500 1000 500 3.1 3.0 -40 5.5 4000 Iavdd - Supply Current - mA Iavdd - Supply Current - mA 3.8 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 0 0 80 Figure 37. Supply Current vs Free-Air Temperature 14 262043 100 200 300 400 fs - sampling frequency - kSPS 500 Figure 38. Supply Current vs Sampling Frequency Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 ADS8319 www.ti.com SLAS600C – MAY 2008 – REVISED DECEMBER 2016 Typical Characteristics (continued) 200 +VA = 5 V, +VBD = 2.7 V, Vref = 5 V, TA = 30°C 18 16 Iavdd-pd - Powerdown Current - nA Iavdd*VA - Power Dissipation - mW 20 14 12 10 8 6 4 2 180 160 140 120 100 80 60 40 20 0 0 100 200 300 400 fs - sampling frequency - kSPS 0 4.5 500 Figure 39. Power Dissipation vs Sampling Frequency 400 350 300 250 200 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 +VA = 5 V, +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS, TA = 30°C 0 150 10000 20000 30000 Codes 50000 60000 50 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 80 Figure 42. DNL Figure 41. Power-Down Current vs Free-Air Temperature INL 1 0.8 0.6 0.4 0.2 FFT +VA = 5 V, +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS, TA = 30°C Amplitude - dB INL - LSB 40000 100 0 -40 0 -0.2 -0.4 -0.6 -0.8 -1 0 5.5 DNL +VA = 5 V +VBD = 2.7 V, Vref = 4.096 V, fs = 0.0 KSPS DNL - LSB 450 5 +VA - Supply Voltage - V Figure 40. Power-Down Current vs Supply Voltage 500 Iavdd-PD - Powerdown Current - nA +VBD = 2.7 V, Vref = 4.096 V, fs = 0.0 KSPS, TA = 30°C 10000 20000 30000 40000 50000 60000 0 -20 -40 -60 -80 +VA = 5 V, +VBD = 2.7 V, Vref = 5 V, fi = 1.9 kHz, fs = 500 KSPS, TA = 30°C -100 -120 -140 -160 -180 -200 0 50000 100000 150000 200000 250000 f - Frequency - Hz Codes Figure 43. INL Figure 44. FFT Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 15 ADS8319 SLAS600C – MAY 2008 – REVISED DECEMBER 2016 www.ti.com 8 Detailed Description 8.1 Overview The ADS8319 is a high-speed, low-power, successive approximation register (SAR) analog-to-digital converter (ADC) that uses an external reference. The architecture is based on charge redistribution, which inherently includes a sample and hold function. The ADS8319 is a single channel device. The analog input is provided to two input pins: +IN and –IN where –IN is a pseudo differential input and is limited to ±0.1 V. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both +IN and –IN inputs are disconnected from any internal function. The ADS8319 has an internal clock that is used to run the conversion, and hence the conversion requires a fixed amount of time. After a conversion is completed, the device reconnects the sampling capacitors to the +IN and –IN pins, and the device is in the acquisition phase. During this phase the device is powered down and conversion data can be read. The device digital output is available in SPI compatible format. It easily interfaces with microprocessors, DSPs, or FPGAs. This is a low pin count device; however, it offers six different options for the interface. They can be grossly classified as CS mode (3 or 4-wire interface) and daisy chain mode. In both modes it can either be with or without a busy indicator, where the busy indicator is a bit preceeding the 16-bit serial data. The 3-wire interface CS mode is useful for applications which require galvanic isolation on-board, where as 4-wire interface CS mode makes it easy to control an individual device while having multiple devices on-board. The daisy chain mode is provided to hook multiple devices in a chain like a shift register and is useful to reduce component count and the number of signal traces on the board. 8.2 Functional Block Diagram +VBD +VA SAR O/P Drive COMP I/P Shift Reg IN+ CDAC IN- REFIN Conversion and I/O Control Logic ADS8319 SDO SDI SCLK CONVST GND Copyright © 2016, Texas Instruments Incorporated 16 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 ADS8319 www.ti.com SLAS600C – MAY 2008 – REVISED DECEMBER 2016 8.3 Feature Description 8.3.1 Analog Input When the converter samples the input, the voltage difference between the +IN and –IN inputs is captured on the internal capacitor array. The voltage on +IN is limited to GND – 0.1 V to VREF + 0.1 V and on –IN it is limited to GND – 0.1 to GND + 0.1 V; where as the differential signal is [(+IN) – (–IN)]. This allows the input to reject small signals which are common to both the +IN and –IN inputs. Device in Hold Mode 218 W +IN 55 pF 4 pF +VA AGND 4 pF 218 W -IN 55 pF Figure 45. Input Equivalent Circuit The (peak) input current through the analog inputs depends upon a number of factors: sample rate, input voltage, and source impedance. The current into the ADS8319 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (59 pF) to a 18-bit settling level within the minimum acquisition time. When the converter goes into hold mode, the input impedance is greater than 1 GΩ. Take care regarding the absolute analog input voltage. To maintain linearity of the converter, the +IN and –IN inputs and the span [(+IN) – (–IN)] must be within the limits specified. Outside of these ranges, converter linearity may not meet specifications. Ensure that the output impedance of the sources driving the +IN and –IN inputs are matched. If this is not observed, the two inputs could have different settling times. This may result in an offset error, gain error, and linearity error which change with temperature and input voltage. Typically the –IN input is grounded at the input decoupling capacitor. 8.3.2 Driver Amplifier Choice The analog input to the converter must be driven with a low noise op-amp like the THS4031 or OPA211. TI recommends a 5-Ω resitor and a 1-nF capacitor as a RC filter at the input pins to low-pass filter the noise from the source. The input to the converter is a unipolar input voltage from 0 V to VREF. The minimum –3-dB bandwidth of the driving operational amplifier can be calculated with Equation 1. f–3 dB = (ln(2) × (n + 2)) / (2π × tACQ) where • n is equal to 16, the resolution of the ADC (in the case of the ADS8319) (1) When tACQ = 600 ns (minimum acquisition time), the minimum bandwidth of the driving circuit is approximately 3 MHz (including RC following the driver OPA). The bandwidth can be relaxed if the acquisition time is increased by the application. Typically a low noise OPA with ten times or higher bandwidth is selected. The driving circuit bandwidth is adjusted (to the required value) with a RC following the OPA. TI recommends the OPA211 or THS4031 for driving high-resolution high-speed ADCs. 8.3.3 Driver Amplifier Configurations It is better to use a unity gain, noninverting buffer configuration. As explained before a RC following the OPA limits the input circuit bandwidth just enough for 16-bit settling. Higher bandwidth reduces the settling time (beyond what is required) but increases the noise in the ADC sampled signal, and hence the ADC output. Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 17 ADS8319 SLAS600C – MAY 2008 – REVISED DECEMBER 2016 www.ti.com Feature Description (continued) 0-Vref +VA + THS4031 or OPA211 ADS8319 5W +IN 1nF 50 W -IN 5W Copyright © 2016, Texas Instruments Incorporated Figure 46. Input Drive Configuration 8.3.4 Reference The ADS8319 can operate with an external reference from 2.25 V to +VA + 0.1 V. A clean, low noise, welldecoupled reference voltage on this pin is required to ensure good performance of the converter. A low noise band-gap reference like the REF5040 or REF5050 can be used to drive this pin. A ceramic decoupling capacitor is required between the REF+ and GND pins of the converter, as shown in Figure 47. The capacitor must be placed as close as possible to the pins of the device. 50 W REF5050 OUT + + - 47 mF, 1.5 W ESR (High ESR) 10 mF OPA365 REFIN TRIM + - 4.7 mF, Low ESR IN + ADS8319 IN - Copyright © 2016, Texas Instruments Incorporated Figure 47. External Reference Driving Circuit 18 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 ADS8319 www.ti.com SLAS600C – MAY 2008 – REVISED DECEMBER 2016 Feature Description (continued) REF5050 OUT + - 22 mF 47 mF, 1.5 W ESR (High ESR) REFIN TRIM + - 4.7 mF, Low ESR IN + ADS8319 IN - Copyright © 2016, Texas Instruments Incorporated Figure 48. Direct External Reference Driving Circuit 8.3.5 Power Saving The ADS8319 has an auto power-down feature. The device powers down at the end of every conversion. The input signal is acquired on sampling capacitors while the device is in the power-down state, and at the same time the conversion results are available for reading. The device powers up by itself on the start of the conversion. As discussed before, the conversion runs on an internal clock and takes a fixed time. As a result, device power consumption is directly proportional to the speed of operation. 8.3.6 Digital Output The device digital output is SPI compatible, see CS Mode for more information. Table 1 lists the output codes corresponding to various analog input voltages. Table 1. Output Codes DESCRIPTION ANALOG VALUE (V) DIGITAL OUTPUT STRAIGHT BINARY (1) BINARY CODE HEX CODE Positive full scale +VREF – 1 LSB 1111 1111 1111 1111 FFFF Midscale VREF / 2 1000 0000 0000 0000 8000 Midscale – 1 LSB VREF / 2 – 1 LSB 0111 1111 1111 1111 7FFF Zero 0 0000 0000 0000 0000 0000 (1) Output codes apply for Full-scale = VREF and Least-significant bit (LSB) = VREF / 65536 8.3.7 SCLK Input The device uses SCLK for serial data output. Data is read after the conversion is over and the device is in the acquisition phase. It is possible to use a free running SCLK for the device, but TI recommends stopping the clock during a conversion, as the clock edges can couple with the internal analog circuit and can affect conversion results. 8.4 Device Functional Modes 8.4.1 CS Mode CS Mode is selected if SDI is high at the rising edge of CONVST. As indicated before there are four different interface options available in this mode, namely 3-wire CS mode without busy indicator, 3-wire CS mode with busy indicator, 4-wire CS mode without busy indicator, and 4-wire CS mode with busy indicator. Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 19 ADS8319 SLAS600C – MAY 2008 – REVISED DECEMBER 2016 www.ti.com Device Functional Modes (continued) 8.4.1.1 3-Wire CS Mode Without Busy Indicator The three-wire interface option in CS mode is selected if SDI is tied to +VBD, as shown in Figure 49. In the three-wire interface option, CONVST acts like CS. The device samples the input signal and enters the conversion phase on the rising edge of CONVST, at the same time SDO goes to 3-state; see Figure 50. Conversion is done with the internal clock and it continues irrespective of the state of CONVST. As a result it is possible to bring CONVST (acting as CS) low after the start of the conversion to select other devices on the board. But it is absolutely necessary that CONVST is high again before the minimum conversion time (tcnv) is elapsed. A high level on CONVST at the end of the conversion ensures the device does not generate a busy indicator. Digital Host ADS8319 +VBD CONVST CNV SCLK CLK SDO SDI SDI Copyright © 2016, Texas Instruments Incorporated Figure 49. Connection Diagram, 3-Wire CS Mode Without Busy Indicator (SDI = 1) tcyc t1 CONVST tacq tcnv ACQUISITION CONVERSION ACQUISITION tclkl t2 SCLK 1 ten 2 t3 SDO D15 16 15 tclkh D14 tdis tclk D1 D0 Figure 50. Interface Timing Diagram, 3-Wire CS Mode Without Busy Indicator (SDI = 1) When the conversion is over, the device enters the acquisition phase and powers down. On the falling edge of CONVST, SDO comes out of three state, and the device outputs the MSB of the data. After this, the device outputs the next lower data bits on every falling edge of SCLK. SDO goes to 3-state after the 16th falling edge of SCLK or CONVST high, whichever occurs first. A minimum of 15 falling edges of SCLK must occur during the low period of CONVST. 20 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 ADS8319 www.ti.com SLAS600C – MAY 2008 – REVISED DECEMBER 2016 Device Functional Modes (continued) 8.4.1.2 3-Wire CS Mode With Busy Indicator The three-wire interface option in CS mode is selected if SDI is tied to +VBD, as shown in Figure 51. In the three-wire interface option, CONVST acts like CS. The device samples the input signal and enters the conversion phase on the rising edge of CONVST, at the same time SDO goes to 3-state; see Figure 52. Conversion is done with the internal clock and it continues irrespective of the state of CONVST. As a result it is possible to toggle CONVST (acting as CS) after the start of the conversion to select other devices on the board. But it is absolutely necessary that CONVST is low again before the minimum conversion time (tcnv) is elapsed and continues to stay low until the end of maximum conversion time. A low level on the CONVST input at the end of a conversion ensures the device generates a busy indicator. Digital Host Device CNV CONVST +VBD SDI SCLK +VBD SDO CLK SDI IRQ Figure 51. Connection Diagram, 3-Wire CS Mode With Busy Indicator tcyc t1 CONVST tacq tcnv ACQUISITION CONVERSION ACQUISITION tclkl t2 SCLK 1 2 3 t3 SDO D15 D14 16 tclk D1 17 tclkh tdis D0 Figure 52. Interface Timing Diagram, 3-Wire CS Mode With Busy Indicator (SDI = 1) When the conversion is over, the device enters the acquisition phase and powers down, and the device forces SDO out of three state and outputs a busy indicator bit (low level). The device outputs the MSB of data on the first falling edge of SCLK after the conversion is over and continues to output the next lower data bits on every subsequent falling edge of SCLK. SDO goes to three state after the 17th falling edge of SCLK or CONVST high, whichever occurs first. A minimum of 16 falling edges of SCLK must occur during the low period of CONVST. Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 21 ADS8319 SLAS600C – MAY 2008 – REVISED DECEMBER 2016 www.ti.com Device Functional Modes (continued) 8.4.1.3 4-Wire CS Mode Without Busy Indicator As mentioned before for selecting CS mode it is necessary that SDI is high at the time of the CONVST rising edge. Unlike in three-wire interface option, SDI is controlled by digital host and acts like CS. As shown in Figure 53, SDI goes to a high level before the rising edge of CONVST. The rising edge of CONVST while SDI is high selects CS mode, forces SDO to three state, samples the input signal, and the device enters the conversion phase. In the 4-wire interface option CONVST must be at a high level from the start of the conversion until all of the data bits are read. Conversion is done with the internal clock and it continues irrespective of the state of SDI. As a result it is possible to bring SDI (acting as CS) low to select other devices on the board. But it is absolutely necessary that SDI is high again before the minimum conversion time (tcnv) is elapsed. CONVST t6 SDI (CS) #1 t4 t5 SDI (CS) #2 tcnv ACQUISITION tacq CONVERSION ten ACQUISITION tclkl t2 SCLK 1 ten 2 t3 SDO D15#1 17 16 15 tclkh tclk D14#1 D1#1 31 18 D15#2 D14#2 D0#1 32 tdis tdis D1#2 D0#2 Figure 53. Interface Timing Diagram, 4-Wire CS Mode Without Busy Indicator When the conversion is over, the device enters the acquisition phase and powers down. SDI falling edge can occur after the maximum conversion time (tcnv). It is necessary that SDI be high at the end of the conversion, so that the device does not generate a busy indicator. The falling edge of SDI brings SDO out of 3-state and the device outputs the MSB of the data. Subsequent to this the device outputs the next lower data bits on every falling edge of SCLK. SDO goes to three state after the 16th falling edge of SCLK or SDI (CS) high, whichever occurs first. As shown in Figure 54, it is possible to hook multiple devices on the same data bus. In this case the second device SDI (acting as CS) can go low after the first device data is read and device 1 SDO is in three state. CS1 CS2 CNV CONVST SDI CONVST SDO SCLK SDI SDO SDI SCLK CLK ADS8319#1 ADS8319#2 Digital Host Copyright © 2016, Texas Instruments Incorporated Figure 54. Connection Diagram, 4-Wire CS Mode Without Busy Indicator 22 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 ADS8319 www.ti.com SLAS600C – MAY 2008 – REVISED DECEMBER 2016 Device Functional Modes (continued) Ensure that CONVST and SDI are not low together at any time during the cycle. 8.4.1.4 4-Wire CS Mode With Busy Indicator As mentioned before for selecting CS mode it is necessary that SDI is high at the time of the CONVST rising edge. Unlike in the three-wire interface option, SDI is controlled by the digital host and acts like CS. SDI goes to a high level before the rising edge of CONVST; see Figure 55. The rising edge of CONVST while SDI is high selects CS mode, forces SDO to three state, samples the input signal, and the device enters the conversion phase. In the 4-wire interface option CONVST must be at a high level from the start of the conversion until all of the data bits are read. Conversion is done with the internal clock and it continues irrespective of the state of SDI. As a result it is possible to toggle SDI (acting as CS) to select other devices on the board. But it is absolutely necessary that SDI is low before the minimum conversion time (tcnv) is elapsed and continues to stay low until the end of the maximum conversion time. A low level on the SDI input at the end of a conversion ensures the device generates a busy indicator. tcyc t6 CNVST t5 SDI (CS) t 4 tacq tcnv ACQUISITION CONVERSION ACQUISITION tclkh t2 1 SCLK 2 3 t3 SDO D15 17 16 tclkl tdis tclk D14 D1 D0 Figure 55. Interface Timing Diagram, 4-Wire CS Mode With Busy Indicator CS SDI CNV CONVST + VBD SDO ADS8319 CLK SDI IRQ Digital Host Copyright © 2016, Texas Instruments Incorporated Figure 56. Connection Diagram, 4-Wire CS Mode With Busy Indicator Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 23 ADS8319 SLAS600C – MAY 2008 – REVISED DECEMBER 2016 www.ti.com Device Functional Modes (continued) When the conversion is over, the device enters the acquisition phase and powers down, forces SDO out of three state, and outputs a busy indicator bit (low level). The device outputs the MSB of the data on the first falling edge of SCLK after the conversion is over and continues to output the next lower data bits on every falling edge of SCLK. SDO goes to three state after the 17th falling edge of SCLK or SDI (CS) high, whichever occurs first. Ensure that CONVST and SDI are not low together at any time during the cycle. 8.4.2 Daisy-Chain Mode Daisy chain mode is selected if SDI is low at the time of CONVST rising edge. This mode is useful to reduce wiring and hardware like digital isolators in the applications where multiple (ADC) devices are used. In this mode all of the devices are connected in a chain (SDO of one device connected to the SDI of the next device) and data transfer is analogous to a shift register. Like CS mode even this mode offers operation with or without a busy indicator. 8.4.2.1 Daisy-Chain Mode Without Busy Indicator Figure 57 shows the connection diagram. SDI for device 1 is tied to ground, SDO of device 1 goes to SDI of device 2, and so on. SDO of the last device in the chain goes to the digital host. CONVST for all of the devices in the chain are tied together. In this mode there is no CS signal. The device SDO is driven low when SDI low selects daisy chain mode and the device samples the analog input and enters the conversion phase. It is necessary that SCLK is low at the rising edge of CONVST so that the device does not generate a busy indicator at the end of the conversion. In this mode CONVST continues to be high from the start of the conversion until all of the data bits are read. Once started, conversion continues irrespective of the state of SCLK. CNV CONVST SDI CONVST SDO SDI SDO SCLK SCLK Device 1 Device 2 SDI CLK Digital Host Figure 57. Connection Diagram, Daisy-Chain Mode Without Busy Indicator (SDI = 0) 24 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 ADS8319 www.ti.com SLAS600C – MAY 2008 – REVISED DECEMBER 2016 Device Functional Modes (continued) tcyc t6 CONVST tacq tcnv ACQUISITION ACQUISITION CONVERSION t7 tclkl t2 SCLK 1 2 tclk #1-D15 SDO #1, SDI #2 #1-D14 17 18 #1-D15 #1-D14 16 15 t8 32 31 tclkh #1-D1 #1-D0 #2-D1 #2-D0 t3 #2-D15 SDO #2 #2-D14 #1-D1 #1-D0 Figure 58. Interface Timing Diagram, Daisy-Chain Mode Without Busy Indicator At the end of the conversion, every device in the chain initiates output of its conversion data starting with the MSB bit. Further the next lower data bit is output on every falling edge of SCLK. While every device outputs its data on the SDO pin, it also receives previous device data on the SDI pin (other than device #1) and stores it in the shift register. The device latches incoming data on every falling edge of SCLK. SDO of the first device in the chain goes low after the 16th falling edge of SCLK. All subsequent devices in the chain output the stored data from the previous device in MSB first format immediately following their own data word. It requires 16 × N clocks to read data for N devices in the chain. 8.4.2.2 Daisy-Chain Mode With Busy Indicator Figure 59 shows the connection diagram. SDI for device 1 is wired to its CONVST and CONVST for all the devices in the chain are wired together. SDO of device 1 goes to SDI of device 2, and so on. SDO of the last device in the chain goes to the digital host. In this mode there is no CS signal. On the rising edge of CONVST, all of the device in the chain sample the analog input and enter the conversion phase. For the first device, SDI and CONVST are wired together, and the setup time of SDI to rising edge of CONVST is adjusted so that the device still enters chain mode even though SDI and CONVST rise together. It is necessary that SCLK is high at the rising edge of CONVST so that the device generates a busy indicator at the end of the conversion. In this mode, CONVST continues to be high from the start of the conversion until all of the data bits are read. Once started, conversion continues irrespective of the state of SCLK. CNV CONVST SDI CONVST SDO SDI IRQ SDO SCLK SCLK Device 1 Device 2 SDI CLK Digital Host Figure 59. Connection Diagram, Daisy-Mode With Busy Indicator (SDI = 0) Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 25 ADS8319 SLAS600C – MAY 2008 – REVISED DECEMBER 2016 www.ti.com Device Functional Modes (continued) tcyc t6 CONVST tacq tcnv ACQUISITION ACQUISITION CONVERSION t7 tclkl t2 1 SCLK 2 3 16 t8 SDO #1, SDI #2 17 18 19 32 33 #1-D15 #1-D14 #1-D1 #1-D0 tclk tclkh #1-D15 #1-D14 #1-D1 #1-D0 #2-D1 #2-D0 t3 SDO #2 #2-D15 #2-D14 Figure 60. Interface Timing Diagram, Daisy-Chain Mode With Busy Indicator At the end of the conversion, all the devices in the chain generate busy indicators. On the first falling edge of SCLK following the busy indicator bit, all of the devices in the chain output their conversion data starting with the MSB bit. After this the next lower data bit is output on every falling edge of SCLK. While every device outputs its data on the SDO pin, it also receives the previous device data on the SDI pin (except for device 1) and stores it in the shift register. Each device latches incoming data on every falling edge of SCLK. SDO of the first device in the chain goes high after the 17th falling edge of SCLK. All subsequent devices in the chain output the stored data from the pervious device in MSB first format immediately following their own data word. It requires 16 × N + 1 clock pulses to read data for N devices in the chain. 26 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 ADS8319 www.ti.com SLAS600C – MAY 2008 – REVISED DECEMBER 2016 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information To maximize the performance of data acquisition (DAQ) system based on a high precision, successive approximation register (SAR), analog-to-digital converter (ADC), the input driver and the reference driver circuits must be designed properly and must be optimized. This section details some general principles for designing these circuits, followed by an application circuit designed using the ADS8319. 9.2 Typical Application This section describes a typical application circuit using the ADS8319. For simplicity, the power-supply circuit and decoupling capacitors are not shown in this circuit diagram. Copyright © 2016, Texas Instruments Incorporated Figure 61. Unipolar Single-Ended Input DAQ System 9.2.1 Design Requirements This application circuit for ADS8319 (as shown in Figure 61) is designed to achieve the key specific performance at a maximum specified throughput of 500 kSPS below: • SNR > 92 dB • THD < 111 dB • Lower power consumption 9.2.2 Detailed Design Procedure The reference driver circuit illustrated in Figure 61 generates 5-V DC using a single supply. This circuit is suitable to drive the reference at sampling rates of up to 500 kSPS. To keep the noise low and maximize the dynamic range, a high-precision, low-noise REF5050 voltage reference is used in this DAQ system Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 27 ADS8319 SLAS600C – MAY 2008 – REVISED DECEMBER 2016 www.ti.com Typical Application (continued) For the input driver, the distortion of the amplifier must be at least 10 dB less than the ADC distortion. The lowpower feature of ADS8319 makes it suitable for a low power DAQ system design. The THS4281 (low-power, high-speed voltage-feedback operational amplifier) is a perfect choice for input and reference driver of ADS8319 to offer a very low quiescent current (less than 1 mA) across the supply and temperature and drive large capacitive loads that regulate the voltage at the input and reference input pins of the ADC, its high bandwidth (40 MHz, specified at gain of 2) can make the signal settle quickly, also the Rail-to-Rail input and output feature can maximize the dynamic range of ADC as a driver. Finally, the components of the balanced low-pass RC filter are chosen such that the noise from the front-end circuit is kept low without adding distortion to the input signal. For detailed design information, see Low Power Input and Reference Driver Circuit for Reference Driver Circuit for ADS8318 and ADS8319 (SBOA118). 9.2.3 Application Curves This section presents the performance results obtained on several devices for the driver and shown in Figure 62 through Figure 64. Table 2 summarizes the test results obtained for the circuit shown in Figure 61. Table 2. Performance Results for ADS8319 DAQ System ADS8319 DATA SHEET LIMITS ADS8319 WITH THS4031 DNLMAX PARAMETER < 1.5 0.54 ADS8319 WITH THS4281 0.65 DNLMin > –1 –0.5 –0.53 INLMAX < 2.5 0.62 0.83 INLMIN > –2.5 –0.95 –0.65 SNR >92 dB 93.9 dB 92.5 dB THD –111 (typical) –113 dB –113 dB SFDR 113 (typical) 115 dB 115 dB SINAD 93.8 (typical) 93.8 dB 92.4 dB — 205.6 mW 38.44 mW Circuit power consumption 1.9-kHz input signal Figure 62. FFT 28 Figure 63. Typical DNL Graph Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 ADS8319 www.ti.com SLAS600C – MAY 2008 – REVISED DECEMBER 2016 Figure 64. Typical INL Graph 10 Power Supply Recommendations The ADS8319 is designed to operate using an analog supply voltage from 4.5 V to 5.5 V and a digital supply voltage from 2.375 V to 5.5 V. Both supplies must be well regulated. The analog supply must always be greater than or equal to the digital supply. A 1-µF ceramic decoupling capacitor is required at each supply pin and must be placed as close as possible to the device. 11 Layout 11.1 Layout Guidelines Figure 65 shows one of the board layouts as an example when using ADS8319 in a circuit. • TI recommends a printed-circuit board (PCB) with at least four layers, and keeping all critical components on the top layer. • Analog input signals and the reference input signals must be kept away from noise sources. Crossing digital lines with the analog signal path must be avoided. The analog input and the reference signals are routed on to the left side of the board and the digital connections are routed on the right side of the device. • Due to the dynamic currents that occur during conversion and data transfer, each supply pin (AVDD and DVDD) must have a decoupling capacitor that keeps the supply voltage stable. TI recommends using one 1-µF ceramic capacitor at each supply pin. • A layout that interconnects the converter and accompanying capacitors with the low inductance path is critical for achieving optimal performance. Using 15-mil vias to interconnect components to a solid analog ground plane at the subsequent inner layer minimizes stray inductance. Avoid placing vias between the supply pin and the decoupling capacitor. Any inductance between the supply capacitor and the supply pin of the converter must be kept to less than 5 nH by placing the capacitor within 0.2 inches from the supply or input pins of the ADS8319 and by using 20-mil traces, as shown in Figure 65. • Dynamic currents are also present at the REFIN pin during the conversion phase. Therefore, good decoupling is critical to achieve optimal performance. The inductance between the reference capacitor and the REFIN pin must be kept to less than 2 nH by placing the capacitor within 0.1 inches from the REFIN pin and by using 20-mil traces. • TI recommends a single 10-µF, X7R-grade, 0805-size ceramic capacitor with at least a 10-V rating for good performance over temperature range. • A small, 0.1-Ω to 0.47-Ω, 0603-size resistor placed in series with the reference capacitor keeps the overall impedance low and constant, especially at very high frequencies. • Avoid using additional lower value capacitors because the interactions between multiple capacitors can affect the ADC performance at higher sampling rates. • Place the RC filters immediately next to the input pins. Among surface-mount capacitors, COG (NPO) ceramic capacitors provide the best capacitance precision. The type of dielectric used in COG (NPO) ceramic capacitors provides the most stable electrical properties over voltage, frequency, and temperature changes. Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 29 ADS8319 SLAS600C – MAY 2008 – REVISED DECEMBER 2016 www.ti.com R AVDD 11.2 Layout Example EF GND DVDD REF 1: REF Analog Input GND DVDD GND 1PF 1PF 0.1O t 0.47O AVDD 10PF GND 47O 10: DVDD 2: AVDD 9: SDI 3: AINP 8: SCLK 4: AINN 7: SDO 5: GND 6: CONVST 47O GND SDO 47O Figure 65. Board Layout Example 30 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 ADS8319 www.ti.com SLAS600C – MAY 2008 – REVISED DECEMBER 2016 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: Low Power Input and Reference Driver Circuit for Reference Driver Circuit for ADS8318 and ADS8319 (SBOA118) 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS8319 31 PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS8319IBDGSR ACTIVE VSSOP DGS 10 2500 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 CEN ADS8319IBDGST ACTIVE VSSOP DGS 10 250 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 CEN ADS8319IBDRCR ACTIVE VSON DRC 10 3000 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 CEP ADS8319IBDRCT ACTIVE VSON DRC 10 250 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 CEP ADS8319IDGSR ACTIVE VSSOP DGS 10 2500 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 CEN ADS8319IDGST ACTIVE VSSOP DGS 10 250 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 CEN ADS8319IDRCT ACTIVE VSON DRC 10 250 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 CEP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of