ADS8320EB/250

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents Reference Design ADS8320 SBAS108E – MAY 2000 – REVISED DECEMBER 2016 ADS8320 16-Bit, High-Speed, 2.7-V to 5-V microPower Sampling Analog-to-Digital Converter 1 Features 3 Description • • The ADS8320 device is a 16-bit, sampling analog-todigital (A/D) converter with ensured specifications over a 2.7-V to 5.25-V supply range. It requires very little power even when operating at the full 100-kHz data rate. At lower data rates, the high speed of the device enables it to spend most of its time in the power-down mode. The average power dissipation is less than 100 mW at 10-kHz data rate. 1 • • • • 100-kHz Sampling Rate microPower: – 1.8 mW at 100 kHz and 2.7 V – 0.3 mW at 10 kHz and 2.7 V Power Down: 3 µA (Maximum) 8-Pin VSSOP Package Pin-Compatible to ADS7816 and ADS7822 Serial (SPI™/SSI) Interface 2 Applications • • • • • • • Battery-Operated Systems Remote Data Acquisition Isolated Data Acquisition Simultaneous Sampling, Multichannel Systems Industrial Controls Robotics Vibration Analysis The ADS8320 also features operation from 2 V to 5.25 V, a synchronous serial (SPI/SSI compatible) interface, and a differential input. The reference voltage can be set to any level within the range of 500 mV to VCC. Ultra-low power and small size make the ADS8320 ideal for portable and battery-operated systems. It is also a perfect fit for remote data acquisition modules, simultaneous multi-channel systems, and isolated data acquisition. The ADS8320 is available in an 8-pin VSSOP package. Device Information(1) PART NUMBER ADS8320 PACKAGE VSSOP (8) BODY SIZE (NOM) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Block Diagram Control SAR VREF DOUT +In CDAC Serial Interface ±In S/H Amp Comparator DCLOCK CS/SHDN Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADS8320 SBAS108E – MAY 2000 – REVISED DECEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 6 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics: VCC = 5 V......................... Electrical Characteristics: VCC = 2.7 V...................... Typical Characteristics .............................................. Detailed Description ............................................ 11 7.1 Overview ................................................................. 11 7.2 Functional Block Diagram ....................................... 12 7.3 Feature Description................................................. 12 7.4 Device Functional Modes........................................ 13 8 Application and Implementation ........................ 16 8.1 Application Information............................................ 16 8.2 Typical Applications ................................................ 16 9 Power Supply Recommendations...................... 22 10 Layout................................................................... 22 10.1 Layout Guidelines ................................................. 22 10.2 Layout Example .................................................... 23 10.3 Power Dissipation ................................................. 23 11 Device and Documentation Support ................. 27 11.1 11.2 11.3 11.4 11.5 11.6 Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 27 27 27 27 27 27 12 Mechanical, Packaging, and Orderable Information ........................................................... 27 4 Revision History Changes from Revision D (March 2007) to Revision E Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 • Added Thermal Information table ........................................................................................................................................... 4 • Changed Application Circuits section To: Typical Connection Diagram .............................................................................. 11 2 Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: ADS8320 ADS8320 www.ti.com SBAS108E – MAY 2000 – REVISED DECEMBER 2016 5 Pin Configuration and Functions DGK Package 8-Pin VSSOP Top View VREF 1 +In 2 8 +VCC 7 DCLOCK ADS8320 ±In 3 6 DOUT GND 4 5 CS/SHDN Pin Functions PIN NO. NAME TYPE (1) DESCRIPTION 1 VREF AI Reference input 2 +In AI Noninverting input 3 –In AI Inverting input: Connect to ground or to remote ground sense point. 4 GND GND 5 CS/SHDN DI Chip select when LOW; Shutdown mode when HIGH. 6 DOUT DO The serial output data word is comprised of 16 bits of data. In operation the data is valid on the falling edge of DCLOCK. The second clock pulse after the falling edge of CS enables the serial output. After one null bit the data is valid for the next 16 edges. 7 DCLOCK DI Data clock synchronizes the serial data transfer and determines conversion speed. 8 +VCC PWR (1) Ground Power supply AI = Analog Input, DI = Digital Input, DO = Digital Output, GND = Ground, PWR = Power Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: ADS8320 3 ADS8320 SBAS108E – MAY 2000 – REVISED DECEMBER 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT 6 V VCC Analog input –0.3 VCC + 0.3 V Logic input –0.3 6 °C External reference voltage 5.5 V Input current to any pin except supply ±10 mA Case temperature 100 °C Junction temperature 150 °C Storage temperature, Tstg 125 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE Electrostatic discharge V(ESD) (1) (2) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN Low voltage levels Supply voltage, VCC to GND NOM MAX 2.7 3.3 5-V logic levels 4.75 –IN to GND –0.1 +IN to GND –0.1 VCC + 0.1 0 VREF –40 85 Reference input voltage, VREF 5 5.25 0.5 Analog input voltage +IN to – (–IN) Operating temperature, TA VCC 0 UNIT V V 0.5 V °C 6.4 Thermal Information ADS8320 THERMAL METRIC (1) DGK (VSSOP) UNIT 8 PINS RθJA Junction-to-ambient thermal resistance 163.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 56.6 °C/W RθJB Junction-to-board thermal resistance 83.4 °C/W ψJT Junction-to-top characterization parameter 6.7 °C/W ψJB Junction-to-board characterization parameter 82 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: ADS8320 ADS8320 www.ti.com SBAS108E – MAY 2000 – REVISED DECEMBER 2016 6.5 Electrical Characteristics: VCC = 5 V at –40°C to 85°C, VREF = 5 V, –IN = GND, fSAMPLE = 100 kHz, and fCLK = 24 × fSAMPLE (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RESOLUTION Resolution 16 Bits ANALOG INPUT Full-scale input span Absolute input +In – (–In) 0 VREF +In –0.1 VCC + 0.1 –In –0.1 1 Capacitance Leakage current V V 45 pF 1 nA SYSTEM PERFORMANCE No missing codes Integral linearity error Offset error ADS8320E 14 ADS8320EB 15 ADS8320E ±0.008% ±0.018% ADS8320EB ±0.006% ±0.012% ±1 ±2 ±0.5 ±1 ADS8320E ADS8320EB Offset temperature drift Gain error ±3 ADS8320E FSR mV µV/°C ±0.05% ADS8320EB FSR ±0.024% Gain error temperature drift Noise Power-supply rejection ratio Bits 4.7 V < VCC < 5.25 V ±0.3 ppm/°C 20 µVrms 3 LSB (1) SAMPLING DYNAMICS Conversion time 16 Acquisition time Clock Cycles 4.5 Throughput rate Clock frequency Clock Cycles 0.024 100 kHz 2.4 MHz DYNAMIC CHARACTERISTICS Total harmonic distortion VIN = 5 VP-P at 10 kHz SINAD VIN = 5 VP-P at 10 kHz Spurious-free dynamic VIN = 5 VP-P at 10 kHz SNR ADS8320E –84 ADS8320EB –86 ADS8320E 82 ADS8320EB 84 ADS8320E 84 ADS8320EB 86 ADS8320E 90 ADS8320EB 92 dB dB dB dB REFERENCE INPUT Voltage Resistance 0.5 VCC CS = GND, fSAMPLE = 0 Hz 5 CS = VCC 5 40 Current drain (1) fSAMPLE = 0 Hz 0.8 CS = VCC 0.1 V GΩ 80 µA 3 LSB means Least Significant Bit with VREF equal to 2.5 V, one LSB is 0.038 mV. Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: ADS8320 5 ADS8320 SBAS108E – MAY 2000 – REVISED DECEMBER 2016 www.ti.com Electrical Characteristics: VCC = 5 V (continued) at –40°C to 85°C, VREF = 5 V, –IN = GND, fSAMPLE = 100 kHz, and fCLK = 24 × fSAMPLE (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT Logic family Logic levels CMOS VIH IIH = 5 µA 3 VCC + 0.3 VIL IIL = 5 µA –0.3 0.8 VOH IOH = –250 µA VOL IOL = 250 µA 4 V 0.4 Data format Straight Binary POWER SUPPLY REQUIREMENTS VCC Specified performance 4.75 5.25 V 2 5.25 V VCC (2) Quiescent current 900 fSAMPLE = 10 kHz (3) (4) Power dissipation Power down (2) (3) (4) 1700 200 CS = VCC µA 4.5 8.5 mW 0.3 3 µA See Typical Characteristics for more information. fCLK = 2.4 MHz, CS = VCC for 216 clock cycles out of every 240. See Power Dissipation for more information regarding lower sample rates. 6.6 Electrical Characteristics: VCC = 2.7 V at –40°C to 85°C, VREF = 5 V, –IN = GND, fSAMPLE = 100 kHz, and fCLK = 24 × fSAMPLE (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RESOLUTION Resolution 16 Bits ANALOG INPUT Full-scale input span Absolute input +In – (–In) 0 VREF +In –0.1 VCC + 0.1 –In –0.1 0.5 Capacitance Leakage current V V 45 pF 1 nA SYSTEM PERFORMANCE No missing codes Integral linearity error Offset error ADS8320E 14 ADS8320EB 15 ADS8320E ±0.008% ±0.018% ADS8320EB ±0.006% ±0.012% ±1 ±2 ±0.5 ±1 ADS8320E ADS8320EB Offset temperature drift Gain error ±3 ADS8320E ADS8320EB ±0.024% Noise (1) 6 2.7 V < VCC < 3.3 V FSR mV µV/°C ±0.05% Gain error temperature drift Power-supply rejection ratio Bits FSR ±0.3 ppm/°C 20 ppm/°C 3 LSB (1) LSB means Least Significant Bit with VREF equal to 2.5 V, one LSB is 0.038 mV. Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: ADS8320 ADS8320 www.ti.com SBAS108E – MAY 2000 – REVISED DECEMBER 2016 Electrical Characteristics: VCC = 2.7 V (continued) at –40°C to 85°C, VREF = 5 V, –IN = GND, fSAMPLE = 100 kHz, and fCLK = 24 × fSAMPLE (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SAMPLING DYNAMICS Conversion time 16 Acquisition time Clock Cycles 4.5 Throughput rate Clock frequency Clock Cycles 0.024 100 kHz 2.4 MHz DYNAMIC CHARACTERISTICS Total harmonic distortion VIN = 2.7 VP-P at 1 kHz SINAD VIN = 2.7 VP-P at 1 kHz Spurious-free dynamic VIN = 2.7 VP-P at 1 kHz SNR ADS8320E –86 ADS8320EB –88 ADS8320E 84 ADS8320EB 86 ADS8320E 86 ADS8320EB 88 ADS8320E 88 ADS8320EB 90 dB dB dB dB REFERENCE INPUT Voltage 0.5 Resistance Current drain VCC CS = GND, fSAMPLE = 0 Hz 5 CS = VCC 5 20 50 CS = VCC 0.1 3 V GΩ µA DIGITAL INPUT/OUTPUT Logic Family Logic levels CMOS VIH IIH = 5 µA 2 VCC + 0.3 VIL IIL = 5 µA –0.3 0.8 VOH IOH = –250 µA VOL IOL = 250 µA 2.1 V 0.4 Data format Straight Binary POWER SUPPLY REQUIREMENTS VCC Specified performance VCC (2) Quiescent current See (3) (2) (3) (4) (5) 3.3 2 5.25 2 2.7 650 fSAMPLE = 10 kHz (4) (5) Power dissipation Power down 2.7 CS = VCC 1300 100 V V µA 1.8 3.8 mW 0.3 3 µA See Typical Characteristics for more information. The maximum clock rate of the ADS8320 is less than 2.4 MHz in this power supply range. fCLK = 2.4 MHz, CS = VCC for 216 clock cycles out of every 240. See Power Dissipation for more information regarding lower sample rates. Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: ADS8320 7 ADS8320 SBAS108E – MAY 2000 – REVISED DECEMBER 2016 www.ti.com 6.7 Typical Characteristics 3.0 2.0 2.0 0.0 Non Linearity (LSB) Integral Non Linearity (LSB) 1.0 ±1.0 ±2.0 ±3.0 ±4.0 1.0 0.0 ±1.0 ±2.0 ±5.0 ±6.0 0000H 4000H 8000H C000H ±3.0 0000H FFFFH 4000H 8000H Hex Code Hex Code Figure 1. Integral Non-Linearity (INL) vs Code (25°C) 600 500 5V Supply Current (nA) Supply Current (µA) 1000 800 2.7V 600 400 400 5V 300 200 100 200 0 0 ±50 0 ±25 25 50 75 100 ±50 0 ±25 Temperature (°C) 25 50 75 100 Temperature (°C) Figure 3. Supply Current vs Temperature Figure 4. Power-Down Supply Current Code (25°C) 1200 1000 1000 Sample Rate (kHz) Quiescent Current (µA) FFFFH Figure 2. Differential Non-Linearity Error vs Code (25°C) 1200 800 600 100 10 400 200 1 1 2 3 4 5 1 VCC (V) 2 3 4 5 VCC (V) Figure 5. Quiescent Current vs VCC 8 C000H Submit Documentation Feedback Figure 6. Maximum Sample Rate vs VCC Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: ADS8320 ADS8320 www.ti.com SBAS108E – MAY 2000 – REVISED DECEMBER 2016 Typical Characteristics (continued) 3 6 VCC = 5V 5 Delta from +25 C (LSB) Change in Offset (LSB) 2 4 3 2 1 0 ±1 1 5V 0 2.7V í1 í2 ±2 í3 ±3 1 2 3 Reference Voltage (V) 4 í50 5 0 í25 25 50 Temperature (°C) 75 100 Figure 8. Change In Offset vs Temperature Figure 7. Change In Offset vs Reference Voltage 5 6 VCC = 5V 4 Delta from 25°C (LSB) Change in Gain (LSB) 4 3 2 1 0 2 0 5V ±2 2.7V ±4 ±1 ±6 ±2 1 2 3 Reference Voltage (V) 4 ±50 5 0 25 50 75 100 Temperature (°C) Figure 9. Change In Gain Error vs Reference Voltage Figure 10. Change In Gain Error vs Temperature 10 0 VCC = 5V 9 Peak-to-Peak Noise (LSB) ±20 Amplitude (dB) ±25 ±40 ±60 ±80 ±100 ±120 8 7 6 5 4 3 2 1 0 ±140 0 10 20 30 Frequency (kHz) 40 50 Figure 11. Frequency Spectrum (8192 Point FFT, FIN = 10.120 kHz, –0.3 dB) 0.1 1 Reference Voltage (V) 10 Figure 12. Peak-to-Peak Noise vs Reference Voltage Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: ADS8320 9 ADS8320 SBAS108E – MAY 2000 – REVISED DECEMBER 2016 www.ti.com Typical Characteristics (continued) 0 100 Signal-to-Noise Ratio ±10 Total Harmonic Distortion (dB) Spurious-Free Dynamic Range and Signal-to-Noise Ratio (dB) 90 80 Spurious-Free Dynamic Range 70 60 50 40 30 20 ±20 ±30 ±40 ±50 ±60 ±70 ±80 10 ±90 0 ±100 1 10 Frequency (kHz) 50 1 100 Figure 13. Spurious-Free Dynamic Range and Signal-toNoise Ratio vs Frequency Signal-to-(Noise + Distortion) (dB) Signal-to-(Noise + Distortion) (dB) 90 90 80 70 60 50 40 30 20 10 1 10 Frequency (kHz) 50 80 70 60 50 40 30 20 ±40 0 100 Figure 15. Signal-to-(Noise + Distortion) vs Frequency 70 70 60 60 50 40 5V 30 20 2.7V ±35 ±30 ±25 ±20 ±15 Input Level (dB) ±10 0 ±5 Figure 16. Signal-to-(Noise + Distortion) vs Input Level Reference Current (µA) Reference Current (µA) 100 Figure 14. Total Harmonic Distortion vs Frequency 100 50 5V 40 30 2.7V 20 10 0 0 20 40 60 Sample Rate (kHz) 80 100 10 ±50 ±25 0 25 50 75 100 Temperature (°C) Figure 17. Reference Current vs Sample Rate 10 10 Frequency (kHz) Figure 18. Reference Current vs Temperature Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: ADS8320 ADS8320 www.ti.com SBAS108E – MAY 2000 – REVISED DECEMBER 2016 7 Detailed Description 7.1 Overview The ADS8320 device is a classic successive approximation register (SAR) analog-to-digital (A/D) converter. The architecture is based on capacitive redistribution, which inherently includes a sample and hold function. The converter is fabricated on a 0.6µm CMOS process. The architecture and process allow the ADS8320 to acquire and convert an analog signal at up to 100,000 conversions per second while consuming less than 4.5 mW from +VCC. The ADS8320 requires an external reference, an external clock, and a single power source (VCC). The external reference can be any voltage between 500 mV and VCC. The value of the reference voltage directly sets the range of the analog input. The reference input current depends on the conversion rate of the ADS8320. The external clock can vary between 24 kHz (1-kHz throughput) and 2.4 MHz (100-kHz throughput). The duty cycle of the clock is essentially unimportant, as long as the minimum high and low times are at least 200 ns (VCC = 2.7 V or greater). The minimum clock frequency is set by the leakage on the capacitors internal to the ADS8320. The analog input is provided to two input pins: +In and –In. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function. The digital result of the conversion is clocked out by the DCLOCK input and is provided serially, most significant bit first, on the DOUT pin. The digital data that is provided on the DOUT pin is for the conversion currently in progress—there is no pipeline delay. It is possible to continue to clock the ADS8320 after the conversion is complete and to obtain the serial data least significant bit first. See Device Functional Modes for more information. 7.1.1 Typical Connection Diagram Figure 19 shows a basic data acquisition system. The ADS8320 input range is 0 V to VCC, as the reference input is connected directly to the power supply. The 5-Ω resistor and 1-µF to 10-µF capacitor filter the microcontroller noise on the supply, as well as any high-frequency noise from the supply itself. The exact values must be picked such that the filter provides adequate rejection of the noise. +2.7 V to +5.25 V 5Ÿ + 1 µF to 10 µF ADS8320 VREF VCC +In CS ±In DOUT 0.1µF GND + 1 µF to 10 µF Microcontroller DCLOCK Copyright © 2016, Texas Instruments Incorporated Figure 19. Typical Connection Diagram With ADS8320 Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: ADS8320 11 ADS8320 SBAS108E – MAY 2000 – REVISED DECEMBER 2016 www.ti.com 7.2 Functional Block Diagram Control SAR VREF DOUT +In CDAC Serial Interface ±In S/H Amp DCLOCK CS/SHDN Comparator Copyright © 2016, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Analog Input The +In and –In input pins allow for a differential input signal. Unlike some converters of this type, the –In input is not resampled later in the conversion cycle. When the converter goes into the hold mode, the voltage difference between +In and –In is captured on the internal capacitor array. The range of the –In input is limited to –0.1 V to 1 V (–0.1 V to 0.5 V when using a 2.7-V supply). Because of this, the differential input can be used to reject only small signals that are common to both inputs. Thus, the –In input is best used to sense a remote signal ground that may move slightly with respect to the local ground potential. The input current on the analog inputs depends on a number of factors: sample rate, input voltage, source impedance, and power-down mode. Essentially, the current into the ADS8320 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (45 pF) to a 16-bit settling level within 4.5 clock cycles. When the converter goes into the hold mode or while it is in the power down mode, the input impedance is greater than 1 GΩ. Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the –In input must not drop below GND – 100 mV or exceed GND + 1 V. The +In input must always remain within the range of GND – 100 mV to VCC + 100 mV. Outside of these ranges, the converter linearity may not meet specifications. To minimize noise, low bandwidth input signals with lowpass filters must be used. 7.3.2 Reference Input The external reference sets the analog input range. The ADS8320 operates with a reference in the range of 500 mV to VCC. There are several important implications of this. As the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. This is often referred to as the Least Significant Bit (LSB) size and is equal to the reference voltage divided by 65,536. This means that any offset or gain error inherent in the A/D converter appears to increase, in terms of LSB size, as the reference voltage is reduced. The noise inherent in the converter also appears to increase with lower LSB size. With a 5-V reference, the internal noise of the converter typically contributes only 1.5-LSB peak-to-peak of potential error to the output code. When the external reference is 500 mV, the potential error contribution from the internal noise is 10 times larger (15 LSBs). The errors due to the internal noise are gaussian in nature and can be reduced by averaging consecutive conversion results. For more information regarding noise, see Figure 12. Note that the Effective Number of Bits (ENOB) figure is calculated based on the converter’s signal-to-(noise + distortion) ratio with a 1-kHz, 0-dB input signal. SINAD is related to ENOB as shown in Equation 1. 12 Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: ADS8320 ADS8320 www.ti.com SBAS108E – MAY 2000 – REVISED DECEMBER 2016 Feature Description (continued) SINAD = 6.02 × ENOB + 1.76 (1) With lower reference voltages, extra care must be taken to provide a clean layout including adequate bypassing, a clean power supply, a low-noise reference, and a low-noise input signal. Because the LSB size is lower, the converter is also more sensitive to external sources of error such as nearby digital signals and electromagnetic interference. 7.3.3 Noise The noise floor of the ADS8320 itself is extremely low, as can be seen from Figure 20 and Figure 21, and is much lower than competing A/D converters. It was tested by applying a low-noise DC input and a 5-V reference to the ADS8320 and initiating 5000 conversions. The digital output of the A/D converter varies in output code due to the internal noise of the ADS8320. This is true for all 16-bit SAR-type A/D converters. Using a histogram to plot the output codes, the distribution must appear bell-shaped with the peak of the bell curve representing the nominal code for the input value. The ±1σ, ±2σ, and ±3σ distributions represents the 68.3%, 95.5%, and 99.7%, respectively, of all codes. The transition noise can be calculated by dividing the number of codes measured by 6 and this yields the ±3σ distribution or 99.7% of all codes. Statistically, up to 3 codes could fall outside the distribution when executing 1000 conversions. The ADS8320, with < 3 output codes for the ±3σ distribution, yields a