ADS8323

ADS8323 ADS 832 ® 3 SBAS224B – DECEMBER 2001 – REVISED MAY 2002 16-Bit, 500kSPS, microPower Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES q q q q q HIGH-SPEED PARALLEL INTERFACE 500kSPS SAMPLING RATE LOW POWER: 85mW at 500kSPS BIPOLAR INPUT RANGE TQFP-32 PACKAGE DESCRIPTION The ADS8323 is a 16-bit, 500kSPS Analog-to-Digital Converter (ADC) with an internal 2.5V reference. The device includes a 16-bit capacitor-based SAR ADC with inherent sample-and-hold. The ADS8323 offers a full 16-bit interface, or an 8-bit option where data is read using two read cycles. The ADS8323 is available in a TQFP-32 package and is specified over the industrial –40°C to +85°C temperature range. APPLICATIONS q q q q HIGH-SPEED DATA AQUISITION OPTICAL POWER MONITORING MOTOR CONTROL ATE SAR Output Latches and Three State Drivers BYTE ADS8323 Parallel Data Output +IN CDAC –IN S/H Amp Comparator Conversion and Control Logic Internal +2.5V Ref CLOCK CONVST CS RD BUSY REFIN REFOUT Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001, Texas Instruments Incorporated www.ti.com PACKAGE/ORDERING INFORMATION MAXIMUM INTEGRAL LINEARITY ERROR (LSB) ±8 NO MISSING CODES ERROR (LSB) PACKAGE-LEAD 14 TQFP-32 SPECIFICATION TEMPERATURE RANGE –40°C to 85°C PRODUCT ADS8323Y PACKAGE DESIGNATOR(1) PBS ORDERING NUMBER ADS8323Y/250 ADS8323Y/2K ADS8323YB/250 ADS8323YB/2K TRANSPORT MEDIA, QUANTITY Tape and Reel, 250 Tape and Reel, 2000 Tape and Reel, 250 Tape and Reel, 2000 " ADS8323YB " ±6 " 15 " TQFP-32 " PBS " –40°C to 85°C " " " " " " NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings over operating free-air temperature (unless otherwise noted)(1) Supply Voltage, DGND to DVDD .............................................................. –0.3V to 6V Supply Voltage, AGND to AVDD ............................................................... –0.3V to 6V Analog Input Voltage Range ..................... AGND - 0.3V to AVDD + 0.3V Reference Input Voltage ........................... AGND - 0.3V to AVDD + 0.3V Digital Input Voltage Range ...................... DGND - 0.3V to DVDD + 0.3V Ground Voltage Differences, AGND to DGND ................................ ±0.3V Voltage Differences, DVDD to AGND ..................................... –0.3V to 6V Power Dissipation .......................................................................... 850mW Operating Virtual Junction Temperature Range, TJ ........ –40°C to 150°C Operating Free-Air Temperature Range, TA ...................... –40°C to 85°C Storage Temperature Range, TSTG .................................. –65°C to 150°C Lead Temperature 1.6mm (1/16 inch) from Case for 10sec ..................... 260°C NOTE: (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions of extended periods may affect device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. RECOMMENDED OPERATING CONDITIONS POWER SUPPLY Supply Voltage AVDD(1) DVDD(1) MIN 4.75 4.75 TYP 5.0 5.0 MAX 5.25 5.25 UNIT V V PACKAGE –REFIN 1.5 2.5 +REFIN 2.55 V V TQFP-32 DISSIPATION RATING TABLE TA ≤ 25°C POWER RATING 1636mW DERATING FACTOR ABOVE TA = 25°C(1) 13.09mW/°C TA = 70°C POWER RATING 1047mW TA = 85°C POWER RATING 850mW ANALOG/REFERENCE INPUTS Differential analog input voltage (IN+ to IN–) External Reference Voltage NOTE: (1) The voltage difference between AVDD and DVDD terminals cannot exceed 0.3V to maintain performance specifications. NOTE: (1) This is the inverse of the traditional junction-to-ambient thermal resistance (RθJA). Thermal resistances are not production tested and are for informational purposes only. EQUIVALENT INPUT CIRCUIT AVDD RON 20Ω AIN C(SAMPLE) 20pF DIN DVDD AGND Diode Turn-On Voltage: 0.35V Equivalent Analog Input Circuit DGND Equivalent Digital Input Circuit 2 ADS8323 www.ti.com SBAS224B ELECTRICAL CHARACTERISTICS At –40°C to +85°C, +DVDD = +AVDD = +5V, VREF = +2.5V, fSAMPLE = 500kSPS, and fCLK = 20 • fSAMPLE, unless otherwise specified. ADS8323Y PARAMETER RESOLUTION ANALOG INPUT Full-Scale Input Span(1) Absolute Input Range Capacitance Leakage Current SYSTEM PERFORMANCE No Missing Codes Integral Linearity Error Differential Linearity Error Offset Error Gain Error(3) Common-Mode Rejection Ratio Noise Power-Supply Rejection SAMPLING DYNAMICS Conversion Time Acquisition Time Throughput Rate Aperture Delay Aperture Jitter Small-Signal Bandwidth Step Response Overvoltage Recovery DYNAMIC CHARACTERISTICS Total Harmonic Distortion(4) SINAD Spurious-Free Dynamic Range REFERENCE OUTPUT Voltage Source Current Drift Line Regulation REFERENCE INPUT Range DIGITAL INPUT/OUTPUT Logic Family Logic Levels: VIH VIL VOH VOL Data Format POWER-SUPPLY REQUIREMENT Power-Supply Voltage +AVDD +DVDD Supply Current Power Dissipation TEMPERATURE RANGE Specified Performance ✻ Specifications same as ADS8323Y. NOTES: (1) Ideal input span; does not include gain or offset error. (2) LSB means Least Signifcant Bit, with VREF equal to +2.5V; 1LSB = 76µV. (3) Measured relative to an ideal, full-scale input (+In – (–In)) of 4.9999V. Thus, gain error includes the error of the internal voltage reference. (4) Calculated on the first nine harmonics of the input frequency. VIN = 5Vp-p at 100kHz VIN = 5Vp-p at 100kHz VIN = 5Vp-p at 100kHz IOUT = 0 Static Load IOUT = 0 4.75V ≤ VCC ≤ 5.25V 2.475 14 ±4 ±3 ±1 ±0.25 70 50 60 ±3 1.6 0.4 500 10 30 20 100 150 –90 81 94 2.50 25 0.6 1.5 CMOS IIH ≤ +5µA IIL ≤ –5µA IOH = –1.6mA IOL = +1.6mA 3.0 –0.3 4.0 +DVDD 0.8 ✻ ✻ ✻ 2.55 ✻ ✻ ✻ ✻ ✻ ✻ V V V V 2.525 10 2.48 ✻ ✻ ✻ ✻ ✻ –93 83 96 ✻ ✻ ✻ ✻ 2.52 ✻ ±8 ±2 ±0.5 +IN – (–IN) +IN –IN –VREF –0.3 –0.3 25 ±1 15 ±3 ±1 ±0.5 ±0.12 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ±6 ±1 ±0.25 CONDITIONS MIN TYP MAX 16 +VREF AVDD + 0.3 AVDD + 0.3 ✻ ✻ ✻ ✻ ✻ MIN ADS8323YB TYP MAX ✻ ✻ ✻ ✻ UNITS Bits V V V pF nA Bits LSB(2) LSB mV % of FSR dB dB µVrms LSB µs µs kSPS ns ps MHz ns ns dB dB dB V µA ppm/°C mV V At DC VIN = 1Vp-p at 1MHz At FFFFH Output Code 0.4 Binary Two’s Complement 4.75 4.75 fSAMPLE = 500kSPS fSAMPLE = 500kSPS –40 5 5 17 85 5.25 5.25 25 125 +85 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ V V mA mW °C ✻ ADS8323 SBAS224B www.ti.com 3 TIMING CHARACTERISTICS(1)(2) All specifications typical at –40°C to +85°C, +DVDD = +5V. ADS8323Y PARAMETER Conversion Time Acquisition Time CLOCK Period CLOCK HIGH Time CLOCK LOW Time CONVST LOW to CLOCK HIGH CONVST LOW Time CONVST LOW to BUSY HIGH CS LOW to CONVST LOW CONVST HIGH CLOCK HIGH to BUSY LOW CS HIGH CS LOW to RD LOW RD HIGH to CS HIGH RD LOW Time RD LOW to Data Valid Data Hold from RD HIGH BYTE Change to RD LOW(3) RD HIGH Time SYMBOL tCONV tACQ tC1 tW1 tW2 tD1 tW3 tD2 tD3 tW4 tD4 tW5 tD5 tD6 tW6 tD7 tD8 tD9 tW7 MIN TYP MAX 1.6 0.4 100 40 40 10 20 25 0 20 25 0 0 0 50 40 5 0 20 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ MIN ADS8323YB TYP MAX ✻ ✻ UNITS µs µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES: (1) All input signals are specified with rise and fall times of 5ns, tR = tF = 5ns (10% to 90% of DVDD), and timed from a voltage level of (VIL + VIH) /2. (2) See timing diagram, below. (3) BYTE is asynchronous; when BYTE is 0, bits 15 through 0 appear at DB15-DB0. When BYTE is 1, bits 15 through 8 appear on DB7-DB0. RD may remain LOW between changes in BYTE. TIMING DIAGRAM tC1 tW2 tW1 CLOCK Acquisition 1 2 3 4 Conversion tCONV 5 17 18 19 20 1 2 3 4 17 18 19 20 Acquisition tACQ tD1 CONVST tW3 tW4 BUSY tD2 tD4 BYTE tD3 CS tD5 RD tD7 tW6 tD8 tD6 tW5 tD9 tW7 DB15-D8 Bits 15-8 Bits 15-8 FF DB7-D0 Bits 7-0 Bits 7-0 Bits 15-8 4 ADS8323 www.ti.com SBAS224B PIN CONFIGURATION Top View TQFP REFOUT +AVDD AGND REFIN +IN 32 31 30 29 28 27 26 25 –IN NC NC DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 1 2 3 4 ADS8323 5 6 7 8 9 DB7 24 CS 23 BYTE 22 RD 21 CONVST 20 CLOCK 19 DGND 18 +DVDD 17 BUSY 10 DB6 11 DB5 12 DB4 13 DB3 14 DB2 15 DB1 16 DB0 PIN ASSIGNMENTS PIN 1 2 3 4 5 6 3 8 9 10 11 12 13 14 15 16 17 18 NAME DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BUSY +DVDD I/O DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO P DESCRIPTION Data Bit 15 - MSB Data Bit 14 Data Bit 13 Data Bit 12 Data Bit 11 Data Bit 10 Data Bit 9 Data Bit 8 Data Bit 7 Data Bit 6 Data Bit 5 Data Bit 4 Data Bit 3 Data Bit 2 Data Bit 1 Data Bit 0 - LSB HIGH when a conversion is in progress. Digital Power Supply, +5VDC. PIN 19 20 NAME DGND CLOCK I/O P DI DESCRIPTION Digital Ground An external CMOS compatible clock can be applied to the CLOCK input to synchronize the conversion process to an external source. Convert Start, Active LOW. Synchronization pulse for the parallel output, Active LOW. Selects 8 most significant bits (LOW) or 8 least significant bits (HIGH). Data valid on pins 9-16. Chip Select, Active LOW. Inverting Input Channel Noninverting Input Channel Analog Ground Analog Power Supply, +5VDC. No Connect No Connect Reference Input. When using the internal 2.5V reference tie this pin directly to REFOUT. Reference Output 21 22 23 24 25 26 27 28 29 30 31 32 CONVST RD BYTE CS –IN +IN AGND +AVDD NC NC REFIN REFOUT DI DI DI DI AI AI P P — — AI AO NOTE: AI is Analog Input, AO is Analog Output, DI is Digital Input, DO is Digital Output, and P is Power-Supply Connection. ADS8323 SBAS224B www.ti.com 5 TYPICAL CHARACTERISTICS At –40°C to +85°C, +DVDD = +AVDD = +5V, VREF = +2.5V, fSAMPLE = 500kSPS, and fCLK = 20 • fSAMPLE, unless otherwise specified. SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-(NOISE+DISTORTION) vs INPUT FREQUENCY 90 FREQUENCY SPECTRUM (4096 Point FFT; fIN = 100.1kHz, –0.2dB) 0 –30 SNR, SINAD (dB) Amplitude (dB) –50 –70 –90 –110 –130 0 25 50 75 100 125 150 175 200 225 250 Frequency (kHz) 85 SNR 80 SINAD 75 1 10 Frequency (kHz) 100 250 SPURIOUS-FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY 100 –100 INL+ vs TEMPERATURE 0.3 22.9 95 –95 0.2 15.3 SFDR (dB) THD (dB) SFDR THD 85 –85 0.1 7.6 80 –80 0 0 75 1 10 Frequency (kHz) 100 250 –75 –0.1 –40 –7.6 –20 0 20 40 Temperature (°C) 60 80 100 INL– vs TEMPERATURE 0.05 3.8 0.25 DNL+ vs TEMPERATURE 19.1 0 Delta (LSB) 0 Delta (LSB) 0.15 11.4 –0.05 –3.8 Delta (µV) 0.05 3.8 –0.10 –7.6 –0.05 –3.8 –0.15 –11.4 –0.20 –40 –20 0 20 40 Temperature (°C) 60 80 –15.3 100 –0.15 –40 –11.4 –20 0 20 40 Temperature (°C) 60 80 100 6 ADS8323 www.ti.com SBAS224B Delta (µV) Delta (µV) 90 –90 Delta (LSB) TYPICAL CHARACTERISTICS (Cont.) At –40°C to +85°C, +DVDD = +AVDD = +5V, VREF = +2.5V, fSAMPLE = 500kSPS, and fCLK = 20 • fSAMPLE, unless otherwise specified. DNL– vs TEMPERATURE 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –40 45.8 30.5 15.3 10 8 6 4 2 0 –2 –40 GAIN ERROR vs TEMPERATURE 762.9 610.4 457.8 305.2 152.6 0 –152.6 –20 0 20 40 Temperature (°C) 60 80 100 Delta (LSB) Delta (LSB) Delta (µV) 0 –15.3 –30.5 –45.8 100 –20 0 20 40 Temperature (°C) 60 80 VREF vs TEMPERATURE 2.0 1.0 0.0 –1.0 26.2 13.1 0 –13.1 IQ vs TEMPERATURE 0.8 0.4 Delta (LSB) Delta (mV) –2.0 –3.0 –4.0 –5.0 –6.0 –7.0 –8.0 –40 –20 0 20 40 60 80 100 Temperature (°C) –26.2 –39.3 –52.4 –65.5 –78.6 –91.8 –104.9 Delta (mA) 0 –0.4 –0.8 –1.2 –40 –20 0 20 40 Temperature (°C) 60 80 100 BIPOLAR ZERO vs TEMPERATURE 1.4 1 0.6 0.2 –0.2 –0.6 –1 –40 106.8 76.3 45.8 Delta (µV) 5.4 4.4 3.4 2.4 1.4 0.4 –0.6 –40 POSITIVE FULL-SCALE vs TEMPERATURE 412.0 335.7 253.4 183.1 106.8 30.5 –45.8 –20 0 20 40 Temperature (°C) 60 80 100 Delta (LSB) Delta (LSB) 15.3 –15.3 –45.8 –76.3 100 –20 0 20 40 Temperature (°C) 60 80 ADS8323 SBAS224B www.ti.com 7 Delta (µV) Delta (µV) TYPICAL CHARACTERISTICS (Cont.) At –40°C to +85°C, +DVDD = +AVDD = +5V, VREF = +2.5V, fSAMPLE = 500kSPS, and fCLK = 20 • fSAMPLE, unless otherwise specified. NEGATIVE FULL-SCALE vs TEMPERATURE 1 0 –1 –2 –3 –4 –5 –40 76.3 0 –76.3 –152.6 –228.9 –305.2 –381.5 100 4 3 2 1 0 –1 –2 –3 –4 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE Delta (LSB) Delta (µV) INL (LSB) DNL (LSB) –20 0 20 40 Temperature (°C) 60 80 2.5 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Decimal Code THEORY OF OPERATION The ADS8323 is a high-speed Successive Approximation Register (SAR) 16-bit ADC with an internal 2.5V bandgap reference that operates from a single +5V supply. The input is fully differential with a typical common-mode rejection of 70dB. The part accepts a differential analog input voltage in the range of –VREF to +VREF, centered on the common-mode voltage (see the Analog Input section). The part will also accept bipolar input ranges when a level shift circuit is used at the front end (see Figure 7). See Figure 1 for the basic operating circuit for the ADS8323. The ADS8323 requires an external clock to run the conversion process. This clock can vary between 25kHz (1.25kHz throughput) and 10MHz (500kSPS throughput). The duty cycle of the clock is unimportant as long as the minimum HIGH and LOW times are at least 40ns and the clock period is at least 100ns. The minimum clock frequency is governed by the parasitic leakage of the Capacitive Digital-to-Analog Converter (CDAC) capacitors internal to the ADS8323. The analog input is provided to two input pins, +IN and –IN. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. A conversion is initiated on the ADS8323 by bringing CONVST (pin 21) LOW for a minimum of 20ns. CONVST LOW places the sample-and-hold amplifier in the hold state and the conversion process is started. The BUSY output (pin 17) will go HIGH when the conversion begins and will stay HIGH during the conversion. While a conversion is in progress, both inputs are disconnected from any internal function. When the conversion result is latched into the output register, the BUSY signal will go LOW. The data can be read from the parallel output bus following the conversion by bringing both RD and CS LOW. NOTE: This mode of operation is described in more detail in the Timing and Control section of this data sheet. SAMPLE-AND-HOLD SECTION The sample-and-hold on the ADS8323 allow the ADC to accurately convert an input sine wave of full-scale amplitude to 16-bit resolution. The input bandwidth of the sample-andhold is greater than the Nyquist rate (Nyquist equals one-half of the sampling rate) of the ADC even when the ADC is operated at its maximum throughput rate of 500kSPS. The typical small-signal bandwidth of the sample-and-hold amplifier is 20MHz. Typical aperture delay time, or the time it takes for the ADS8323 to switch from the sample to the hold mode following the negative edge of the CONVST signal, is 10ns. The average delta of repeated aperture delay values is typically 30ps (also known as aperture jitter). These specifications reflect the ability of the ADS8323 to capture AC input signals accurately at the exact same moment in time. REFERENCE If the internal reference is used, REFOUT (pin 32) should be directly connected to REFIN (pin 31). The ADS8323 can operate, however, with an external reference in the range of 1.5V to 2.55V for a corresponding full-scale range of 3.0V to 5.1V. The internal reference of the ADS8323 is doublebuffered. If the internal reference is used to drive an external load, a buffer is provided between the reference and the load applied to REFOUT (pin 32) (the internal reference can typically source or sink 10µA of current; compensation capacitance should be at least 0.1µF to minimize noise). If an external reference is used, the second buffer provides isolation between the external reference and the CDAC. This buffer is also used to recharge all of the capacitors of the CDAC during conversion. 8 ADS8323 www.ti.com SBAS224B +5V Analog Supply 10µF + 0.1µF 0.1µF + 20pF – Analog Input 32 31 30 29 28 27 26 25 NC NC REFIN REFOUT +AVDD AGND IN+ IN– 1 2 3 4 5 6 7 8 DB15 DB14 DB13 DB12 CS 24 BYTE 23 RD 22 CONVST 21 ADS8323 CLOCK 20 DGND 19 +DVDD 18 BUSY 17 Chip Select Read Input Conversion Start Clock Input DB11 DB10 DB9 DB8 Busy Output DB7 DB6 DB5 DB4 DB3 DB2 DB1 15 9 10 11 12 13 14 16 FIGURE 1. Typical Circuit Configuration. ANALOG INPUT The analog input is bipolar and fully differential. There are two general methods of driving the analog input of the ADS8323: single-ended or differential, as shown in Figures 2 and 3. When the input is single-ended, the –IN input is held at the common-mode voltage. The +IN input swings around the same common voltage and the peak-to-peak amplitude is the (common-mode + VREF) and the (common-mode – VREF). The value of VREF determines the range over which the common-mode voltage may vary (see Figure 4). –VREF to +VREF peak-to-peak Common Voltage Single-Ended Input ADS8323 VREF peak-to-peak Common Voltage ADS8323 VREF peak-to-peak Differential Input FIGURE 2. Methods of Driving the ADS8323 either SingleEnded or Differential. ADS8323 SBAS224B DB0 When the input is differential, the amplitude of the input is the difference between the +IN and –IN input, or (+IN) – (–IN). The peak-to-peak amplitude of each input is ±1/2VREF around this common voltage. However, since the inputs are 180° out-of-phase, the peak-to-peak amplitude of the differential voltage is +VREF to –VREF. The value of VREF also determines the range of the voltage that may be common to both inputs (see Figure 5). In each case, care should be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are matched. If matching is not observed, it may result in offset error, which changes with temperature. Often, a small capacitor (20pF) between the positive and negative inputs helps to match their impedance. The input current on the analog inputs depends on a number of factors: sample rate, input voltage, and source impedance. Essentially, the current into the ADS8323 charges the internal capacitor array during the sampling period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (25pF) to a 16-bit settling level within 4 clock cycles (400ns), if the minimum acquisition time is used. When the converter goes into the hold mode, the input impedance is greater than 1GΩ. Care must be taken regarding the absolute analog input voltage. The +IN and –IN inputs should always remain within the range of AGND – 0.3V to AVDD + 0.3V. www.ti.com 9 CM + VREF +VREF CM Voltage +IN –IN = CM Voltage –VREF CM – VREF t Single-Ended Inputs +IN CM + 1/2VREF CM Voltage CM – 1/2VREF –IN +VREF –VREF t Differential Inputs (+IN) + (–IN) , Common-Mode Voltage (Single-Ended Mode) = IN–. 2 The maximum differential voltage between +IN and –IN of the ADS8323 is VREF. See Figures 4 and 5 for a further explanation of the common voltage range for single-ended and differential inputs. NOTES: Common-Mode Voltage (Differential Mode) = FIGURE 3. Using the ADS8323 in the Single-Ended and Differential Input Modes. 5 AVDD = 5V 4 3.8 5 4.55 4 AVDD = 5V 4.025 Common Voltage Range (V) 3 Common Voltage Range (V) Single-Ended Input 2.75 2.25 3 Differential Input 2 2 1 1.2 1 0.45 0 0.975 0 –1 1.0 1.5 2.0 VREF (V) 2.55 2.5 3.0 –1 1.0 1.5 2.0 VREF (V) 2.55 2.5 3.0 FIGURE 4. Single-Ended Input: Common-Mode Voltage Range vs VREF. FIGURE 5. Differential Input: Common-Mode Voltage Range vs VREF. 10 ADS8323 www.ti.com SBAS224B NOISE Figure 6 shows the transition noise of the ADS8323. A lowlevel DC input was applied to the analog-input pins and the converter was put through 8192 conversions. The digital output of the ADC will vary in output code due to the internal noise of the ADS8323. This is true for all 16-bit SAR-type ADCs. The ADS8323, with five output codes for the σ distribution, will yield a < ±0.8LSB transition noise at 5V operation. Remember that to achieve this low-noise performance, the peak-to-peak noise of the input signal and reference must be < 50µV. 5052 4kΩ 20kΩ R1 OPA132 +IN (pin 26) –IN (pin 25) Bipolar Input R2 OPA353 BIPOLAR INPUT ±10V ±5V ±2.5V R1 1kΩ 2kΩ 4kΩ R2 5kΩ 10kΩ 20kΩ ADS8323 REFOUT (pin 32) 2.5V FIGURE 7. Level Shift Circuit for Bipolar Input Ranges. DIGITAL INTERFACE 1968 818 54 0014 300 TIMING AND CONTROL See the timing diagram in the Timing Characteristics section for detailed information on timing signals and their requirements. The ADS8323 uses an external clock (CLOCK, pin 20) that controls the conversion rate of the CDAC. With a 10MHz external clock, the ADC sampling rate is 500kSPS that corresponds to a 2µs maximum throughput time. 0015 0016 Code 0017 0018 FIGURE 6. Histogram of 8192 Conversions of a Low-Level DC Input. EXPLANATION OF CLOCK, BUSY AND BYTE PINS CLOCK—An external clock must be provided for the ADS8323. The maximum clock frequency is 10MHz and that provides 500kSPS throughput. The minimum clock frequency is 25kHz and that provides 1.25kHz throughput. The minimum clock cycle is 100ns (see Timing Diagram, tC1), and CLOCK must remain HIGH (see Timing Diagram, tW1) or LOW (see Timing Diagram, tW2) for at least 40ns. BUSY—Initially BUSY output is LOW. Reading data from output register or sampling the input analog signal will not affect the state of the BUSY signal. After the CONVST input goes LOW and conversion starts, a maximum of 25ns later the BUSY output will go HIGH. That signal will stay HIGH during conversion and will provide the status of the internal ADC to the DSP or uC. At the end of conversion, on the rising edge of 17th clock cycle, new data from the internal ADC is latched into the output registers. The BUSY signal will go LOW a maximum of 25ns later (see Timing Diagram, tD4). BYTE—The output data will appear as a full 16-bit word on DB15-DB0 (MSB-LSB or D15-D0) if BYTE is LOW. If there is only an 8-bit bus available on a board, the result may also be read on an 8-bit bus by using only DB7-DB0. In this case, two reads are necessary (see Timing Diagram). The first, as before, leaving BYTE LOW and reading the 8 least significant bits on DB7-DB0, then bringing BYTE HIGH. When BYTE is HIGH, the upper 8 bits (D15-D8) will appear on DB7-DB0. AVERAGING Averaging the digital codes can compensate the noise of the ADC. By averaging conversion results, transition noise will be reduced by a factor of 1/√n, where n is the number of averages. For example, averaging 4 conversion results will reduce the transition noise by 1/2 to ±0.4LSB. Averaging should only be used for input signals with frequencies near DC. For AC signals, a digital filter can be used to low-pass filter and decimate the output codes. This works in a similar manner to averaging—for every decimation by 2, the signal-to-noise ratio will improve 3dB. BIPOLAR INPUTS The differential inputs of the ADS8323 were designed to accept bipolar inputs (–VREF and +VREF) around the common-mode voltage, which corresponds to a 0V to 5V input range with a 2.5V reference. By using a simple op amp circuit featuring four high-precision external resistors, the ADS8323 can be configured to accept bipolar inputs. The conventional ±2.5V, ±5V, and ±10V input ranges could be interfaced to the ADS8323 using the resistor values shown in Figure 7. ADS8323 SBAS224B www.ti.com 11 START OF A CONVERSION AND READING DATA By bringing the CONVST signal LOW, the input data is immediately placed in the hold mode (10ns). Although CS must be LOW when CONVST goes LOW to initiate a conversion. The conversion follows with the next rising edge of CLOCK. If it is important to detect a hold command during a certain clock cycle, then the falling edge of the CONVST signal must occur at least 10ns before the rising edge of CLOCK (see Timing Diagram, tD1). The CONVST signal can remain LOW without initiating a new conversion. The CONVST signal must be HIGH for at least 20ns (see Timing Diagram, tW4) before it is brought LOW again and CONVST must stay LOW for at least 20ns (see Timing Diagram, tW3). Once a CONVST signal goes LOW, further impulses of this signal are ignored until the conversion is finished or the part is reset. When the conversion is finished (after 16 clock cycles) the sampling switches will close and sample the new value. The start of the next conversion must be delayed to allow the input capacitor of the ADS8323 to be fully charged. This delay time depends on the driving amplifier, but should be at least 400ns. To gain acquisition time, the falling edge of CONVST must take place just before the rising edge of CLOCK (see Timing Diagram, tD1). One conversion cycle requires 20 clock cycles. However, reading data during the conversion or on a falling hold edge might cause a loss in performance. Reading Data (RD, CS)—In general, the data outputs are in tri-state. Both CS and RD must be LOW to enable these outputs. RD and CS must stay LOW together for at least 40ns (see Timing Diagram, tD7) before the output data is valid. RD must remain HIGH for at least 20ns (see Timing Diagram, tW7) before bringing it back LOW for a subsequent read command. 16 clock-cycles after the start of a conversion (next rising edge of clock after the falling edge of CONVST), the new data is latched into the output register and the reading process can start again. CS being LOW tells the ADS8323 that the bus on the board is assigned to the ADS8323. If an ADC shares a bus with digital gates, there is a possibility that digital (high-frequency) noise gets coupled into the ADC. If the bus is just used by the ADS8323, CS can be hard-wired to ground. The output data should not be read 125ns prior to the falling edge of CONVST and 10ns after the falling edge. The ADS8323’s output is in Binary Two’s Complement format (see Figure 8). DESCRIPTION Full-Scale Range Least Significant Bit (LSB) +Full Scale Midscale Midscale – 1LSB Zero ANALOG VALUE 2 • VREF 2 • VREF/65535 BINARY CODE +VREF – 1 LSB 0V 0V – 1 LSB –VREF 0111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 1000 0000 0000 0000 HEX CODE 7FFF 0000 FFFF 8000 LAYOUT For optimum performance, care should be taken with the physical layout of the ADS8323 circuitry. This is particularly true if the CLOCK input is approaching the maximum throughput rate. As the ADS8323 offers single-supply operation, it will often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it will be to achieve good performance from the converter. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. Thus, during any single conversion for an n-bit SAR converter, there are n “windows” in which large external transient voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, or high-power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. Their error can change if the external event changes in time with respect to the CLOCK input. On average, the ADS8323 draws very little current from an external reference as the reference voltage is internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive the bypass capacitor or capacitors without oscillation. A 0.1µF bypass capacitor is recommended from pin 31 directly to ground. The AGND and DGND pins should be connected to a clean ground point. In all cases, this should be the “analog” ground. Avoid connections which are too close to the grounding point of a microcontroller or digital signal processor. If required, run a ground trace directly from the converter to the powersupply entry point. The ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry. As with the GND connections, VDD should be connected to a +5V power supply plane, or trace, that is separate from the connection for digital logic until they are connected at the power entry point. Power to the ADS8323 should be clean and well bypassed. A 0.1µF ceramic bypass capacitor should be placed as close to the device as possible. In addition, a 1µF to 10µF capacitor is recommended. If needed, an even larger capacitor and a 5Ω or 10Ω series resistor may be used to low-pass filter a noisy supply. In some situations, additional bypassing may be required, such as a 100µF electrolytic capacitor, or even a Pi filter made up of inductors and capacitors all designed to essentially low-pass filter the +5V supply, removing the high-frequency noise. DIGITAL OUTPUT BINARY TWO’S COMPLEMENT TABLE I. Ideal Input Voltages and Output Codes. 12 ADS8323 www.ti.com SBAS224B Binary Two’s Complement BTC 0111 1111 1111 1111 0111 1111 1111 1110 0111 1111 1111 1101 65535 65534 65533 Digital Output Code 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 32769 32768 32767 1000 0000 0000 0010 2 1000 0000 0000 0001 1 0 1000 0000 0000 0000 VNFS = VCM – VREF = 0V 0.000038V 0.000076V 0.000152V 16-BIT 2.499962V 2.500038V VBPZ = 2.5V VPFS = VCM + VREF = 5V VPFS – 1LSB = 4.999924V 4.999848V 1LSB = 76µV VCM = 2.5V VREF = 2.5V Unipolar Analog Input Voltage Bipolar Input, Binary Two’s Complement Output: (BTC) Negative Full-Scale Code = VNFS = 8000H, Vcode = VCM – VREF Bipolar Zero Code = VBPZ = 0000H, Vcode = VCM Positive Full-Scale Code = VPFS = 7FFFH, Vcode = (VCM + VREF) – 1LSB FIGURE 8. Ideal Conversion Characteristics (Condition: Single-Ended. VCM = IN– = 2.5V, VREF = 2.5V). ADS8323 SBAS224B Step www.ti.com 13 PACKAGE DRAWING PBS (S-PQFP-G32) 0,23 0,17 24 17 MPQF027 – NOVEMBER 1995 PLASTIC QUAD FLATPACK 0,50 0,08 M 25 16 32 9 0,13 NOM 1 3,50 TYP 5,05 SQ 4,95 7,10 SQ 6,90 1,05 0,95 8 Gage Plane 0,25 0,10 MIN 0,70 0,40 0°– 7° Seating Plane 1,20 MAX 0,08 4087735/A 11/95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. 14 ADS8323 www.ti.com SBAS224B PACKAGE OPTION ADDENDUM www.ti.com 9-Dec-2004 PACKAGING INFORMATION Orderable Device ADS8323Y/250 ADS8323Y/2K ADS8323YB/250 ADS8323YB/2K (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE Package Type TQFP TQFP TQFP TQFP Package Drawing PBS PBS PBS PBS Pins Package Eco Plan (2) Qty 32 32 32 32 250 2000 250 2000 None None None None Lead/Ball Finish CU SNPB CU SNPB CU SNPB CU SNPB MSL Peak Temp (3) Level-3-220C-168 HR Level-3-220C-168 HR Level-3-220C-168 HR Level-3-220C-168 HR The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. 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