ADS8329IBRSATG4

Burr Brown Products from Texas Instruments ADS8329 ADS8330 SLAS516 – DECEMBER 2006 LOW POWER, 16-BIT, 1-MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE FEATURES • • • 2.7-V to 5.5-V Analog Supply, Low Power: – 15.5 mW (1 MHz, +VA = 3 V, +VBD = 1.8 V) 1-MHz Sampling Rate 3 V ≤ +VA ≤ 5.5 V, 900-kHz Sampling Rate 2.7 V ≤ +VA ≤ 3 V Excellent DC Performance – ±1.0 LSB Typ, ±1.75 LSB Max INL – ±0.5 LSB Typ, ±1 LSB Max DNL – 16-Bit NMC Over Temperature – ±0.5 mV Max Offset Error at 3 V – ±1 mV Max Offset Error at 5 V Excellent AC Performance at fi = 100 kHz with 92 dB SNR, 102 dB SFDR, –102 dB THD Built-In Conversion Clock (CCLK) 1.65 V to 5.5 V I/O Supply – SPI/DSP Compatible Serial – SCLK up to 50 MHz Comprehensive Power-Down Modes: – Deep Powerdown – Nap Powerdown – Auto Nap Powerdown Unipolar Input Range: 0 V to Vref Software Reset Global CONVST (Independent of CS) Programmable Status/Polarity EOC/INT 16-Pin 4 x 4 QFN Package Multi-Chip Daisy Chain Mode Programmable TAG Bit Output Auto/Manual Channel Select Mode (ADS8330) APPLICATIONS • • • • • • • Communications Transducer Interface Medical Instruments Magnetometers Industrial Process Control Data Acquisition Systems Automatic Test Equipment DESCRIPTION The ADS8329 is a low power, 16-bit, 1-MSPS analog-to-digital converter with a unipolar input. The device includes a 16-bit capacitor-based SAR A/D converter with inherent sample and hold. The ADS8330 is based on the same core and includes a 2-to-1 input MUX with programmable option of TAG bit output. Both the ADS8329 and ADS8330 offer a high-speed, wide voltage serial interface and are capable of chain mode operation when multiple converters are used. These converters are available in a 4x4 QFN package and are fully specified for operation over the industrial –40°C to +85°C temperature range. Low Power, High-Speed SAR Converter Family Type/Speed 16 Bit Pseudo-Diff Single Dual 500 kHz ADS8327 ADS8328 1 MHz ADS8329 ADS8330 • • • • • • • • • • • • ADS8330 +IN1 +IN0 COM ADS8329 NC +IN −IN REF+ REF− + _ SAR OUTPUT LATCH and 3−STATE DRIVER CONVERSION and CONTROL LOGIC SDO CDAC COMPARATOR OSC FS/CS SCLK SDI CONVST EOC/INT/CDI Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated ADS8329 ADS8330 SLAS516 – DECEMBER 2006 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) MODEL MAXIMUM INTEGRAL LINEARITY (LSB) MAXIMUM DIFFERENTIAL LINEARITY (LSB) MAXIMUM OFFSET ERROR (mV) PACKAGE TYPE PACKAGE DESIGNATOR TEMPERATURE RANGE ORDERING INFORMATION TRANSPORT MEDIA QUANTITY Small tape and reel 250 Tape and reel 3000 Small tape and reel 250 Tape and reel 3000 Small tape and reel 250 Tape and reel 3000 Small tape and reel 250 Tape and reel 3000 ADS8329IRSAT ADS8329I ±2.5 –1/+2 ±0.8 4X4 QFN-16 RSA –40°C to 85°C ADS8329IRSAR ADS8329IBRSAT ADS8329IB ±1.75 ±1 ±0.5 4X4 QFN-16 RSA –40°C to 85°C ADS8329IBRSAR ADS8330IRSAT ADS8330I ±2.5 –1/+2 ±0.8 4X4 QFN-16 RSA –40°C to 85°C ADS8330IRSAR ADS8330IBRSAT ADS8330IB ±1.75 ±1 ±0.5 4X4 QFN-16 RSA –40°C to 85°C ADS8330IBRSAR (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) UNIT Voltage +IN to AGND –IN to AGND +VA to AGND Voltage +VBD to BDGND AGND to BDGND Digital input voltage to BDGND Digital output voltage to BDGND TA Tstg Operating free-air temperature range Storage temperature range Junction temperature (TJ max) Lead temperature, soldering 4x4 QFN-16 Package Power dissipation θJA thermal impedance (1) Vapor phase (60 sec) Infrared (15 sec) –0.3 V to +VA + 0.3 V –0.3 V to +VA + 0.3 V –0.3 V to 7 V –0.3 V to 7 V –0.3 V to 0.3 V –0.3 V to +VBD + 0.3 V –0.3 V to +VBD + 0.3 V –40°C to 85°C –65°C to 150°C 150°C 215°C 220°C (TJMax - TA)/θJA 47°C/W Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 Submit Documentation Feedback www.ti.com ADS8329 ADS8330 SLAS516 – DECEMBER 2006 SPECIFICATIONS TA = –40°C to 85°C, +VA = 5 V, +VBD = +5.5 V to +1.65 V, Vref = 5 V, fSAMPLE = 1 MHz (unless otherwise noted) PARAMETER ANALOG INPUT Full-scale input voltage Absolute input voltage Input capacitance Input leakage current Input channel isolation, ADS8330 only SYSTEM PERFORMANCE Resolution No missing codes INL Integral linearity Differential linearity Offset error (3) Offset error drift EG Gain error Gain error drift CMRR Common mode rejection ratio Noise PSRR Power supply rejection ratio At FFFFh output code (3) At dc VI = 0.4 Vpp at 1 MHz ADS8329IB, ADS8330IB ADS8329I, ADS8330I ADS8329IB, ADS8330IB ADS8329I, ADS8330I ADS8329IB, ADS8330IB ADS8329I, ADS8330I FSR = 5 V – 0.25 16 –1.75 -2.5 –1 –1 –1 –1.25 ±1.2 ±1.5 ±0.4 ±0.5 ±0.27 ±0.8 0.4 –0.04 0.75 70 50 33 78 0.25 1.75 2.5 1 2 1 1.25 16 Bits Bits LSB (2) LSB (2) No ongoing conversion, DC Input At dc VI = ±1.25 Vpp at 50 kHz -1 109 101 (1) TEST CONDITIONS MIN TYP MAX UNIT +IN – (–IN) or (+INx – COM) +IN, +IN0, +IN1 –IN or COM 0 AGND – 0.2 AGND – 0.2 40 +Vref +VA + 0.2 AGND + 0.2 45 1 V V pF nA dB DNL EO mV PPM/°C %FSR PPM/°C dB µV RMS dB SAMPLING DYNAMICS tCONV tSAMPLE1 tSAMPLE2 Conversion time Acquisition time Throughput rate Aperture delay Aperture jitter Step response Overvoltage recovery 5 10 100 100 Manual trigger Auto trigger 3 3 1 18 CCLK CCLK MHz ns ps ns ns (1) (2) (3) Ideal input span, does not include gain or offset error. LSB means least significant bit Measured relative to an ideal full-scale input [+IN – (–IN)] of 4.096 V when +VA = 5 V. Submit Documentation Feedback 3 ADS8329 ADS8330 SLAS516 – DECEMBER 2006 www.ti.com SPECIFICATIONS (continued) TA = –40°C to 85°C, +VA = 5 V, +VBD = +5.5 V to +1.65 V, Vref = 5 V, fSAMPLE = 1 MHz (unless otherwise noted) PARAMETER DYNAMIC CHARACTERISTICS THD Total harmonic distortion (4) TEST CONDITIONS MIN TYP MAX UNIT VIN = 5 Vpp at 10 kHz VIN = 5 Vpp at 100 kHz VIN = 5 Vpp at 10 kHz ADS8329/30IB ADS8329/30I 90 –102 –95 93 92 90 92 90 105 97 30 dB SNR Signal-to-noise ratio VIN = 5 Vpp at 100 kHz VIN = 5 Vpp at 10 kHz VIN = 5 Vpp at 100 kHz VIN = 5 Vpp at 10 kHz VIN = 5 Vpp at 100 kHz dB SINAD Signal-to-noise + distortion dB SFDR Spurious free dynamic range -3dB Small signal bandwidth dB MHz CLOCK Internal conversion clock frequency SCLK External serial clock EXTERNAL VOLTAGE REFERENCE INPUT Vref Input reference range Resistance (5) 21 Used as I/O clock only As I/O clock and conversion clock 5.5 V ≥ +VA ≥ 4.5 V 1 22.9 24.5 50 42 MHz MHz Vref[REF+ – (REF–)] (REF–) – AGND 0.3 –0.1 5 5 0.1 V kΩ Reference input 40 DIGITAL INPUT/OUTPUT Logic family — CMOS VIH VIL II Ci VOH VOL CO CL High-level input voltage Low-level input voltage Input current Input capacitance High-level output voltage Low-level output voltage Output capacitance Load capacitance Data format — straight binary POWER SUPPLY REQUIREMENTS Power supply voltage +VBD +VA 1-MHz Sample rate Supply current Nap mode PD Mode Buffer I/O supply current Power dissipation TEMPERATURE RANGE TA Operating free-air temperature –40 85 °C 1 MSPS +VA = 5 V, +VBD = 5 V +VA = 5 V, +VBD = 1.8 V 1.65 4.5 3.3 5 7.0 0.3 4 1.7 44 35 48 39.5 5.5 5.5 7.8 0.5 50 V V mA nA mA mW 5.5 V ≥ +VBD ≥ 4.5 V, IO = 100 µA 5.5 V ≥ +VBD ≥ 4.5 V, IO = 100 µA +VBD – 0.6 0 5 30 5.5 V ≥ +VBD ≥ 4.5 V 5.5 V ≥ +VBD ≥ 4.5 V VI = +VBD or BDGND 0.65 × (+VBD) –0.3 -50 5 +VBD 0.4 +VBD + 0.3 0.35 × (+VBD) 50 V V nA pF V V pF pF (4) (5) Calculated on the first nine harmonics of the input frequency Can vary ±30% 4 Submit Documentation Feedback www.ti.com ADS8329 ADS8330 SLAS516 – DECEMBER 2006 SPECIFICATIONS TA = –40°C to 85°C, +VBD = +VA × 1.5 to +1.65 V, Vref = 2.5 V, fSAMPLE = 1 MHz for 3 V ≤ +VA ≤ 3.6 V, fSAMPLE = 900 kHz for 3 V < +VA ≤ 2.7 V using external clock (unless otherwise noted) PARAMETER ANALOG INPUT Full-scale input voltage Absolute input voltage Input capacitance Input leakage current Input channel isolation, ADS8330 only SYSTEM PERFORMANCE Resolution No missing codes INL Integral linearity ADS8329IB, ADS8330IB ADS8329I, ADS8330I DNL Differential linearity ADS8329IB, ADS8330IB ADS8329I, ADS8330I ADS8329IB, ADS8330IB ADS8329I, ADS8330I Offset error drift EG Gain error Gain error drift CMRR Common mode rejection ratio Noise PSRR Power supply rejection ratio At FFFFh output code (3) At dc VI = 0.4 Vpp at 1 MHz FSR = 2.5 V – 0.25 16 –1.75 –2.5 –1 –1 – 0.5 –0.8 ±1 ±1.5 ±0.5 ±0.8 ±0.05 ±0.2 0.8 –0.04 0.5 70 50 33 78 0.25 1.75 2.5 1 2 0.5 0.8 PPM/°C %FSR PPM/°C dB µV RMS dB mV LSB (2) 16 Bits Bits LSB (2) No ongoing conversion, DC Input At dc VI = ±1.25 Vpp at 50 kHz -1 108 101 (1) TEST CONDITIONS MIN TYP MAX UNIT +IN – (–IN) or (+INx – COM) +IN, +IN0, +IN1 –IN or COM 0 AGND – 0.2 AGND – 0.2 40 +Vref +VA + 0.2 AGND + 0.2 45 1 V V pF nA dB EO Offset error (3) SAMPLING DYNAMICS tCONV tSAMPLE1 tSAMPLE2 Conversion time Acquisition time Throughput rate Aperture delay Aperture jitter Step response Overvoltage recovery 5 10 100 100 Manual trigger Auto trigger 3 3 1 18 CCLK CCLK MHz ns ps ns ns (1) (2) (3) Ideal input span, does not include gain or offset error. LSB means least significant bit Measured relative to an ideal full-scale input [+IN – (–IN)] of 2.5 V when +VA = 3 V. Submit Documentation Feedback 5 ADS8329 ADS8330 SLAS516 – DECEMBER 2006 www.ti.com SPECIFICATIONS (continued) TA = –40°C to 85°C, +VBD = +VA × 1.5 to +1.65 V, Vref = 2.5 V, fSAMPLE = 1 MHz for 3 V ≤ +VA ≤ 3.6 V, fSAMPLE = 900 kHz for 3 V < +VA ≤ 2.7 V using external clock (unless otherwise noted) PARAMETER DYNAMIC CHARACTERISTICS THD Total harmonic distortion (4) TEST CONDITIONS MIN TYP MAX UNIT VIN = 2.5 Vpp at 10 kHz VIN = 2.5 Vpp at 100 kHz VIN = 2.5 Vpp at 10 kHz VIN = 2.5 Vpp at 100 kHz VIN = 2.5 Vpp at 10 kHz VIN = 2.5 Vpp at 100 kHz VIN = 2.5 Vpp at 10 kHz VIN = 2.5 Vpp at 100 kHz –102 –93 89 88 88.5 88 104 94.2 30 dB SNR Signal-to-noise ratio dB SINAD Signal-to-noise + distortion dB SFDR Spurious free dynamic range -3dB Small signal bandwidth dB MHz CLOCK Internal conversion clock frequency SCLK External serial clock EXTERNAL VOLTAGE REFERENCE INPUT Vref Input reference range Resistance (5) 21 Used as I/O clock only As I/O clock and conversion clock 3.6 V ≥ +VA ≥ 2.7 V Reference input 1 22.3 23.5 42 42 MHz MHz Vref[REF+ – (REF–)] (REF–) – AGND 2.475 –0.1 40 3 0.1 V kΩ DIGITAL INPUT/OUTPUT Logic family — CMOS VIH VIL II Ci VOH VOL CO CL High-level input voltage Low-level input voltage Input current Input capacitance High-level output voltage Low-level output voltage Output capacitance Load capacitance Data format — straight binary POWER SUPPLY REQUIREMENTS +VBD Power supply voltage +VA fs ≤ 1 MHz fs ≤ 900 kHz 1-MHz Sample rate, 3 V ≤ +VA ≤ 3.6 V Supply current 900-kHz Sample rate, 2.7 V ≤ +VA ≤ 3 V Nap mode PD Mode Buffer I/O supply current Power dissipation TEMPERATURE RANGE TA Operating free-air temperature –40 85 °C 1 MSPS, +VBD = 1.8 V +VBD = 1.8 V, 3 V ≤ +VA ≤ 3.6 V +VBD = 1.8 V, 2.7 V ≤ +VA ≤ 3 V 1.65 3 2.7 5.1 4.84 0.25 2 0.05 15.5 13.2 19 0.4 50 nA mA mW +VA 1.5 × (+VA) 3.6 3.6 6.1 mA V V (+VA × 1.5) V ≥ +VBD ≥ 1.65 V, IO = 100 µA (+VA × 1.5) V ≥ +VBD ≥ 1.65 V, IO = 100 µA +VBD – 0.6 0 5 30 (+VA × 1.5) V ≥ +VBD ≥ 1.65 V (+VA × 1.5) V ≥ +VBD ≥ 1.65 V VI = +VBD or BDGND 0.65 × (+VBD) –0.3 -50 5 +VBD 0.4 +VBD + 0.3 0.35 × (+VBD) 50 V V nA pF V V pF pF (4) (5) Calculated on the first nine harmonics of the input frequency Can vary ±30% 6 Submit Documentation Feedback www.ti.com ADS8329 ADS8330 SLAS516 – DECEMBER 2006 (1) (2) TIMING CHARACTERISTICS All specifications typical at –40°C to 85°C, +VA = +VBD = 5 V PARAMETER fCCLK Frequency, conversion clock, CCLK, fCCLK = 1/2 fSCLK Setup time, falling edge of CS to EOC Hold time, falling edge of CS to EOC Pulse duration, CONVST low Setup time, falling edge of CS to EOS Hold time, falling edge of CS to EOS Setup time, rising edge of CS to EOS Hold time, rising edge of CS to EOS Setup time, falling edge of CS to SCLK Pulse duration, SCLK low Pulse duration, SCLK high I/O Clock only I/O and conversion clock tc(SCLK) Cycle time, SCLK I/O Clock, chain mode I/O and conversion clock, chain mode td(SCLKF-SDOINVALID) td(SCLKF-SDOVALID) td(CSF-SDOVALID) tsu(SDI-SCLKF) th(SDI-SCLKF) td(CSR-SDOZ) tsu(lastSCLKF-CSR) td(SDO-CDI) (1) (2) Delay time, falling edge of SCLK to SDO invalid Delay time, falling edge of SCLK to SDO valid Delay time, falling edge of CS to SDO valid, SDO MSB output Setup time, SDI to falling edge of SCLK Hold time, SDI to falling edge of SCLK Delay time, rising edge of CS/FS to SDO 3-state Setup time, last falling edge of SCLK before rising edge of CS/FS Delay time, CDI high to SDO high in daisy chain mode 10-pF Load, chain mode 10 16 10-pF Load 10-pF Load 10-pF Load 8 4 5 External Internal tsu(CSF-EOC) th(CSF-EOC) twL(CONVST) tsu(CSF-EOS) th(CSF-EOS) tsu(CSR-EOS) th(CSR-EOS) tsu(CSF-SCLK1R) twL(SCLK) twH(SCLK) MIN 0.5 21 1 0 40 20 20 20 20 5 8 8 20 23.8 20 23.8 5 12 12 2000 ns ns ns ns ns ns ns ns 2000 ns tc(SCLK) - 5 tc(SCLK) - 8 tc(SCLK) - 8 22.9 TYP MAX 21 24.5 CCLK ns ns ns ns ns ns ns ns ns UNIT MHz All input signals are specified with tr = tf = 1.5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See timing diagrams. Submit Documentation Feedback 7 ADS8329 ADS8330 SLAS516 – DECEMBER 2006 www.ti.com TIMING CHARACTERISTICS All specifications typical at –40°C to 85°C, +VA = 2.7 v, +VBD = 1.8 V (unless otherwise noted) PARAMETER External, 3 V ≤ +VA ≤ 3.6 V fCCLK tsu(CSF-EOC) th(CSF-EOC) twL(CONVST) tsu(CSF-EOS) th(CSF-EOS) tsu(CSR-EOS) th(CSR-EOS) tsu(CSF-SCLK1R) twL(SCLK) twH(SCLK) Frequency, conversion clock, CCLK, fCCLK = 1/2 fSCLK Setup time, falling edge of CS to EOC Hold time, falling edge of CS to EOC Pulse duration, CONVST low Setup time, falling edge of CS to EOS Hold time, falling edge of CS to EOS Setup time, rising edge of CS to EOS Hold time, rising edge of CS to EOS Setup time, falling edge of CS to SCLK Pulse duration, SCLK low Pulse duration, SCLK high I/O Clock only I/O and conversion clock, 3 V ≤ +VA ≤ 3.6 V I/O and conversion clock, 2.7 V ≤ +VA < 3 V tc(SCLK) Cycle time, SCLK I/O Clock, chain mode I/O and conversion clock, chain mode, 3 V ≤ +VA ≤ 3.6 V I/O and conversion clock, chain mode, 2.7 V ≤ +VA < 3 V td(SCLKF-SDOINVALID) td(SCLKF-SDOVALID) td(CSF-SDOVALID) tsu(SDI-SCLKF) th(SDI-SCLKF) td(CSR-SDOZ) tsu(lastSCLKF-CSR) td(SDO-CDI) (1) (2) Delay time, falling edge of SCLK to SDO invalid Delay time, falling edge of SCLK to SDO valid Delay time, falling edge of CS to SDO valid, SDO MSB output Setup time, SDI to falling edge of SCLK Hold time, SDI to falling edge of SCLK Delay time, rising edge of CS/FS to SDO 3-state Setup time, last falling edge of SCLK before rising edge of CS/FS Delay time, CDI high to SDO high in daisy chain mode 10-pF Load, chain mode 10 23 10-pF Load 10-pF Load 10-pF Load 8 4 8 External, 2.7 V ≤ +VA ≤ 3 V Internal (1) (2) MIN 0.5 0.5 21 1 0 40 20 20 20 20 5 8 8 23.8 23.8 26.5 23.8 23.8 TYP MAX 21 18.9 UNIT MHz CCLK ns ns ns ns ns ns 22.3 23.5 tc(SCLK) - 5 tc(SCLK) - 8 tc(SCLK) - 8 ns ns ns 2000 2000 ns 2000 26.5 8 2000 ns 23 23 ns ns ns ns ns ns ns All input signals are specified with tr = tf = 1.5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See timing diagrams. 8 Submit Documentation Feedback www.ti.com ADS8329 ADS8330 SLAS516 – DECEMBER 2006 PIN ASSIGNMENTS ADS8329 ADS8330 RSA PACKAGE (TOP VIEW) RSA PACKAGE (TOP VIEW) AGND REF− REF− AGND COM 14 16 15 14 13 12 11 10 9 +IN 16 15 13 12 11 10 9 REF+(REFIN) NC CONVST EOC/INT/CDI 1 2 3 4 5 6 7 8 RESERVED +VA +VBD SCLK REF+(REFIN) NC CONVST EOC/INT/CDI +IN0 −IN 1 2 3 4 5 6 7 8 +IN1 +VA +VBD SCLK FS/CS BDGND FS/CS NC − No internal connection BDGND SDO SDO SDI SDI Submit Documentation Feedback 9 ADS8329 ADS8330 SLAS516 – DECEMBER 2006 www.ti.com ADS8329 Terminal Functions NAME AGND BDGND CONVST NO. QFN 15 8 3 I/O – – I Analog ground Interface ground Freezes sample and hold, starts conversion with next rising edge of internal clock Status output. If programmed as EOC, this pin is low (default) when a conversion is in progress. If programmed as an interrupt (INT), this pin is low for a preprogrammed duration after the end of conversion and a valid data is to be output. The polarity of EOC or INT is programmable. This pin can also be used as a chain data input when the device is operated in chain mode. Frame sync signal for TMS320 DSP serial interface or chip select input for SPI interface slave select (SS-). Non inverting input Inverting input, usually connected to ground No connection. External reference input. Connect to AGND through individual via. Connect to AGND or +VA Clock for serial interface Serial data in Serial data out Analog supply, +2.7 V to +5.5 VDC. Interface supply DESCRIPTION EOC/ INT/ CDI 4 O FS/CS +IN -IN NC REF+ REFRESERVED SCLK SDI SDO +VA +VBD 5 13 14 2 1 16 12 9 6 7 11 10 I I I – I I I I I O ADS8330 Terminal Functions NAME AGND BDGND COM CONVST NO. QFN 15 8 14 3 I/O – – I I Analog ground Interface ground Common inverting input, usually connected to ground Freezes sample and hold, starts conversion with next rising edge of internal clock Status output. If programmed as EOC, this pin is low (default) when a conversion is in progress. If programmed as an interrupt (INT), this pin is low for a preprogrammed duration after the end of conversion and a valid data is to be output. The polarity of EOC or INT is programmable. This pin can also be used as a chain data input when the device is operated in chain mode. Frame sync signal for TMS320 DSP serial interface or chip select input for SPI interface Second noninverting input. First noninverting input No connection. External reference input. Connect to AGND through individual via. Clock for serial interface Serial data in (conversion start and reset possible) Serial data out Analog supply, +2.7 V to +5.5 VDC. Interface supply DESCRIPTION EOC/ INT/ CDI 4 O FS/CS +IN1 +IN0 NC REF+ REFSCLK SDI SDO +VA +VBD 5 12 13 2 1 16 9 6 7 11 10 I I I – I I I I O 10 Submit Documentation Feedback www.ti.com ADS8329 ADS8330 SLAS516 – DECEMBER 2006 MANUAL TRIGGER / READ While Sampling (use internal CCLK, EOC and INT polarity programmed as active low) CONVST EOS EOC Nth EOS twL(CONVST) Nth tCONV = 18 CCLKs EOC EOC (active low) tSAMPLE1 = 3 CCLKs min INT (active low) tSAMPLE1 = 3 CCLKs min th(CSF-EOC) th(CSF-EOS) th(CSR-EOS) tsu(CSF-EOC) th(CSF-EOC) tsu(CSF-EOS) 1 CS/FS SCLK 1 . . . . . . . . . . . . . . . . . . . . 16 td(CSR-EOS) = 20 ns min Nth 1101b SDO SDI 1101b Nth−1th READ Result READ Result Figure 1. Timing for Conversion and Acquisition Cycles for Manual Trigger (Read while sampling) AUTO TRIGGER / READ While Sampling (use internal CCLK, EOC and INT polarity programmed as active low) CONVST = 1 EOS EOC EOS EOC EOS 1 Nth EOC (active low) tCONV = 18 CCLKs INT (active low) th(CSF-EOC) Nth tSAMPLE2 = 3 CCLKs tCONV = 18 CCLKs th(CSF-EOS) tSAMPLE2 = 3 CCLKs tsu(CSF-EOS) CS/FS SCLK SDO SDI 1 . . . . . . . . . . . . . . . . . . .16 N − 1th tsu(CSF-EOS) 1 . . . . . . . . . . . . . . . . . . .16 N − 1th th(CSF-EOC) 1110b. . . . . . . . . . . . . . 1101b 1101b CONFIGURE READ Result READ Result Figure 2. Timing for Conversion and Acquisition Cycles for Autotrigger (Read while sampling) Submit Documentation Feedback 11 ADS8329 ADS8330 SLAS516 – DECEMBER 2006 MANUAL TRIGGER / READ While Converting (use internal CCLK, EOC and INT polarity programmed as active low) www.ti.com CONVST Nth twL(CONVST) Nth tCONV = 18 CCLKs N − 1th EOC EOS EOS N + 1th EOC (active low) tSAMPLE1 = 3 CCLKs min INT (active low) tsu(CSF-EOS) CS/FS tsu(CSF-EOC) SCLK 1 . . . . . . . . . . . . . . . . . . . .16 th(CSF-EOS) tsu(CSR-EOS) th(CSF-EOC) 1 N th 1101b SDO SDI 1101b N − 1th READ Result READ Result Figure 3. Timing for Conversion and Acquisition Cycles for Manual Trigger (Read while converting) AUTO TRIGGER / READ While Converting (use internal CCLK, EOC and INT polarity programmed as active low) CONVST = 1 EOS EOC EOS EOC EOC (active low) N + 1th tCONV = 18 CCLKs INT (active low) tsu(CSF-EOS) th(CSR-EOS) CS/FS Nth tSAMPLE2 = 3 CCLKs min th(CSF-EOS) tCONV = 18 CCLKs tSAMPLE2 = 3 CCLKs min tsu(CSR-EOS) th(CSF-EOS) 1 . . . . . . . . . . . . . . . . . . 16 SCLK SDO SDI 1 . . . . . . . . . . . . . . . . . . .16 N−1 th 1 . . . . . . . . . . . . . . . . . . 16 N−1 th 1101b tsu(CSR-EOS) N th ?? 1110b . . . . . . . . . . . . . . . 1101b CONFIGURE READ Result READ Result Figure 4. Timing for Conversion and Acquisition Cycles for Autotrigger (Read while converting) 12 Submit Documentation Feedback EOS www.ti.com ADS8329 ADS8330 SLAS516 – DECEMBER 2006 1 2 3 4 5 6 7 14 15 16 SCLK tsu(CSF−SCLK1R) CS/FS tc(SCLK) twH(SCLK) tsu(LastSCLK−CSR) twL(SCLK) td(SCLKF−SDOINVALID) td(CSR−SDOZ) td(CSF−SDOVALID) SDO Hi−Z MSB MSB−1 MSB−2 MSB−3 MSB−4 td(SCLKF−SDOVALID) MSB−5 MSB−6 LSB+2 LSB+1 LSB th(SDI−SCLKF) SDI MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 LSB+2 LSB+1 LSB tsu(SDI−SCLKF) Figure 5. Detailed SPI Transfer Timing MANUAL TRIGGER / READ While Sampling (use internal CCLK active high, EOC and INT active low, TAG enabled, auto channel select) Nth CH0 CONVST twL(CONVST) EOC Nth CH1 twL(CONVST) EOC (active low) EOS Nth CH0 tCONV = 18 CCLKs tSAMPLE1 = 3 CCLKs min Nth CH1 tCONV = 18 CCLKs INT (active low) tsu(CSF-EOS) th(CSF-EOC) CS/FS SCLK 1 . . . . . . . . . . . . . . . . . . . . . . . 16 17 1 . . . . . . . . . . . . . . . . . . . . . . . 16 17 td(CSR-EOS) = 20 ns MIN SDO SDI Hi−Z N−1th CH1 Nth CH0 Hi−Z TAG = 0 TAG = 1 1101b 1101b READ Result READ Result Figure 6. Simplified Dual Channel Timing Submit Documentation Feedback 13 ADS8329 ADS8330 SLAS516 – DECEMBER 2006 www.ti.com TYPICAL CHARACTERISTICS At –40°C to 85°C, Vref [REF+ – (REF–)] = 5 V when +VA = +VBD = 5 V or Vref [REF+ – (REF–)] = 2.5 V when +VA = +VBD = 3 V, fSCLK = 42 MHz, or Vref = 2.5 when +VA = +VBD = 2.7 V, fSCLK = 37.8 MHz, fi = DC for DC curves, fi = 100 kHz for AC curves with 5-V supply and fi = 10 kHz for AC curves with 3-V supply (unless otherwise noted) CROSSTALK vs FREQUENCY 110 1 DIFFERENTIAL NONLINEARITY vs FREE-AIR TEMPERATURE 2 INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE 105 0.8 1.5 +VA = 5 V Crosstalk -dB 100 DNL - LSB 0.6 +VA = 3 V INL - LSB 95 +VA = 5 V 90 1 +VA = 3 V 0.4 +VA = 5 V 0.5 0.2 85 +VA = 3 V 80 0 50 100 150 f - Frequency - kHz 200 0 -40 -25 -10 5 20 35 50 65 80 0 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 80 TA - Free-Air Temperature - °C Figure 7. DIFFERENTIAL NONLINEARITY vs EXTERNAL CLOCK FREQUENCY 1 2 Figure 8. INTEGRAL NONLINEARITY vs EXTERNAL CLOCK FREQUENCY 1 Figure 9. DIFFERENTIAL NONLINEARITY vs EXTERNAL CLOCK FREQUENCY +VA = 3 V +VA = 5 V MAX 0.5 1.5 1 0.5 +VA = 5 V MAX 0.5 MAX INL - LSB DNL - LSB 0 MIN -0.5 0 -0.5 -1 -1.5 MIN DNL - LSB 0 MIN -0.5 -1 0.1 1 10 External Clock Frequency - MHz 100 -2 0.1 10 1 External Clock Frequency - MHz 100 -1 0.1 1 10 External Clock Frequency - MHz 100 Figure 10. Figure 11. Figure 12. 14 Submit Documentation Feedback www.ti.com ADS8329 ADS8330 SLAS516 – DECEMBER 2006 TYPICAL CHARACTERISTICS (continued) INTEGRAL NONLINEARITY vs EXTERNAL CLOCK FREQUENCY 2 1 OFFSET VOLTAGE vs FREE-AIR TEMPERATURE 1 OFFSET VOLTAGE vs SUPPLY VOLTAGE +VA = 3 V 1.5 MAX 1 0.5 0.8 Offset Voltage - mV +VA = 5 V 0.5 Offset Voltage - mV INL - LSB 0.6 0 -0.5 MIN -1 -1.5 -2 0.1 0 +VA = 3 V 0.4 -0.5 0.2 1 10 External Clock Frequency - MHz 100 -1 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 80 0 2.7 3.2 3.7 4.2 4.7 +VA - Supply Voltage - V 5.2 Figure 13. Figure 14. Figure 15. POWER SUPPLY REJECTION RATIO vs SUPPLY RIPPLE FREQUENCY -80 GAIN ERROR vs FREE-AIR TEMPERATURE 0 0.10 GAIN ERROR vs SUPPLY VOLTAGE PSRR - Power Supply Rejection Ratio - dB -0.02 0.05 -78 Gain Error - %FSR +VA = 5 V -0.04 Gain Error - %FSR -76 +VA = 3 V -0.06 0 -74 +VA = 5 V -72 -0.05 -0.08 +VA = 3 V -70 0 20 40 60 f - Frequency - kHz 80 100 -0.10 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 80 -0.10 2.7 3.2 3.7 4.2 4.7 5.2 +VA - Supply Voltage - V Figure 16. Figure 17. SIGNAL-TO-NOISE AND DISTORTION vs INPUT FREQUENCY SINAD - Signal-To-Noise and Distortion - dB 95 -90 Figure 18. SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY 95 TOTALHARMONIC DISTORTION vs INPUT FREQUENCY THD - Total Harmonic Distortion - dB +VA = 3 V -95 +VA = 5 V -100 SNR - Signal-To-Noise Ratio - dB 93 +VA = 5 V 93 +VA = 5 V 91 91 89 +VA = 3 V 89 +VA = 3 V -105 87 87 85 0 20 40 60 80 fi - Input Frequency - kHz 100 85 0 20 40 60 80 fi - Input Frequency - kHz 100 -110 0 20 40 60 80 fi - Input Frequency - kHz 100 Figure 19. Figure 20. Figure 21. 15 Submit Documentation Feedback ADS8329 ADS8330 SLAS516 – DECEMBER 2006 www.ti.com TYPICAL CHARACTERISTICS (continued) SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY 110 100 fi = 10 kHz SIGNAL-TO-NOISE RATIO vs FULL SCALE RANGE SINAD - Signal-To-Noise and Distortion - dB 100 SIGNAL-TO-NOISE AND DISTORTION vs FULL SCALE RANGE fi = 10 kHz 95 SFDR - Spurious Free Dynamic Range - dB 108 SNR - Signal-To-Noise Ratio - dB 95 106 104 102 100 98 96 94 92 90 0 20 40 60 80 fi - Input Frequency - kHz 100 +VA = 3 V +VA = 5 V 90 +VA = 3 V +VA = 5 V 85 90 +VA = 3 V +VA = 5 V 85 80 80 75 70 0 1 2 3 Full Scale Range - V 4 5 75 70 0 1 3 2 Full Scale Range - V 4 5 Figure 22. TOTAL HARMONIC DISTORTION vs FULL SCALE RANGE -80 Figure 23. SPURIOUS FREE DYNAMIC RANGE vs FULL SCALE RANGE SFDR - Spurious Free Dynamic Range - dB 110 -90 Figure 24. TOTAL HARMONIC DISTORTION vs FREE-AIR TEMPERATURE THD - Total Harmonic Distortion - dB THD - Total Harmonic Distortion - dB fi = 10 kHz -85 fi = 10 kHz 105 +VA = 3 V +VA = 5 V 100 +VA = 5 V -95 -90 -95 +VA = 5 V -100 +VA = 3 V -105 95 -100 +VA = 3 V 90 -105 85 80 0 -110 0 1 2 3 Full Scale Range - V 4 5 1 2 3 Full Scale Range - V 4 5 -110 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 80 Figure 25. Figure 26. Figure 27. SIGNAL-TO-NOISE AND DISTORTION vs FREE-AIR TEMPERATURE SINAD - Signal-To-Noise and Distortion - dB 95 SPURIOUS FREE DYNAMIC RANGE vs FREE-AIR TEMPERATURE SFDR - Spurious Free Dynamic Range - dB 110 95 SIGNAL-TO-NOISE RATIO vs FREE-AIR TEMPERATURE SNR - Signal-To-Noise Ratio - dB 93 +VA = 5 V 93 105 +VA = 3 V 91 91 +VA = 5 V 100 +VA = 3 V 89 89 +VA = 5 V 95 +VA = 3 V 87 87 90 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 80 85 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - ºC 80 85 -40 -25 -10 5 20 35 50 65 80 TA - Free-Air Temperature - ºC Figure 28. 16 Figure 29. Submit Documentation Feedback Figure 30. www.ti.com ADS8329 ADS8330 SLAS516 – DECEMBER 2006 TYPICAL CHARACTERISTICS (continued) EFFECTIVE NUMBER OF BITS vs FREE-AIR TEMPERATURE 16 24 INTERNAL CLOCK FREQUENCY vs SUPPLY VOLTAGE 24 INTERNAL CLOCK FREQUENCY vs FREE-AIR TEMPERATURE ENOB - Effective Number of Bits - Bits Internal Clock Frequency - MHz Internal Clock Frequency - MHz 3.2 3.7 4.2 4.7 +VA - Supply Voltage - V 5.2 23.5 23.5 15.50 23 23 +VA = 5 V 15 22.5 22.5 22 +VA = 3 V 14.50 22 21.5 21 2.7 21.5 14 -40 -25 -10 5 20 35 50 65 80 TA - Free-Air Temperature - ºC 21 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - ºC 80 Figure 31. ANALOG SUPPLY CURRENT vs SUPPLY VOLTAGE 400 7.5 fs = 1 MSPS NAP Mode Figure 32. ANALOG SUPPLY CURRENT vs SUPPLY VOLTAGE 10 PD Mode Figure 33. ANALOG SUPPLY CURRENT vs SUPPLY VOLTAGE Analog Supply Current - mA 7.0 6.5 6.0 5.5 5.0 4.5 2.7 Analog Supply Current - mA 360 Analog Supply Current - nA 8 320 6 280 4 240 2 3.2 3.7 4.2 4.7 5.2 +VA - Supply Voltage - V 200 2.7 3.2 3.7 4.2 4.7 +VA - Supply Voltage - V 5.2 0 2.7 3.2 3.7 4.2 4.7 +VA - Supply Voltage - V 5.2 Figure 34. ANALOG SUPPLY CURRENT vs SAMPLE RATE 500 7 Auto NAP Figure 35. ANALOG SUPPLY CURRENT vs SAMPLE RATE PD Mode Analog Supply Current - mA Analog Supply Current - mA 400 7.5 7 6.5 6 5.5 5 4.5 0 1 5 9 13 17 Sample Rate - kHz 4 -40 Figure 36. ANALOG SUPPLY CURRENT vs FREE-AIR TEMPERATURE fs = 1 MSPS Analog Supply Current - mA +VA = 5 V 6 5 4 +VA = 5 V 300 +VA = 5 V 200 +VA = 3 V 3 2 1 0 1 10 100 Sample Rate - kHz 1000 +VA = 3 V 100 +VA = 3 V -25 -10 5 20 35 50 65 TA - Free-Air Temperature - ºC 80 Figure 37. Figure 38. Figure 39. Submit Documentation Feedback 17 ADS8329 ADS8330 SLAS516 – DECEMBER 2006 www.ti.com TYPICAL CHARACTERISTICS (continued) ANALOG SUPPLY CURRENT vs FREE-AIR TEMPERATURE 0.4 NAP Mode Analog Supply Current - mA 0.36 0.32 +VA = 5 V 0.28 +VA = 3 V 0.24 0.2 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - ºC 80 Figure 40. INL 1.75 1.5 1.0 0.5 +VA = 5 V INL - Bits 0 -0.5 -1.0 -1.5 -1.75 0 10000 20000 30000 Code 40000 50000 60000 Figure 41. DNL 1 +VA = 5 V 0.5 DNL - Bits 0 -0.5 -1 0 10000 20000 30000 Code 40000 50000 60000 Figure 42. 18 Submit Documentation Feedback www.ti.com ADS8329 ADS8330 SLAS516 – DECEMBER 2006 TYPICAL CHARACTERISTICS (continued) INL 1.75 1.5 1.0 0.5 +VA = 3 V INL - Bits 0 -0.5 -1.0 -1.5 -1.75 0 10000 20000 30000 Code 40000 50000 60000 Figure 43. DNL 1 +VA = 3 V 0.5 DNL - Bits 0 -0.5 -1 0 10000 20000 30000 Code 40000 50000 60000 Figure 44. FFT 0 -20 -40 5 kHz Input, +VA = 3 V, fs = 1 MSPS, Vref = 2.5 V Amplitude - dB -60 -80 -100 -120 -140 -160 0 100 200 f - Frequency - kHz 300 400 500 Figure 45. Submit Documentation Feedback 19 ADS8329 ADS8330 SLAS516 – DECEMBER 2006 www.ti.com TYPICAL CHARACTERISTICS (continued) FFT 0 -20 -40 10 kHz Input, +VA = 3 V, fs = 1 MSPS, Vref = 2.5 V Amplitude - dB -60 -80 -100 -120 -140 -160 0 100 200 f - Frequency - kHz 300 400 500 Figure 46. 0 -20 -40 FFT 100 kHz Input, +VA = 3 V, fs = 1 MSPS, Vref = 2.5 V Amplitude - dB -60 -80 -100 -120 -140 -160 0 100 200 f - Frequency - kHz 300 400 500 Figure 47. 0 -20 -40 FFT 5 kHz Input, +VA = 5 V, fs = 1 MSPS, Vref = 5 V Amplitude - dB -60 -80 -100 -120 -140 -160 0 100 200 f - Frequency - kHz 300 400 500 Figure 48. 20 Submit Documentation Feedback www.ti.com ADS8329 ADS8330 SLAS516 – DECEMBER 2006 TYPICAL CHARACTERISTICS (continued) FFT 20 0 -20 10 kHz Input, +VA = 5 V, fs = 1 MSPS, Vref = 5 V Amplitude - dB -40 -60 -80 -100 -120 -140 -160 0 100 200 f - Frequency - kHz 300 400 500 Figure 49. FFT 0 -20 -40 100 kHz Input, +VA = 5 V, fs = 1 MSPS, Vref = 5 V Amplitude - dB -60 -80 -100 -120 -140 -160 0 100 200 f - Frequency - kHz 300 400 500 Figure 50. THEORY OF OPERATION The ADS8329/30 is a high-speed, low power, successive approximation register (SAR) analog-to-digital converter (ADC) that uses an external reference. The architecture is based on charge redistribution, which inherently includes a sample/hold function. The ADS8329/30 has an internal clock that is used to run the conversion but can also be programmed to run the conversion based on the external serial clock, SCLK. The ADS8329 has one analog input. The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both +IN and –IN inputs are disconnected from any internal function. The ADS8330 has two inputs. Both inputs share the same common pin - COM. The negative input is the same as the -IN pin for the ADS8329. The ADS8330 can be programmed to select a channel manually or can be programmed into the auto channel select mode to sweep between channel 0 and 1 automatically. ANALOG INPUT When the converter enters hold mode, the voltage difference between the +IN and –IN inputs is captured on the internal capacitor array. The voltage on the –IN input is limited between AGND – 0.2 V and AGND + 0.2 V, allowing the input to reject small signals which are common to both the +IN and –IN inputs. The +IN input has a range of –0.2 V to Vref + 0.2 V. The input span [+IN – (–IN)] is limited to 0 V to Vref. The (peak) input current through the analog inputs depends upon a number of factors: sample rate, input Submit Documentation Feedback 21 ADS8329 ADS8330 SLAS516 – DECEMBER 2006 www.ti.com THEORY OF OPERATION (continued) voltage, and source impedance. The current into the ADS8329/30 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (45 pF) to a 16-bit settling level within the minimum acquisition time (120 ns). When the converter goes into hold mode, the input impedance is greater than 1 GΩ. Care must be taken regarding the absolute analog input voltage. To maintain linearity of the converter, the +IN and –IN inputs and the span [+IN – (–IN)] should be within the limits specified. Outside of these ranges, converter linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass filters should be used. Care should be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are matched. If this is not observed, the two inputs could have different settling times. This may result in an offset error, gain error, and linearity error which change with temperature and input voltage. Device in Hold Mode 150 W 4 pF 4 pF −IN AGND +VA 150 W 40 pF AGND 40 pF +IN Figure 51. Input Equivalent Circuit Driver Amplifier Choice The analog input to the converter needs to be driven with a low noise, op-amp like the THS4031 or OPA365. An RC filter is recommended at the input pins to low-pass filter the noise from the source. Two resistors of 20 Ω and a capacitor of 470 pF are recommended. The input to the converter is a unipolar input voltage in the range 0 V to Vref. The minimum -3dB bandwidth of the driving operational amplifier can be calculated to: f3db = (ln(2) ×(n+1))/(2π × tACQ) where n is equal to 16, the resolution of the ADC (in the case of the ADS8329/30). When tACQ = 120 ns (minimum acquisition time), the minimum bandwidth of the driving amplifier is 15.6 MHz. The bandwidth can be relaxed if the acquisition time is increased by the application. The OPA365, OPA827, or THS4031 from Texas Instruments are recommended. The THS4031 used in the source follower configuration to drive the converter is shown in the typical input drive configuration, Figure 52. Bipolar to Unipolar Driver In systems where the input is bipolar, the THS4031 can be used in the inverting configuration with an additional DC bias applied to its + input so as to keep the input to the ADS8329/30 within its rated operating voltage range. This configuration is also recommended when the ADS8329/30 is used in signal processing applications where good SNR and THD performance is required. The DC bias can be derived from the REF3225 or the REF3240 reference voltage ICs. The input configuration shown in Figure 53 is capable of delivering better than 91 dB SNR and –96 dB THD at an input frequency of 10 kHz. In case bandpass filters are used to filter the input, care should be taken to ensure that the signal swing at the input of the bandpass filter is small so as to keep the distortion introduced by the filter minimal. In such cases, the gain of the circuit shown in Figure 53 can be increased to keep the input to the ADS8329/30 large to keep the SNR of the system high. Note that the gain of the system from the + input to the output of the THS4031 in such a configuration is a function of the gain of the AC signal. A resistor divider can be used to scale the output of the REF3225 or REF3240 to reduce the voltage at the DC input to THS4031 to keep the voltage at the input of the converter within its rated operating range. 22 Submit Documentation Feedback www.ti.com ADS8329 ADS8330 SLAS516 – DECEMBER 2006 THEORY OF OPERATION (continued) Input Signal (0 V to 4 V) THS4031 20 W 470 pF −IN/COM 50 W 20 W ADS8329/30 +VA +IN/(+IN1 or +IN0) 5V Figure 52. Unipolar Input Drive Configuration ADS8329 1 V DC THS4031 20 W 470 pF Input Signal (−2V to 2 V) −IN/COM 600 W 20 W +VA +IN/(+IN1 or +IN0) 5V 600 W Figure 53. Bipolar Input Drive Configuration REFERENCE The ADS8329/30 can operate with an external reference with a range from 0.3 V to 5 V. A clean, low noise, well-decoupled reference voltage on this pin is required to ensure good performance of the converter. A low noise band-gap reference like the REF3240 can be used to drive this pin. A 22-µF ceramic decoupling capacitor is required between the REF+ and REF- pins of the converter. These capacitors should be placed as close as possible to the pins of the device. The REF- should be connected to its own via to the analog ground plane with the shortest possible distance. CONVERTER OPERATION The ADS8329/30 has an oscillator that is used as an internal clock which controls the conversion rate. The frequency of this clock is 21 MHz minimum. The oscillator is always on unless the device is in the deep powerdown state or the device is programmed for using SCLK as the conversion clock (CCLK). The minimum acquisition (sampling) time takes 3 CCLKs (this is equivalent to 120 ns at 24.5 MHz) and the conversion time takes 18 conversion clocks (CCLK) (~780 ns) to complete one conversion. The conversion can also be programmed to run based on the external serial clock, SCLK, if is so desired. This allows a system designer to achieve system synchronization. The serial clock SCLK, is first reduced to 1/2 of its frequency before it is used as the conversion clock (CCLK). For example, with a 42-MHz SCLK this provides a 21-MHz clock for conversions. If it is desired to start a conversion at a specific rising edge of the SCLK when the external SCLK is programmed as the source of the conversion clock (CCLK) (and manual start of conversion is selected), the setup time between CONVST and that rising SCLK edge should be observed. This ensures the conversion is complete in 18 CCLKs (or 36 SCLKs). The minimum setup time is 20 ns to ensure synchronization between CONVST and SCLK. In many cases the conversion can start one SCLK period (or CCLK) later which results in a 19 CCLK (or 37 SCLK) conversion. The 20 ns setup time is not required once synchronization is relaxed. Submit Documentation Feedback 23 ADS8329 ADS8330 SLAS516 – DECEMBER 2006 www.ti.com THEORY OF OPERATION (continued) The duty cycle of SCLK is not critical as long as it meets the minimum high and low time requirements of 8 ns. Since the ADS8329/30 is designed for high-speed applications, a higher serial clock (SCLK) must be supplied to be able to sustain the high throughput with the serial interface and so the clock period of SCLK must be at most 1 µs (when used as conversion clock (CCLK). The minimum clock frequency is also governed by the parasitic leakage of the capacitive digital-to-analog (CDAC) capacitors internal to the ADS8329/30. CFR_D10 Conversion Clock (CCLK) =1 OSC SPI Serial Clock (SCLK) =0 Divider 1/2 Figure 54. Converter Clock Manual Channel Select Mode The conversion cycle starts with selecting an acquisition channel by writing a channel number to the command register (CMR). This cycle time can be as short as 4 serial clocks (SCLK). Auto Channel Select Mode Channel selection can also be done automatically if auto channel select mode is enabled. This is the default channel select mode. The dual channel converter, ADS8330, has a built-in 2-to-1 MUX. If the device is programmed for auto channel select mode then signals from channel 0 and channel 1 are acquired with a fixed order. Channel 0 is accessed first in the next cycle after the command cycle that configured CFR_D11 to 1 for auto channel select mode. This automatic access stops the cycle after the command cycle that sets CFR_D11 to 0. Start of a Conversion The end of acquisition or sampling instance (EOS) is the same as the start of a conversion. This is initiated by bringing the CONVST pin low for a minimum of 40 ns. After the minimum requirement has been met, the CONVST pin can be brought high. CONVST acts independent of FS/CS so it is possible to use one common CONVST for applications requiring simultaneous sample/hold with multiple converters. The ADS8329/30 switches from sample to hold mode on the falling edge of the CONVST signal. The ADS8329/30 requires 18 conversion clock (CCLK) edges to complete a conversion. The conversion time is equivalent to 1500 ns with a 12-MHz internal clock. The minimum time between two consecutive CONVST signals is 21 CCLKs. A conversion can also be initiated without using CONVST if it is so programmed (CFR_D9 = 0). When the converter is configured as auto trigger, the next conversion is automatically started 3 conversion clocks (CCLK) after the end of a conversion. These 3 conversion clocks (CCLK) are used as the acquisition time. In this case the time to complete one acquisition and conversion cycle is 21 CCLKs. Table 1. Different Types of Conversion MODE SELECT CHANNEL Auto Channel Select (1) Automatic No need to write channel number to the CMR. Use internal sequencer for the ADS8330. Manual (1) Manual Channel Select Write the channel number to the CMR. START CONVERSION Auto Trigger Start a conversion based on the conversion clock CCLK. Manual Trigger Start a conversion with CONVST. Auto channel select should be used with auto trigger and also with the TAG bit enabled. 24 Submit Documentation Feedback www.ti.com ADS8329 ADS8330 SLAS516 – DECEMBER 2006 Status Output EOC/INT When the status pin is programmed as EOC and the polarity is set as active low, the pin works in the following manner: The EOC output goes LOW immediately following CONVST going LOW when manual trigger is programmed. EOC stays LOW throughout the conversion process and returns to HIGH when the conversion has ended. The EOC output goes low for 3 conversion clocks (CCLK) after the previous rising edge of EOC, if auto trigger is programmed. This status pin is programmable. It can be used as an EOC output (CFR_D[7:6] = 1, 1) where the low time is equal to the conversion time. This status pin can be used as INT. (CFR_D[7:6] = 1, 0) which is set LOW at the end of a conversion is brought to HIGH (cleared) by the next read cycle. The polarity of this pin, used as either function (EOC or INT), is programmable through CFR_D7. Power-Down Modes The ADS8329/30 has a comprehensive built-in power-down feature. There are three power-down modes: Deep power-down mode, Nap power-down mode, and auto nap power-down mode. All three power-down modes are enabled by setting the related CFR bits. The first two power-down modes are activated when enabled. A wakeup command, 1011b, can resume device operation from a power-down mode. Auto nap power-down mode works slightly different. When the converter is enabled in auto nap power-down mode, an end of conversion instance (EOC) puts the device into auto nap powerdown. The beginning of sampling resumes operation of the converter. The contents of the configuration register is not affected by any of the power-down modes. Any ongoing conversion when nap or deep powerdown is activated is aborted. 100 +VA − Supply Current − mA 10 1 0.1 20 10020 20020 Settling Time − ns 30020 40020 Figure 55. Typical Analog Supply Current Drop vs Time After Powerdown Submit Documentation Feedback 25 ADS8329 ADS8330 SLAS516 – DECEMBER 2006 www.ti.com Deep Power-Down Mode Deep power-down mode can be activated by writing to configuration register bit CFR_D2. When the device is in deep power-down mode, all blocks except the interface are in powerdown. The external SCLK is blocked to the analog block. The analog blocks no longer have bias currents and the internal oscillator is turned off. In this mode, power dissipation falls from 5 mA to 1 µA in 2 µs. The wake-up time after a powerdown is 1 µs. When bit D2 in the configuration register is set to 0, the device is in deep powerdown. Setting this bit to 1 or sending a wake-up command can resume the converter from the deep power-down state. Nap Mode In nap mode the ADS8329/230 turns off biasing of the comparator and the mid-volt buffer. In this mode power dissipation falls from 7 mA in normal mode to about 0.3 mA in 200 ns after the configuration cycle. The wake-up (resume) time from nap power-down mode is 3 CCLKs (120 ns with a 24.5-MHz conversion clock). As soon as the CFR_D3 bit in the control register is set to 0, the device goes into nap power-down mode, regardless of the conversion state. Setting this bit to 1 or sending a wake-up command can resume the converter from the nap power-down state. Auto Nap Mode Auto nap mode is almost identical to nap mode. The only difference is the time when the device is actually powered down and the method to wake up the device. Configuration register bit D4 is only used to enable/disable auto nap mode. If auto nap mode is enabled, the device turns off biasing after the conversion has finished, which means the end of conversion activates auto nap powerdown mode. Power dissipation falls from 7 mA in normal mode to about 0.3 mA in 200 ns. A CONVST resumes the device and turns biasing on again in 3 CCLKs (120 ns with a 24.5-MHz conversion clock). The device can also be woken up by disabling auto nap mode when bit D4 of the configuration register is set to 1. Any channel select command 0XXXb, wake up command or the set default mode command 1111b can also wake up the device from auto nap powerdown. NOTE: 1. This wake-up command is the word 1011b in the command word. This command sets bits D2 and D3 to 1 in the configuration register but not D4. But a wake-up command does remove the device from either one of these power-down states, deep/nap/auto nap powerdown. 2. Wake-up time is defined as the time between when the host processor tries to wake up the converter and when a convert start can occur. Table 2. Power-Down Mode Comparisons TYPE OF POWERDOWN Normal operation Deep powerdown Nap powerdown POWER CONSUMPTION 7 mA/5.1 mA 7 nA/1 nA 0.3 mA/0.2 mA Setting CFR Setting CFR EOC (end of conversion) 100 µs 200 µs 200 µs Woken up by command 1011b Woken up by command 1011b to achieve 6.6 mA since (1.3 + 12)/2 = 6.6 Woken up by CONVST, any channel select command, default command 1111b, or wake up command 1011b. 1 µs 3 CCLKs Set CFR Set CFR ACTIVATED BY ACTIVATION TIME RESUME POWER BY RESUME TIME ENABLE Auto nap powerdown 3 CCLKs Set CFR 26 Submit Documentation Feedback www.ti.com ADS8329 ADS8330 SLAS516 – DECEMBER 2006 N EOS EOC Converter State EOS N+1 EOC N+1 −th Conversion N+1 EOC EOS EOC N+1 −th Conversion =18 CCLK Activation CONVST Converter State N −th Conversion N+1 −th Sampling Read While Converting 20 ns MIN 1 CCLK MIN CS (For Read Result) Read N−1 −th Result Read While Sampling 0 ns MIN 20 ns MIN CS (For Read Result) Read N −th Result Figure 56. Read While Converting vs Read While Sampling (Manual trigger) Manual Trigger CONVST EOS Converter State Resume N −th Sampling >=3CCLK N −th Conversion =18 CCLK N Activation Resume N+1 −th Sampling >=3CCLK 20 ns MIN Read While Converting CS 1 CCLK MIN Read N−1 −th Result 20 ns MIN Read N −th Result 20 ns MIN Read While Sampling Read N−1 −th CS Result 20 ns MIN 20 ns MIN 0 ns MIN Read N −th Result 20 ns MIN 20 ns MIN 20 ns MIN Figure 57. Read While Converting vs Read While Sampling with Deep or Nap Powerdown Submit Documentation Feedback 27 ADS8329 ADS8330 SLAS516 – DECEMBER 2006 40 ns MIN N N+1 www.ti.com Manual Trigger Case 1 CONVST EOC (programmed Active Low) EOS EOC EOS Converter State Resume N −th Sampling >=3CCLK N −th Conversion =18 CCLK 6 CCLKs POWERDOWN Resume N+1 −th Sampling >=3CCLK N+1 −th Conversion =18 CCLK 6 CCLKs EOC POWERDOWN 20 ns MIN Read N −th Result 20 ns MIN 1 CCLK MIN 20 ns MIN EOC N+1 −th Conversion =18 CCLK POWER DOWN 20 ns MIN Read N −th Result 20 ns MIN 20 ns MIN 20 ns MIN Read While Converting 20 ns MIN CS Read N−1 −th Result 20 ns MIN Read While Sampling 1 CCLK MIN 0 ns MIN CS Read N−1 −th Result 20 ns MIN Manual Trigger Case 2 (wake up by CONVST) CONVST EOC (programmed Active Low) N N+1 40 ns MIN Read N −th Result EOS Converter State EOC Resume N −th Sampling >=3CCLK N −th Conversion =18 CCLK POWER DOWN Resume N+1 −th Sampling >=3CCLK Read While Converting 20 ns MIN CS Read N−1 −th Result Read While Sampling 20 ns MIN 20 ns MIN 0 ns MIN Read N −th Result 20 ns MIN CS Read N−1 −th Result Figure 58. Read While Converting vs Read While Sampling with Auto Nap Powerdown Total Acquisition + Conversion Cycle Time: Automatic: Manual: Manual + nap powerdown: Manual + auto nap powerdown: Manual + auto nap powerdown: 28 = 21 CCLKs ≥ 21 CCLKs ≥ 4 SCLK + 3 CCLK + 3 CCLK + 18 CCLK +16 SCLK ≥ 4 SCLK + 3 CCLK + 3 CCLK + 18 CCLK +16 SCLK (use wakeup to resume) ≥ 1 CCLK + 3 CCLK + 3 CCLK + 18 CCLK +16 SCLK (use CONVST to resume) Manual + deep powerdown: ≥ 4SCLK + 100 µs + 3 CCLK + 18 CCLK +16 SCLK + 1 µs Submit Documentation Feedback EOS www.ti.com ADS8329 ADS8330 SLAS516 – DECEMBER 2006 DIGITAL INTERFACE The serial interface is compatible with Motorola SPI. The serial clock is designed to accommodate the latest high-speed processors with an SCLK up to 50 MHz. Each cycle is started with the falling edge of FS/CS. The internal data register content which is made available to the output register at the EOC presented on the SDO output pin at the falling edge of FS/CS. This is the MSB. Output data are changed at the falling edge of SCLK so that the host processor can read it at the next rising edge. Serial data input is latched at the falling edge of SCLK. The complete serial I/O cycle starts with the first rising edge of SCLK after the falling edge of FS/CS and ends 16 (see NOTE) falling edges of SCLK later. The serial interface is very flexible. It works with both CPOL = 0 or CPOL = 1. The interface ignores data if a falling edge arrives before the first rising edge. This means the falling edge of FS/CS may fall while SCLK is high. The same relaxation applies to the rising edge of FS/CS where SCLK may be high or low as long as the last SCLK falling edge happens before the rising edge of FS/CS. NOTE: There are cases where a cycle is 4 SCLKs or up to 24 SCLKs depending on the read mode combination. See Table 3 for details. Internal Register The internal register consists of two parts, 4 bits for the command register (CMR) and 12 bits for configuration data register (CFR). Table 3. Command Set Defined by Command Register (CMR) (1) D[15:12] 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110 1111b (1) (2) HEX 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh COMMAND Select analog input channel 0 (2) Select analog input channel 1 (2) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Wake up Read CFR Read data Write CFR Default mode (load CFR with default value) D[11:0] Don't care Don't care Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Don't care Don't care Don't care CFR Value Don't care WAKE UP FROM AUTO NAP Y Y Y Y Y Y Y Y – – – Y – – – Y MINIMUM SCLKs REQUIRED 4 4 4 4 4 4 4 4 – – – 4 16 16 16 4 R/W – – – – – – – – – – – W R R W W When SDO is not in 3-state (FS/CS low and SCLK running), the bits from SDO are always part (depending on how many SCLKs are supplied) of the previous conversion result. These two commands apply to the ADS8330 only. WRITING TO THE CONVERTER There are two different types of writes to the register, a 4-bit write to the CMR and a full 16-bit write to the CMR plus CFR. The command set is listed in Table 3. A simple command requires only 4 SCLKs and the write takes effect at the 4th falling edge of SCLK. A 16-bit write or read takes at least 16 SCLKs (see Table 5 for exceptions that require more than 16 SCLKs). Submit Documentation Feedback 29 ADS8329 ADS8330 SLAS516 – DECEMBER 2006 www.ti.com Configuring the Converter and Default Mode The converter can be configuring with command 1110b (write to the CFR) or command 1111b (default mode). A write to the CFR requires a 4-bit command followed by 12-bits of data. A 4-bit command takes effect at the 4th falling edge of SCLK. A CFR write takes effect at the 16th falling edge of SCLK. A default mode command can be achieved by simply tying SDI to +VBD. As soon as the chip is selected at least four 1s are clocked in by SCLK. The default value of the CFR is loaded into the CFR at the 4th falling edge of SCLK. CFR default values are all 1s (except for CFR_D1, this bit is ignored by the ADS8329 and is always read as a 0). The same default values apply for the CFR after a power-on reset (POR) and SW reset. READING THE CONFIGURATION REGISTER The host processor can read back the value programmed in the CFR by issuing command 1100b. The timing is similar to reading a conversion result except CONVST is not used and there is no activity on the EOC/INT pin. The CFR value read back contains the first four MSBs of conversion data plus valid 12-bit CFR contents. Table 4. Configuration Register (CFR) Map SDI BIT CFR - D[11 - 0] Channel select mode D11 Default = 1 0: Manual channel select enabled. Use channel select commands to access a different channel. Conversion clock (CCLK) source select 0: Conversion clock (CCLK) = SCLK/2 1: Conversion clock (CCLK) = Internal OSC 1: Auto channel select enabled. All channels are sampled and converted sequentially until the cycle after this bit is set to 0. DEFINITION D10 Default = 1 D9 Default = 1 D8 Default = 1 D7 Default = 1 Trigger (conversion start) select: start conversion at the end of sampling (EOS). If D9 = 0, the D4 setting is ignored. 0: Auto trigger automatically starts (4 internal clocks after EOC inactive) Don't care Pin 10 polarity select when used as an output (EOC/INT) 0: EOC Active high / INT active high Pin 10 function select when used as an output (EOC/INT) 0: Pin used as INT Pin 10 I/O select for chain mode operation 0: Pin 10 is used as CDI input (chain mode enabled) 1: Pin 10 is used as EOC/INT output 1: Pin used as EOC 1: EOC Active low / INT active low 1: Manual trigger manually started by falling edge of CONVST Don't care D6 Default = 1 D5 Default = 1 D4 Default = 1 Auto nap powerdown enable/disable (mid voltage and comparator shut down between cycles). This bit setting is ignored if D9 = 0. 0: Auto nap powerdown enabled (not activated) 1: Auto nap powerdown disabled D3 Default = 1 Nap powerdown (mid voltage and comparator shut down between cycles). This bit is set to 1 automatically by wake-up command. 0: Enable/activate device in nap powerdown Deep powerdown. This bit is set to 1 automatically by wake-up command. 0: Enable/activate device in deep powerdown TAG bit enable. This bit is ignored by the ADS8329 and is alway read 0. 0: TAG bit disabled. Reset 0: System reset 1: Normal operation 1: TAG bit output enabled. TAG bit appears at the 17th SCLK. 1: Remove device from deep powerdown (resume) 1: Remove device from nap powerdown (resume) D2 Default = 1 D1 Default = 0: ADS8329 1: ADS8330 D0 Default = 1 READING CONVERSION RESULT The conversion result is available to the input of the output data register (ODR) at EOC and presented to the output of the output register at the next falling edge of CS or FS. The host processor can then shift the data out via the SDO pin any time except during the quiet zone. This is 20 ns before and 20 ns after the end of sampling (EOS) period. End of sampling (EOS) is defined as the falling edge of CONVST when manual trigger is used or the end of the 3rd conversion clock (CCLK) after EOC if auto trigger is used. 30 Submit Documentation Feedback www.ti.com ADS8329 ADS8330 SLAS516 – DECEMBER 2006 The falling edge of FS/CS should not be placed at the precise moment (minimum of at least one conversion clock (CCLK) delay) at the end of a conversion (by default when EOC goes high), otherwise the data is corrupt. If FS/CS is placed before the end of a conversion, the previous conversion result is read. If FS/CS is placed after the end of a conversion, the current conversion result is read. The conversion result is 16-bit data in straight binary format as shown in Table 4. Generally 16 SCLKs are necessary, but there are exceptions where more than 16 SCLKS are required (see Table 5). Data output from the serial output (SDO) is left adjusted MSB first. The trailing bits are filled with the TAG bit first (if enabled) plus all zeros. SDO remains low until FS/CS is brought high again. SDO is active when FS/CS is low. The rising edge of FS/CS 3-states the SDO output. NOTE: Whenever SDO is not in 3-state (when FS/CS is low and SCLK is running), a portion of the conversion result is output at the SDO pin. The number of bits depends on how many SCLKs are supplied. For example, a manual select channel command cycle requires 4 SCLKs, therefore 4 MSBs of the conversion result are output at SDO. The exception is SDO outputs all 1s during the cycle immediately after any reset (POR or software reset). If SCLK is used as the conversion clock (CCLK) and a continuous SCLK is used, it is not possible to clock out all 16 SDO bits during the sampling time (6 SCLKs) because of the quiet zone requirement. In this case it is better to read the conversion result during the conversion time (36 SCLKs or 48 SCLKs in auto nap mode). Table 5. Ideal Input Voltages and Output Codes DESCRIPTION Full scale range Least significant bit (LSB) Full scale Midscale Midscale – 1 LSB Zero Vref Vref/65536 +Vref– 1 LSB Vref/2 Vref/2– 1 LSB 0V ANALOG VALUE DIGITAL OUTPUT STRAIGHT BINARY BINARY CODE 1111 1111 1111 1111 1000 0000 0000 0000 0111 1111 1111 1111 0000 0000 0000 0000 HEX CODE FFFF 8000 7FFF 0000 TAG Mode The ADS8330 includes a feature, TAG, that can be used as a tag to indicate which channel sourced the converted result. An address bit is added after the LSB read out from SDO indicating which channel the result came from if TAG mode is enabled. This address bit is 0 for channel 0 and 1 for channel 1. The converter requires more than the 16 SCLKs that are required for a 4 bit command plus 12 bit CFR or 16 data bits because of the additional TAG bit. Chain Mode The ADS8329/30 can operate as a single converter or in a system with multiple converters. System designers can take advantage of the simple high-speed SPI compatible serial interface by cascading them in a single chain when multiple converters are used. A bit in the CFR is used to reconfigure the EOC/INT status pin as a secondary serial data input, chain data input (CDI), for the conversion result from an upstream converter. This is chain mode operation. A typical connection of three converters is shown in Figure 59. Submit Documentation Feedback 31 ADS8329 ADS8330 SLAS516 – DECEMBER 2006 www.ti.com Micro Controller INT GPIO1 GPIO2 GPIO3 SDOSCLK SDI SDI SCLK CONVST CS ADS8329 #1 SDO EOC/INT SDI SCLK CONVST CS ADS8329 #2 CDI SDO SDI SCLK CONVST CS ADS8329 #3 CDI SDO Program device #1 CFR_D[7:5] = XX0b Program device #2 and #3 CFR_D[7:5] = XX1b Figure 59. Multiple Converters Connected Using Chain Mode When multiple converters are used in chain mode, the first converter is configured in regular mode while the rest of the converters downstream are configured in chain mode. When a converter is configured in chain mode, the CDI input data goes straight to the output register, therefore the serial input data passes through the converter with a 16 SCLK (if the TAG feature is disabled) or a 24 SCLK delay, as long as CS is active. See Figure 60 for detailed timing. In this timing the conversion in each converters are done simultaneously. Cascaded Manual Trigger/Read While Sampling (Use internal CCLK, EOC active low, and INT active low) CS held low during the N times 16 bits transfer cycle. CONVST #1, CONVST #2, CONVST #3 EOC #1 (active low) INT #3 (active low) CS/FS #1 SCLK #1, SCLK #2, SCLK #3 SDO #1, CDI #2 CS/FS #2, CS/FS #3 SDO #2, CDI #3 Hi-Z td(SDO-CDI) N − 1th from #2 Nth from #1 Nth from #1 1 . . . . . . . . . . . . . . . . . . 16 1 . . . . . . . . . . . . . . . . . . 16 EOS Nth EOC tCONV = 18 CCLKs tSAMPLE1 = 3 CCLKs min td(CSR-EOS) = 20 ns min 1 . . . . . . . . . . . . . . . . . . 16 Hi-Z Nth from #1 Hi-Z td(CSR-EOS) = 20 ns min Hi-Z SDO #3 SDI #1, SDI #2, SDI #3 Hi-Z td(SDO-CDI) Nth from #3 N − 1th from #2 Nth from #1 Hi-Z 1110............ 1101b 1101b CONFIGURE READ Result READ Result Figure 60. Simplified Cascade Mode Timing with Shared CONVST and Continuous CS 32 Submit Documentation Feedback EOS www.ti.com ADS8329 ADS8330 SLAS516 – DECEMBER 2006 Care must be given to handle the multiple CS signals when the converters are operating in chain mode. The different chip select signals must be low for the entire data transfer (in this example 48 bits for three converters). The first 16-bit word after the falling chip select is always the data from the chip that received the chip select signal. Case 1: If chip select is not toggled (CS stays low), the next 16 bits are data from the upstream converter, and so on. This is shown in Figure 60. If there is no upstream converter in the chain, as converter #1 in the example, the same data from the converter is going to be shown repeatedly. Case 2: If the chip select is toggled during a chain mode data transfer cycle, as illustrated in Figure 61, the same data from the converter is read out again and again in all three discrete 16-bit cycles. This is not a desired result. Cascaded Manual Trigger/Read While Sampling (Use internal CCLK, EOC, and INT polarity programmed as active low) CS held low during the N times 16 bits transfer cycle. CONVST #1, CONVST #2, CONVST #3 EOC #1 (active low) INT #1 (active low) CS/FS #1 SCLK #1, SCLK #2, SCLK #3 SDO #1, CDI #2 CS/FS #2 SCLK #2, SDO #2, CDI #3 CS/FS #3 SDO #3 SDI #1, SDI #2, SDI #3 Nth from #3 1110............ N − 1th from #2 1101b 1101b Nth from #1 1 16 1 16 1 16 These SCLKs are optional. EOC EOS Nth tCONV = 18 CCLKs tSAMPLE1 = 3 CCLKs min td(EOS-CSF) = 20 ns min td(CSR-EOS) = 20 ns min Nth from #1 Nth from #1 Nth from #1 td(EOS-CSF) = 20 ns min td(CSR-EOS) = 20 ns min N − 1th from #2 Nth from #1 td(EOS-CSF) = 20 ns min Nth from #1 td(CSR-EOS) = 20 ns min CONFIGURE READ Result READ Result Figure 61. Simplified Cascade Mode Timing with Shared CONVST and Discrete CS Figure 62 shows a slightly different scenario where CONVST is not shared by the second converter. Converters #1 and #3 have the same CONVST signal. In this case, converter #2 simply passes previous conversion data downstream. EOS Submit Documentation Feedback 33 ADS8329 ADS8330 SLAS516 – DECEMBER 2006 www.ti.com Cascaded Manual Trigger/Read While Sampling (Use internal CCLK, EOC active low and INT active low) CS held low during the N times 16 bits transfer cycle. CONVST #1, CONVST #3 Note : old data shown. EOS EOC EOC #1 (active low) INT #1 (active low) CS/FS #1 SCLK #1, SCLK #2, SCLK #3 SDO #1, CDI #2 CS/FS #2, CS/FS #3 SDO #2, CDI #3 Nth tCONV = 18 CCLKs tSAMPLE1 = 3 CCLKs min td(CSR-EOS) = 20 ns min 1 . . . . . . . . . . . . . . . . . .16 1 . . . . . . . . . . . . . . . . . .16 1 . . . . . . . . . . . . . . . . . .16 Hi-Z Nth from #1 Hi-Z td(CSR-EOS) = 20 ns min td(SDO-CDI) Hi-Z N − 1th from #2 Nth from #1 Hi-Z SDO #3 SDI #1, SDI #2, SDI #3 Hi-Z td(SDO-CDI) Nth from #3 1110............ 1101b N − 1th from #2 Nth from #1 1101b Hi-Z CONFIGURE READ Result READ Result Figure 62. Simplified Cascade Timing (Separate CONVST) The number of SCLKs required for a serial read cycle depends on the combination of different read modes, TAG bit, chain mode, and the way a channel is selected, i.e., auto channel select. This is listed in Table 6. Table 6. Required SCLKs For Different Read Out Mode Combinations CHAIN MODE AUTO CHANNEL TAG ENABLED CFR.D1 ENABLED CFR.D5 SELECT CFR.D11 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 NUMBER OF SCLK PER SPI READ 16 ≥17 16 ≥17 16 24 16 24 None MSB is TAG bit plus zero(s) None TAG bit plus 7 zeros None TAG bit plus 7 zeros None TAG bit plus 7 zeros TRAILING BITS 34 Submit Documentation Feedback EOS CONVST #2 = 1 www.ti.com ADS8329 ADS8330 SLAS516 – DECEMBER 2006 SCLK skew between converters and data path delay through the converters configured in chain mode can affect the maximum frequency of SCLK. The delay can also be affected by supply voltage and loading. It may be necessary to slow down the SCLK when the devices are configured in chain mode. ADS8329 # 3 CDI Logic Delay Plus PAD 2.7 ns Logic D Delay < = 8 .3 ns CLK Q Logic Delay Plus PAD 8.3 ns SDO Serial data output ADS8329 # 2 CDI Logic Delay Plus PAD 2.7 ns Logic D Delay < = 8 .3 ns CLK Q Logic Delay Plus PAD 8.3 ns SDO ADS8329 # 1 CDI Logic Delay Plus PAD 2.7 ns Logic D Delay < = 8 .3 ns CLK Q Logic Delay Plus PAD 8.3 ns SDO Serial data input SCLK input Figure 63. Typical Delay Through Converters Configured in Chain Mode RESET The converter has two reset mechanisms, a power-on reset (POR) and a software reset using CFR_D0. These two mechanisms are NOR-ed internally. When a reset (software or POR) is issued, all register data are set to the default values (all 1s) and the SDO output (during the cycle immediately after reset) is set to all 1s. The state machine is reset to the power-on state. SW RESET POR SET SAR Shift Register Conversion Clock Latched by End Of Conversion EOC EOC Latched by Falling Edge of CS CS Intermediate Latch Output Register SDO SCLK CDI Figure 64. Digital Output Under Reset Condition Submit Documentation Feedback 35 ADS8329 ADS8330 SLAS516 – DECEMBER 2006 www.ti.com APPLICATION INFORMATION TYPICAL CONNECTION Analog +5 V 4.7 mF AGND Ext Ref Input 22 mF AGND +VA REF+ REF− AGND IN+ IN− FS/CS SDO SDI SCLK Interface Supply +1.8 V BDGND CONVST 4.7 mF EOC/INT +VBD Analog Input Host Processor ADS8329 Figure 65. Typical Circuit Configuration 36 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 8-Jan-2007 PACKAGING INFORMATION Orderable Device ADS8329IBRSAR ADS8329IBRSARG4 ADS8329IBRSAT ADS8329IBRSATG4 ADS8329IRSAR ADS8329IRSARG4 ADS8329IRSAT ADS8329IRSATG4 ADS8330IBRSAR ADS8330IBRSARG4 ADS8330IBRSAT ADS8330IBRSATG4 ADS8330IRSAR ADS8330IRSARG4 ADS8330IRSAT ADS8330IRSATG4 (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type QFN QFN QFN QFN QFN QFN QFN QFN QFN QFN QFN QFN QFN QFN QFN QFN Package Drawing RSA RSA RSA RSA RSA RSA RSA RSA RSA RSA RSA RSA RSA RSA RSA RSA Pins Package Eco Plan (2) Qty 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 3000 Green (RoHS & no Sb/Br) 3000 Green (RoHS & no Sb/Br) 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) 3000 Green (RoHS & no Sb/Br) 3000 Green (RoHS & no Sb/Br) 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) 3000 Green (RoHS & no Sb/Br) 3000 Green (RoHS & no Sb/Br) 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 8-Jan-2007 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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