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ADS8331, ADS8332
SBAS363E – DECEMBER 2009 – REVISED AUGUST 2016
ADS833x Low-Power, 16-Bit, 500-kSPS, 4- and 8-Channel Unipolar Input
Analog-to-Digital Converters With Serial Interface
1 Features
2 Applications
•
•
•
•
•
•
•
•
1
•
•
•
•
•
•
Low-Power, Flexible Supply Range:
– 2.7-V to 5.5-V Analog Supply
– 8.7 mW (250 kSPS in Auto-NAP Mode,
VA = 2.7 V, VBD = 1.65 V)
– 14.2 mW (500 kSPS, VA = 2.7 V,
VBD = 1.65 V)
Up to 500-kSPS Sampling Rate
Excellent DC Performance:
– ±1.2 LSB Typical, ±2 LSB Maximum INL at
2.7 V
– ±0.6 LSB Typical, –1, 1.5 LSB Maximum DNL
at 2.7 V
– 16-Bit NMC Over Temperature
Excellent AC Performance at 5 V, fIN = 1 kHz:
– 91.5-dB SNR, 101-dB SFDR, –100-dB THD
Flexible Analog Input Arrangement:
– On-Chip 4-, 8-Channel Mux With Breakout
– Auto, Manual Channel Select and Trigger
Other Hardware Features:
– On-Chip Conversion Clock (CCLK)
– Software, Hardware Reset
– Programmable Status, Polarity EOC/INT
– Daisy-Chain Mode
– Global CONVST (Independent of CS)
– Deep, Nap, and Auto-NAP Powerdown Modes
– SPI™, DSP Compatible Serial Interface
– Separate I/O Supply: 1.65 V to VA
– SCLK up to 40 MHz (VA = VBD = 5 V)
24-Pin 4-mm × 4-mm VQFN and 24-Pin TSSOP
Packages
Communications
Transducer Interfaces
Medical Instruments
Magnetometers
Industrial Process Controls
Data Acquisition Systems
Automatic Test Equipment
3 Description
The ADS8331 is a low-power, 16-bit, 500-k samplesper-second (SPS) analog-to-digital converter (ADC)
with a unipolar, 4-to-1 multiplexer (mux) input. The
device includes a 16-bit capacitor-based successive
approximation register (SAR) ADC with inherent
sample and hold.
The ADS8332 is based on the same core and
includes a unipolar 8-to-1 input mux. Both devices
offer a high-speed, wide-voltage serial interface and
are capable of daisy-chain operation when multiple
converters are used.
These converters are available in 24-pin, 4 × 4 VQFN
and 24-pin TSSOP packages and are fully specified
for operation over the industrial –40°C to 85°C
temperature range.
Device Information(1)
PART NUMBER
ADS833x
PACKAGE
BODY SIZE (NOM)
VQFN (24)
4.00 mm × 4.00 mm
TSSOP (24)
7.80 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Block Diagram
MUXOUT
IN[0:3]
or
IN[0:7]
ADCIN
SAR
M
U
X
+
_
COM
REF+
REF-
Output
Latch
and
3-State
Driver
SDO
CDAC
FS/CS
Comparator
Conversion
and
Control
Logic
SCLK
SDI
CONVST
EOC/INT/CDI
RESET
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS8331, ADS8332
SBAS363E – DECEMBER 2009 – REVISED AUGUST 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Companion Products.............................................
Device Comparison ...............................................
Pin Configuration and Functions .........................
Specifications.........................................................
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
9
1
1
1
2
3
4
4
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics: VA = 2.7 V ....................... 7
Electrical Characteristics: VA = 5 V .......................... 9
Timing Requirements: VA = 2.7 V .......................... 11
Timing Characteristics: VA = 5 V ............................ 12
Typical Characteristics: DC Performance ............... 14
Typical Characteristics: AC Performance ............. 17
Detailed Description ............................................ 20
9.1 Overview ................................................................. 20
9.2
9.3
9.4
9.5
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
20
20
22
29
10 Application and Implementation........................ 37
10.1 Application Information.......................................... 37
10.2 Typical Applications ............................................. 41
11 Power Supply Recommendations ..................... 44
12 Layout................................................................... 44
12.1 Layout Guidelines ................................................. 44
12.2 Layout Example .................................................... 46
13 Device and Documentation Support ................. 47
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
47
47
47
47
47
47
48
14 Mechanical, Packaging, and Orderable
Information ........................................................... 48
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (October 2015) to Revision E
•
Page
Changed VA parameter maximum specification in Recommended Operating Conditions table ........................................... 6
Changes from Revision C (May 2012) to Revision D
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
Changes from Revision B (December 2010) to Revision C
Page
•
Changed name of last column in Low-Power, High-Speed, SAR Converter Family table..................................................... 4
•
Deleted 4-channel and 8-channel rows from 14-Bit Pseudo-Diff resolution in Low-Power, High-Speed, SAR
Converter Family table ........................................................................................................................................................... 4
•
Added last paragraph to Start of a Conversion section........................................................................................................ 25
•
Changed VA value from 3.3 V to 2.7 V and VREF value from 4.096 V to 2.5 V.................................................................... 38
Changes from Revision A (November 2010) to Revision B
•
2
Page
Deleted Ordering Information table ....................................................................................................................................... 6
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Copyright © 2009–2016, Texas Instruments Incorporated
Product Folder Links: ADS8331 ADS8332
ADS8331, ADS8332
www.ti.com
SBAS363E – DECEMBER 2009 – REVISED AUGUST 2016
5 Companion Products
Part number
Name
REF3240
4.096V 4ppm/°C, 100uA SOT23-6 Series (Bandgap) Voltage Reference
DAC8562
16-bit, dual-channel, low-power, ultra-low glitch, buffered voltage output DAC with 2.5V,4ppm/°C ref
DAC8568
16-bit, octal-channel, ultra-low glitch, voltage output DAC with 2.5V, 2ppm/°C internal reference
LM5160
OPA2348
Wide Input 65V, 1.5A Synchronous Step-Down DC-DC Conv
1MHz, 45uA, RRIO, Dual Op Amp
Copyright © 2009–2016, Texas Instruments Incorporated
Product Folder Links: ADS8331 ADS8332
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ADS8331, ADS8332
SBAS363E – DECEMBER 2009 – REVISED AUGUST 2016
www.ti.com
6 Device Comparison
RESOLUTION
CHANNELS
fS ≤ 250 kSPS
250 kSPS < fS ≤ 500 kSPS
500 kSPS < fS ≤ 1 MSPS
8
—
ADS8698
—
4
—
ADS8694
—
18 bits
8
16 bits
4
ADS8344
ADS8688
ADS8345
ADS8688A
ADS8341
ADS8684
—
ADS8342
ADS8343
TLC3548
8
TLC3578
14 bits
TLC3544
4
TLC3574
—
ADS8684A
ADS8678
—
ADS8674
ADS7263
7 Pin Configuration and Functions
PW Package
24-Pin TSSOP
Top View
IN3
IN2
IN1
IN0
COM
MUXOUT
24
23
22
21
20
19
RGE Package
24-Pin VQFN With Exposed Thermal Pad
Top View
IN1
1
24
IN0
IN2
2
23
COM
IN3
3
22
MUXOUT
IN4/NC(3)
4
21
ADCIN
IN5/NC(3)
5
20
AGND
IN6/NC(3)
6
19
REF-
IN4/NC(1)
1
18
ADCIN
IN7/NC(3)
7
18
REF+
RESET
8
17
VA
IN5/NC
(1)
2
17
AGND
IN6/NC
(1)
3
16
REF-
IN7/NC
(1)
4
15
REF+
RESET
5
14
VA
EOC/INT/CDI
6
13
VBD
SDO
(1)
NC = No internal connection (ADS8331 only).
(2)
Connect thermal pad to analog ground.
(3)
NC = No internal connection (ADS8331 only).
Thermal Pad
(Bottom Side)
12
13
CONVST
12
11
SDI
(2)
DGND
DGND
10
14
SDO
11
9
FS/CS
ADS8331
ADS8332
SDI
CONVST
8
VBD
15
FS/CS
16
10
7
9
SCLK
EOC/INT/CDI
SCLK
ADS8331
ADS8332
Pin Functions: ADS8331
PIN
I/O
DESCRIPTION
NAME
TSSOP
VQFN
ADCIN
21
18
I
AGND
20
17
—
Analog ground
DGND
14
11
—
Digital interface ground
COM
23
20
I
Common ADC input (usually connected to AGND)
CONVST
15
12
I
Conversion start. Freezes sample and hold, starts conversion.
4
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ADC input
Copyright © 2009–2016, Texas Instruments Incorporated
Product Folder Links: ADS8331 ADS8332
ADS8331, ADS8332
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SBAS363E – DECEMBER 2009 – REVISED AUGUST 2016
Pin Functions: ADS8331 (continued)
PIN
NAME
TSSOP
EOC/INT/CDI
9
I/O
DESCRIPTION
6
O/O/I
Status output. If programmed as end-of-conversion (EOC), this pin is low (default) when a
conversion is in progress. If programmed as an interrupt (INT), this pin is low (default) after
the end of conversion and returns high after FS/CS goes low. The polarity of EOC or INT is
programmable.
This pin can also be used as a chain data input (CDI) when operated in daisy-chain mode.
VQFN
FS/CS
11
8
I
Frame sync signal for DSP (such as TMS320™ DSP) or chip select input for SPI.
IN[0:3]
1-3, 24
21-24
I
Mux inputs
NC
4-7
1-4
—
No connection
MUXOUT
22
19
O
Mux output
REF+
18
15
I
External reference input
REF–
19
16
—
RESET
8
5
I
External reset (active low)
SCLK
10
7
I
SPI clock for serial interface
SDI
12
9
I
SPI serial data in
SDO
13
10
O
SPI serial data out
VA
17
14
—
Analog supply, 2.7 V to 5.5 V
VBD
16
13
—
Digital interface supply
External reference ground (connect to AGND through an individual via on the printed-circuitboard)
Pin Functions: ADS8332
PIN
I/O
DESCRIPTION
NAME
TSSOP
VQFN
ADCIN
21
18
I
AGND
20
17
—
Analog ground
DGND
14
11
—
Digital interface ground
COM
23
20
I
Common ADC input (usually connected to AGND)
CONVST
15
12
I
Conversion start. Freezes sample and hold, starts conversion.
EOC/INT/CDI
9
6
O/O/I
ADC input
Status output. If programmed as end-of-conversion (EOC), this pin is low (default) when a
conversion is in progress. If programmed as an interrupt (INT), this pin is low (default) after
the end of conversion and returns high after FS/CS goes low. The polarity of EOC or INT is
programmable.
This pin can also be used as a chain data input (CDI) when operated in daisy-chain mode.
FS/CS
11
8
I
Frame sync signal for DSP (such as TMS320™ DSP) or chip select input for SPI.
IN[0:7]
1-7, 24
1-4, 2124
I
Mux inputs
MUXOUT
22
19
O
Mux output
REF+
18
15
I
External reference input
REF–
19
16
—
RESET
8
5
I
External reset (active low)
SCLK
10
7
I
SPI clock for serial interface
SDI
12
9
I
SPI serial data in
SDO
13
10
O
SPI serial data out
VA
17
14
—
Analog supply, 2.7 V to 5.5 V
VBD
16
13
—
Digital interface supply
External reference ground (connect to AGND through an individual via on the printed-circuitboard)
Copyright © 2009–2016, Texas Instruments Incorporated
Product Folder Links: ADS8331 ADS8332
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ADS8331, ADS8332
SBAS363E – DECEMBER 2009 – REVISED AUGUST 2016
www.ti.com
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Voltage
MIN
MAX
INX, MUXOUT, ADCIN, REF+ to AGND
–0.3
VA + 0.3
UNIT
COM, REF– to AGND
–0.3
0.3
VA to AGND
–0.3
7
VBD to DGND
–0.3
7
AGND to DGND
V
–0.3
0.3
Digital input voltage to DGND
–0.3
VBD + 0.3
V
Digital output voltage to DGND
–0.3
VBD + 0.3
V
4×4
VQFN-24
Package
Power dissipation
TSSOP-24
Package
Power dissipation
(TJMax – TA) / RθJA
RθJA thermal impedance
°C/W
(TJMax – TA) / θJA
RθJA thermal impedance
Operating free-air temperature, TA
–40
Junction temperature, TJ Max
Storage temperature range, Tstg
(1)
W
47
–65
W
47
°C/W
85
°C
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
8.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
VA
Analog supply voltage
2.7
3
5.5
UNIT
V
VBD
Digital supply voltage
1.65
3
VA + 0.2
V
8.4 Thermal Information
ADS833x
THERMAL METRIC (1)
RGE (VQFN)
PW (TSSOP)
24 PINS
24 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
31.9
78.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
29.2
12.1
°C/W
RθJB
Junction-to-board thermal resistance
8.7
33.8
°C/W
ψJT
Junction-to-top characterization parameter
0.3
0.3
°C/W
ψJB
Junction-to-board characterization parameter
8.7
33.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.25
NA
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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Copyright © 2009–2016, Texas Instruments Incorporated
Product Folder Links: ADS8331 ADS8332
ADS8331, ADS8332
www.ti.com
SBAS363E – DECEMBER 2009 – REVISED AUGUST 2016
8.5 Electrical Characteristics: VA = 2.7 V
at TA = –40°C to 85°C, VA = 2.7 V, VBD = 1.65 V to 2.7 V, VREF = 2.5 V, and fSAMPLE = 500 kSPS (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
ANALOG INPUT
Full-scale input voltage
(1)
Absolute input voltage
INX – COM, ADCIN – COM
0
VREF
INX, ADCIN
AGND – 0.2
VA + 0.2
COM
AGND – 0.2
AGND + 0.2
V
Input capacitance
ADCIN
40
Input leakage current
Unselected ADC input
±1
45
nA
pF
16
Bits
SYSTEM PERFORMANCE
Resolution
No missing codes
INL
Integral linearity
DNL
Differential linearity
EO
Offset error (3)
16
–3
±2
3
ADS8331IB, ADS8332IB
–2
±1.2
2
ADS8331I, ADS8332I
–1
±0.6
2
ADS8331IB, ADS8332IB
–1
±0.6
1.5
–0.5
±0.15
0.5
Offset error drift
±1
Offset error matching
EG
–0.2
Gain error
–0.25
Gain error drift
–0.06
–0.003
LSB (2)
LSB (2)
mV
PPM/°C
0.2
mV
0.25
%FSR
±0.4
Gain error matching
PSRR
Bits
ADS8331I, ADS8332I
PPM/°C
0.003
%FSR
Transition noise
28
μV RMS
Power-supply rejection ratio
74
dB
18
CCLK
SAMPLING DYNAMICS
tCONV
tSAMPLE1
tSAMPLE2
Conversion time
Manual-trigger mode
Acquisition time
3
Auto-trigger mode
CCLK
3
Throughput rate
500
kSPS
DYNAMIC CHARACTERISTICS
THD
Total harmonic distortion
(4)
VIN = 2.5 VPP at 1 kHz
–101
VIN = 2.5 VPP at 10 kHz
–95
VIN = 2.5 VPP at 1 kHz
SNR
Signal-to-noise ratio
VIN = 2.5 VPP at 10 kHz
VIN = 2.5 VPP at 1 kHz
SINAD
Signal-to-noise + distortion
VIN = 2.5 VPP at 10 kHz
SFDR
Spurious-free dynamic range
Crosstalk
–3-dB small-signal bandwidth
(1)
(2)
(3)
(4)
ADS8331I, ADS8332I
ADS8331IB, ADS8332IB
88
89
ADS8331I, ADS8332I
86.5
ADS8331IB, ADS8332IB
87.5
ADS8331I, ADS8332I
87.5
ADS8331IB, ADS8332IB
88.5
ADS8331I, ADS8332I
ADS8331IB, ADS8332IB
dB
86
dB
dB
87
VIN = 2.5 VPP at 1 kHz
103
VIN = 2.5 VPP at 10 kHz
98
VIN = 2.5 VPP at 1 kHz
125
VIN = 2.5 VPP at 100 kHz
108
INX – COM with MUXOUT tied to ADCIN
17
ADCIN – COM
30
dB
dB
MHz
Ideal input span; does not include gain or offset error.
LSB means least significant bit.
Measured relative to an ideal full-scale input (INX – COM) of 2.5 V when VA = 2.7 V.
Calculated on the first nine harmonics of the input frequency.
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Electrical Characteristics: VA = 2.7 V (continued)
at TA = –40°C to 85°C, VA = 2.7 V, VBD = 1.65 V to 2.7 V, VREF = 2.5 V, and fSAMPLE = 500 kSPS (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
10.5
11
12.2
MHz
CLOCK
Internal conversion clock
frequency
25
MHz
1
21
MHz
(REF+) – (REF–)
1.2
2.525
(REF–) – AGND
–0.1
0.1
SCLK external serial clock
Used as I/O clock only
Used as both I/O clock and conversion clock
EXTERNAL VOLTAGE REFERENCE INPUT
VREF
Input
reference
range (5)
Resistance
(6)
Reference input
20
V
kΩ
DIGITAL INPUT/OUTPUT
Logic family
CMOS
1.65 V < VBD < 2.5 V
VIH
High-level input voltage
VIL
Low-level input voltage
II
Input current
CI
Input capacitance
VOH
High-level output voltage
VA ≥ VBD ≥ 1.65V, IO = 100 μA
VOL
Low-level output voltage
VA ≥ VBD ≥ 1.65 V, IO = –100 μA
CO
SDO pin capacitance
Hi-Z state
CL
Load capacitance
2.5 V ≤ VBD ≤ VA
0.8 × VBD
VBD + 0.3
0.65 × VBD
VBD + 0.3
1.65 < VBD < 2.5 V
–0.3
0.1 × VBD
2.5 V ≤ VBD ≤ VA
–0.3
0.25 × VBD
VIN = VBD or DGND
–1
1
5
V
μA
pF
VBD – 0.6
VBD
0
0.4
5
Data format
V
V
V
pF
30
pF
Straight binary
POWER-SUPPLY REQUIREMENTS
VA
Analog supply voltage (5)
2.7
3.6
V
VBD
Digital I/O supply voltage
1.65
VA + 0.2
V
IA
IBD
Analog supply current
Digital I/O supply current
Power dissipation
fSAMPLE = 500 kSPS
5.2
fSAMPLE = 250 kSPS in Auto-NAP mode
3.2
Nap mode, SCLK = VBD or DGND
6.5
mA
325
400
μA
Deep PD mode, SCLK = VBD or DGND
50
250
nA
fSAMPLE = 500 kilobytes per second
0.1
0.4
fSAMPLE = 250 kSPS in Auto-NAP mode
0.05
VA = 2.7 V, VBD = 1.65 V, fSAMPLE = 500 kSPS
14.2
VA = 2.7V, VBD = 1.65 V, fSAMPLE = 250 kSPS in AutoNAP mode
8.72
mA
18.2
mW
TEMPERATURE RANGE
TA
(5)
(6)
8
Operating free-air temperature
–40
85
°C
The ADS8331, ADS8332 operates with VA from 2.7 V to 5.5 V, and VREF between 1.2 V and VA. However, the device may not meet the
specifications listed in the Electrical Characteristics when VA is from 3.6 V to 4.5 V.
Can vary ±30%.
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Product Folder Links: ADS8331 ADS8332
ADS8331, ADS8332
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SBAS363E – DECEMBER 2009 – REVISED AUGUST 2016
8.6 Electrical Characteristics: VA = 5 V
at TA = –40°C to 85°C, VA = 5 V, VBD = 1.65 V to 5 V, VREF = 4.096 V, and fSAMPLE = 500 kSPS (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
ANALOG INPUT
Full-scale input voltage
(1)
INX – COM, ADCIN – COM
Absolute input voltage
0
VREF
INX, ADCIN
AGND – 0.2
VA + 0.2
COM
AGND – 0.2
AGND + 0.2
V
Input capacitance
ADCIN
40
Input leakage current
Unselected ADC input
±1
45
nA
pF
16
Bits
SYSTEM PERFORMANCE
Resolution
No missing codes
INL
Integral linearity
DNL
Differential linearity
EO
Offset error (3)
16
–3
±2
3
ADS8331IB, ADS8332IB
–2
±1
2
ADS8331I, ADS8332I
–1
±1
2
ADS8331IB, ADS8332IB
–1
±0.5
1.5
–1
±0.23
1
Offset error drift
±1
Offset error matching
EG
–0.125
Gain error
–0.25
Gain error drift
–0.06
–0.003
LSB (2)
LSB (2)
mV
PPM/°C
0.125
mV
0.25
%FSR
±0.02
Gain error matching
PSRR
Bits
ADS8331I, ADS8332I
PPM/°C
0.003
%FSR
Transition noise
30
μV RMS
Power-supply rejection ratio
78
dB
18
CCLK
SAMPLING DYNAMICS
tCONV
tSAMPLE1
tSAMPLE2
Conversion time
Manual-trigger mode
Acquisition time
Auto-trigger mode
3
CCLK
3
Throughput rate
500
kSPS
DYNAMIC CHARACTERISTICS
VIN = 4.096 VPP at 1 kHz
THD
Total harmonic distortion
SNR
(4)
VIN = 4.096 VPP at
10 kHz
VIN = 4.096 VPP at
1 kHz
Signal-to-noise ratio
–94
ADS8331IB,
ADS8332IB
–95
ADS8331I,
ADS8332I
90.5
ADS8331IB,
ADS8332IB
91.5
VIN = 4.096 VPP at 10 kHz
SINAD
SFDR
VIN = 4.096 VPP at
1 kHz
Signal-to-noise + distortion
Spurious-free dynamic range
Crosstalk
–3-dB small-signal bandwidth
(1)
(2)
(3)
(4)
–100
ADS8331I,
ADS8332I
dB
dB
88
ADS8331I,
ADS8332I
90
ADS8331IB,
ADS8332IB
91
VIN = 4.096 VPP at 10 kHz
87
VIN = 4.096 VPP at 1 kHz
101
VIN = 4.096 VPP at 10 kHz
96
VIN = 4.096 VPP at 1 kHz
119
VIN = 4.096 VPP at 100 kHz
107
INX – COM with MUXOUT tied to
ADCIN
22
ADCIN – COM
40
dB
dB
dB
MHz
Ideal input span; does not include gain or offset error.
LSB means least significant bit.
Measured relative to an ideal full-scale input (INX – COM) of 4.096 V when VA = 5 V.
Calculated on the first nine harmonics of the input frequency.
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Electrical Characteristics: VA = 5 V (continued)
at TA = –40°C to 85°C, VA = 5 V, VBD = 1.65 V to 5 V, VREF = 4.096 V, and fSAMPLE = 500 kSPS (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
10.9
11.5
12.6
MHz
CLOCK
Internal conversion clock frequency
Used as I/O clock only
SCLK external serial clock
40
Used as both I/O clock and conversion
clock
1
21
MHz
EXTERNAL VOLTAGE REFERENCE INPUT
VREF
Input reference
range (5)
Resistance
(REF+) – (REF–)
1.2
(REF–) – AGND
–0.1
(6)
Reference input
4.096
4.2
0.1
20
V
kΩ
DIGITAL INPUT/OUTPUT
Logic family
CMOS
1.65 < VBD < 2.5 V
VIH
High-level input voltage
VIL
Low-level input voltage
II
Input current
CI
Input capacitance
VOH
High-level output voltage
VA ≥ VBD ≥ 1.65 V, IO = 100 μA
VOL
Low-level output voltage
VA ≥ VBD ≥ 1.65 V, IO = –100 μA
CO
SDO pin capacitance
Hi-Z state
CL
Load capacitance
2.5 V ≤ VBD ≤ VA
0.8 × VBD
VBD + 0.3
0.65 × VBD
VBD + 0.3
1.65 < VBD < 2.5 V
–0.3
0.1 × VBD
2.5 V ≤ VBD ≤ VA
–0.3
0.25 × VBD
VIN = VBD or DGND
–1
1
5
V
µA
pF
VBD – 0.6
VBD
0
0.4
5
Data format
V
V
V
pF
30
pF
5.5
V
VA + 0.2
V
Straight binary
POWER-SUPPLY REQUIREMENTS
VA
Analog supply voltage (5)
4.5
VBD
Digital I/O supply voltage
1.65
IA
IBD
Analog supply current
Digital I/O supply current
Power dissipation
5
fSAMPLE = 500 kSPS
6.6
fSAMPLE = 250 kSPS in Auto-NAP mode
4.2
Nap mode, SCLK = VBD or DGND
7.75
mA
390
500
μA
Deep PD mode, SCLK = VBD or
DGND
80
250
nA
fSAMPLE = 500 kSPS
1.2
2
fSAMPLE = 250 kSPS in Auto-NAP mode
0.7
VA = 5 V, VBD = 5 V, fSAMPLE = 500
kSPS
39
VA = 5 V, VBD = 5 V, fSAMPLE = 250
kSPS in Auto-NAP mode
24.5
mA
48.75
mW
TEMPERATURE RANGE
TA
(5)
(6)
10
Operating free-air temperature
–40
85
°C
The ADS8331, ADS8332 operates with VA from 2.7 V to 5.5 V, and VREF between 1.2 V and VA. However, the device may not meet the
specifications listed in the Electrical Characteristics when VA is from 3.6 V to 4.5 V.
Can vary ±30%.
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SBAS363E – DECEMBER 2009 – REVISED AUGUST 2016
8.7 Timing Requirements: VA = 2.7 V
at TA = –40°C to 85°C, VA = 2.7 V, and VBD = 1.65 V (unless otherwise noted) (1) (2)
MIN NOM
External, fCCLK = 1/2 fSCLK
MAX
0.5
10.5
UNIT
fCCLK
Frequency, conversion clock, CCLK
tSU1
Setup time, rising edge of CS to EOC (3)
Read while converting
tH1
CS hold time with respect to EOC (3)
Read while sampling
tWL1
tWH1
tSU2
Setup time, rising edge of CS to EOS
tH2
CS hold time with respect to EOS
tSU3
Setup time, falling edge of CS to first falling edge of SCLK
14
tWL2
Pulse duration, SCLK low
17
tSCLK – tWH2
ns
tWH2
Pulse duration, SCLK high
12
tSCLK – tWL2
ns
Internal
10.5
12.2
MHz
1
CCLK
25
ns
Pulse duration, CONVST low
40
ns
Pulse duration, CS high
40
ns
Read while sampling
25
ns
Read while converting
25
ns
I/O clock only
Cycle time, SCLK
ns
40
I/O and conversion clocks
tSCLK
11
47.6
I/O clock, daisy-chain mode
I/O and conversion clocks,
daisy-chain mode
1000
ns
40
47.6
1000
tD1
Delay time, falling edge of SCLK to SDO invalid
10-pF load
tD2
Delay time, falling edge of SCLK to SDO valid
10-pF load
35
ns
tD3
Delay time, falling edge of CS to SDO valid, SDO MSB output
10-pF load
35
ns
tSU4
Setup time, SDI to falling edge of SCLK
8
ns
tH3
Hold time, SDI to falling edge of SCLK
8
ns
tD4
Delay time, rising edge of CS to SDO 3-state
tSU5
Setup time, last falling edge of SCLK before rising edge of CS
15
ns
tH4
Hold time, last falling edge of SCLK before rising edge of CS
2
ns
ns
tSU6
(4)
8
10-pF load
15
Setup time, rising edge of SCLK to rising edge of CS
10
tH5 (4)
Hold time, rising edge of SCLK to rising edge of CS
2
tD5
Delay time, falling edge of CS to deactivation of INT
(1)
(2)
(3)
(4)
ns
10-pF load
ns
ns
40
ns
All input signals are specified with tr = tf = 1.5 ns (10% to 90% of VBD) and timed from a voltage level of (VIL + VIH) / 2.
See the timing diagrams.
The EOC and EOS signals are the inverse of each other.
Applies to the 5th or 17th rising SCLK when sending 4-bit or 16-bit commands, respectively, to the ADS8331, ADS8332.
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8.8 Timing Characteristics: VA = 5 V
at TA = –40°C to 85°C, and VA = VBD = 5 V (unless otherwise noted) (1) (2)
MIN
External, fCCLK = 1/2 fSCLK
fCCLK
Frequency, conversion clock, CCLK
tSU1
Setup time, rising edge of CS to EOC (3)
Read while converting
tH1
CS hold time with respect to EOC (3)
Read while sampling
tWL1
tWH1
tSU2
Setup time, rising edge of CS to EOS
tH2
CS hold time with respect to EOS
tSU3
Setup time, falling edge of CS to first falling edge of SCLK
tWL2
Pulse duration, SCLK low
tWH2
Pulse duration, SCLK high
Internal
MAX
0.5
10.9
10.5
11.5
12.6
UNIT
MHz
1
CCLK
20
ns
Pulse duration, CONVST low
40
ns
Pulse duration, CS high
40
ns
Read while sampling
20
ns
Read while converting
20
ns
8
I/O clock only
Cycle time, SCLK
ns
12
tSCLK – tWH2
ns
11
tSCLK – tWL2
ns
25
I/O and conversion clocks
tSCLK
TYP
47.6
I/O clock, daisy-chain mode
I/O and conversion clocks,
daisy-chain mode
1000
ns
25
47.6
1000
tD1
Delay time, falling edge of SCLK to SDO invalid
10-pF load
tD2
Delay time, falling edge of SCLK to SDO valid
10-pF load
20
ns
tD3
Delay time, falling edge of CS to SDO valid, SDO MSB output
10-pF load
20
ns
tSU4
Setup time, SDI to falling edge of SCLK
8
ns
tH3
Hold time, SDI to falling edge of SCLK
8
ns
tD4
Delay time, rising edge of CS to SDO 3-state
tSU5
Setup time, last falling edge of SCLK before rising edge of CS
10
ns
tH4
Hold time, last falling edge of SCLK before rising edge of CS
2
ns
ns
tSU6
(4)
5
10-pF load
10
Setup time, rising edge of SCLK to rising edge of CS
10
tH5 (4)
Hold time, rising edge of SCLK to rising edge of CS
2
tD5
Delay time, falling edge of CS to deactivation of INT
(1)
(2)
(3)
(4)
ns
ns
ns
10-pF load
20
ns
All input signals are specified with tr = tf = 1.5 ns (10% to 90% of VBD) and timed from a voltage level of (VIL + VIH) / 2.
See the timing diagrams.
The EOC and EOS signals are the inverse of each other.
Applies to the 5th or 17th rising SCLK when sending 4-bit or 16-bit commands, respectively, to the ADS8331, ADS8332.
tWL1
CONVST
EOC
(active low)
tSU2
tH1
tSU5
CS
tSCLK
SCLK
tD1
SDO
High-Z
MSB
MSB - 1 MSB - 2 MSB - 3
tD3
SDI
'1'
LSB + 1
tD2
LSB
TAG2
X
X
TAG1
tD4
TAG0
'0'
High-Z
'0'
tSU4
'1'
'0'
'1'
X
X
X
X
X
tH3
Figure 1. Read While Sampling (Shown With Manual-Trigger Mode)
12
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SBAS363E – DECEMBER 2009 – REVISED AUGUST 2016
CONVST
21 Conversion Clock Cycles
EOC
(active low)
tH2
tSU1
CS
tWL2
tSU3
tH4
SCLK
tWH2
High-Z
SDO
MSB
LSB
MSB - 1 MSB - 2 MSB - 3
TAG2
tSU5
TAG1
High-Z
TAG0
tD4
'1'
SDI
'1'
'0'
X
'1'
X
X
X
X
Figure 2. Read While Converting (Shown With Auto-Trigger Mode at 500 kSPS)
tSU6
CS
tH5
tSU3
SCLK
tH3
MSB
SDI
tD3
MSB - 1
tD1
MSB - 1
MSB
SDO
MSB - 2
LSB + 1
LSB
tD2
LSB + 1
MSB - 2
LSB
Don’t Care
tD4
‘0’
Figure 3. SPI I/O
CS
tH1
EOC
(active low)
tD5
INT
(active low)
Figure 4. Relationship among CS, EOC, and INT
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8.9 Typical Characteristics: DC Performance
at TA = 25°C, VREF (REF+ – REF–) = 4.096 V when VA = VBD = 5 V or VREF (REF+ – REF–) = 2.5 V when VA = VBD = 2.7
V, fSCLK = 21 MHz, and fSAMPLE = 500 kSPS (unless otherwise noted)
3
3
VA = VBD = 2.7V
VREF = 2.500V
2
2
1
ILE (LSB)
1
ILE (LSB)
VA = VBD = 5.0V
VREF = 4.096V
0
0
-1
-1
-2
-2
-3
0000h
4000h
8000h
Output Code
C000h
-3
0000h
FFFFh
Figure 5. Integral Linearity Error vs Code
3
FFFFh
VA = VBD = 5.0V
VREF = 4.096V
2
1
DLE (LSB)
DLE (LSB)
C000h
Figure 6. Integral Linearity Error vs Code
1
0
0
-1
-1
-2
-2
-3
0000h
4000h
8000h
Output Code
C000h
FFFFh
-3
0000h
Figure 7. Differential Linearity Error vs Code
4000h
8000h
Output Code
C000h
FFFFh
Figure 8. Differential Linearity Error vs Code
500
8.0
7.5
VREF = 4.096V
VREF = 4.096V
450
Nap Current (mA)
7.0
IA (mA)
8000h
Output Code
3
VA = VBD = 2.7V
VREF = 2.500V
2
4000h
6.5
VREF = 2.500V
6.0
5.5
VREF = 2.500V
400
350
5.0
4.5
300
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
4.0
VA (V)
VA (V)
Figure 9. Analog Supply Current vs Analog Supply Voltage
14
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Figure 10. Analog Supply Current in NAP Mode vs
Analog Supply Voltage
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SBAS363E – DECEMBER 2009 – REVISED AUGUST 2016
Typical Characteristics: DC Performance (continued)
at TA = 25°C, VREF (REF+ – REF–) = 4.096 V when VA = VBD = 5 V or VREF (REF+ – REF–) = 2.5 V when VA = VBD = 2.7
V, fSCLK = 21 MHz, and fSAMPLE = 500 kSPS (unless otherwise noted)
120
8
VA = VBD = 5.0V
VREF = 4.096V
6
IA (mA)
Deep Power-Down Current (nA)
7
5
4
3
VA = VBD = 2.7V
VREF = 2.500V
2
1
100
80
60
40
50
100
150 200 250 300
Sampling Rate (kHz)
350
400
0
-50
450
Figure 11. Analog Supply Current vs Sampling Rate in AutoNAP Mode
-25
0
75
100
4
D Gain (LSB relative to +25°C)
11.7
VREF = 4.096V
VREF = 2.500V
11.2
10.7
10.2
3
VA = VBD = 2.7V
VREF = 2.500V
2
1
0
VA = VBD = 5.0V
VREF = 4.096V
-1
-2
-3
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
-4
-50
-25
0
VA (V)
Figure 13. Internal Clock Frequency vs
Analog Supply Voltage
75
100
1.0
5
DIA (mA relative to +25°C)
0.8
4
VA = VBD = 2.7V
VREF = 2.500V
3
2
1
0
-1
-2
VA = VBD = 5.0V
VREF = 4.096V
-3
-4
-5
-6
-50
25
50
Temperature (°C)
Figure 14. Change in Gain vs Temperature
6
D Offset (LSB relative to +25°C)
25
50
Temperature (°C)
Figure 12. Deep Power-Down Current vs Temperature
12.2
Frequency (MHz)
VA = VBD = 2.7V
VREF = 2.500V
20
0
0
VA = VBD = 5.0V
VREF = 4.096V
0.6
0.4
0.2
0
VA = VBD = 2.7V
VREF = 2.500V
-0.2
-0.4
-0.6
VA = VBD = 5.0V
VREF = 4.096V
-0.8
-25
0
25
50
Temperature (°C)
75
Figure 15. Change in Offset vs Temperature
100
-1.0
-50
-25
0
25
50
Temperature (°C)
75
100
Figure 16. Change in Analog Supply Current vs
Temperature
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Typical Characteristics: DC Performance (continued)
at TA = 25°C, VREF (REF+ – REF–) = 4.096 V when VA = VBD = 5 V or VREF (REF+ – REF–) = 2.5 V when VA = VBD = 2.7
V, fSCLK = 21 MHz, and fSAMPLE = 500 kSPS (unless otherwise noted)
150
D Frequency (kHz relative to +25°C)
1.0
DIBD (mA relative to +25°C)
0.8
0.6
VA = VBD = 2.7V
VREF = 2.500V
0.4
0.2
0
-0.2
VA = VBD = 5.0V
VREF = 4.096V
-0.4
-0.6
-0.8
-1.0
-50
-25
0
25
50
Temperature (°C)
75
125
100
VA = VBD = 2.7V
VREF = 2.500V
75
50
25
0
-25
-50
VA = VBD = 5.0V
VREF = 4.096V
-75
-100
-125
-150
-50
100
Figure 17. Change in Digital Supply Current vs Temperature
0
-25
25
50
Temperature (°C)
75
100
Figure 18. Change in Internal Clock Frequency vs
Temperature
D Nap Current Relative to +25°C (mA)
25
VA = VBD = 2.7V
VREF = 2.500V
20
15
10
5
VA = VBD = 5.0V
VREF = 4.096V
0
-5
-10
-15
-20
-25
-50
-25
0
25
50
Temperature (°C)
75
100
Figure 19. Change in Analog Supply Current in NAP Mode vs Temperature
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SBAS363E – DECEMBER 2009 – REVISED AUGUST 2016
8.10 Typical Characteristics: AC Performance
at TA = 25°C, VREF (REF+ – REF–) = 4.096 V when VA = VBD = 5 V or VREF (REF+ – REF–) = 2.5 V when VA = VBD = 2.7
V, fSCLK = 21 MHz, and fSAMPLE = 500 kSPS (unless otherwise noted)
VA = VBD = 2.7V
VREF = 2.500V
6336
4791
1665
1643
1088
768
53
7FFD
7FFE
7FFF
8000
40
0
8001
7FFD
0
7FFE
Code
0
8000
8001
0
VA = VBD = 2.7V
VREF = 2.500V
-20
VA = VBD = 5.0V
VREF = 4.096V
-20
-40
Amplitude (dB)
-40
Amplitude (dB)
7FFF
Code
Figure 21. Output Code Histogram for a DC Input
(8192 Conversions)
Figure 20. Output Code Histogram for a DC Input
(8192 Conversions)
-60
-80
-100
-60
-80
-100
-120
-120
-140
-140
-160
-160
0
50
100
150
200
250
0
50
Frequency (kHz)
100
150
200
250
Frequency (kHz)
Figure 22. Frequency Spectrum
(8192 Point FFT, fIN = 1.0376 kHz, –0.2 dB)
Figure 23. Frequency Spectrum
(8192 Point FFT, fIN = 1.0376 kHz, –0.2 dB)
0
0
VA = VBD = 2.7V
VREF = 2.500V
-20
VA = VBD = 5.0V
VREF = 4.096V
-20
-40
Amplitude (dB)
-40
Amplitude (dB)
VA = VBD = 5.0V
VREF = 4.096V
-60
-80
-100
-60
-80
-100
-120
-120
-140
-140
-160
-160
0
50
100
150
200
250
0
50
Frequency (kHz)
100
150
200
250
Frequency (kHz)
Figure 24. Frequency Spectrum
(8192 Point FFT, fIN = 10.0708 kHz, –0.2 dB)
Figure 25. Frequency Spectrum
(8192 Point FFT, fIN = 10.0708 kHz, –0.2 dB)
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Typical Characteristics: AC Performance (continued)
at TA = 25°C, VREF (REF+ – REF–) = 4.096 V when VA = VBD = 5 V or VREF (REF+ – REF–) = 2.5 V when VA = VBD = 2.7
V, fSCLK = 21 MHz, and fSAMPLE = 500 kSPS (unless otherwise noted)
95
93
fIN = 1.03760kHz, -0.2dB
91
90
SNR (dB)
SINAD (dB)
VA = VBD = 5.0V
VREF = 4.096V
VA = VBD = 5.0V
VREF = 4.096V
92
90
89
85
VA = VBD = 2.7V
VREF = 2.500V
88
87
80
-25
0
25
50
75
100
10
1
100
Temperature (°C)
fIN (kHz)
Figure 26. Signal-to-Noise + Distortion vs Temperature
Figure 27. Signal-to-Noise Ratio vs
Input Frequency
-65
105
-70
100
-75
95
-80
SFDR (dB)
THD (dB)
-50
VA = VBD = 5.0V
VREF = 4.096V
-85
-90
250
VA = VBD = 2.7V
VREF = 2.500V
90
VA = VBD = 5.0V
VREF = 4.096V
85
80
75
-95
VA = VBD = 2.7V
VREF = 2.500V
-100
70
65
-105
1
10
100
250
10
1
100
250
fIN (kHz)
fIN (kHz)
Figure 28. Total Harmonic Distortion vs Input Frequency
Figure 29. Spurious-Free Dynamic Range vs Input
Frequency
95
16.0
VA = VBD = 5.0V
VREF = 4.096V
90
VA = VBD = 5.0V
VREF = 4.096V
15.5
15.0
14.5
85
ENOB (Bits)
SINAD (dB)
VA = VBD = 2.7V
VREF = 2.500V
VA = VBD = 2.7V
VREF = 2.500V
80
75
14.0
13.5
VA = VBD = 2.7V
VREF = 2.500V
13.0
12.5
12.0
70
11.5
11.0
65
1
10
100
250
10
1
fIN (kHz)
Figure 30. Signal-to-Noise + Distortion vs Input Frequency
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100
250
fIN (kHz)
Figure 31. Effective Number of Bits vs Input Frequency
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Typical Characteristics: AC Performance (continued)
95
90
85
80
75
70
65
60
55
50
45
40
35
-95
VRIPPLE = 0.5VPP
VA = VBD = 2.7V
VREF = 2.500V
-100
Crosstalk (dB)
PSRR (dB)
at TA = 25°C, VREF (REF+ – REF–) = 4.096 V when VA = VBD = 5 V or VREF (REF+ – REF–) = 2.5 V when VA = VBD = 2.7
V, fSCLK = 21 MHz, and fSAMPLE = 500 kSPS (unless otherwise noted)
VA = VBD = 5.0V
VREF = 4.096V
-105
-110
VA = VBD = 5.0V
VREF = 4.096V
-115
-120
VA = VBD = 2.7V
VREF = 2.500V
-125
-130
0.1
1
10
Ripple Frequency (kHz)
100
500
10
1
100
250
fIN (kHz)
Figure 32. Power-Supply Rejection Ratio vs Power-Supply
Ripple Frequency
Figure 33. Crosstalk vs Input Frequency
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9 Detailed Description
9.1 Overview
The ADS833x is a high-speed, low-power, successive approximation register (SAR) analog-to-digital converter
(ADC) that uses an external reference. The architecture is based on charge redistribution, which inherently
includes a sample/hold function.
The ADS833x has an internal clock that is used to run the conversion. However, the ADS833x can be
programmed to run the conversion based on the external serial clock (SCLK).
The analog input to the ADS833x is provided to two input pins: one of the INX input channels and the shared
COM pin. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor
array. While a conversion is in progress, both INX and COM inputs are disconnected from any internal function.
The ADS8331 has four analog inputs while the ADS8332 has eight inputs. All inputs share the same common
pin, COM. Both the ADS8331 and ADS8332 can be programmed to select a channel manually or can be
programmed into the auto channel select mode to sweep through the input channels automatically.
9.2 Functional Block Diagram
MUXOUT
IN[0:3]
or
IN[0:7]
ADCIN
Output
Latch
and
3-State
Driver
SAR
M
U
X
+
_
CDAC
FS/CS
Comparator
COM
SDO
Conversion
and
Control
Logic
REF+
REF-
SCLK
SDI
CONVST
EOC/INT/CDI
RESET
9.3 Feature Description
9.3.1 Signal Conditioning
The ADS833x has the flexibility to add signal conditioning between the MUXOUT and ADCIN pins, such as a
programmable gain amplifier (PGA) or filter. This feature reduces the system component count and cost because
each input channel does not require separate signal conditioning circuits, especially if the source impedance
connected to each channel is similar in value.
9.3.2 Analog Input
When the converter enters the hold mode, the voltage difference between the INX and COM inputs is captured
on the internal capacitor array. The voltage on the COM pin is limited from (AGND – 0.2 V) to (AGND + 0.2 V).
This limitation allows the ADS833x to reject small signals that are common to both the INX and COM inputs. The
INX inputs have a range of –0.2 V to (VA + 0.2 V). The input span of (INX – COM) is limited to 0 V to VREF.
The peak input current through the analog inputs depends upon a number of factors: reference voltage, sample
rate, input voltage, and source impedance. The current flowing into the ADS833x charges the internal capacitor
array during the sample period. After this capacitance has been fully charged, there is no further input current.
The source of the analog input voltage must be able to charge the maximum input capacitance (45 pF) to a 16bit settling level within the minimum acquisition time (238 ns). When the converter goes into hold mode, the input
impedance is greater than 1 GΩ.
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Feature Description (continued)
Take care when regarding the absolute analog input voltage. To maintain linearity of the converter, the INX
inputs, the COM input, and the input span of (INX – COM) should be within the limits specified. If these inputs are
outside of these ranges, the linearity of the converter may not meet specifications. To minimize noise, lowbandwidth input signals with low-pass filters should be used. Ensure that the output impedance of the sources
driving the INX and COM inputs are matched, as shown in Figure 34. If this matching is not observed, the two
inputs could have different settling times, which may result in an offset error, gain error, and linearity error that
change with temperature and input voltage.
MUXOUT ADCIN
Device in Hold Mode; Last Input Sampled from IN0
ESD
50W
IN0
ESD
INX
ESD
ESD
40W
40pF
ESD
4pF
50W
55W
COM
AGND
40pF
ESD
VA
AGND
Figure 34. Input Equivalent Circuit
9.3.2.1 Driver Amplifier Choice
To take advantage of the high sample rate offered by the ADS833x, the analog inputs to the converter should be
driven with low-noise operational amplifiers (op amps), such as the OPA365, OPA211, OPA827, or THS4031. TI
recommends a RC filter at each of the input channels to low-pass filter noise generated by the input driving
sources. These channels can accept unipolar signals with voltages between INX and COM in the range of 0 V to
VREF. If RC filters are not used between the op amps and the input channels, the minimum –3-dB bandwidth
required by the driving op amps for the sampled signals to settle to within 1/2 LSB of the final voltage can be
calculated using Equation 1:
(n + 1) ´ ln(2)
f-3dB ³
2p ´ tSAMPLE_MIN
where
•
•
n = resolution of the converter (n = 16 for the ADS833x).
tSAMPLE_MIN = minimum acquisition time.
(1)
The minimum value of tSAMPLE in Electrical Characteristics: VA = 2.7 V and Electrical Characteristics: VA = 5 V is
238 ns (3 CCLKs with the internal oscillator at 12.6 MHz). Substituting these values for n and tSAMPLE_MIN into
Equation 1 shows f–3 dB must be at least 7.9 MHz. This bandwidth can be relaxed if the acquisition time is
increased or an RC filter is added between the driving operational amplifier and the corresponding input channel
(see Texas Instruments' Application Report, Determining Minimum Acquisition Times for SAR ADCs When a
Step Function is Applied to the Input (SBAA173) and associated references for additional information, available
for download at www.ti.com). The OPA365 used in the source-follower (unity-gain) configuration is shown in
Figure 35 with recommended values for the RC filter.
Input Signal
(0V to 4V)
MUXOUT
ADCIN
VA
20W
OPA365
5V
INX
1000pF
ADS8331
ADS8332
COM
Figure 35. Unipolar Input Drive Configuration
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Feature Description (continued)
9.3.2.2 Bipolar to Unipolar Driver
In systems where the input signal is bipolar, op amps such as the OPA365 and OPA211 can be used in the
inverting configuration with a DC bias applied to the noninverting input to keep the input signal to the ADS833x
within its rated operating voltage range. TI also recommends this configuration when the ADS833x is used in
signal-processing applications where good SNR and THD performance is required. The DC bias can be derived
from low-noise reference voltage ICs such as the REF5025 or REF5040. The input configuration shown in
Figure 36 is capable of delivering better than 91-dB SNR and –99-dB THD at an input frequency of 1 kHz. If
bandpass filters are used to filter the input to the driving operational amplifier, the signal swing at the input of the
bandpass filter should be small enough to minimize the distortion introduced by the filter. In these cases, the gain
of the circuit shown in Figure 36 can be increased to maintain a large enough input signal to the ADS833x to
keep the system SNR as high as possible.
MUXOUT
ADCIN
5V
2.048VDC
VA
20W
OPA211
600W
INX
ADS8331
ADS8332
1000pF
Input Signal
(-2V to +2V)
600W
COM
Figure 36. Bipolar Input Drive Configuration
9.4 Device Functional Modes
9.4.1 Reference
The ADS833x can operate with an external reference with a range from 1.2 V to 4.2 V. A clean, low-noise
reference voltage on this pin is required to ensure good converter performance. A low-noise band-gap reference
such as the REF5025 or REF5040 can be used to drive this pin. A 10-μF ceramic bypass capacitor is required
between the REF+ and REF– pins of the converter. This capacitor should be placed as close as possible to the
pins of the device. The REF– pin should not be connected to the AGND pin of the converter; instead, the REF–
pin must be connected to the analog ground plane with a separate via.
9.4.2 Converter Operation
The ADS833x has an internal oscillator that can be used as the conversion clock (CCLK) source. The minimum
frequency of this oscillator is 10.5 MHz. The internal oscillator is only active during the conversion period unless
the converter is using Auto-Trigger or Auto-NAP modes. The minimum acquisition, sampling time for the
ADS833x is 3 CCLKs (250 ns with a 12-MHz conversion clock), while the minimum conversion time is 18 CCLKs
(1500 ns with a 12-MHz conversion clock).
As shown in Figure 37, the ADS833x can also be programmed to run conversions using the external serial clock
(SCLK). This feature allows system designers to achieve system synchronization. Each rising edge of SCLK
toggles the state of the conversion clock (CCLK), which reduces the frequency of SCLK by a factor of two before
it is used as CCLK. For example, a 21-MHz SCLK provides a 10.5-MHz CCLK. If the start of a conversion must
occur on a specific rising edge of SCLK when the external serial clock is used for the conversion clock (and
Manual-Trigger mode is enabled), a minimum setup time of 20 ns between the falling edge of CONVST and the
rising edge of SCLK must be met. This timing ensures the conversion is completed in 18 CCLKs (36 SCLKs).
The duty cycle of SCLK is not critical, as long as the minimum high and low times (11 ns for VA = 5 V) are
satisfied. Because the ADS833x is designed for high-speed applications, a high-frequency serial clock must be
supplied to maintain the high throughput of the interface. This requirement can be accomplished if the period of
SCLK is at most 1 μs when SCLK is used as the conversion clock (CCLK). The 1-μs maximum period for SCLK
is also set by the leakage of charge from the capacitors in the capacitive digital-to-analog converter (CDAC)
block in the ADS833x. If SCLK is used as the conversion clock, the SCLK source must have minimal rise, fall
times and low jitter to provide the best converter performance.
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Device Functional Modes (continued)
CFR_D10
Conversion Clock
(CCLK)
=1
Oscillator
SPI Serial
Clock (SCLK)
=0
Divide by 2
Figure 37. Conversion Clock Source
9.4.2.1 Manual Channel Select Mode
Manual Channel Select mode is enabled through the Configuration register (CFR) by setting the CFR_D11 bit to
0 (see Table 5). The acquisition process starts with selecting an input channel. This selection is done by writing
the desired channel number to the Command register (CMR); see Table 4 for further details. The associated
timing diagram is shown in Figure 38.
CS
SCLK
< 30ns
Mux switch
CHOLD
CHNEW
Figure 38. Manual Channel Select Timing
9.4.2.2 Auto Channel Select Mode
Channel selection can also be done automatically if Auto Channel Select mode (default) is enabled (CFR_D11 =
1). If the device is programmed for Auto Channel Select mode, then signals from all channels are acquired in a
fixed order. In Auto Channel Select mode, the first conversion after entering this mode is always from the
channel of the last conversion completed before this mode is enabled. The channels are then sequentially
scanned up to and including the last channel (that is, channel 3 for the ADS8331 and channel 7 for the
ADS8332) and then back to the channel that started the sequence. For example, if the last channel used in the
conversion before enabling Auto Channel Select mode was channel 2, the sequence for the ADS8332 would be:
2, 3, 4, 5, 6, 7, 2, and so forth, as shown in Figure 39. If the last channel in Manual Channel Select mode
happened to be channel 7, the sequence would be: 7, 7, 7, and so forth. Figure 40 shows when the next channel
in the sequence activates during Auto Channel Select mode. This timing allows the next channel to settle before
it is acquired. This automatic sequencing stops the cycle after CFR_D11 is set to 0.
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Device Functional Modes (continued)
Manual Channel Select Channel 2
Enable Auto Channel Select
Conversion Start is Automatic or Manual
Manual- or Auto-Trigger Mode
Ch 2
Ch 7
Ch 3
Ch 6
Ch 4
Ch 5
Figure 39. Auto Channel Select for the ADS8332
CCLK
EOC
(active low)
Channel #
1 CCLK Minimum
N-1
N
Figure 40. Channel-Number Update in Auto Channel Select Mode Timing
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Device Functional Modes (continued)
9.4.2.3 Start of a Conversion
The end of acquisition is the same as the start of a conversion. This process is initiated by bringing the CONVST
pin low for a minimum of 40 ns. After the minimum requirement has been met, the CONVST pin can be brought
high. CONVST acts independently of FS/CS so it is possible to use one common CONVST for applications that
require simultaneous sample/hold with multiple converters. The ADS833x switches from sample to hold mode on
the falling edge of the CONVST signal. The ADS833x requires 18 conversion clock (CCLK) cycles to complete a
conversion. The conversion time is equivalent to 1500 ns with a 12-MHz internal clock. The minimum time
between two consecutive CONVST signals is 21 CCLKs.
A conversion can also be initiated without using CONVST if the ADS833x is programmed for Auto-Trigger mode
(CFR_D9 = 0). When the converter is configured in this mode, and with CFR_D8 = 0, the next conversion is
automatically started three conversion clocks (CCLK) after the end of a conversion. These three conversion
clocks (CCLK) are used for the acquisition time. In this case, the time to complete one acquisition and
conversion cycle is 21 CCLKs. Table 1 summarizes the different conversion modes.
Table 1. Different Types of Conversion
MODE
Automatic
Manual
(1)
SELECT CHANNEL
START CONVERSION
Auto Channel Select (1)
Auto-Trigger Mode
No need to write channel number to CMR. Use internal sequencer for ADS833x.
Start a conversion based on conversion
clock CCLK
Manual Channel Select
Manual-Trigger Mode
Write channel number to CMR
Start a conversion with CONVST
Auto channel select should be used with Auto-Trigger mode and TAG bit output enabled.
Manual Channel select with Auto-Trigger mode enabled is generally used when continuous conversions from a
single channel are desired. In this mode, cycling the input mux to change the channel requires that conversions
are halted by setting the converter to Manual-Trigger mode. When the proper input channel is selected, the
converter can be placed back to Auto-Trigger mode to continue continuous conversions from the new channel.
9.4.2.4 Status Output Pin (EOC/INT)
The status output pin is programmable. It can be used as an EOC output (CFR_D[7:6] = 11) where the low time
is equal to the conversion time. When the status pin is programmed as EOC and the polarity is set as active low,
the pin works in the following manner: the EOC output goes low immediately following CONVST going low with
Manual-Trigger mode enabled. EOC stays low throughout the conversion process and returns high when the
conversion has ended. If Auto-Trigger mode is enabled, the EOC output remains high for three conversion clocks
(CCLK) after the previous rising edge of EOC.
This status pin can also be used as an interrupt output, INT (CFR_D[7:6] = 10), which is set low at the end of a
conversion, and is brought high (cleared) by the next read cycle. The polarity of this pin, whether used as EOC
or INT, is programmable through the CFR_D7 bit.
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9.4.2.5 Power-Down Modes and Acquisition Time
There are three power-down modes that reduce power dissipation: Nap, Deep, and Auto-NAP. The first two, Nap
and Deep Power-Down modes, are enabled or disabled by bits CFR_D3 and CFR_D2, respectively, in the
Configuration register (see Table 5 for details).
Deep Power-Down mode provides maximum power savings. When this mode is enabled, the analog core in the
converter is shut down, and the analog supply current falls from 6.6 mA (VA = 5 V) to 1 μA in 2 μs. The wake-up
time from Deep Power-Down mode is 1 μs. The device can wake up from Deep Power-Down mode by either
disabling this mode, issuing the wake-up command, loading the default value into the CFR, or performing a reset
(either with the software reset command, CFR_D0 bit, or the external reset). See Table 4 and Table 5 along with
the Reset Function section for further information.
In Nap Power-Down mode, the bias currents for the analog core of the device are significantly reduced. Because
the bias currents are not completely shut off, the ADS833x can wake up from this power-down mode much faster
than from Deep Power-Down mode. After Nap Power-Down mode is enabled, the analog supply current falls
from 6.6 mA (VA = 5 V) to 0.39 mA in 200 ns. The wake-up time from this mode is three conversion clock cycles
(CCLK). The device can wake up from Nap Power-Down mode in the same manner as waking up from Deep
Power-Down mode.
The third power-down mode, Auto-NAP, is enabled or disabled by bit CFR_D4 in the Configuration register (see
Table 5 for details). Once this mode is enabled, the device is controlled by the digital core logic on the chip. The
device is automatically placed into Nap Power-Down mode after the next end of conversion (EOC). The analog
supply current falls from 6.6mA (VA = 5 V) to 0.39 mA in 200 ns. A conversion start wakes up the device in three
conversion clock cycles. Issuing the wake-up command, loading the default value into the CFR, disabling AutoNAP Power-Down mode, issuing a manual channel select command, or resetting the device can wake the
ADS833x from Auto-NAP Power-Down mode. A comparison of the three power-down modes is listed in Table 2.
Table 2. Comparison of Power-Down Modes
TYPE OF POWERDOWN
POWER
CONSUMPTION
(VA = 5 V)
POWER-DOWN
BY:
POWER-DOWN TIME
WAKEUP BY:
ENABLE
Normal operation
6.6 mA
—
—
—
—
Deep power-down
1 μA
Setting CFR_D2
2 μs
Wakeup command 1011b
1 μs
Set CFR_D2
Nap power-down
0.39 mA
Setting CFR_D3
200 ns
Wakeup command 1011b
3 CCLKs
Set CFR_D3
0.39 mA
EOC (end of
conversion)
200 ns
CONVST, any channel select command, default
command 1111b, or wakeup command 1011b.
3 CCLKs
Set CFR_D4
Auto-NAP powerdown
—
WAKE-UP TIME
The default acquisition time is three conversion clock (CCLK) cycles. Figure 41 shows the timing diagram for
CONVST, EOC, and Auto-NAP power-down signals in Manual-Trigger mode. As shown in the diagram, the
device wakes up after a conversion is triggered by the CONVST pin going low. However, a conversion is not yet
started at this time. The conversion start signal to the analog core of the chip is internally generated no less than
six conversion clock (CCLK) cycles later, to allow at least three CCLKs for wake up and three CCLKs for
acquisition. The ADS833x enters Nap Power-Down mode one conversion cycle after the end of conversion
(EOC).
CCLK
CONVST
CONVST_OUT
(internal)
3 + 3 = 6 Cycles
1 Cycle
NAP_ACTIVE
(internal)
EOC
(active low)
Figure 41. Timing for CONVST, EOC, and Auto-NAP Power-Down Signals in Manual-Trigger Mode (Three
Conversion Clock Cycles for Acquisition)
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The ADS833x can support sampling rates of up to 500 kSPS in Auto-Trigger mode. This rate is selectable by
programming the CFR_D8 bit in the Configuration register. In 500-kSPS mode, consecutive conversion start
pulses to the analog core are generated 21 conversion clock cycles apart. In 250-kSPS mode, consecutive
conversion-start pulses are 42 conversion clock cycles apart. The Nap and Deep Power-Down modes are
available with either sampling rate; however, Auto-NAP mode is available only with a sampling rate of 250 kSPS
when Auto-Trigger mode is enabled. The analog core cannot be powered down when the Auto-NAP mode
sampling rate is 500 kSPS because at that rate, there is no period of time when the analog core is not actively
being used.
Figure 42 shows the timing diagram for conversion start and Auto-NAP power-down signals for a 250-kSPS
sampling rate in Auto-Trigger mode. For a 16-bit ADC output word, consecutive new conversion start pulses are
generated 2 × (18 + 3) cycles apart. NAP_ACTIVE (the signal to power down the analog core in Nap and AutoNAP modes) goes low six (3 + 3) conversion clock cycles before the conversion start falling edge, thus powering
up the analog core. It takes three conversion clock cycles after NAP_ACTIVE goes low to power up the analog
core. The analog core is powered down a cycle after the end of a conversion. For a 16-bit ADC with a 500-kSPS
sampling rate and three conversion clock cycle sampling, consecutive conversion start pulses are generated 21
conversion clock cycles apart.
1
2
3
19
20
21
37
38
42
43
CCLK
CONVST_OUT
(internal)
EOC
(active low)
NAP_ACTIVE
(internal)
Figure 42. Timing for Conversion Start and Auto-NAP Power-Down Signals in Auto-Trigger Mode (250kSPS Sampling and Three Conversion Clock Cycles for Acquisition)
Timing diagrams for reading from the ADS833x with various trigger and power-down modes are shown in
Figure 43 through Figure 45. The total (acquisition + conversion) times for the different trigger and power-down
modes are listed in Table 3.
Table 3. Total Acquisition + Conversion Times
MODE
ACQUISITION + CONVERSION TIME
Auto-Trigger at 500 kSPS
= 21 CCLK
Manual-Trigger
≥ 21 CCLK
Manual-Trigger with Deep Power Down
≥ 4 SCLK + 1 μs + 3 CCLK + 18 CCLK + 16 SCLK + 2 μs
Manual-Trigger with Nap Power Down
≥ 4 SCLK + 3 CCLK + 3 CCLK + 18 CCLK + 16 SCLK + 200 ns
Manual-Trigger with Auto-NAP Power Down
≥ 4 SCLK + 3 CCLK + 3 CCLK + 18 CCLK + 1 CCLK + 200 ns (using wakeup to resume)
≥ 3 CCLK + 3 CCLK + 18 CCLK + 1 CCLK + 200 ns (using CONVST to resume)
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EOS
EOC
EOS
EOC
(active low)
Sample (N + 1)
Conversion N
tH2
Read While Converting
CS
EOC
(N+1)
N
CONVST
Conversion (N + 1)
tSU1
Read Result (N - 1)
Read While Sampling
tSU2
tH1
CS
Read Result N
Figure 43. Read While Converting vs Read While Sampling (Manual-Trigger Mode)
BLANKSPACE
Wakeup
Sample N
Conversion N
³ 3 CCLK
= 18 CCLK
Read Result
(N - 1)
Note
(2)
Power-Down Wakeup
Sample (N + 1)
Conversion (N + 1)
³ 3 CCLK
= 18 CCLK
Note
(2)
Read Result
(N - 1)
Note
(1)
Power-Down
tH2
Note
(3)
Note
(2)
Note
(3)
Note
(2)
Read Result
N
tSU2
Read While Sampling
CS
Note
(1)
tH2
Read While Converting
CS
EOS
EOC
EOS
Converter State
EOC
(N+1)
N
CONVST
Note
(3)
tSU2
Read Result
N
(1)
Converter is in acquisition mode between end of conversion and activation of Nap or Deep Power-Down mode.
(2)
Command on SDI pin to wake-up converter (minimum of four SCLKs).
(3)
Command on SDI pin to place converter into Nap or Deep Power-Down mode (minimum of 16 SCLKs).
Note
(3)
Figure 44. Read While Converting vs Read While Sampling With Nap or Deep Power Down
(Manual-Trigger Mode)
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MANUAL TRIGGER CASE 1 (Wakeup Using CONVST):
tWL1
(N+1)
N
CONVST
Converter State
Wakeup
Sample N
Conversion N
³ 3 CCLK
= 18 CCLK
³ 6 CCLK
Note
(1)
tH2
Read While Converting
Power-Down Wakeup
Sample (N + 1)
Conversion (N + 1)
³ 3 CCLK
= 18 CCLK
³ 6 CCLK
tSU1
tSU1
tSU2
Read Result
N
Read Result
(N - 1)
CS
Power-Down
Read Result
N
tSU2
Read While Sampling
Note
(1)
tH2
Read Result
(N - 1)
CS
EOC
EOS
EOS
EOC
EOC
(active low)
MANUAL TRIGGER CASE 2 (Wakeup Using Wakeup Command):
tWL1
(N+1)
N
CONVST
Converter State
Wakeup
Sample N
Conversion N
³ 3 CCLK
= 18 CCLK
tH2
Read While Converting
CS
Power-Down Wakeup
Conversion (N + 1)
³ 3 CCLK
= 18 CCLK
Read Result
(N - 1)
Note
(1)
tH2
Note
(2)
Power-Down
tSU1
Read Result
N
tSU2
Note
(2)
EOC
Sample (N + 1)
tSU1
Read Result
(N - 1)
Note
(2)
Read While Sampling
CS
Note
(1)
EOS
EOS
EOC
EOC
(active low)
tSU2
Note
(2)
(1)
Time between end of conversion and Nap Power Down mode is 1 CCLK.
(2)
Command on SDI to wake-up converter (minimum of four SCLKs).
Read Result
N
Figure 45. Read While Converting vs Read While Sampling With Auto-NAP Power Down
9.5 Programming
9.5.1 Digital Interface
The serial interface is designed to accommodate the latest high-speed processors with an SCLK frequency of up
to 40 MHz (VA = VBD = 5 V). Each cycle starts with the falling edge of FS/CS. The internal data register content,
which is made available to the output register at the end of conversion, is presented on the SDO output pin on
the falling edge of FS/CS. The first bit is the most significant bit (MSB). The output data bits are valid on the
falling edge of SCLK with the tD2 delay (see the Timing Requirements: VA = 2.7 V and Timing Characteristics:
VA = 5 V) so that the host processor can read the data on the falling edge. Serial data input is also read on the
falling edge of SCLK.
The complete serial I/O cycle starts after the falling edge of FS/CS and ends 16 falling edges of SCLK later (see
NOTE). The serial interface works with CPOL = 1, CPHA = 0. This setting means the falling edge of FS/CS may
fall while SCLK is high. The same timing relaxation applies to the rising edge of FS/CS where SCLK may be high
or low as long as the last SCLK falling edge happens before the rising edge of FS/CS.
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Programming (continued)
NOTE
There are cases where a cycle can be anywhere from 4 SCLKs up to 24 SCLKs,
depending on the read mode combination. See Table 4 for details.
9.5.1.1 Internal Register
The internal register consists of two parts: four bits for the Command register (CMR) and 12 bits for the
Configuration register (CFR).
Table 4. Command Set Defined by Command Register (CMR) (1)
(1)
(2)
30
D[11:0]
WAKE UP
FROM AUTONAP
MINIMUM
SCLKs
REQUIRED
R/W
Select analog input channel 0
Don't care
Y
4
W
Select analog input channel 1
Don't care
Y
4
W
2h
Select analog input channel 2
Don't care
Y
4
W
0011b
3h
Select analog input channel 3
Don't care
Y
4
W
0100b
4h
Select analog input channel 4 (2)
Don't care
Y
4
W
0101b
5h
Select analog input channel 5 (2)
Don't care
Y
4
W
0110b
6h
Select analog input channel 6
(2)
Don't care
Y
4
W
0111b
7h
Select analog input channel 7 (2)
Don't care
Y
4
W
1000b
8h
Reserved
Reserved
—
—
—
1001b
9h
Reserved
Reserved
—
—
—
1010b
Ah
Reserved
Reserved
—
—
—
1011b
Bh
Wake up
Don't care
Y
4
W
1100b
Ch
Read CFR
Don't care
—
16
R
1101b
Dh
Read data
Don't care
—
16
R
1110b
Eh
Write CFR
CFR Value
—
16
W
1111b
Fh
Default mode
(load CFR with default value)
Don't care
Y
4
W
D[15:12]
HEX
0000b
0h
0001b
1h
0010b
COMMAND
The first four bits from SDO after the falling edge of FS/CS are the four MSBs from the previous conversion result. The next 12 bits from
SDO are the contents of the CFR.
These commands apply only to the ADS8332; they are reserved (not available) for the ADS8331.
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9.5.2 Writing to the Converter
There are two different types of writes to the register: a 4-bit write to the CMR and a full 16-bit write to the CMR
plus CFR. The command set is listed in Table 4 and the configuration register map is listed in Table 5. A simple
command requires only four SCLKs; the write takes effect on the fourth falling edge of SCLK. A 16-bit write or
read takes at least 16 SCLKs (see Table 7 for exceptions that require more than 16 SCLKs).
9.5.2.1 Configuring the Converter and Default Mode
The converter can be configured with command 1110b (write to the CFR) or command 1111b (default mode). A
write to the CFR requires a 4-bit command followed by 12 bits of data. A 4-bit command takes effect on the
fourth falling edge of SCLK. A write to the CFR takes effect on the 16th falling edge of SCLK.
The CFR default value for each bit is 1. The default values are applied to the CFR after issuing command 1111b
or when the device is reset with a power-on reset (POR), software reset, or external reset using the RESET pin
(see the Reset Function section).
The communication protocol of the ADS833x is full duplex. That is, data are transmitted to and from the device
simultaneously. For example, the input mux channel can be changed via the SDI pin while data are being read
through the SDO pin. All commands, except Read CFR, output conversion data on the SDO pin. If a Read CFR
command is issued, the Read Data command can then be used to read back the conversion result.
9.5.3 Reading the Configuration Register
The host processor can read back the value programmed in the CFR by issuing command 1100b. The timing is
similar to reading a conversion result except CONVST is not used. There is also no activity on the EOC/INT pin.
The CFR value readback contains the first four bits (MSBs) of the previous conversion data plus the 12-bit CFR
contents.
Table 5. Configuration Register (CFR) Map
CFR SDI BIT
(Default = FFFh)
DEFINITION
BIT = 0
Channel select mode
BIT = 1
Manual channel select enabled. Use channel Auto channel select enabled. Channels are
select commands to access a desired
sampled and converted sequentially until the
channel.
cycle after this bit is set to 0.
D11
D10
Conversion clock (CCLK) source select
D9
Trigger (conversion start) select: start
Auto-Trigger: conversions automatically start
conversion at the end of sampling (EOS). If
three conversion clocks after EOC at 500
D9 = 0 and D8 = 0, the D4 setting is
kSPS
ignored.
Conversion clock (CCLK) = SCLK / 2
D8
Sample rate for Auto-Trigger mode
500kSPS (21 CCLKs)
250 kSPS (42 CCLKs)
D7
Pin 10 polarity select when used as an
output (EOC/INT)
EOC/INT active high
EOC/INT active low
D6
Pin 10 function select when used as an
output (EOC/INT)
Pin used as INT
Pin used as EOC
D5
Pin 10 I/O select for daisy-chain mode
operation
Pin 10 is used as CDI input
(daisy-chain mode enabled)
Pin 10 is used as EOC/INT output
D4
Auto-NAP Power-Down enable or disable.
This bit setting is ignored if D9 = 0 and D8
=0.
Auto-NAP Power-Down mode enabled (not
activated)
Auto-NAP Power-Down mode disabled
D3
Nap Power Down. This bit is set to 1
automatically by wake-up command.
Nap Power-Down enabled
Nap Power-Down disabled
(resume normal operation)
D2
Deep Power Down. This bit is set to 1
automatically by wake-up command.
Deep Power-Down enabled
Deep Power-Down disabled
(resume normal operation)
D1
TAG bit output enable
TAG bit output disabled
TAG bit output enabled. TAG bits appear
after conversion data
D0
Software reset
System reset, returns to 1 automatically
Normal operation
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Conversion clock (CCLK) = internal OSC
Manual-Trigger: conversions manually start
on falling edge of CONVST
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9.5.4 Reading the Conversion Result
The conversion result is available to the input of the output data register (ODR) at EOC and presented to the
output of the output register at the next falling edge of FS/CS. The host processor can then shift the data out
through the SDO pin at any time except during the quiet zone. This duration is 20 ns before and 20 ns after the
end of sampling (EOS) period. End of sampling (EOS) is defined as the falling edge of CONVST when ManualTrigger mode is used or the end of the third conversion clock (CCLK) after EOC if Auto-Trigger mode is used.
The falling edge of FS/CS should not be placed at the precise moment at the end of a conversion (by default
when EOC goes high). Otherwise, the data could be corrupt. If FS/CS is placed before the end of a conversion,
the previous conversion result is read. If FS/CS is placed after the end of a conversion, the current conversion
result is read.
The conversion result is 16-bit data in straight binary format as shown in Table 6. Generally 16 SCLKs are
necessary, but there are exceptions when more than 16 SCLKs are required (see Table 7). Data output from the
serial output (SDO) is left-adjusted MSB first. The trailing bits are filled with three TAG bits first (if enabled) plus
all 0s. SDO remains low until FS/CS is brought high again.
SDO is active when FS/CS is low. The rising edge of FS/CS 3-states the SDO output.
NOTE
Whenever SDO is not in 3-state (that is, when FS/CS is low and SCLK is running), a
portion of the conversion result is output at the SDO pin. The number of bits depends on
how many SCLKs are supplied. For example, a manual channel select command cycle
requires 4 SCLKs. Therefore, four MSBs of the conversion result are output at SDO. The
exception is when SDO outputs all 1s during the cycle immediately after any reset (POR,
software reset, or external reset).
If SCLK is used as the conversion clock (CCLK) and a continuous SCLK is used, it is not possible to clock out all
16 bits from SDO during the sampling time (6 SCLKs) because of the quiet zone requirement. In this case, it is
better to read the conversion result during the conversion time (36 SCLKs or 48 SCLKs in Auto-NAP mode).
Table 6. Ideal Input Voltages and Output Codes
DIGITAL OUTPUT
DESCRIPTION
Full-scale range
ANALOG VALUE
STRAIGHT BINARY
BINARY CODE
HEX CODE
—
VREF
—
Least significant bit (LSB)
VREF / 65536
—
—
Full-scale
VREF – 1 LSB
1111 1111 1111 1111
FFFF
Midscale
Midscale – 1 LSB
Zero
VREF / 2
1000 0000 0000 0000
8000
VREF / 2– 1 LSB
0111 1111 1111 1111
7FFF
0V
0000 0000 0000 0000
0000
9.5.4.1 TAG Mode
The ADS833x includes a TAG feature that can be used to indicate which channel sourced the converted result. If
TAG mode is enabled, three address bits are added after the LSB of the conversion data is read out from SDO
to indicate which channel corresponds to the result. These address bits are 000 for channel 0, 001 for channel 1,
010 for channel 2, 011 for channel 3, 100 for channel 4, 101 for channel 5, 110 for channel 6, and 111 for
channel 7. The converter requires at least 19 SCLKs when TAG mode is enabled to transfer the 16-bit
conversion result and the three TAG bits.
9.5.4.2 Daisy-Chain Mode
The ADS833x can operate as a single converter or in a system with multiple converters. System designers can
take advantage of the simple, high-speed, SPI-compatible serial interface by cascading converters in a single
chain when multiple converters are used. The CFR_D5 bit in the Configuration register is used to reconfigure the
EOC/INT status pin as the chain data input (CDI) pin, a secondary serial data input, for the conversion result
from an upstream converter. This configuration is called daisy-chain mode operation. A typical connection of
three converters in daisy-chain mode is shown in Figure 46.
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MICROCONTROLLER
INT
CS1
CS2
SDI SCLK CONVST
CS
SDI SCLK
CS
ADS8331/32
#1
SDO
EOC/INT
CS3
SDO SCLK
CONVST
SDI SCLK
CS
ADS8331/32
#2
CDI
Program Device #1: CFR_D5 = ‘1’
SDO
SDI
CONVST
ADS8331/32
#3
CDI
SDO
Program Devices #2 and #3: CFR_D5 = ‘0’
Figure 46. Multiple Converters Connected Using Daisy-Chain Mode
When multiple converters are used in daisy-chain mode, the first converter is configured in regular mode while
the rest of the converters downstream are configured in daisy-chain mode. When a converter is configured in
daisy-chain mode, the CDI input data go straight to the output register. Therefore, the serial input data passes
through the converter with either a 16 SCLK (if the TAG feature is disabled) or 24-SCLK delay, as long as CS is
active. See Figure 47 for detailed timing. In this timing diagram, the conversion in each converter is performed
simultaneously.
Manual Trigger, Read While Sampling
(Use internal CCLK, EOC active low, and TAG mode disabled)
Conversion N
EOS
EOC
EOC #1
(active low)
EOS
CONVST #1
CONVST #2
CONVST #3
tSAMPLE1 = 3 CCLK min
tCONV = 18 CCLK
tSU2
CS #1
SCLK #1
SCLK #2
SCLK #3
SDO #1
CDI #2
1. . . . . . . . . . . . . .16
High-Z
1. . . . . . . . . . . . . .16
1. . . . . . . . . . . . . .16
High-Z
Conversion N
from Device #1
tSU2
CS #2
CS #3
SDO #2
CDI #3
SDO #3
SDI #1
SDI #2
SDI #3
High-Z
High-Z
Don't Care
High-Z
Conversion N
from Device #2
Conversion N
from Device #1
Conversion N
from Device #3
Conversion N
from Device #2
Conversion N
from Device #1
Read Data
Read Data
Configure
High-Z
Don't Care
Figure 47. Simplified Dasiy-Chain Mode Timing With Shared CONVST and Continuous CS
The multiple CS signals must be handled with care when the converters are operating in daisy-chain mode. The
different chip select signals must be low for the entire data transfer (in this example, 48 bits for three
conversions). The first 16-bit word after the falling chip select is always the data from the chip that received the
chip select signal.
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Case 1: If chip select is not toggled (CS stays low), the next 16 bits of data are from the upstream converter, and
so on. This configuration is shown in Figure 47.
Case 2: If the chip select is toggled during a daisy-chain mode data transfer cycle, as illustrated in Figure 48, the
same data from the converter are read out again and again in all three discrete 16-bit cycles. This state is not a
desired result.
Manual Trigger, Read While Sampling
(Use internal CCLK, EOC active low, and TAG mode disabled)
Conversion N
EOS
EOC
EOC #1
(active low)
EOS
CONVST #1
CONVST #2
CONVST #3
tCONV = 18 CCLK
tWH1
tSAMPLE1 = 3 CCLK min
tWH1
tSU2
CS #1
SCLK #1
SCLK #2
SCLK #3
SDO #1
CDI #2
1. . . . . . . . . . . . . .16
High-Z
Conversion N
from Device #1
1. . . . . . . . . . . . . .16
High-Z
tWH1
1. . . . . . . . . . . . . .16
High-Z
Conversion N
from Device #1
tWH1
Conversion N
from Device #1
High-Z
tSU2
CS #2
CS #3
SDO #2
CDI #3
SDO #3
SDI #1
SDI #2
SDI #3
High-Z
High-Z
Don't Care
Conversion N
from Device #2
Conversion N
from Device #3
Configure
High-Z
High-Z
Don't Care
High-Z
Conversion N
from Device #2
High-Z
Conversion N
from Device #3
Read Data
Don't Care
Conversion N
from Device #2
Conversion N
from Device #3
Read Data
High-Z
High-Z
Don't Care
Figure 48. Simplified Daisy-Chain Mode Timing With Shared CONVST and Noncontinuous CS
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Figure 49 shows a slightly different scenario where CONVST is not shared with the second converter. Converters
#1 and #3 have the same CONVST signal. In this case, converter #2 simply passes previous conversion data
downstream.
Manual Trigger, Read While Sampling
(Use internal CCLK, EOC active low, and TAG mode disabled)
CONVST #1
CONVST #3
Conversion N
EOS
EOS
EOC #1
(active low)
EOC
CONVST #2
tSAMPLE1 = 3 CCLK min
tCONV = 18 CCLK
tSU2
CS #1
SCLK #1
SCLK #2
SCLK #3
SDO #1
CDI #2
1. . . . . . . . . . . . . .16
High-Z
1. . . . . . . . . . . . . .16
1. . . . . . . . . . . . . .16
High-Z
Conversion N
from Device #1
tSU2
CS #2
CS #3
SDO #2
CDI #3
SDO #3
SDI #1
SDI #2
SDI #3
(1)
High-Z
High-Z
High-Z
Conversion (N - 1)
from Device #2(1)
Conversion N
from Device #1
Conversion N
from Device #3
Conversion (N - 1)
from Device #2(1)
Conversion N
from Device #1
Read Data
Read Data
Don't Care
Configure
High-Z
Don't Care
Data from device #2 is from previous converison.
Figure 49. Simplified Daisy-Chain Mode Timing with Separate CONVST and Continuous CS
The number of SCLKs required for a serial read cycle depends on the combination of different read modes, TAG
mode, daisy-chain mode, and the manner in which a channel is selected (for example, Auto Channel Select
mode). The required number of SCLKs for different readout modes are listed in Table 7.
Table 7. Required SCLKs kor Different Readout Mode Combinations
DAISY-CHAIN MODE
CFR_D5
TAG MODE
CFR_D1
NUMBER OF SCLK CYCLES
PER SPI READ
1
0
16
1
1
≥ 19
0
0
16
None
0
1
24
TAG bits plus 5 zeros
TRAILING BITS
None
TAG bits plus up to 5 zeros
SCLK skew between converters in a daisy-chain configuration can affect the maximum frequency of SCLK. The
skew can also be affected by supply voltage and loading. It may be necessary to slow down the SCLK when the
devices are configured in daisy-chain mode.
9.5.5 Reset Function
The ADS833x can be reset with three different methods: internal POR, software reset, and external reset using
the RESET pin.
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The internal POR circuit is activated when power is initially applied to the converter. This internal circuit
eliminates the need for commands to be sent to the converter after power on to set the default mode of operation
(see the Power-On Sequence Timing section for further details).
Software reset can be used to place the converter in the default mode by setting the CFR_D0 bit to 0 in the
Configuration register (see Table 5). This bit is automatically returned to 1 (default) after the converter is reset.
This reset method is useful in systems that cannot dedicate a separate control signal to the RESET pin. In these
situations, the RESET pin must be connected to VBD for the ADS833x to operate properly.
If communication in the system becomes corrupted and a software reset cannot be issued, the RESET pin can
be used to reset the device manually. To reset the device and return the device to default mode, this pin must
held low for a minimum of 25 ns.
After the ADS833x detects a reset condition, the minimum time before the device can be reconfigured by FS/CS
going low and data clocking in on SDI is 2 μs.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The two primary circuits required to optimize the performance of a high-precision, successive approximation
register (SAR), analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This
section details some general principles for designing these circuits, and some application circuits designed using
these devices.
10.1.1 ADC Reference Driver
The reference source to the ADC must provide low drift, very accurate DC voltage and support the dynamic
charge requirements without affecting the noise and linearity performance of the device. The output broadband
noise (typically in the order of a few 100 μVRMS) of the reference source must be appropriately filtered by using a
low pass filter with a cut-off frequency of a few hundred hertz. After band-limiting the noise from the reference
source, the next important step is to design a reference buffer that can drive the dynamic load posed by the
reference input of the ADC. At the start of each conversion, the reference buffer must regulate the voltage of the
reference pin within 1 LSB of the intended value. This condition necessitates the use of a large 22-µF bypass
capacitor at the reference pin of the ADC. The amplifier selected to drive the reference input pin must be stable
while driving this large capacitor and should have low output impedance, low offset, and temperature drift
specifications.
10.1.1.1 Reference Driver Circuit for VREF = 4.096 V
The application circuit in Figure 50 shows the schematic of a complete reference driver circuit that generates a
voltage of 4.096-V DC using a single 5-V supply. This circuit is suitable to drive the reference of the ADS8332 at
the maximum throughput of 500 kSPS. The reference voltage of 4.096 V in this design is generated by the lowpower, low drift, low-power REF2041 circuit. The output broadband noise of the reference is filtered by a lowpass filter with a 3-dB cutoff frequency of 159 Hz.
VA=5V
1k
VIN
1 µF
VA=5V
-
REF2041
VREF
+
+
ENABLE
GND
`
1 µF
0.220
OPA320
REF+
1 µF
VBIAS
RBUF_FLT
0.220
22 µF
VA
1 µF
V+
ADS8331/32
10 µF
VA=5V
REF-
AGND
Figure 50. Reference Driver Schematic for VA = 5 V, VREF = 4.096 V
The OPA320 is a precision, high bandwidth (20 MHz), low-noise (7 nV / √Hz) operational amplifier. The lownoise, and low power consumption of this amplifier makes the OPA320 a good choice to drive the reference input
of the ADS833x. The REF+ input is bypassed with a 22-μF bypass capacitor. The 22-µF reference bypass
capacitor is high enough to make the OPA320 amplifier unstable, therefore a small resistor (RBUF_FLT) is required
to isolate the amplifier output and improve stability. The value of RBUF_FLT is dependent on the output impedance
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Application Information (continued)
of the driving amplifier as well as the circuit frequency response. Typical values of RBUF_FLT range from 0.1 Ω to 2
Ω and the exact value can be found by using SPICE simulations. In the case of the OPA320 in the reference
driver example in Figure 50, the value of RBUF_FLT is 220 mΩ providing >55° of phase margin while driving the
22-µF bypass capacitor. It should be noted that higher values of RBUF_FLT cause high voltage spikes at the
reference pin which affects the conversion accuracy.
10.1.1.2 Reference Driver Circuit for VREF=2.5 V, VA=2.7 V
The circuit shown in Figure 51 can be used to generate a 3-V reference using a 3.3-V supply. This circuit is
suitable to drive the reference of the ADS8332 at the maximum throughput of 500 kSPS. The reference voltage
of 3 V in this design is generated by the low-power, low drift, REF2025. The output broadband noise of the
reference is filtered by a low-pass filter with a 3-dB cutoff frequency of 159 Hz.
VA=2.7V
1k
VIN
1 µF
VA=2.7V
-
REF2025
VREF
+
+
OPA320
RBUF_FLT
0.220
ENABLE
0.220
GND
1 µF
REF+
22 µF
1 µF
VBIAS
VA
1 µF
V+
ADS8331/32
10 µF
REF-
VA=2.7V
AGND
Figure 51. Reference Driver Schematic for VA = 2.7 V, VREF = 2.5 V
10.1.2 ADC Input Driver
To take advantage of the high sample rate offered by the ADS833x, the analog inputs (INx) of the device should
be driven with low noise operational amplifiers. The optimal input driver circuit for a high precision SAR ADC
consists of a driving amplifier and a fly-wheel RC filter. The amplifier driving the ADC must have low output
impedance and be able to charge the internal sampling capacitor (45pF) to a 16-bit settling level within the
minimum acquisition time. The RC filter helps attenuate the sampling charge injection from the switchedcapacitor input stage of the ADC and helps to reduce the wideband noise contributed by the front-end circuit.
Careful design of the front-end circuit is critical to meet the linearity and noise performance of a high-precision
ADC.
10.1.2.1 Input Amplifier Selection
The selection criteria for the input driver amplifier is dependent on the input signal type and the performance
goals of the data acquisition system. Some key amplifier specifications to consider while selecting an appropriate
amplifier to drive the inputs of the ADC are:
• Small-signal bandwidth: Select the small-signal bandwidth of the input amplifiers to be as high as possible
after meeting the power budget of the system. Higher bandwidth reduces the closed-loop output impedance
of the amplifier, thus allowing the amplifier to more easily drive the RC filter at the ADC inputs. Higher
bandwidth also minimizes the harmonic distortion at higher input frequencies. To maintain the overall stability
of the input driver circuit, the amplifier bandwidth should be selected as described in Equation 2:
1
§
·
Unity GainBandwi dth t 4 u ¨
¸
© 2S u RFLT u CFLT ¹
•
38
(2)
Noise: Noise contribution of the front-end amplifiers should be as low as possible to prevent any degradation
in SNR performance of the system. As a rule of thumb, to ensure that the noise performance of the data
acquisition system is not limited by the front-end circuit, the total noise contribution from the front-end circuit
should be kept below 20% of the input-referred noise of the ADC. Noise from the input driver circuit is bandlimited by designing a low cutoff frequency RC filter and is calculated by Equation 3:
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Product Folder Links: ADS8331 ADS8332
ADS8331, ADS8332
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SBAS363E – DECEMBER 2009 – REVISED AUGUST 2016
Application Information (continued)
§ V 1 _ AMP _ PP ·
¸
NG u ¨ f
¸
¨
6 .6
¹
©
2
en2 _ REF _ RMS u
1 V
S
u fREF _ 3 dB d u FSR u 10
2
3 2 2
SNR dB
20
where
•
•
•
•
•
V1 / f_AMP_PP is the peak-to-peak flicker noise in µV
en_RMS is the amplifier broadband noise density in nV / √Hz
f–3dB is the 3-dB bandwidth of the RC filter
NG is the noise gain of the front-end circuit, which is equal to 1 in a buffer configuration
THD AMP d THD ADC 10(dB)
•
(3)
Distortion: Both the ADC and the input driver introduce non-linearity in a data acquisition block. As a rule of
thumb, to ensure that the distortion performance of the data acquisition system is not limited by the front-end
circuit, the distortion of the input driver should be at least 10-dB lower than the distortion of the ADC, as
shown in Equation 4:
(4)
Settling Time: For DC signals with fast transients that are common in a multiplexed application, the input
signal must settle to the desired accuracy at the inputs of the ADC during the acquisition time window. This
condition is critical to maintain the overall linearity performance of the ADC. Typically, the amplifier data
sheets specify the output settling performance only up to 0.01% with a resistive load which may not be
sufficient for the desired accuracy. Therefore, the settling behavior of the input driver with the RC filter load
should always be verified by TINA™- SPICE simulations before selecting the amplifier.
10.1.2.2 ADC Input RC Filter
An RC filter is designed as a low-pass, RC filter, for which the 3-dB bandwidth is optimized based on specific
application requirements. For DC signals with fast transients (including multiplexed input signals), a highbandwidth filter is designed to allow accurate settling of the signal at the ADC inputs during the small acquisition
time window. For AC signals, the filter bandwidth should be kept low to band-limit the noise fed into the ADC
input, thereby increasing the signal-to- noise ratio (SNR) of the system.
A filter capacitor, CFLT, connected across the ADC inputs (as shown in Figure 52), reduces the noise from the
front-end drive circuitry, minimizes the effects of the sampling charge injection and provides a charge bucket to
quickly charge the internal sample-and-hold capacitors during the acquisition process. As a rule of thumb, the
value of this capacitor should be at least 10 times the specified value of the ADC sampling capacitance. For
these devices, the input sampling capacitance is equal to 45 pF. Thus, the value of CFLT should be greater than
450 pF. For applications measuring AC signals, COG (NPO) ceramic capacitors provide the best capacitance
precision. The type of dielectric used in COG (NPO) ceramic capacitors provides the most stable electrical
properties over voltage, frequency, and temperature changes.
Driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier
marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of
the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a
result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance,
input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability
and distortion of the design. For low distortion applications, TI recommends limiting the value of RFLT to a
maximum of 50 Ω to avoid any significant degradation in linearity and THD performance.
The input amplifier bandwidth should be much higher than the cutoff frequency of the anti-aliasing filter. TI
strongly recommends performing a SPICE simulation to confirm that the amplifier has more than 40° phase
margin with the selected RC filter.
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Product Folder Links: ADS8331 ADS8332
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Application Information (continued)
RFLT ” 50
MUXOUT
f
1
3 dB
2S u RFLT u CFLT
CFLT • 450 pF
V
AINx
+
ADCIN
ADS8331/32
COM
GND
Figure 52. ADC Input RC Filter
40
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Product Folder Links: ADS8331 ADS8332
ADS8331, ADS8332
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10.2
SBAS363E – DECEMBER 2009 – REVISED AUGUST 2016
Typical Applications
10.2.1 DAQ Circuit for Low Noise and Distortion Performance for a 10-kHz Input Signal at 500 kSPS
Figure 53 illustrates a typical data acquisition circuit using the ADS833x for the lowest noise and distortion
performance using a 10-kHz input signal at 500 kSPS.
REFERENCE DRIVE CIRCUIT
VA=5V
-
REF2041
1k
VIN
1 µF
+
VREF
+
OPA320
RBUF_FLT
0.220
ENABLE
0.220
1 µF
VA=5V
VBIAS
GND
22 µF
10 µF
MUXOUT
+
Input Signal
(30mV to
4.096V)
40
+
REF+
ADCIN
REF5V
Ch0
VA
OPA320
1.5 nF
VA=5V
ADC
+
40
Chn
+
SDO
FS/CS
SDI
SCLK
EOC/INT/CDI
CONVST
To
Host
OPA320
1.5 nF
MUX
VA=5V
COM
Mode of Operation:
Throughput 350nS
INPUT DRIVERS
Figure 53. Typical Circuit Configuration
10.2.1.1 Design Requirements
This section describes an application circuit (Figure 53) optimized for using the ADS833x with lowest noise and
distortion performance at ADC throughput of 500kSPS across all channels, using Manual Trigger mode with
Auto-Nap mode disabled. The throughput per channel is dependent on the number of channels selected in the
multiplexer scanning sequence. For example, the throughput per channel is equal to 250 kSPS if two channels
are selected, but it is equal to 125 kSPS per channel if four channels are selected in the sequence and so forth.
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Typical Applications (continued)
10.2.1.2 Detailed Design Procedure
The signal is processed by a low noise, low distortion, operational amplifier in the non-inverting configuration and
a low-pass RC filter before being fed into the ADC. The OPA320 features rail-to-rail input operation with a zerocrossover distortion topology that eliminates the transition region typical in many rail-to-rail complementary input
stage amplifiers making it ideal to use in the non-inverting configuration. As a rule of thumb, the distortion from
the input driver should be at least 10-dB less than the ADC distortion. Therefore, the driver circuit uses the lowpower, wide bandwidth (20 MHz) OPA320 as an input driver, which provides exceptional AC performance
because of its low-noise, and low distortion specifications. In addition, the components of the RC filter are
selected such that the noise from the front-end circuit is limited without adding distortion to the input signal.
Driver Amplifier Choice lists some more driver amplifier choices for applications that require high throughput
operation with minimum acquisition time.
10.2.1.3 Application Curve
Figure 54 shows the FFT test results obtained with the ADS833x operating at full throughput of 500 kSPS and
the circuit configuration of Figure 53.
Figure 54. FFT Plot Showing Performance of ADS8331, ADS8332 With a 10-kHz Input Signal at 500 kSPS
42
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ADS8331, ADS8332
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SBAS363E – DECEMBER 2009 – REVISED AUGUST 2016
Typical Applications (continued)
10.2.2 Ultra Low-Power DAQ Circuit for DC Input Signals at 10 kSPS per Channel
Figure 55 illustrates a typical data acquisition circuit that is optimized for using the ADS833x in low power, low
throughput applications for monitoring static or DC signals.
R1=30
OPA320 MUXOUT to ADCIN Amplifier:
Mode of Operation: 1000nS
+
+
OPA320
C1=1 nF
COG/NPO
VA=2.7V
MUXOUT
+
VREF=2.5V,
Input Signal
(50mV to 3.0V)
220
+
ADCIN
2.7V
Ch0
VA
OPA333
VA=2.7V
0.047 µF
Cx
COG/NPO
ADC
+
220
Chn
+
OPA333
0.047 µF
VA=2.7
SDO
FS/CS
SDI
SCLK
EOC/INT/CDI
CONVST
To
Host
Cn
COG/NPO
MUX
NOTE:
OPA333 buffer circuit for low-power, slow throughput
applications monitoring DC signals.
When scanning through multiplexer channels, limit the
COM
maximum effective sampling rate per channel
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