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ADS8353-Q1
SBAS931A – JANUARY 2019 – REVISED MARCH 2019
ADS8353-Q1 Automotive, 16-bit, 2-channel,
simultaneous-sampling, 600-kSPS, analog-to-digital converter
1 Features
2 Applications
•
•
•
•
1
•
•
•
•
•
•
•
•
Qualified for automotive applications
AEC-Q100 qualified with the following results:
– Temperature grade 1: –40°C to 125°C, TA
– Device HBM ESD classification level 2
– Device CDM ESD classification level C4B
16-bit resolution
Simultaneous sampling of two channels
Supports single-ended and pseudo-differential
inputs
Two software-selectable, unipolar input ranges:
– (0 V to VREF) or (0 V to 2x VREF)
Up to 600-kSPS sampling speed
Excellent dc performance:
– ±1-LSB typ DNL
– ±1-LSB typ INL
– ±0.05% gain error
Excellent ac performance:
– 89-dB SNR
– –100-dB THD
Dual, low-drift (10 ppm/°C), programmable
2.5-V internal reference
•
•
•
Battery management systems (BMS)
Motor controls:
Resolvers for EV/HEV drive motor
Isolation fault detection
Engine control units (ECU)
Automotive sensor digitization
3 Description
The ADS8353-Q1 is a 16-bit, dual-channel, highspeed,
simultaneous-sampling,
analog-to-digital
converter (ADC) that supports single-ended and
pseudo-differential analog inputs.
The
ADS8353-Q1
includes
two
individually
programmable reference sources that can be used for
system-level gain calibration. Also, a flexible serial
interface that can operate over a wide power-supply
range enables easy communication with a large
variety of host controllers. Power consumption for a
given throughput can be optimized by using the two
low-power modes supported by the device. The
ADS8353-Q1 is fully specified over the temperature
range (–40°C to +125°C) and is available in a 16-pin
TSSOP package.
Device Information(1)
PART NUMBER
ADS8353-Q1
PACKAGE
TSSOP (16)
BODY SIZE (NOM)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application Diagram
ADS8353-Q1
REF_A
16-Bit
SAR ADC
ADC_A
Serial
Interface
ADC_B
16-Bit
SAR ADC
REF_B
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS8353-Q1
SBAS931A – JANUARY 2019 – REVISED MARCH 2019
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 6
Timing Requirements ................................................ 8
Switching Characteristics .......................................... 8
Typical Characteristics ............................................ 10
Detailed Description ............................................ 13
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
13
13
14
20
7.5 Programming........................................................... 20
7.6 Register Maps ......................................................... 27
8
Application and Implementation ........................ 30
8.1 Application Information............................................ 30
8.2 Typical Application .................................................. 32
9 Power Supply Recommendations...................... 34
10 Layout................................................................... 35
10.1 Layout Guidelines ................................................. 35
10.2 Layout Example .................................................... 35
11 Device and Documentation Support ................. 36
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
36
36
36
36
36
36
36
12 Mechanical, Packaging, and Orderable
Information ........................................................... 36
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (January 2019) to Revision A
•
2
Page
Changed device status from Advance Information to Production Data ................................................................................. 1
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SBAS931A – JANUARY 2019 – REVISED MARCH 2019
5 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
AINP_A
1
16
AVDD
AINM_A
2
15
GND
REFIO_A
3
14
SDO_B
REFGND_A
4
13
SDO_A
REFGND_B
5
12
SCLK
REFIO_B
6
11
CS
AINM_B
7
10
SDI
AINP_B
8
9
DVDD
Not to scale
Pin Functions
PIN
NAME
TSSOP
I/O
AINM_A
2
Analog input
Negative analog input, channel A
DESCRIPTION
AINM_B
7
Analog input
Negative analog input, channel B
AINP_A
1
Analog input
Positive analog input, channel A
AINP_B
8
Analog input
Positive analog input, channel B
AVDD
16
Supply
CS
11
Digital input
DVDD
9
Digital I/O supply
GND
15
Supply
Digital ground
REFGND_A
4
Supply
Reference ground potential A
REFGND_B
5
Supply
Reference ground potential B
REFIO_A
3
Analog input/output
Reference voltage input/output, channel A
REFIO_B
6
Analog input/output
Reference voltage input/output, channel B
SCLK
12
Digital input
Clock for serial communication
SDI
10
Digital input
Data input for serial communication
SDO_A
13
Digital output
Data output for serial communication, channel A and channel B
SDO_B
14
Digital output
Data output for serial communication, channel B
Supply voltage for ADC operation
Chip-select signal; active low
Digital I/O supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted) (1)
MIN
MAX
AVDD to REFGND_x (2) or GND
–0.3
6
V
DVDD to GND
–0.3
6
V
REFGND_x – 0.3
AVDD + 0.3
V
DVDD + 0.3
DVDD + 0.3
V
GND – 0.3
GND + 0.3
Input current to any pin except supply pins
-10
10
mA
Junction temperature, TJ
–40
125
°C
Storage temperature, Tstg
–65
150
°C
Analog (AINP_x and AINM_x) (3) and reference input
(REFIO_x) voltage with respect to REFGND_x
Digital input voltage with respect to GND
REFGND_x
(1)
(2)
(3)
UNIT
V
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
REFGND_x refers to REFGND_A and REFGND_B. REFIO_x refers to REFIO_A and REFIO_B.
AINP_x refers AINP_A and AINP_B. AINM_x refers to AINM_A and AINM_B.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
4
Electrostatic discharge
Charged-device model (CDM),
per AEC Q100-001, level C4B
UNIT
±2000
Corner pins (1,8,9 and
16)
±750
All other pins
±500
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VREF range, internal reference
4.5
5
5.5
VREF range, external reference VEXT_REF < 4.5 V
4.5
5
5.5
VREF range, external reference VEXT_REF > 4.5 V
VEXT_REF
5
5.5
2x VREF range, internal reference
5
5
5.5
2x VREF range, external reference
2 x VEXT_REF
5
5.5
1.65
3.3
5.5
UNIT
POWER SUPPLY
AVDD
DVDD
Analog supply voltage
(AVDD to AGND)
Digital supply voltage
V
V
ANALOG INPUTS (Single-Ended Configuration)
VREF range, single-ended input, AINM_x = GND
0
VREF
2x VREF range, single-ended input, AINM_x =
GND
0
2 x VREF
Absolute input voltage
(AINP_x to
REFGND_x) (2)
VREF range
0
VREF
2x VREF range, AVDD ≥ 2x VREF
0
2 x VREF
Absolute input voltage
(AINM_x to
REFGND_x)
VREF range, single-ended input
–0.1
0.1
2x VREF range, single-ended input, AVDD ≥ 2 x
VREF
–0.1
0.1
–VREF / 2
VREF / 2
–VREF
VREF
FSR
Full-scale input range
(AINP_x to AINM_x) (1)
VINP
VINM
V
V
V
ANALOG INPUTS (Pseudo-Differential Configuration)
FSR
VINP
VINM
Full-scale input range
(AINP_x-AINM_x)
VREF range, pseudo-differential input, AINM_x =
VREF/2
2x VREF range, pseudo-differential input,
AINM_x = VREF, AVDD ≥ 2x VREF
Absolute input voltage
(AINP_x to
REFGND_x)
VREF range
Absolute input voltage
(AINP_x to
REFGND_x) (2)
2x VREF range, AVDD ≥ 2x VREF
Absolute input voltage
(AINM_x -REFGND_x)
VREF range, pseudo-differential input
Absolute input voltage
(AINM_x -REFGND_x)
2x VREF range, single-ended input, AVDD ≥ 2x
VREF
V
0
VREF
V
0
2 x VREF
VREF / 2 –0.1
VREF / 2+0.1
VREF–0.1
VREF+0.1
V
EXTERNAL REFERENCE INPUT
VREFIO
REFIO_x (3) input
voltage
VREF range
2.4
2.5
AVDD
2x VREF range
2.4
2.5
AVDD / 2
–40
25
125
V
TEMPERATURE RANGE
TA
(1)
(2)
(3)
Ambient temperature
°C
AINP_x refers to analog input pins AINP_A and AINP_B. AINM_x refers to analog input pins AINM_A and AINM_B.
REFGND_x refers to reference ground pins REFGND_A and REFGND_B.
REFIO_x refers to voltage reference inputs REFIO_A and REFIO_B.
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6.4 Thermal Information
ADS8353-Q1
THERMAL METRIC (1)
PW (TSSOP)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
99
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
29.6
°C/W
45
ΨJT
°C/W
Junction-to-top characterization parameter
1.4
°C/W
YJB
Junction-to-board characterization parameter
44.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
at AVDD = 5 V, DVDD = 3.3 V, VREF_A = VREF_B = VREF = 2.5 V (internal), and fDATA = 600 kSPS (unless otherwise noted);
minimum and maximum values at TA = –40°C to 125°C; typical values are at TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESOLUTION
Resolution
16
Bits
DC ACCURACY
NMC
No missing codes
INL
Integral nonlinearity
DNL
Differential nonlinearity
EIO
Input offset error
16
–4
±1
Bits
4
±0.6
EIO match
ADC_A to ADC_B
LSB
–1
±0.5
1
–1
±0.5
1
dEIO/dT
Input offset thermal drift
EG
Gain error
Referenced to the voltage at REFIO_x
–0.1
±0.05
0.1
EG match
ADC_A to ADC_B
–0.1
±0.05
0.1
dEG/dT
1
Gain error thermal drift
Referenced to the voltage at REFIO_x
LSB
mV
mV
µV/°C
%FS
%FS
ppm/°
C
1
AC ACCURACY
VREF = 2.5 V, VREF input range
SINAD
Signal-to-noise + distortion
80.2
VREF = 2.5 V, 2x VREF input range
83.9
VREF = 5 V, VREF input range
88.7
VREF = 2.5 V, VREF input range
SNR
Signal-to-noise ratio
80.5
VREF = 2.5 V, 2x VREF input range
Total harmonic distortion
SFDR
Spurious-free dynamic range
dB
83
84
VREF = 5 V, VREF input range
THD
83
dB
89
VREF = 2.5 V, VREF input range
–100
VREF = 2.5 V, 2x VREF input range
–100
VREF = 5 V, VREF input range
–100
VREF = 2.5 V, VREF input range
105
VREF = 2.5 V, 2 x VREF input range
105
VREF = 5 V, VREF input range
105
dB
dB
ANALOG INPUT
Ci
Input capacitance
Ilkg
Input leakage current
In sample mode
40
In hold mode
pF
4
0.1
µA
INTERNAL VOLTAGE REFERENCE
VREFOUT
Reference output voltage
REFDAC_x = 1FFh (default) at 25°C
VREF-match
VREF_A to VREF_B matching
REFDAC_x = 1FFh (default) at 25°C
6
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2.495
2.5
±1
2.505
V
mV
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Electrical Characteristics (continued)
at AVDD = 5 V, DVDD = 3.3 V, VREF_A = VREF_B = VREF = 2.5 V (internal), and fDATA = 600 kSPS (unless otherwise noted);
minimum and maximum values at TA = –40°C to 125°C; typical values are at TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
REFDAC_x resolution (1)
TYP
MAX
UNIT
1.1
mV
dVREFOUT/dT
Reference voltage temperature
drift
REFDAC_x = 1FFh (default) at 25°C
±10
ppm/°
C
dVREFOUT/dt
Long-term stability
1000 hours
150
ppm
RO
Internal reference output
impedance
IREFOUT
CREFOUT
tREFON
Reference output settling time
1
Ω
Reference output dc current
2
mA
Reference output capacitor
10
µF
8
ms
300
µA
10
µF
±0.1
µA
VOLTAGE REFERENCE INPUT
IREF
Average reference input current
CREF
External ceramic reference
capacitor
Ilkg(dc)
DC leakage current
Per ADC
SAMPLING DYNAMICS
tA
Aperture delay
tA match
tAJIT
ADC_A to ADC_B
Aperture jitter
DIGITAL INPUTS
8
ns
40
ps
50
ps
(2)
VIH
DVDD > 2.3 V
0.7
DVDD
DVDD
+ 0.3
DVDD ≤ 2.3 V
0.8
DVDD
DVDD
+ 0.3
DVDD > 2.3 V
–0.3
0.3
DVDD
DVDD ≤ 2.3 V
–0.3
0.2
DVDD
High-level input voltage
VIL
Low-level input voltage
Input current
±10
V
V
nA
DIGITAL OUTPUTS (2)
VOH
High-level output voltage
IOH = 500-µA source
VOL
Low-level output voltage
IOL = 500-µA sink
0.8
DVDD
DVDD
V
0
0.2
DVDD
V
POWER SUPPLY
AIDD
Analog supply current
AVDD = 5 V, fastest throughput internal
reference
8.5
10
AVDD = 5 V, fastest throughput external
reference (3)
7.5
3.6
AVDD = 5V, no conversion internal
reference
5.5
7
AVDD = 5 V, no conversion external
reference (3)
4.5
AVDD = 5 V, STANDBY mode internal
reference
2.5
AVDD = 5 V, STANDBY mode external
reference (3)
1
Power-down mode
(1)
(2)
(3)
mA
10
50
µA
Refer to the Reference section for more details.
Specified by design; not production tested.
With internal reference powered down, CFR.B6 = 0.
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Electrical Characteristics (continued)
at AVDD = 5 V, DVDD = 3.3 V, VREF_A = VREF_B = VREF = 2.5 V (internal), and fDATA = 600 kSPS (unless otherwise noted);
minimum and maximum values at TA = –40°C to 125°C; typical values are at TA = 25°C
PARAMETER
DIDD
TEST CONDITIONS
Digital supply current
TYP
MAX
UNIT
0.5
mA
DVDD = 5 V, Cload = 10 pF, fastest
throughput
Power dissipation (normal
operation)
PD
MIN
DVDD = 3.3 V, Cload = 10 pF, fastest
throughput
1
AVDD = 5 V, fastest throughput, internal
reference
42.5
50
mW
6.6 Timing Requirements
at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values
at TA = –40°C to +125°C; typical values at TA = 25°C.
MAX
UNIT
tPH_CK
CLOCK high time
MIN
0.4
0.6
tCLK
tPL_CK
CLOCK low time
0.4
0.6
tCLK
fCLK
CLOCK frequency
20
MHz
tACQ
NOM
32-clock, dual SDO mode
33 x
tCLK tCONV
32-clock, single SDO mode
49 x
tCLK tCONV
Acquisition time
tCONV
Conversion time
tPH_CS
CS high time
730
tPH_CS_SHRT
CS high time after frame abort
tSU_CSCK
tD_CKCS
tSU_CKDI
ns
ns
40
ns
150
ns
Setup time: CS falling edge to SCLK falling edge
15
ns
Delay time: Last SCLK falling edge to CS rising edge
15
ns
Setup time: DIN data valid to SCLK falling edge
5
ns
tHT_CKDI
Hold time: SCLK falling edge to (previous) data valid on DIN
5
ns
tPU_STDBY
Power-up time from STANDBY mode
1
µs
tPU_SPD
Power-up time from SPD mode
With internal reference
3
With external reference
1
ms
6.7 Switching Characteristics
at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values
at TA = –40°C to +125°C; typical values at TA = 25°C.
PARAMETER
MAX
UNIT
600
kSPS
Delay time: CS falling edge to data
enable
12
ns
tDZ_CSDO
Delay time: CS rising edge to data going
to 3-state
12
ns
tD_CKDO
Delay time: SCLK falling edge to next
data valid
20
ns
tTHROUGHPUT
Throughput time
fTHROUGHPUT
Throughput
tDV_CSDO
8
TEST CONDITIONS
MIN
TYP
1.666
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CS
CS
tSU_CSCK
SCLK
1
SCLK
1
2
12
2
13
14
15
16
tSU_CKDI
tHT_CKDI
tDV_CSDO
SDO
SDI
B15
B4
B14
B3
B2
B1
Sample
N+1
Sample
N
CS
tPL_CK
tSCLK
tD_CKCS
tPH_CK
SCLK
1
2
N-9
N-8
N-7
N-6
N-5
N-4
N-3
N-2
N-1
N
tD_CKDO
SDO
V
V
D9
tDZ_CSDO
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 1. Serial Interface Timing Diagram
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6.8 Typical Characteristics
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 600 kSPS (unless otherwise noted)
0
85.2
85
-20
84.8
84.6
-60
Amplitude (dB)
Amplitude (dB)
-40
-80
-100
-120
84.4
84.2
84
83.8
83.6
83.4
-140
83.2
-160
83
-180
0
30
60
90 120 150 180 210
fIN, Input Frequency (kHz)
240
270
82.8
-60
300
-40
-20
D012
fIN = 2 kHz, SNR = 84.6 dB, THD = –107.6 dB
0
20
40
60
80
Free-Air Temperature (qC)
100
120
140
D014
fIN = 2 kHz
Figure 2. Typical FFT
Figure 3. SNR vs Temperature
85.2
89.5
85
89
84.8
88.5
88
84.4
SNR (dBFS)
SINAD (dBFS)
84.6
84.2
84
83.8
83.6
87.5
87
86.5
86
83.4
85.5
83.2
83
85
82.8
-60
84.5
2.4
-40
-20
0
20
40
60
80
Free-Air Temperature (qC)
100
120
140
2.7
3
D011
fIN = 2 kHz
3.3
3.6
3.9
4.2
Reference voltage (V)
4.5
4.8
5.1
D013
fIN = 2 kHz
Figure 4. SINAD vs Temperature
Figure 5. SNR vs Reference Voltage
-72
89.5
Total Harmonic Distortion (dB)
89
88.5
SINAD (dBFS)
88
87.5
87
86.5
86
85.5
-80
-88
-96
-104
-112
85
84.5
2.4
2.7
3
3.3
3.6
3.9
4.2
Reference voltage (V)
4.5
4.8
5.1
-120
-40
D010
fIN = 2 kHz
40
80
Free-Air Temperature (qC)
120
160
D016
fIN = 2 kHz
Figure 6. SINAD vs Reference Voltage
10
0
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Figure 7. THD vs Temperature
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Typical Characteristics (continued)
-80
12
-88
10
IAVDD Dynamic (mA)
Total Harmonic Distortion (dB)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 600 kSPS (unless otherwise noted)
-96
-104
-112
8
6
4
-120
2
2.5
3
3.5
4
4.5
Reference voltage (V)
5
2
-60
5.5
-30
0
30
60
90
Free-Air Temperature (qC)
D015
120
150
D018
fIN = 2 kHz
Figure 9. Analog Supply Current vs Temperature
18000
10
15000
12000
8
Frequency
6
9000
6000
4
3000
2
32774
32773
32772
32771
32770
32769
32768
32767
32766
D017
32765
21
32764
18
32763
9
12
15
SCLK Frequency (MHz)
32762
6
32759
3
32761
0
0
32760
IAVDD Dynamic (mA)
Figure 8. THD vs Reference Voltage
12
D005
65536 data points, VIN-DIFF = 0 V
Figure 11. DC Histogram
1.5
450
1
FSR)
600
300
Gain Error (
Offset Error (PV)
Figure 10. Analog Supply Current vs SCLK Frequency
150
0
-150
-60
0.5
0
-0.5
-30
0
30
60
90
Free-Air Temperature (qC)
120
150
-1
-60
D009
Figure 12. Offset Error vs Temperature
-30
0
30
60
90
Free-Air Temperature (qC)
120
150
D004
Figure 13. Gain Error vs Temperature
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Typical Characteristics (continued)
2
2
1.5
1.5
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 600 kSPS (unless otherwise noted)
1
0.5
0
-0.5
-1
-1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2
0
13705
27410
41115
Code
54820
65535
0
13705
Figure 14. Typical DNL
54820
65535
D008
Figure 15. Typical INL
3
2
DNL_MIN
DNL_MAX
1.6
INL_MIN
INL_MAX
1.2
Integral Nonlinearity (LSB)
Differentail Nonlinearity (LSB)
27410
41115
Code
D003
0.8
0.4
0
-0.4
-0.8
-1.2
2
1
0
-1
-1.6
-2
-40
-10
20
50
80
Free-Air Temperature (qC)
110
-2
-60
140
-30
D001
Figure 16. DNL vs Temperature
0
30
60
90
Free-Air Temperature (C)q
INL_MIN
INL_MAX
2
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
D006
2
DNL_MIN
DNL_MAX
1
0
-1
2.8
3.2
3.6
4
4.4
Reference Voltage (V)
4.8
5.2
1
0
-1
-2
-3
2.4
2.8
D002
Figure 18. DNL vs Reference Voltage
12
150
Figure 17. INL vs Temperature
3
-2
2.4
120
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3.2
3.6
4
4.4
Reference Voltage (V)
4.8
5.2
D007
Figure 19. INL vs Reference Voltage
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7 Detailed Description
7.1 Overview
The ADS8353-Q1 is a 16-bit, dual-channel, high-speed, simultaneous-sampling, analog-to-digital converter
(ADC). The ADS8353-Q1 supports single-ended and pseudo-differential input signals. The device provides a
simple, serial interface to the host controller and operates over a wide range of analog and digital power
supplies.
The device has two independently programmable internal references to achieve system-level gain error
correction. The Functional Block Diagram section provides a functional block diagram of the device.
7.2 Functional Block Diagram
REF_A
Comparator
S/H
CDAC
SAR
ADC_A
Serial
Interface
ADC_B
SAR
S/H
CDAC
Comparator
REF_B
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7.3 Feature Description
7.3.1 Reference
The device has two simultaneous sampling ADCs (ADC_A and ADC_B). ADC_A and ADC_B operate with
reference voltages present on the REFIO_A and REFIO_B pins, respectively. Decouple the REFIO_A and
REFIO_B pins with the REFGND_A and REFGND_B pins, respectively, with 10-µF decoupling capacitors.
Figure 20 shows that the device supports operation either with an internal or external reference source. The
reference voltage source is determined by setting bit 6 of the configuration register (CFR.B6). This bit is common
to ADC_A and ADC_B.
AINP_A
AINM_A
ADC_A
REFGND_A
REFDAC_A
DAC_A
10 PF
REFIO_A
CFR.B6
Enable
INTREF
REFIO_B
REFDAC_B
10 PF
DAC_B
REFGND_B
AINP_B
AINM_B
ADC_B
Figure 20. Reference Configurations and Connections
When CFR.B6 is 0, the device shuts down the internal reference source (INTREF) and ADC_A and ADC_B
operate on external reference voltages provided by the user on the REFIO_A and REFIO_B pins, respectively.
When CFR.B6 is 1, the device operates with the internal reference source (INTREF) connected to REFIO_A and
REFIO_B via DAC_A and DAC_B, respectively. In this configuration, VREF_A and VREF_B can be changed
independently by writing to the respective user-programmable registers, REFDAC_A and REFDAC_B,
respectively. See the Register Maps section for more details.
14
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Feature Description (continued)
7.3.2 Analog Inputs
The ADS8353-Q1 supports single-ended or pseudo-differential analog inputs on both ADC channels. These
inputs are sampled and converted simultaneously by the two ADCs, ADC_A and ADC_B. ADC_A samples and
converts (VAINP_A – VAINM_A), and ADC_B samples and converts (VAINP_B – VAINM_B).
Figure 21a and Figure 21b show equivalent circuits for the ADC_A and ADC_B analog input pins, respectively.
Series resistance, RS, represents the on-state sampling switch resistance (typically 50 Ω) and CSAMPLE is the
device sampling capacitor (typically 40 pF).
AVDD
AVDD
RS
CSAMPLE
AINP_A
RS
CSAMPLE
RS
CSAMPLE
AINP_B
GND
GND
AVDD
AVDD
RS
CSAMPLE
AINM_A
AINM_B
GND
GND
a) ADC_A
b) ADC_B
Figure 21. Equivalent Circuit for the Analog Input Pins
7.3.2.1 Analog Input: Full-Scale Range Selection
The full-scale range (FSR) supported at the analog inputs of the device is programmable with bit B9 of the
configuration register (CFR.B9). This bit is common for both ADCs (ADC_A and ADC_B). Equation 1 and
Equation 2 give the FSR:
For CFR.B9 = 0, FSR_ADC_A = 0 to VREF_A and FSR_ADC_B = 0 to VREF_B
For CFR.B9 = 1, FSR_ADC_A = 0 to 2 × VREF_A and FSR_ADC_B = 0 to 2 × VREF_B
(1)
where:
•
VREF_A and VREF_B are the reference voltages going to ADC_A and ADC_B, respectively (as described in the
Reference section).
(2)
Therefore, with appropriate settings of the REFDAC_A and REFDAC_B registers, CFR.B7, and CFR.B9, the
maximum dynamic range of the ADC can be used.
Make sure that the ADC analog supply (AVDD) is as in Equation 3 and Equation 4 when CFR.B9 is set to 1:
2 × VREF_A ≤ AVDD ≤ AVDD(max)
2 × VREF_B ≤ AVDD ≤ AVDD(max)
(3)
(4)
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Feature Description (continued)
7.3.2.2 Analog Input: Single-Ended and Pseudo-Differential Configurations
The ADS8353-Q1 can support single-ended or pseudo-differential input configurations.
For supporting single-ended inputs, B7 in the configuration register (CFR.B7) must be set to 0 (CFR.B7 = 0) and
AINM_A and AINM_B must be externally connected to GND.
For supporting pseudo-differential inputs, CFR.B7 must be set to 1 (CFR.B7 = 1) and AINM_A and AINM_B must
be externally connected to FSR_ADC_A / 2 and FSR_ADC_B / 2, respectively. CFR.B7 is common to both
ADCs.
The CFR.B9 and CFR.B7 settings can be combined as shown in Table 1 to select the desired input
configuration.
Table 1. Input Configurations
INPUT RANGE SELECTION
AINM SELECTION
CONNECTION DIAGRAM
VREF_x
VREF_x
REFIO_x
AINP_x
CFR.B9 = 0
(FSR_ADC_A = 0 to VREF_A)
(FSR_ADC_B = 0 to VREF_B)
CFR.B7 = 0
(AINM_A = GND)
(AINM_B = GND)
0V
Device
AINM_x
2 u VREF_x
VREF_x
REFIO_x
AINP_x
CFR.B9 = 1
(FSR_ADC_A = 0 to 2 x VREF_A)
(FSR_ADC_B = 0 to 2 x VREF_B)
CFR.B7 = 0
(AINM_A = GND)
(AINM_B = GND)
0V
Device
AINM_x
16
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Feature Description (continued)
Table 1. Input Configurations (continued)
INPUT RANGE SELECTION
AINM SELECTION
CONNECTION DIAGRAM
VREF_x
VREF_x
REFIO_x
AINP_x
0V
CFR.B9 = 0
(FSR_ADC_A = VREF_A)
(FSR_ADC_B = VREF_B)
CFR.B7 = 1
(AINM_A = VREF_A/2)
(AINM_B = VREF_B/2)
Device
AINM_x
VREF_x / 2
2 u VREF_x
VREF_x
REFIO_x
AINP_x
0V
CFR.B9 = 1
(FSR_ADC_A = 2 x VREF_A)
(FSR_ADC_B = 2 x VREF_B)
CFR.B7 = 1
(AINM_A = VREF_A)
(AINM_B = VREF_B)
Device
AINM_x
VREF_x
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7.3.3 Transfer Function
The device supports two input configurations:
1. Single-ended inputs, CFR.B7 = 0 (default), or
2. Pseudo-differential inputs, CFR.B7 = 1
The device also supports two output data formats:
1. Straight binary output, CFR.B4 = 0 (default), or
2. Two's compliment output, CFR.B4 = 1
Equation 5 calculates the device resolution:
1 LSB = (FSR_ADC_x) / (2N)
where:
•
•
N = 16
FSR_ADC_x = the full-scale input range of the ADC (see the Analog Inputs section for more details)
(5)
Table 2 and Table 3 show the different input voltages and the corresponding output codes from the device.
Table 2. Transfer Characteristics for Straight Binary Output (CFR.B4 = 0, Default)
AINP_x
AINM_x
Pseudo-differential
(CFR.B7 = 1)
STRAIGHT BINARY (CFR.B4 = 0, Default)
AINP_x - AINM_x
CODE
≤ 1 LSB
ZC
0000
FSR_ADC_x / 2
MC
7FFF
≥ FSR_ADC_x – 1 LSB
≥ FSR_ADC_x – 1 LSB
FSC
FFFF
≤ 1 LSB
≤ –FSR_ADC_x / 2 + 1 LSB
ZC
0000
0
MC
7FFF
≥ FSR_ADC_x / 2 – 1 LSB
FSC
FFFF
≤ 1 LSB
Single-ended
(CFR.B7 = 0, default)
OUTPUT CODE (Hex)
INPUT VOLTAGE
INPUT
CONFIGURATION
FSR_ADC_x / 2
FSR_ADC_x / 2
0
FSR_ADC_x / 2
≥ FSR_ADC_x – 1 LSB
ADS8353-Q1
Table 3. Transfer Characteristics for Two's Compliment Output (CFR.B4 = 1)
OUTPUT CODE (Hex)
INPUT VOLTAGE
INPUT
CONFIGURATION
AINP_x
AINM_x
≤ 1 LSB
Single-ended
(CFR.B7 = 0, default)
FSR_ADC_x / 2
0
≥ FSR_ADC_x – 1 LSB
≤ 1 LSB
Pseudo-differential
(CFR.B7 = 1)
FSR_ADC_x / 2
≥ FSR_ADC_x – 1 LSB
18
FSR_ADC_x / 2
TWO'S COMPLIMENT (CFR.B4 = 1,
Default)
AINP_x - AINM_x
CODE
ADS8353-Q1
≤ 1 LSB
NFSC
8000
FSR_ADC_x / 2
MC
0000
≥ FSR_ADC_x – 1 LSB
PFSC
7FFF
≤ –FSR_ADC_x / 2 + 1 LSB
NFSC
8000
0
MC
0000
≥ FSR_ADC_x / 2 – 1 LSB
PFSC
7FFF
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Figure 22 shows the ideal device transfer characteristics for the single-ended analog input.
PFSC
MC
MC
ZC
NFSC
1 LSB
FSR_ADC_x / 2
VIN
ADC Code (Hex)
Twos Compliment Output Format
ADC Code (Hex)
Straight Binary Output Format
FSC
FSR_ADC_x ± 1 LSB
Single-Ended Analog Input
(AINP_x ± AINM_x)
Figure 22. Ideal Transfer Characteristics for a Single-Ended Analog Input
Figure 23 shows the ideal device transfer characteristics for the pseudo-differential analog input.
PFSC
-FSR_ADC_x/2
+ 1 LSB
MC
0
FSR_ADC_x/2
± 1 LSB
ZC
MC
ADC Code (Hex)
Twos Compliment Output Format
ADC Code (Hex)
Straight Binary Output Format
FSC
NFSC
Pseudo-Differential Analog Input
(AINP_x ± AINM_x)
Figure 23. Ideal Transfer Characteristics for a Pseudo-Differential Analog Input
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7.4 Device Functional Modes
The device provides three user-programmable registers: the configuration register (CFR), the REFDAC_A
register, and the REFDAC_B register. These registers support write (see the Write to User-Programmable
Registers section) and readback (see the Reading User-Programmable Registers section) operations and allow
the ADC behavior to be customized for specific application requirements.
The device supports two interface modes (see the Conversion Data Read section), two low-power modes (see
the Low-Power Modes section), and a short-cycling or reconversion feature (see the Frame Abort, Reconversion,
or Short-Cycling section).
7.5 Programming
7.5.1 Serial Interface
The device uses the serial clock (SCLK) for synchronizing data transfers in and out of the device.
The CS signal defines one conversion and serial transfer frame. A frame starts with a CS falling edge and ends
with a CS rising edge. Between the start and end of the frame, a minimum of N SCLK falling edges must be
provided to validate the read or write operation. As shown in Table 4, N depends upon the interface mode used
to read the conversion result. When N SCLK falling edges are provided, the write operation attempted in the
frame is validated and the internal user-programmable registers are updated on the subsequent CS rising edge.
This CS rising edge also ends the frame.
Table 4. SCLK Falling Edges for a Valid Write Operation
MINIMUM SCLK FALLING EDGES REQUIRED TO
VALIDATE WRITE OPERATION N
INTERFACE MODE
32-CLK, dual-SDO mode (default); see the 32-CLK, Dual-SDO Mode section
32
32-CLK, single-SDO mode; see the 32-CLK, Single-SDO Mode section
48
If CS is brought high before providing N SCLK falling edges, the write operation attempted in the frame is not
valid. See the Frame Abort, Reconversion, or Short-Cycling section for more details.
7.5.2 Write to User-Programmable Registers
The device features three user-programmable registers: the configuration register (CFR), the REFDAC_A
register, and the REFDAC_B register. These registers can be written with the device SDI pin. The first 16 bits of
data on SDI are latched into the device on the first 16 SCLK falling edges. However, the new configuration takes
effect only when the read or write operation is validated. If these registers are not required to update, SDI must
remain low during the respective frames.
The first four SDI data bits (B[15:12]) determine what operation is performed (that is, either a read or write
operation or no operation), which register address the operation uses, and the function of the next 12 SDI data
bits (B[11:0]). Table 5 lists the various combinations supported for B[15:12].
Table 5. Data Write Operation
B15
B14
B13
B12
0
0
0
0
No operation is performed
These bits are ignored
0
0
0
1
REFDAC_A read
000h; see the Reading User-Programmable Registers section
0
0
1
0
REFDAC_B read
000h; see the Reading User-Programmable Registers section
0
0
1
1
CFR read
000h; see the Reading User-Programmable Registers section
1
0
0
0
CFR write
See the CFR register
1
0
0
1
REFDAC_A write
See the REFDAC register
1
0
1
0
REFDAC_B write
See the REFDAC register
1
0
1
1
No operation is performed
These bits are ignored
X
1
X
X
No operation is performed
These bits are ignored
20
OPERATION
FUNCTION OF BITS B[11:0]
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7.5.3 Data Read Operation
The device supports two types of read operations: reading user-programmable registers and reading conversion
results.
7.5.3.1 Reading User-Programmable Registers
The device supports a readback option for all user-programmable registers: CFR, REFDAC_A, and REFDAC_B.
Figure 24 shows a detailed timing diagram for this operation.
Frame (F)
Frame (F+1)
Frame (F+2)
Frame (F+3)
CS
SCLK
1
2
N
1
2
4
3
5
16
48
SDO-A
Valid Data
Valid data as per device configuration.
SDO-B
Valid Data
Valid data as per device configuration.
SDI
No change in device
configuration
B14 B13 B12
B15
X
X
X
1
2
R15 R14
15
16
R1
R0
47
1
48
2
N
Valid Data
Valid Data
X
No change in device
configuration
Device configuration for frame (F+3)
NOTE: N is a function of the device configuration, as described in Table 4.
Figure 24. Register Readback Timing
To readback the user-programmable register settings, transmit the appropriate control word, as shown in
Table 6, to the device during frame (F+1). Frame (F+1) must have at least 48 SCLK falling edges.
Table 6. Control Word to Readback User-Programmable Registers
CONTROL WORD TO BE PROGRAMMED IN FRAME (F+1)
USER-PROGRAMMABLE REGISTER
B[15:12] (Binary)
B[11:0] (Hex)
CFR
0011b
000h
REFDAC_A
0001b
000h
REFDAC_B
0010b
000h
Frame (F+2) must have at least 48 SCLK falling edges. During frame (F+2), SDO_A outputs the contents of the
selected user-programmable register on the first 16 SCLK falling edges (as shown in Table 7) and then outputs
0's for any subsequent SCLK falling edges. The SDO_B pin outputs 0's for all SCLK falling edges.
Table 7. Register Data Read Back
USERPROGRAMMABLE
REGISTER
DATA READ ON SDO-A IN FRAME (F+2)
R15
R14
R13
R12
R11
—
R3
R2
R1
R0
CFR
0
0
1
1
CFG.B11
—
CFG.B3
CFG.B2
CFG.B1
CFG.B0
REFDAC_A
0
0
0
1
REFDAC_A.D8
—
REFDAC_A.D0
0
0
0
REFDAC_B
0
0
1
0
REFDAC_B.D8
—
REFDAC_B.D0
0
0
0
Register settings programmed during frame (F+2) determine the device configuration in frame (F+3).
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7.5.3.2 Conversion Data Read
The device provides two different interface modes for reading the conversion result. These modes offer flexible
hardware connections and firmware programming. Table 8 shows how to select one of the two interface modes.
Table 8. Interface Mode Selection
CFR.B11
CFR.B10
INTERFACE MODE
MINIMUM SCLK FALLING EDGES
REQUIRED TO VALIDATE WRITE
OPERATION N
0
0
32-CLK, dual-SDO mode (default)
32
0
1
32-CLK, single-SDO mode
48
In the 32-CLK interface modes, the device uses an internal clock to convert the sampled analog signal. The
conversion is completed during the first 16 periods of SCLK and the conversion result can be read on the
subsequent SCLK falling edges.
The following sections detail the various interface modes supported by the device.
7.5.3.2.1 32-CLK, Dual-SDO Mode (CFR.B11 = 0, CFR.B10 = 0, Default)
The 32-CLK, dual-SDO mode is the default mode supported by the device. This mode can also be selected by
writing CFR.B11 = 0 and CFR.B10 = 0.
In this mode, the SDO_A pin outputs the ADC_A conversion result and the SDO_B pin outputs the ADC_B
conversion result. Figure 25 shows a detailed timing diagram for this mode.
Sample
N
Sample
N+1
tTHROUGHPUT
tACQ
tCONV
CS
SCLK
1
2
14
15
16
SDO_A and SDO_B
17
18
25
26
27
28
29
30
31
32
D15
D14
D7
D6
D5
D4
D3
D2
D1
D0
Data from sample N
SDI
B15
B14
B2
B1
B0
X
X
X
X
X
X
X
X
X
Figure 25. 32-CLK, Dual-SDO Mode Timing Diagram
A CS falling edge brings the serial data bus out of 3-state and also outputs a 0 on the SDO_A and SDO_B pins.
The device converts the sampled analog input during the conversion time (tCONV). SDO_A and SDO_B read 0
during this period. After completing the conversion process, the sample-and-hold circuit returns to sample mode.
The device outputs the MSBs of ADC_A and ADC_B on the SDO_A and SDO_B pins, respectively, on the 16th
SCLK falling edge. As shown in Table 9, the subsequent SCLK falling edges are used to shift out the rest of the
bits of the conversion result.
Table 9. Data Launch Edge
LAUNCH EDGE
DEVICE
PINS
CS
SCLK
CS
↓
↓1
—
↓15
↓16
—
↓27
↓28
↓29
↓30
↓31
↓32 ...
↑
SDO-A
0
0
—
0
D15_A
—
D4_A
D3_A
D2_A
D1_A
D0_A
0 ...
Hi-Z
SDO-B
0
0
—
0
D15_B
—
D4_B
D3_B
D2_B
D1_B
D0_B
0 ...
Hi-Z
ADS8353-Q1
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In this mode, at least 32 SCLK falling edges must be given to validate the read or write frame. A CS rising edge
ends the frame and puts the serial bus into 3-state.
See the Timing Requirements table for timing specifications specific to this serial interface mode.
7.5.3.2.2 32-CLK, Single-SDO Mode (CFR.B11 = 0, CFR.B10 = 1)
The 32-CLK, single-SDO mode provides the option of using only one SDO pin (SDO_A) to read conversion
results from both ADCs (ADC_A and ADC_B). SDO_B remains in 3-state and can be treated as a no connect
(NC) pin.
This mode can be selected by writing CFR.B11 = 0 and CFR.B10 = 1. Figure 26 shows a detailed timing diagram
for this mode.
Sample
N
Sample
N+1
tTHROUGHPUT
tACQ
tCONV
CS
SCLK
1
2
14
15
16
17
18
28
29
30
31
32
33
44
34
45
46
47
48
25
D15
SDO_A
D14
D4
D3
D2
D1
D0
D15
D4
D14
ADC A Data
SDI
B15
B14
B2
B1
B0
X
X
D3
D2
D1
D0
ADC B Data
X
X
X
X
X
X
X
Figure 26. 32-CLK, Single-SDO Mode Timing Diagram
A CS falling edge brings the serial data bus out of 3-state and also outputs a 0 on the SDO_A pin. The device
converts the sampled analog input during the conversion time (tCONV). SDO_A reads 0 during this period. After
competing the conversion process, the sample-and-hold circuit goes back into sample mode. The device outputs
the MSB of ADC_A on the SDO_A pin on the 16th SCLK falling edge. As shown in Table 10, the subsequent
SCLK falling edges are used to shift out the conversion result of ADC_A followed by the conversion result of
ADC_B on the SDO_A pin.
Table 10. Data Launch Edge
LAUNCH EDGE
DEVICE
ADS8353Q1
PIN
SDOA
CS
SCLK
CS
↓
↓1
—
↓15
↓16
—
↓27
↓28
↓29
↓30
↓31
↓32
—
↓43
↓44
↓45
↓46
↓47
↓48 ...
↑
0
0
—
0
D15_A
—
D4_A
D3_A
D2_A
D1_A
D0_A
D15_B
—
D4_B
D3_B
D2_B
D1_B
D0_B
0 ...
Hi-Z
In this mode, at least 48 SCLK falling edges must be given to validate the read or write frame. A CS rising edge
ends the frame and puts the serial bus into 3-state.
See the Timing Requirements table for timing specifications specific to this serial interface mode.
7.5.4 Low-Power Modes
In normal mode of operation, all internal circuits of the device are always powered up and the device is always
ready to commence a new conversion. This mode enables the device to support the rated throughput. The
device also supports two low-power modes to optimize the power consumption at lower throughputs: STANDBY
mode and software power-down (SPD) mode.
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7.5.4.1 STANDBY Mode
The device supports a STANDBY mode of operation where some of the internal circuits of the device are
powered down. However, if bit 6 in configuration register is set to 1 (CFR.B6 = 1), then the internal reference is
not powered down and the contents of the REFDAC_A and REFDAC_B registers are retained to enable faster
power-up to a normal mode of operation.
As shown in Figure 27, a valid write operation in frame (F) programs the configuration register with B5 set to 1
(CFR.B5 = 1) and places the device into a STANDBY mode of operation on the following CS rising edge. While
in STANDBY mode, SDO_A and SDO_B output all 1s when CS is low and remain in 3-state when CS is high.
To remain in STANDBY mode, SDI must remain low in the subsequent frames.
Device enters
STANDBY mode
Frame (F)
Frame (F+1)
Device in
STANDBY mode
CS
SCLK
1
2
3
4
5
6
7
SDO-A and
SDO-B
8
9
10
11
12
13
14
15
1
N
16
2
Valid Data as per device configuration
CFG.B[5] = 1
SDI
CFG.B[15:12] = 1000b
CFG.B[4:0] = 00000b
CFG.B[11:6]
NOTE: N is a function of the device configuration, as described in Table 4.
Figure 27. Enter STANDBY Mode
As shown in Figure 28, a valid write operation in frame (F+3) writes the configuration register with B5 set to 0
(CFR.B5 = 0) and brings the device out of STANDBY mode on the following CS rising edge. Frame (F+3) must
have at least 48 SCLK falling edges.
After exiting the STANDBY mode, a delay of tPU_STDBY must elapse for the internal circuits to fully power-up and
resume normal operation in frame (F+4). Device configuration for frame (F+4) is determined by the status of the
CFR.B[11:6] bits programmed during frame (F+3).
Frame (F+2)
CS
SCLK
Frame (F+3)
Device in
STANDBY
mode
tPU_STDBY
1
2
3
4
5
SDO-A
and
SDO-B
SDI
Frame (F+4)
Device exits
STANDBY mode
6
7
8
9
10
11
12
13
14
15
16
1
48
CFG.B[11:6]
15
16
N
Valid Data as per device configuration
These bits set device
configuration for Frame (F+4)
CFG.B[5] = 0
CFG.B[15:12] = 1000b
2
CFG.B[4:0] = 00000b
CFG settings for Frame (F+5)
NOTE: N is a function of the device configuration, as described in Table 4.
Figure 28. Exit STANDBY Mode
See the Timing Requirements table for timing specifications for this operating mode.
24
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7.5.4.2 Software Power-Down (SPD) Mode
In software power-down (SPD) mode, all internal circuits (including the internal references) are powered down.
However, the contents of the REFDAC_A and REFDAC_B registers are retained.
As shown in Figure 29, to enter SPD mode, the device must be selected (by bringing CS low) and SDI must be
kept high for a minimum of 48 SCLK cycles during frame (F). The device goes to SPD on the CS rising edge
following frame (F). While in SPD mode, SDO_A and SDO_B go to 3-state irrespective of the status of the CS
signal.
To remain in SPD mode, SDI must remain high in all subsequent frames.
Device enters SPD
mode
Frame (F)
Frame (F+1)
Device in SPD
mode
CS
SCLK
1
2
SDO-A and
SDO-B
3
47
1
48
2
Valid Data as per device configuration
SDI
Figure 29. Enter SPD Mode
As shown in Figure 30, to exit SPD mode, the device must be selected (by bringing CS low) and SDI must be
kept low for a minimum of 48 SCLK cycles during frame (F+3). The device starts powering-up on a CS rising
edge following frame (F+3). After frame (F+3), a delay of tPU_SPD must elapse before programming the
configuration register.
A valid write operation in frame (F+4) sets the device configuration for frame (F+5). Frame (F+4) must have at
least 48 SCLK falling edges. Discard the output data in frame (F+4).
Frame (F+2)
Frame (F+3)
Frame (F+4)
Device exits
SPD
Frame (F+5)
tPU_SPD
CS
SCLK
Device in
SPD
1
2
47
48
1
2
SDO-A
and
SDO-B
SDI
15
16
1
48
Invalid Data
2
15
16
N
Valid Data as per device configuration
CFG settings for Frame (F+5)
CFG settings for Frame (F+6)
NOTE: N is a function of the device configuration, as described in Table 4.
Figure 30. Exit SPD Mode
See the Timing Requirements table for timing specifications for this operating mode.
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7.5.5 Frame Abort, Reconversion, or Short-Cycling
As shown in Figure 31, the minimum number of SCLK falling edges (N) that must be provided between the
beginning and end of the frame depends on the serial interface mode. The SCLK falling edges (N) program the
device and retrieve the conversion result. If CS is brought high before the expected number of SCLK falling
edges are provided, the current frame is aborted and the device starts sampling the new analog input signal.
If frame (F) is aborted, then the register write operation attempted in frame (F) is considered invalid and the
internal registers are not updated. The device continues to have the same configuration in frame (F+1) from
frame (F).
The output data bits latched before the CS rising edge are still valid data that correspond to sample N.
tPL_CS
tPH_CS_SHRT
CS
1
SCLK
2
SDO
Sample
N
Sample
N+1
tCONV
tACQ
tPH_CS_SHRT
CS
SCLK
1
2
SDO
13
14
15
16
17
22
23
24
V
V
V
V
V
Data From Sample N
Figure 31. Frame Abort, Reconversion, or Short-Cycling Feature
See the Timing Requirements table for timing specifications for this operating mode.
26
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7.6 Register Maps
7.6.1 ADS8353-Q1 Registers
Table 11 lists the memory-mapped registers for the ADS8353-Q1 registers. Consider any register offset
addresses not listed in Table 11 as reserved locations and, therefore, do not modify the register contents.
Table 11. ADS8353-Q1 Registers
Offset
Acronym
Register Name
0h
CFR
CFR register
2h
REFDAC
REFDAC register
Section
CFR Register (Offset = 0h) [reset =
0h]
REFDAC Register (Offset = 2h) [reset
= 0h]
Complex bit access types are encoded to fit into small table cells. Table 12 shows the codes that are used for
access types in this section.
Table 12. ADS8353-Q1 Access Type Codes
Access Type
Code
Description
R
Read
W
Write
Read Type
R
Write Type
W
Reset or Default Value
-n
Value after reset or the default value
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7.6.1.1 CFR Register (Offset = 0h) [reset = 0h]
CFR is shown in Figure 32 and described in Table 13.
Return to Summary Table.
Figure 32. CFR Register
15
14
13
12
WRITE_READ_CFR[3:0]
R/W-0000b
7
6
5
INM_SEL
REF_SEL
STANDBY
R/W-0b
R/W-0b
W-0b
4
RD_DATA_
FORMAT
R/W-0b
11
RD_CLK_
MODE
R/W-0b
10
RD_DATA_
LINES
R/W-0b
9
8
INPUT_RANGE
RESERVED
R/W-0b
R/W-0b
3
2
1
0
0[3:0]
R/W-0000b
Table 13. CFR Register Field Descriptions
Bit
15-12
Field
Type
Reset
Description
WRITE_READ_CFR[3:0]
R/W
0000b
These bits select the user-programmable register.
0011b = Select this combination to read the CFR register
1000b = Select this combination to write to CFR register and
enable bits 11:0
11
RD_CLK_MODE
R/W
0b
This bit must be set to 0 (default).
10
RD_DATA_LINES
R/W
0b
This bit provides data line selection for the serial interface.
0b = Use SDO_A to output ADC_A data and SDO_B to output
of ADC_B data (default)
1b = Use only SDO_A to output of ADC_A data followed by
ADC_B data
9
INPUT_RANGE
R/W
0b
This bit selects the maximum input range for the ADC as a function
of the reference voltage provided to the ADC. See the Analog Inputs
section for more details.
0b = FSR equals VREF
1b = FSR equals 2× VREF
8
RESERVED
R/W
0b
This bit must be set to 0 (default).
7
INM_SEL
R/W
0b
This bit selects the voltage to be externally connected to the INM
pin.
0b = INM must be externally connected to the GND potential
(default)
1b = INM must be externally connected to the FSR_ADC_x / 2
6
REF_SEL
R/W
0b
This bit selects the ADC reference voltage source. See the
Reference section for more details.
0b = Use external reference (default)
1b = Use internal reference
5
STANDBY
W
0b
This bit is used by the device to enter or exit STANDBY mode. See
the STANDBY Mode section for more details.
4
RD_DATA_FORMAT
R/W
0b
This bit selects the output data format.
0b = Output is in straight binary format (default)
1b = Output is in two's complement format
3-0
28
0[3:0]
R/W
0000b
These bits must be set to 0 (default).
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7.6.1.2 REFDAC Register (Offset = 2h) [reset = 0h]
REFDAC is shown in Figure 33 and described in Table 14.
Return to Summary Table.
Figure 33. REFDAC Register
15
14
13
WRITE_READ_REFDAC[3:0]
R/W-0000b
7
6
5
D[8:0]
R/W-000000000b
12
11
10
9
D[8:0]
R/W-000000000b
4
3
2
1
RESERVED
R/W-000b
8
0
Table 14. REFDAC Register Field Descriptions
Field
Type
Reset
Description
15-12
Bit
WRITE_READ_REFDAC[3:0]
R/W
0000b
These
bits
select
the
configurable
register
address.
1001 = Select this combination to write to the REFDAC_A register
1010 = Select this combination to write to the REFDAC_B register
11-3
D[8:0]
R/W
000000000b
Data to program the individual DAC output voltage.
These bits are valid only for bits 15:12 = 1001 or bits 15:12 = 1010.
Table 15 shows the relationship between the REFDAC_x
programmed value and the DAC_x output voltage.
2-0
RESERVED
R/W
000b
This bit must be set to 0 (default).
Table 15. REFDAC Settings
(1)
REFDAC_x VALUE (Bits 11:3 in Hex)
B[2:0]
Typical DAC_x OUPTUT VOLTAGE (V) (1)
1FF (default)
000
2.5000
1FE
000
2.4989
1FD
000
2.4978
—
—
—
1D7
000
2.45
—
—
—
1AE
000
2.40
—
—
—
186
000
2.35
—
—
—
15D
000
2.30
—
—
—
134
000
2.25
—
—
—
10C
000
2.20
—
—
—
0E3
000
2.15
—
—
—
0BA
000
2.10
—
—
—
091
000
2.05
—
—
—
069
000
2.00
—
—
—
064 to 000
000
Do not use
Actual output voltage may vary by a few millivolts from the specified value. To obtain the desired output voltage, TI recommends starting
with the specified register setting and then experimenting with five codes on either side of the specified register setting.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The two primary circuits required to maximize the performance of a high-precision, successive approximation
register (SAR), analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This
section details some general principles for designing these circuits, and some application circuits designed using
these devices.
The device supports operation either with an internal or external reference source. See the Reference section for
details about the decoupling requirements.
The reference source to the ADC must provide low-drift and very accurate dc voltage and support the dynamic
charge requirements without affecting the noise and linearity performance of the device. The output broadband
noise (typically in the order of a few 100 μVRMS) of the reference source must be appropriately filtered by using a
low-pass filter with a cutoff frequency of a few hundred hertz. After band-limiting the noise from the reference
source, the next important step is to design a reference buffer that can drive the dynamic load posed by the
reference input of the ADC. At the start of each conversion, the reference buffer must regulate the voltage of the
reference pin within 1 LSB of the intended value. This condition necessitates the use of a large filter capacitor at
the reference pin of the ADC. The amplifier selected to drive the reference input pin must be stable while driving
this large capacitor and must have low output impedance, low offset, and temperature drift specifications. To
reduce the dynamic current requirements and crosstalk between the channels, a separate reference buffer is
recommended for driving the reference input of each ADC channel.
The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and a fly-wheel
RC filter. The amplifier is used for signal conditioning of the input voltage and its low output impedance provides
a buffer between the signal source and the switched capacitor inputs of the ADC. The RC filter helps attenuate
the sampling charge injection from the switched-capacitor input stage of the ADC and functions as an charge
kickback filter to band-limit the wideband noise contributed by the front-end circuit. Careful design of the frontend circuit is critical to meet the linearity and noise performance of a high-precision ADC.
8.1.1 Input Amplifier Selection
Selection criteria for the input amplifiers is highly dependent on the input signal type and the performance goals
of the data acquisition system. Some key amplifier specifications to consider while selecting an appropriate
amplifier to drive the inputs of the ADC are:
• Small-signal bandwidth. Select the small-signal bandwidth of the input amplifiers to be as high as possible
after meeting the power budget of the system. Higher bandwidth reduces the closed-loop output impedance
of the amplifier, thus allowing the amplifier to more easily drive the low cutoff frequency RC filter at the ADC
inputs. Higher bandwidth also minimizes the harmonic distortion at higher input frequencies. Select the
amplifier bandwidth as described in Equation 6 to maintain the overall stability of the input driver circuit:
§
1
Unity Gain Bandwidth t 4 u ¨¨
© 2S u ( RFLT RFLT ) u C FLT
30
·
¸¸
¹
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Application Information (continued)
•
Noise. Noise contribution of the front-end amplifiers must be as low as possible to prevent any degradation in
SNR performance of the system. As a rule of thumb, to ensure that the noise performance of the data
acquisition system is not limited by the front-end circuit, keep the total noise contribution from the front-end
circuit below 20% of the input-referred noise of the ADC. Equation 7 calculates noise from the input driver
circuit. This noise is band-limited by designing a low cutoff frequency RC filter:
§ V 1 _ AM P_ PP ·
¨
¸
NG u 2 u ¨ f
¸¸
6.6
¨
©
¹
2
en2 _ RM S u
S
uf
2
3 dB
d
1 VREF
u
u 10
5
2
§ SNR dB ·
¨
¸
20
©
¹
where:
•
•
•
•
•
V1/f_AMP_PP = the peak-to-peak flicker noise in µV
en_RMS = the amplifier broadband noise density in nV/√Hz
f–3dB = the 3-dB bandwidth of the RC filter
NG = the noise gain of the front-end circuit, which is equal to 1 in a buffer configuration
Distortion. Both the ADC and the input driver introduce nonlinearity in a data acquisition block. As a rule of
thumb, the distortion of the input driver must be at least 10 dB lower than the distortion of the ADC, as shown
in Equation 8, to ensure that the distortion performance of the data acquisition system is not limited by the
front-end circuit.
THD AMP d THD ADC
•
(7)
10 dB
(8)
Settling Time. For dc signals with fast transients that are common in a multiplexed application, the input signal
must settle to the desired accuracy at the inputs of the ADC during the acquisition time window. This
condition is critical to maintain the overall linearity performance of the ADC. Typically, the amplifier data
sheets specify the output settling performance only up to 0.1% to 0.001%, which may not be sufficient for the
desired accuracy. Therefore, always verify the settling behavior of the input driver with TINA™-SPICE
simulations before selecting the amplifier.
8.1.2 Charge Kickback Filter
Converting analog-to-digital signals requires sampling an input signal at a constant rate. Any higher frequency
content in the input signal beyond half the sampling frequency is digitized and folded back into the low-frequency
spectrum. This process is called aliasing. Therefore, an analog, charge kickback filter must be used to remove
the harmonic content from the input signal before being sampled by the ADC. A charge kickback filter is
designed as a low-pass, RC filter, for which the 3-dB bandwidth is optimized based on specific application
requirements. For dc signals with fast transients (including multiplexed input signals), a high-bandwidth filter is
designed to allow accurately settling the signal at the ADC inputs during the small acquisition time window. For
ac signals, keep the filter bandwidth low to band-limit the noise fed into the ADC input, thereby increasing the
signal-to-noise ratio (SNR) of the system.
A filter capacitor, CFLT, connected across the ADC inputs (see Figure 34), filters the noise from the front-end
drive circuitry, reduces the sampling charge injection, and provides a charge bucket to quickly charge the internal
sample-and-hold capacitors during the acquisition process. As a rule of thumb, the value of this capacitor must
be at least 10 times the specified value of the ADC sampling capacitance. For these devices, the input sampling
capacitance is equal to 40 pF. Thus, the value of CFLT must be greater than 400 pF. The capacitor must be a
COG- or NPO-type because these capacitor types have a high-Q, low-temperature coefficient, and stable
electrical characteristics under varying voltages, frequency, and time.
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Application Information (continued)
RFLT
1
f-3dB
CFLT
AINP
=
2Πx RFLT x CFLT
ADS8353-Q1
AINM
GND
RFLT
CFLT
GND
Figure 34. Charge Kickback Filter
Driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier
marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of
the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a
result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance,
input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability
and distortion of the design. For more information on ADC input R-C filter component selection, see the TI
Precision Labs on ti.com.
8.2 Typical Application
Input Driver
AVDD
AVDD
OPA320-Q1
±
49
AINP
+
VIN
3.3nF
Device
+
±
AINM
3.3nF
GND
49
VDC
NOTE: Only one ADC channel is shown in this diagram. Replicate the same circuit for other ADC channels.
Figure 35. DAQ Circuit: Maximum SINAD for a 10-kHz Input Signal at Full Throughput, 32-CLK Interface
AVDD
10 µF
REFGND_A
AVDD
0.1
ADC_A
±
REFIN_A
1k
+
REF34-Q1
1µF
ADS8353-Q1
VOUT
AVDD
10 µF
±
1k
REFIN_B
+
0.1
ADC_B
1µF
REFGND_B
OPA2320-Q1
10 µF
Figure 36. Reference Drive Circuit
32
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Typical Application (continued)
8.2.1 Design Requirements
Table 16 lists the target specifications for this application.
Table 16. Target Specifications
TARGET SPECIFICATIONS
TEST CONDITIONS
SNR
THD
DEVICE
INPUT SIGNAL
FREQUENCY
THROUGHPUT
INTERFACE MODE
> 83 dB
< –100 dB
ADS8353-Q1
10 kHz
Maximum supported
32-CLK, dual-SDO
8.2.2 Detailed Design Procedure
Best practice is for the distortion from the input driver to be at least 10 dB less than the ADC distortion. The
distortion resulting from variation in the common-mode signal is eliminated by using the amplifier in an inverting
gain configuration that establishes a fixed common-mode level for the circuit. This configuration also eliminates
the requirement of rail-to-rail swing at the amplifier input. The low-power OPA320-Q1, used as an input driver,
provides exceptional ac performance because of its extremely low-distortion and high-bandwidth specifications.
In addition, the components of the antialiasing filter are such that the noise from the front-end circuit is kept low
without adding distortion to the input signal.
The application circuit illustrated in Figure 35 is optimized to achieve the lowest distortion and lowest noise for a
10-kHz input signal fed to the ADS8353-Q1 operating at full throughput with the default 32-CLK, dual-SDO
interface mode. The input signal is processed through a high-bandwidth, low-distortion amplifier in an inverting
gain configuration and a low-pass RC filter before being fed into the device.
Figure 36 illustrates the reference driver circuit when operation with an external reference is desired. The
reference voltage is generated by the high-precision, low-noise REF34-Q1 circuit. The output broadband noise of
the reference is heavily filtered by a low-pass filter with a 3-dB cutoff frequency of 160 Hz. The decoupling
capacitor on each reference pin is selected to be 10 µF. The low output impedance, low noise, and fast settling
time make the OPA2320-Q1 a good choice for driving this high capacitive load.
8.2.3 Application Curve
To minimize external components and to maximize the dynamic range of the ADC, the device is configured to
operate with internal reference (CFR.B6 = 1) and 2x VREF_x input full-scale range (CFR.B9 = 1).
Figure 37 shows the FFT plot and test result obtained with the ADS8353-Q1 operating at full throughput with a
32-CLK interface and the circuit configuration of Figure 35.
0
±20
Signal Power (dB)
±40
±60
±80
±100
±120
±140
±160
±180
±200
0
60
120
180
Input Frequency (kHz)
240
300
C301
SNR = 83.5 dB, THD = –101.2 dB, fIN = 10.1 kHz
Figure 37. ADS8353-Q1 in 32-CLK Interface Mode
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9 Power Supply Recommendations
The device has two separate power supplies: AVDD and DVDD. The device operates on AVDD; DVDD is used
for the interface circuits. AVDD and DVDD can be independently set to any value within the permissible ranges.
When using the device with the 2× VREF input range (CFR.B9 = 1), the AVDD supply voltage value defines the
permissible voltage swing on the analog input pins. AVDD must be set as shown in Equation 9, Equation 10, and
Equation 11 to avoid saturation of output codes and to use the full dynamic range on the analog input pins:
AVDD ≥ 2 × VREF_A
AVDD ≥ 2 × VREF_B
4.75 V ≤ AVDD ≤ 5.25 V
(9)
(10)
(11)
Decouple the AVDD and DVDD pins, as shown in Figure 38, with the GND pin using individual 10-µF decoupling
capacitors.
Device
AVDD
AVDD (Pin 16)
10 …F
GND (Pin 15)
10 …F
DVDD
DVDD (Pin 9)
Figure 38. Power-Supply Decoupling
34
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SBAS931A – JANUARY 2019 – REVISED MARCH 2019
10 Layout
10.1 Layout Guidelines
Figure 39 shows a board layout example for the ADS8353-Q1 TSSOP package. Partition the printed circuit board
(PCB) into analog and digital sections. Avoid crossing digital lines with the analog signal path and keep the
analog input signals and the reference input signals away from noise sources. As shown in Figure 39, the analog
input and reference signals are routed on the left side of the board and the digital connections are routed on the
right side of the device.
The power sources to the device must be clean and well-bypassed. Use 10-μF, ceramic bypass capacitors in
close proximity to the analog (AVDD) and digital (DVDD) power-supply pins. Avoid placing vias between the
AVDD and DVDD pins and the bypass capacitors. Connect all ground pins to the ground plane using short, low
impedance paths.
The REFIO-A and REFIO-B reference inputs and outputs are bypassed with 10-μF, X7R-grade, 0805-size, 16-V
rated ceramic capacitors (CREF-x). Place the reference bypass capacitors as close as possible to the reference
REFIO-x pins and connect the bypass capacitors using short, low-inductance connections. Avoid placing vias
between the REFIO-x pins and the bypass capacitors. Small 0.1-Ω to 0.2-Ω resistors (RREF-x) are used in series
with the reference bypass capacitors to improve stability.
The fly-wheel RC filters are placed immediately next to the input pins. Among ceramic surface-mount capacitors,
COG (NPO) ceramic capacitors provide the best capacitance precision. The type of dielectric used in COG
(NPO) ceramic capacitors provides the most stable electrical properties over voltage, frequency, and temperature
changes. Figure 39 shows CIN-A and CIN-B filter capacitors placed across the analog input pins of the device.
10.2 Layout Example
GND
CIN-A
RFLT-A
1
AINP_A
AVDD
16
2
AINM_A
GND
15
3
REFIO_A
SDO_B
14
4
REFGND_A
SDO_A
13
5
REFGND_B
SCLK
12
6
REFIO_B
CS
11
7
AINM_B
SDI
10
8
AINP_B
DVDD
CIN-A
CAVDD
RFLT-A
GND
RREF-A
CREF-A
GND
CREF-B
RREF-B
RFLT-B
CIN-B
CIN-B
9
CDVDD
RFLT-B
GND
GND
Figure 39. Recommended Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
Texas Instruments, TI Precision Labs TI training and videos site
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, OPAx320-Q1 Precision, 20-MHz, 0.9-pA, low-noise, RRIO, CMOS operational amplifier
data sheet
• Texas Instruments, REF34-Q1 Low-drift, low-power, small-footprint series voltage references data sheet
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
TINA, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
36
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ADS8353QPWQ1
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
A8353Q
ADS8353QPWRQ1
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
A8353Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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