ADS8361IDBQR

ADS 836 ADS8361 1 AD S 83 61 SBAS230C – AUGUST 2002 – REVISED SEPTEMBER 2004 Dual, 500kSPS, 16-Bit, 2 + 2 Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES q q q q q q q q q 2 SIMULTANEOUS 16-BIT DACs 4 FULLY DIFFERENTIAL INPUT CHANNELS 2µs THROUGHPUT PER CHANNEL 4µs TOTAL THROUGHPUT FOR FOUR CHANNELS LOW POWER: 150mW INTERNAL REFERENCE FLEXIBLE SERIAL INTERFACE 16-BIT UPGRADE TO THE 12-BIT ADS7861 PIN COMPATIBLE WITH THE ADS7861 DESCRIPTION The ADS8361 is a dual, 16-bit, 500kSPS, Analog-to-Digital (A/D) converter with four fully differential input channels grouped into two pairs for high-speed, simultaneous signal acquisition. Inputs to the sample-and-hold amplifiers are fully differential and are maintained differentially to the input of the A/D converter. This provides excellent common-mode rejection of 80dB at 50kHz, which is important in high-noise environments. The ADS8361 offers a high-speed, dual serial interface and control inputs to minimize software overhead. The output data for each channel is available as a 16-bit word. The ADS8361 is offered in SSOP-24 and QFN-32 (5x5) packages and is fully specified over the –40°C to +85°C operating range. APPLICATIONS q MOTOR CONTROL q MULTI-AXIS POSITIONING SYSTEMS q 3-PHASE POWER CONTROL CH A0+ CH A0– SAR SHA CDAC CH A1+ CH A1– COMP SERIAL DATA A SERIAL DATA B M0 REFIN Internal 2.5V Reference Serial Interface M1 A0 CLOCK CS REFOUT CH B0+ CH B0– SHA CDAC COMP RD BUSY CONVST CH B1+ CH B1– SAR Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002-2004, Texas Instruments Incorporated www.ti.com ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings over operating free-air temperature (unless otherwise noted)(1). Supply Voltage, AGND to AVDD ............................................. –0.3V to 7V Supply Voltage, BGND to BVDD ............................................. –0.3V to 7V Analog Input Voltage ................................. AGND – 0.3V to AVDD + 0.3V Reference Input Voltage ........................... AGND – 0.3V to AVDD + 0.3V Digital Input Voltage .................................. BGND – 0.3V to BVDD + 0.3V Ground Voltage Differences, AGND to BGND ................................ ±0.3V Voltage Differences, BVDD to AGND ..................................... –0.3V to 7V Input Current to Any Pin Except Supply ......................... –20mA to 20mA Power Dissipation ....................................... See Dissipation Rating Table Operating Virtual Junction Temperature Range, TJ ........ –40°C to 150°C Operating Free-Air Temperature Range, TA ...................... –40°C to 85°C Storage Temperature Range, TSTG .................................. –65°C to 150°C Lead Temperature 1.6mm (1/16 inch) from Case for 10s ...................... 260°C NOTE: (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions of extended periods may affect device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION MAXIMUM INTEGRAL LINEARITY ERROR (LSB) ±8 NO MISSING CODES ERROR (LSB) 14 SPECIFIED PACKAGE TEMPERATURE DESIGNATOR(1) RANGE DBQ –40°C to +85°C PRODUCT ADS8361 PACKAGE-LEAD SSOP-24 ORDERING NUMBER ADS8361IDBQ ADS8361IDBQR ADS8361IRHBT ADS8361IRHBR TRANSPORT MEDIA, QUANTITY Rails, 56 Tape and Reel, 2500 Tape and Reel, 250 Tape and Reel, 3000 " ADS8361 " ±8 " 14 " QFN-32 " RHB " –40°C to +85°C " " " " " " NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. RECOMMENDED OPERATING CONDITIONS CONDITIONS Supply Voltage, AGND to AVDD Supply Voltage, BGND to BVDD Reference Input Voltage Operating Common-Mode Signal Analog Inputs Operating Junction Temperature Range Low-Voltage Levels 5V Logic Levels –IN +IN – (–IN) TJ MIN 4.75 2.7 4.5 1.2 2.2 0 –40 NOM 5 5 2.5 2.5 MAX 5.25 3.6 5.5 2.6 2.8 ±VREF 105 UNITS V V V V V V °C PACKAGE DISSIPATION RATING PACKAGE SSOP-24 QFN-32 (5x5) RθJC 28.5°C/W 1.007°C/W RθJA 88°C/W 36.7°C/W DERATING FACTOR ABOVE TA = 25°C 11.364mW/°C 27.25mW/°C TA ≤ 25°C POWER RATING 1420mW 2725mW TA ≤ 70°C POWER RATINGQ 909mW 1499mW TA = 85°C POWER RATING 738mW 1090mW EQUIVALENT INPUT CIRCUIT AVDD RON = 20Ω AIN C(SAMPLE) = 25pF DIN BVDD AGND Diode Turn on Voltage: 0.35V Equivalent Analog Input Circuit BGND Equivalent Digital Input Circuit 2 ADS8361 www.ti.com SBOS230C ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range at –40°C to 85°C, AVDD = 5V, BVDD = 3V, VREF = internal +2.5V, fCLK = 10MHz, and fSAMPLE = 500 kSPS, unless otherwise noted. ADS8361 PARAMETER ANALOG INPUT (FSR) Full-Scale Range(2) Operating Common-Mode Signal Input Switch Resistance Input Capacitance Input Leakage Current Differential Input Switch Resistance Differential Input Capacitance Common-Mode Rejection Ratio (CMRR) DC ACCURACY Resolution No Missing Code Integral Linearity Error Integral Linearity Match Differential Nonlinearity Bipolar Offset Error Bipolar Offset Error Match Bipolar Offset Error Drift Gain Error(6) Gain Error Match Gain Error Drift Noise Power-Supply Rejection Ratio SAMPLING DYNAMICS Conversion Time per A/D Acquisition Time Throughout Rate Aperture Delay Aperture Delay Matching Aperture Jitter Clock Frequency AC ACCURACY Total Harmonic Distortion Spurious-Free Dynamic Range Signal-to-Noise Ratio Signal-to-Noise + Distortion Channel-to-Channel Isolation CONDITIONS MIN TYP(1) MAX ±VREF 2.8 20 25 ±1 40 15 84 80 16 14 Channel 0/1, Same A/D (DNL) (VOS) Channel 0/1, Same A/D (TCVOS) (GERR) (TCGERR) (PSRR) 4.75V < AVDD < 5.25V, with External Reference, at DC 100kHz ≤ fCLK ≤ 10MHz fCLK = 10MHz 1.6 400 ±3 4 +1.5(4) ±0.5 0.5 0.4 ±0.05 0.05 20 60 –70 ±8 UNITS +IN – (–IN) 2.2 –IN = VREF –IN = VREF –IN = VREF At DC VIN = ±1.25Vp-p at 50kHz V V Ω pF nA Ω pF dB dB Bits Bits LSB(3) LSB LSB mV mV ppm/°C % % ppm/°C µVrms dB (NMC) (INL) ±2 1 ±0.5 0.15 (tCONV) (tAQ) 160 500 5 100 50 0.1 (THD) (SFDR) (SNR) (SINAD) VIN VIN VIN VIN VIN = = = = = ±2.5Vp-p ±2.5Vp-p ±2.5Vp-p ±2.5Vp-p ±2.5Vp-p at at at at at 10kHz 10kHz 10kHz 10kHz 10kHz 2.475 –94 94 83 83 96 2.5 ±20 10 12 60 10 0.5 100 1.2 100 2.5 5 10 µs ns kSPS ns ps ps MHz dB dB dB dB dB VOLTAGE REFERENCE OUTPUT Reference Voltage Ouput (VOUT) Initial Accuracy Output Voltage Temperature Drift (dVOUT/dT) Output Voltage Noise Power-Supply Rejection Ratio Output Current Short-Circuit Current Turn On Settling Time VOLTAGE REFERENCE INPUT Reference Voltage Input Reference Input Resistance Reference Input Capacitance Reference Input Current (PSRR) (IOUT) (ISC) 2.525 ±1 f = 0.1Hz to 10Hz, CL = 10µF f = 10Hz to 10kHz, CL = 10µF to 0.1% at CL = 0 (VIN) V % ppm/°C µVp-p µVrms dB µA mA µs V MΩ pF µA 2.6 1 NOTES: (1) All Values are at TA = 25°C. (2) Ideal input span; does not include gain or offset error. (3) LSB means Least Significant Bit, with VREF equal to +2.5V; 1LSB = 76µV. (4) Specified for 14-bit no missing code. (5) Specified for 15-bit no missing code. (6) Measured relative to an ideal, full-scale input (+IN – (–IN)) of 4.9999V. Thus, gain error does not include the error of the internal voltage reference. ADS8361 SBOS230C www.ti.com 3 ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range at –40°C to 85°C, AVDD = 5V, VREF = internal +2.5V, fCLK = 10MHz, and fSAMPLE = 500 kSPS, unless otherwise noted. ADS8361 PARAMETER DIGITAL INPUTS(2) Logic Family High-Level Input Voltage Low-Level Input Voltage Input Current Input Capacitance CONDITIONS MIN TYP(1) MAX UNITS CMOS (VIH) (VIL) (IIN) (CI) 0.7 • VDD –0.3 VI = BVDD or BGND 5 CMOS BVDD = 4.5V, IOH = –100µA BVDD = 4.5V, IOH = –100µA CS = BVDD, VI = BVDD or BGND 4.44 0.5 ±50 5 30 Binary Two’s Complement LVCMOS (VIH) (VIL) (IIN) (CI) BVDD = 3.6V BVDD = 2.7V VI = BVDD or BGND 2 –0.3 5 LVCMOS BVDD = 2.7V, IOH = –100µA BVDD = 2.7V, IOH = –100µA CS = BVDD, VI = BVDD or BGND VDD – 0.2 0.2 ±50 5 30 Binary Two’s Complement V V nA pF pF pF VDD + 0.3 0.8 ±50 V V nA pF V V nA pF pF pF VDD + 0.3 0.3 • VDD ±50 V V nA pF DIGITAL OUTPUTS(2) Logic Family High-Level Output Voltage (VOH) Low-Level Output Voltage (VOL) High-Impedance-State Output Current (IOZ) Output Capacitance (CO) Load Capacitance (CL) Data Format DIGITAL INPUTS(3) Logic Family High-Level Input Voltage Low-Level Input Voltage Input Current Input Capacitance DIGITAL OUTPUTS(3) Logic Family High-Level Output Voltage (VOH) Low-Level Output Voltage (VOL) High-Impedance-State Output Current (IOZ) Output Capacitance (CO) Load Capacitance (CL) Data Format POWER SUPPLY Analog Supply Voltage Digital Supply Voltage Analog Operating Supply Current Digital Operating Supply Current Power Dissipation (AVDD) (BVDD) (AIDD) (BIDD) Low-Voltage Levels 5V Logic Levels BVDD BVDD BVDD BVDD = = = = 3V 5V 3V 5V 4.75 2.7 4.5 150 150 5.25 3.6 5.5 35 1(4) 1(4) 200 200 V V V mA µA µA mW mW NOTES: (1) All Values are at TA = 25°C. (2) Applies for 5.0V nominal supply: BVDD (min) = 4.5V and BVDD (max) = 5.5V. (3) Applies for 3.0V nominal supply: BVDD (min) = 2.7V and BVDD (max) = 3.6V. (4) No clock active (static). 4 ADS8361 www.ti.com SBOS230C BASIC CIRCUIT CONFIGURATION + ADS8361 1 2 3 4 5 6 7 8 9 + BGND CH B1+ CH B1– CH B0+ CH B0– CH A1+ CH A1– CH A0+ CH A0– BVDD 24 SERIAL DATA A 23 SERIAL DATA B 22 BUSY 21 CLOCK 20 CS 19 RD 18 CONVST 17 A0 16 M0 15 M1 14 AVDD 13 + 10µF 0.1µF +2.7V to +5.5V Digital Supply BUSY Output Clock Input Chip Select Read Input Conversion Start A0 Address Select M0 Address Select M1 Address Select +5V Analog Supply 10µF 0.1µF 10 REFIN 10µF 0.1µF 11 REFOUT 12 AGND TRUTH TABLE M0 0 0 0 0 1 1 M1 0 0 1 1 0 1 A0 0 1 0 1 X X TWO-CHANNEL/FOUR-CHANNEL OPERATION Two-Channel Two-Channel Two-Channel Two-Channel Four-Channel Four-Channel DATA ON SERIAL OUTPUTS A and B A and B A Only A Only A and B A Only CHANNELS CONVERTED A0 and B0 A1 and B1 A0 and B0 A1 and B1 Sequential Sequential NOTE: X = Don’t Care. ADS8361 SBOS230C www.ti.com 5 PIN CONFIGURATION ADS8361 BGND CH B1+ CH B1– CH B0+ CH B0– CH A1+ CH A1– CH A0+ CH A0– BVDD SERIAL DATA A Top View SSOP Top View QFN 1 2 3 4 5 6 7 8 9 NC NC NC NC SERIAL DATA A 23 SERIAL DATA B 22 BUSY 21 CLOCK 20 CS 19 RD 18 CONVST 17 A0 16 M0 15 M1 14 AVDD 13 CH B1+ CH B1− CH B0+ CH B0− CH A1+ CH A1− CH A0+ CH A0− 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 NC BVDD 24 BGND 25 24 23 22 21 SERIAL DATA B BUSY CLOCK CS RD CONVST A0 M0 ADS8361 20 19 18 17 10 REFIN 11 REFOUT 12 AGND 10 11 12 13 14 15 NC REFIN AGND NC NOTE: NC = Not Connected. PIN DESCRIPTIONS SSOP QFN PIN PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 28 1 2 3 4 5 6 7 8 9 10 12 13 16 17 NAME BGND CH B1+ CH B1– CH B0+ CH B0– CH A1+ CH A1– CH A0+ CH A0– REFIN REFOUT AGND AVDD M1 M0 DESCRIPTION Digital I/O Ground. Connect directly to analog ground (pin 12). Noninverting Input Channel B1 Inverting Input Channel B1 Noninverting Input Channel B0 Inverting Input Channel B0 Noninverting Input Channel A1 Inverting Input Channel A1 Noninverting Input Channel A0 Inverting Input Channel A0 Reference Input 2.5V Reference Output Analog Ground. Connect directly to digital ground (pin 1). Analog Power Supply, +5VDC. Decouple to analog ground with a 0.1µF ceramic capacitor and a 10µF tantalum capacitor. Selects between the Serial Outputs. When M1 is LOW, both Serial Output A and Serial Output B are selected for data transfer. When M1 is HIGH, Serial output A is configured for both Channel A data and Channel B data; Serial Output B goes into tri-state (i.e., high impedance). Selects between two-channel and four-channel operation. When M0 is LOW, two-channel operation is selected and operates in conjunction with A0. When A0 is HIGH, Channel A1 and Channel B1 are being converted. When A0 is LOW, Channel A0 and Channel B0 are being converted. When M0 is HIGH, four-channel operation is selected. In this mode, all four channels are converted in sequence starting with Channels A0 and B0, followed by Channels A1 and B1. A0 operates in conjunction with M0. With M0 LOW and A0 HIGH, Channel A1 and Channel B1 are converted. With M0 LOW and A0 LOW, Channel A0 and Channel B0 are converted. Convert Start. When CONVST switches from LOW to HIGH, the device switches from the sample to hold mode, independent of the status of the external clock. Synchronization Pulse for the Serial Output. Chip Select. When LOW, the Serial Output A and Serial Output B outputs are active; when HIGH, the serial outputs are tri-stated. An external CMOS-compatible clock can be applied to the CLOCK input to synchronize the conversion process to an external source. The CLOCK pin controls the sampling rate by the equation: fSAMPLE (max) = CLOCK/20. BUSY goes HIGH during a conversion and returns LOW after the third LSB has been transmitted on either the Serial A or Serial B output pin. The Serial Output data word is comprised of channel information and 16 bits of data. In operation, data is valid on the falling edge of DCLOCK for 20 edges after the rising edge of RD. The Serial Output data word is comprised of channel information and 16 bits of data. In operation, data is valid on the falling edge of DCLOCK for 20 edges after the rising edge of RD. When M1 is HIGH, both Channel A data and Channel B data are available. Digital I/O Power Supply, 2.7V to 5.5V 16 17 18 19 20 21 22 23 24 18 19 20 21 22 23 24 25 27 A0 CONVST RD CS CLOCK BUSY SERIAL DATA B SERIAL DATA A BVDD REFOUT AVDD NC M1 16 9 6 ADS8361 www.ti.com SBOS230C TIMING CHARACTERISTICS tCKH CLOCK 0 1 2 3 4 10 11 tCKL t6 CONVST t11 t2 A0 t3 t1 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 t4 RD t5 t7 t8 CS t8 Serial Data A CH 0/1 CH A/B D15 D14 D8 D7 t9 D6 D5 t10 D4 D3 D2 D1 D0 0 0 0 0 D15 D14 D13 D12 Serial Data B CH 0/1 0 D15 D14 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 D15 D14 D13 D12 BUSY tCONV tACQ tCONV TIMING CHARACTERISTICS Timing Characteristics over recommended operating free-air temperature range TMIN to TMAX, AVDD = 5V, REFIN = REFOUT internal reference +2.5V, fCLK = 10MHz, fSAMPLE = 500kSPS, and BVDD = 2.7 ÷ 5.5V (unless otherwise noted). SYMBOL tCONV tACQ tCKP tCKL tCKH tF tR t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 DESCRIPTION Conversion Time Acquisition Time Clock Period Clock LOW Clock HIGH DOUT Fall Time DOUT Rise Time CONVST HIGH Address Setup Time Address Hold Time RD Setup Time RD to CS Hold Time CONVST LOW RD LOW CS Setup Time CLOCK to Data Valid Delay Data Valid After CLOCK(3) CS Setup Time MIN 1.6 0.4 100 40 40 MAX UNITS µs µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns COMMENTS When TCKP = 100ns When TCKP = 100ns 10,000 25 30 15 15 15 15 15 20 20 15 30 1 0 Address latched on falling edge of CLK cycle ‘2’. Before falling edge of CLOCK. After falling edge of CLOCK. Before falling edge of CLOCK (for RD). Maximum delay following rising edge of CLOCK. Time data is valid after second rising edge of CLOCK. Before CONVST NOTES: (1) All input signals are specified with tr = tf = 5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2. (2) See timing diagram above. (3) ‘n – 1’ data will remain valid 1ns after rising edge of next CLOCK cycle. ADS8361 SBOS230C www.ti.com 7 TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = 5V, BVDD = 3V, VREF = internal +2.5V, fCLK = 10MHz, and fSAMPLE = 500kHz, unless otherwise noted. INTEGRAL LINEARITY ERROR vs CODE 5 4 3 2 1 0 –1 –2 –3 –4 8000H DIFFERENTIAL LINEARITY ERROR vs CODE 3 Typical curve for all four channels. 2 DNL (LSB) C000H 0000H Output Code 4000H 7FFFH INL (LSB) 1 0 –1 8000H C000H 0000H Output Code 4000H 7FFFH INTEGRAL LINEARITY MATCH OF CHANNELS A0 AND B0 vs CODE 4 3 2 4 3 2 INTEGRAL LINEARITY MATCH OF CHANNELS A0 AND A1 (or B0 and B1) vs CODE INL Match (LSB) 1 0 –1 –2 –3 –4 8000H INL Match (LSB) C000H 0000H Output Code 4000H FFFFH 1 0 –1 –2 –3 –4 8000H C000H 0000H Output Code 4000H FFFFH DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 4.5 4 3.5 2 3 LSB 4 INTEGRAL LINEARITY ERROR MATCH vs TEMPERATURE Max 3 2 1.5 1 LSB 2.5 1 0 –1 Min –2 0.5 0 –40 0 25 Temperature (°C) 85 –3 –40 0 25 Temperature (°C) 85 8 ADS8361 www.ti.com SBOS230C TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, AVDD = 5V, BVDD = 3V, VREF = internal +2.5V, fCLK = 10MHz, and fSAMPLE = 500kHz, unless otherwise noted. FREQUENCY SPECTRUM (4096 point FFT, fIN = 5kHz, –0.2dB) 0 –20 –40 0 –20 –40 FREQUENCY SPECTRUM (4096 point FFT, fIN = 10kHz, –0.2dB) Amplitude (dB) –60 –80 –100 –120 –140 –160 0 50 100 150 200 250 Frequency (kHz) Amplitude (dB) –60 –80 –100 –120 –140 –160 0 50 100 150 200 250 Frequency (kHz) CHANGE IN BIPOLAR OFFSET vs TEMPERATURE 500 400 300 200 100 0 –100 –200 –40 BIPOLAR OFFSET MATCH vs TEMPERATURE Channel A0/Channel B0 600 500 400 µV µV 300 200 100 0 –40 0 25 Temperature (°C) 85 0 25 Temperature (°C) 85 REFERENCE VOLTAGE vs TEMPERATURE 2.504 2.502 32 31 SUPPLY CURRENT vs TEMPERATURE Supply Current (mA) 0 25 Temperature (°C) 85 2.5 30 29 28 27 26 25 –40 VREF (V) 2.498 2.496 2.494 2.492 –40 0 25 Temperature (°C) 85 ADS8361 SBOS230C www.ti.com 9 INTRODUCTION The ADS8361 is a high-speed, low-power, dual, 16-bit A/D converter that operates from +3V/+5V supply. The input channels are fully differential with a typical common-mode rejection of 80dB. The part contains dual, 4µs successive approximation A/D converter, two differential sample-andhold amplifiers, an internal +2.5V reference with REFIN and REFOUT pins, and a high-speed serial interface. The ADS8361 requires an external clock. In order to achieve the maximum throughput rate of 500kHz, the master clock must be set at 10MHz. A minimum of 20 clock cycles are required for each 16-bit conversion. There are four analog inputs that are grouped into two channels (A and B). Channel selection is controlled by the M0 (pin 14), M1 (pin 15), and A0 (pin 16) pins. Each channel has two inputs (A0, A1 and B0, B1) that are sampled and converted simultaneously, thus preserving the relative phase information of the signals on both analog inputs. The part accepts an analog input voltage in the range of –VREF to +VREF, centered around the internal +2.5V reference. The part will also accept bipolar input ranges when a level shift circuit is used at the front end (see Figure 7). All conversions are initiated on the ADS8361 by bringing the CONVST pin HIGH for a minimum of 15ns. CONVST HIGH places both sample-and-hold amplifiers in the hold state simultaneously and the conversion process is started on both channels. The RD pin (pin 18) can be connected to CONVST to simplify operation. Depending on the status of the M0, M1, and A0 pins, the ADS8361 will (a) operate in either twochannel or four-channel mode and (b) output data on both the Serial A and Serial B output or both channels can be transmitted on the A output only. NOTE: See the Timing and Control section of this data sheet for more information. REFERENCE Under normal operation, the REFOUT pin (pin 2) should be directly connected to the REFIN pin (pin 1) to provide an internal +2.5V reference to the ADS8361. The ADS8361 can operate, however, with an external reference in the range of 1.2V to 2.6V for a corresponding full-scale range of 2.4V to 5.2V. The internal reference of the ADS8361 is buffered. If the internal reference is used to drive an external load, a buffer is provided between the reference and the load applied to pin 2 (the internal reference can typically source 10µA of current— load capacitance should be 0.1µF and 10µF). If an external reference is used, the second buffer provides isolation between the external reference and the Capacitve Digital-toAnalog Converter (CDAC). This buffer is also used to recharge all of the capacitors of both CDACs during conversion. ANALOG INPUT The analog input is bipolar and fully differential. There are two general methods of driving the analog input of the ADS8361: single-ended or differential (see Figures 1 and 2). When the input is single-ended, the –IN input is held at the common-mode voltage. The +IN input swings around the same common voltage and the peak-to-peak amplitude is the (common-mode + VREF) and the (common-mode – VREF). The value of VREF determines the range over which the common-mode voltage may vary (see Figure 3). When the input is differential, the amplitude of the input is the difference between the +IN and –IN input, or (+IN) – (–IN). The peak-to-peak amplitude of each input is ±1/2 VREF around this common voltage. However, since the inputs are 180° out-ofphase, the peak-to-peak amplitude of the differential voltage is +VREF to –VREF. The value of VREF also determines the range of the voltage that may be common to both inputs (see Figure 4). SAMPLE-AND-HOLD SECTION The sample-and-hold amplifiers on the ADS8361 allow the A/D converter to accurately convert an input sine wave of fullscale amplitude to 16-bit accuracy. The input bandwidth of the sample-and-hold is greater than the Nyquist rate (Nyquist equals one-half of the sampling rate) of the A/D converter even when the A/D converter is operated at its maximum throughput rate of 500kHz. Typical aperture delay time, or the time it takes for the ADS8361 to switch from the sample to the hold mode following the CONVST pulse, is 3.5ns. The average delta of repeated aperture delay values is typically 50ps (also known as aperture jitter). These specifications reflect the ability of the ADS8361 to capture AC input signals accurately at the exact same moment in time. –VREF to +VREF peak-to-peak Common Voltage Single-Ended Input ADS8361 VREF peak-to-peak Common Voltage ADS8361 VREF peak-to-peak Differential Input FIGURE 1. Methods of Driving the ADS8361 Single-Ended or Differential. 10 ADS8361 www.ti.com SBOS230C CM + VREF +VREF CM Voltage +IN –IN = CM Voltage –VREF CM – VREF t Single-Ended Inputs +IN CM + 1/2 VREF CM Voltage CM – 1/2 VREF –IN +VREF –VREF t Differential Inputs (+IN) + (–IN) , Common-Mode Voltage (Single-Ended Mode) = IN–. 2 The maximum differential voltage between +IN and –IN of the ADS8361 is VREF. See Figures 3 and 4 for a further explanation of the common voltage range for single-ended and differential inputs. NOTES: Common-Mode Voltage (Differential Mode) = FIGURE 2. Using the ADS8361 in the Single-Ended and Differential Input Modes. 5 4.1 4 AVDD = 5V 5 4.7 AVDD = 5V 4.0 4 Common Voltage Range (V) Common Voltage Range (V) 3 Single-Ended Input 2.7 2.3 3 Differential Input 2 2 1 0.9 1 0.3 1.0 0 0 –1 1.0 1.2 2.0 VREF (V) 2.5 2.6 3.0 –1 1.0 1.2 2.0 VREF (V) 2.5 2.6 3.0 FIGURE 3. Single-Ended Input: Common-Mode Voltage Range vs VREF. In each case, care should be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are matched. Otherwise, this may result in offset error, gain error, and linearity error which will change with both temperature and input voltage. The input current on the analog inputs depend on a number of factors: sample rate, input voltage, and source impedance. Essentially, the current into the ADS8361 charges the internal capacitor array during the sampling period. After this FIGURE 4. Differential Input: Common-Mode Voltage Range vs VREF. capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (25pF) to a 16-bit settling level within 4 clock cycles. When the converter goes into the hold mode, the input impedance is greater than 1GΩ. Care must be taken regarding the absolute analog input voltage. The +IN and –IN inputs should always remain within the range of AGND – 0.3V to AVDD + 0.3V. ADS8361 SBOS230C www.ti.com 11 TRANSITION NOISE The transition noise of the ADS8361 itself is low, as shown in Figure 5. These histograms were generated by applying a low-noise DC input and initiating 8000 conversions. The digital output of the A/D converter will vary in output code due to the internal noise of the ADS8361. This is true for all 16bit, Successive Approximation Register (SAR-type) A/D converters. Using a histogram to plot the output codes, the distribution should appear bell-shaped with the peak of the bell curve representing the nominal code for the input value. The ±1σ, ±2σ, and ±3σ distributions will represent the 68.3%, 95.5%, and 99.7%, respectively, of all codes. The transition noise can be calculated by dividing the number of codes measured by 6 and this will yield the ±3σ distribution, or 99.7%, of all codes. Statistically, up to three codes could fall outside the distribution when executing 1000 conversions. Remember, to achieve this low-noise performance, the peakto-peak noise of the input signal and reference must be < 50µV. BIPOLAR INPUTS The differential inputs of the ADS8361 were designed to accept bipolar inputs (–VREF and +VREF) around the internal reference voltage (2.5V), which corresponds to a 0V to 5V input range with a 2.5V reference. By using a simple op amp circuit featuring a single amplifier and four external resistors, the ADS8361 can be configured to except bipolar inputs. The conventional ±2.5V, ±5V, and ±10V input ranges can be interfaced to the ADS8361 using the resistor values shown in Figure 7. R1 4kΩ 20kΩ Bipolar Input OPA227 600Ω –IN R2 ADS8361 OPA227 REFOUT (pin 11) 2.5V 600Ω +IN 5000 4500 BIPOLAR INPUT ±10V ±5V ±2.5V R1 1kΩ 2kΩ 4kΩ R2 5kΩ 10kΩ 20kΩ Number of Conversions 4000 3500 3000 2500 2000 1500 1000 500 0 32761 32762 32763 32764 32765 32766 Code (decimal) FIGURE 7. Level Shift Circuit for Bipolar Input Ranges. TIMING AND CONTROL The operation of the ADS8361 can be configured in four different modes by using the address pins M0 (pin 14), M1 (pin 15), and A0 (pin 16). The M0 pin selects between two- and four-channel operation (in two-channel operation, the A0 pin selects between Channels 0 and 1; in four-channel operation the A0 pin is ignored and the channels are switched automatically after each conversion). The M1 pin selects between having serial data transmitted simultaneously on both the Serial A data output (pin 23) and the Serial B data output (pin 22) or having both channels output data through the Serial A port. The A0 pin selects either Channel 0 or Channel 1 (see Pin Descriptions and Serial Output Truth Table for more information). The next four sections will explain the four different modes of operation. FIGURE 5. Histogram of 8000 Conversions of a DC Input. 1.4V 3kΩ DATA 100pF CLOAD Test Point Mode I (M0 = 0, M1 = 0) DATA tR tF VOH VOL Voltage Waveforms for DATA Rise-and-Fall Times tR, and tF. FIGURE 6. Test Circuits for Timing Specifications. With the M0 and M1 pins both set to ‘0’, the ADS8361 will operate in two-channel operation (the A0 pin must be used to switch between Channels A and B). A conversion is initiated by bringing CONVST HIGH for a minimum of 15ns. It is very important that CONVST be brought HIGH a minimum of 10ns prior to a falling edge of the external clock or 5ns after the falling edge. If CONVST is brought HIGH within this window, it is then uncertain as to when the ADS8361 will initiate conversion (see Figure 9 for a more detailed descrip- 12 ADS8361 www.ti.com SBOS230C Binary Two’s Complement BTC 0111 1111 1111 1111 0111 1111 1111 1110 0111 1111 1111 1101 65535 65534 65533 Digital Output Code 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 32769 32768 32767 1000 0000 0000 0010 2 1000 0000 0000 0001 1 0 1000 0000 0000 0000 VNFS = VCM – VREF = 0V 0.000038V 0.000076V 0.000152V 2.499962V 2.500038V VBPZ = 2.5V VPFS = VCM + VREF = 5V VPFS – 1LSB = 4.999924V 4.999848V 1LSB = 76µV VCM = 2.5V VREF = 2.5V Unipolar Analog Input Voltage 16-BIT Bipolar Input, Binary Two’s Complement Output: (BTC) Negative Full-Scale Code = VNFS = 8000H, Vcode = VCM – VREF Bipolar Zero Code = VBPZ = 0000H, Vcode = VCM Positive Full-Scale Code = VPFS = 7FFFH, Vcode = (VCM + VREF) – 1LSB FIGURE 8. Ideal Conversion Characteristics (Condition: Single Ended, VCM = chXX– = 2.5V, VREF = 2.5V) tion). Twenty clock cycles are required to perform a single conversion. Immediately following CONVST switching to HIGH, the ADS8361 will switch from the sample mode to the hold mode asynchronous to the external clock. The BUSY output pin will then go HIGH and remain HIGH for the duration of the conversion cycle. On the falling edge of the first cycle of the external clock, the ADS8361 will latch in the address for the next conversion cycle depending on the status of the A0 pin (HIGH = Channel 1, LOW = Channel 0). The address must be selected 15ns prior to the falling edge of cycle one of the external clock and must remain ‘held’ for 15ns following the clock edge. For maximum throughput time, the CONVST and RD pins should be tied together. CS must be brought LOW to enable the CONVST and RD inputs. Data will be valid on the falling edge of all 20 clock cycles per conversion. The first bit of data will be a status flag for either Channel 0 or 1, the second bit will be a second status flag for either Channel A or B. First and second bit will be 0 in Mode I. See Table II below. The subsequent data will be MSB-first through the LSB, followed by two zeros (see Table III and Figures 9 and 10). MODE 1 2 3 4 M0 0 0 1 1 BIT 1 M1 0 1 0 1 BIT 2 CH0/1 0 0 0/1 0/1 CHA/B 0 0 = A/1 = B 0 0 = A/1 = B CHANNEL SELECTION Ch0/1 Selected by A0 Ch0/1 Selected by A0 Ch0/1 Alternating Ch0/1 Alternating DATA OUTPUT On Data A and B Sequentially on Data A On Data A and B Sequentially on Data A TABLE II. Mode Selection. CLOCK CYCLE SERIAL DATA 1 2 3 4 5 6 7 8 9 10 11 DB7 12 DB6 13 DB5 14 DB4 15 DB3 16 DB2 Step 17 DB1 18 DB0 19 0 20 0 CH0 OR CH1 CHA OR CHB DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 TABLE III. Serial Data Output Format. ADS8361 SBOS230C www.ti.com 13 Mode II (M0 = 0, M1 = 1) With M1 set to ‘1’, the ADS8361 will output data on the Serial Data A pin only. All other pins function in the same manner as Mode I except that the Serial Data B output will tri-state (i.e., high impedance) after a conversion following M1 going HIGH. Another difference in this mode involves the CONVST pin. Since it takes 40 clock cycles to output the results from both A/D converters (rather than 20 when M1 = 0), the ADS8361 will take 4µs to complete a conversion on both A/D converters (See Figure 11). output of the analog comparator. Thus, driving any single conversion for an n-bit SAR converter, there are n “windows” in which large external transient voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, or high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. Their error can change if the external event changes in time with respect to the CLOCK input. With this in mind, power to the ADS8361 should be clean and well bypassed. A 0.1µF ceramic bypass capacitor should be placed as close to the device as possible. In addition, a 1µF to 10µF capacitor is recommended. If needed, an even larger capacitor and a 5Ω or 10Ω series resistor may be used to low-pass filter a noisy supply. On average, the ADS8361 draws very little current from an external reference as the reference voltage is internally buffered. However, glitches from the conversion process appear at the VREF input and the reference source must be able to handle this. Whether the reference is internal or external, the VREF pin should be bypassed with a 0.1µF capacitor. An additional larger capacitor may also be used, if desired. If the reference voltage is external and originates from an op amp, make sure that it can drive the bypass capacitor or capacitors without oscillation. No bypass capacitor is necessary when using the internal reference (tie pin 10 directly to pin 11). The GND pin should be connected to a clean ground point. In many cases, this will be the ‘analog’ ground. Avoid connections which are too near the grounding point of a microcontroller or Digital Signal Processor (DSP). If required, run a ground trace directly from the converter to the powersupply entry point. The ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry. Mode III (M0 = 1, M1 = 0) With M0 set to ‘1’, the ADS8361 will cycle through Channels 0 and 1 sequentially (the A0 pin is ignored). At the same time, setting M1 to ‘0’ places both Serial Outputs, A and B, in the active mode (See Figure 12). Mode IV (M0 = 1, M1 = 1) Similar to Mode II, Mode IV uses the Serial A output line to transmit data exclusively. Following the first conversion after M1 goes HIGH, the serial B output will go into tri-state. See Figure 13. As in Mode II, the second CONVST command is always ignored when M1 = 1. READING DATA In all four timing diagrams, the CONVST pin and the RD pins are tied together. If so desired, the two lines can be separated. Data on the Serial Output pins (A and B) will become valid following the third rising SCLK edge following RD rising edge. Refer to Table III for data output format. LAYOUT For optimum performance, care should be taken with the physical layout of the ADS8361 circuitry. This is particularly true if the CLOCK input is approaching the maximum throughput rate. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the APPLICATION INFORMATION In Figures 14 through 17, different connection diagrams to DSPs or microcontrollers are shown. tCKP 100ns CLOCK Cycle 1 Cycle 2 10ns 5ns CONVST A B 10ns 5ns C NOTE: All CONVST commands which occur more than 10ns before the falling edge before cycle ‘1’ of the external clock (Region ‘A’) will initiate a conversion on the rising edge of cycle ‘1’. All CONVST commands which occur 5ns after the falling edge before cycle ‘1’ or 10ns before the falling edge before cycle 2 (Region ‘B’) will initiate a conversion on the rising edge of cycle ‘2’. All CONVST commands which occur 5ns after the falling edge of cycle ‘2’ (Region ‘C’) will initiate a conversion on the rising edge of the next clock period. The CONVST pin should never be switched from LOW to HIGH in the region 10ns prior to the falling edge of the CLOCK and 5ns after the falling edge (gray areas). If CONVST is toggled in this gray area, the conversion could begin on either the same rising edge of the CLOCK or the following edge. FIGURE 9. Conversion Mode. 14 ADS8361 www.ti.com SBOS230C 1 20 CLOCK CONVST Conversion of Ch1 Conversion of Ch0 A0 A0 HIGH, Next Conversion: Ch1 A0 LOW, Next Conversion: Ch0 RD RD Connected to CONVST CS CS HIGH, Outputs in Tri-State Serial Data A 16-Bit Data of Chx 16-Bit Data of ChA1 Serial Data B 16-Bit Data of Chx 16-Bit Data of ChB1 BUSY Conversion of Chx Conversion of Ch1 Conversion of Ch0 TIME 0 1µ 2µ Time (seconds) 3µ 4µ 5µ 6µ FIGURE 10. Mode I, Timing Diagram for M0 = 0 and M1 = 0. 1 20 CLOCK CONVST Conversion of Chx M1 = 1 and 1st CONVST Conversion M1 = 1 and 2nd CONVST No Conversion M1 = 1 and 1st CONVST Conversion M1 = 1 and 2nd CONVST No Conversion A0 A0 HIGH Next Conversion Ch1 A0 LOW Next Conversion Ch0 A0 LOW Next Conversion Ch0 M1 M1 HIGH Only Serial Data A Used as Output Starting with 1st Conversion RD RD Connected with CONVST CS LOW Output Active CS C h A C h M1 = 1 and 2nd CONVST B Data of ChB C h M1 = 1 and 1st CONVST A Data of ChA C h M1 = 1 and 2nd CONVST B Data of ChB Serial Data A 16-Bit Data of ChAx M1 = 1 and 1st CONVST Data of ChA Serial Data B 16-Bit Data of ChBx M1 = 1 Serial Data B in Tri-state BUSY Conversion of Chx M1 = 1 and 1st CONVST Conversion M1 = 1 and 2nd CONVST No Conversion M1 = 1 and 1st CONVST Conversion M1 = 1 and 2nd CONVST No Conversion TIME 0 5µ Time (seconds) 10µ FIGURE 11. Mode II, Timing Diagram for M0 = 0 and M1 = 1. ADS8361 SBOS230C www.ti.com 15 1 CLOCK 20 CONVST 4-Ch Operation and 1st Conversion Ch0 4-Ch Operation and 2nd Conversion Ch1 A0 M0 = 1 A0 Ignored M0 M0 = 1, 4-Ch Operation Starts with Next Conversion RD RD Connected with CONVST CS CS LOW, Output is Active Serial Data A 16-Bit Data of ChAx C h 0 C h 0 16-Bit Data of ChA0 C h 1 C h 1 16-Bit Data of ChA1 Serial Data B 16-Bit Data of ChBx 16-Bit Data of ChB0 16-Bit Data of ChB1 BUSY TIME 0 1µ 2µ Time (seconds) 3µ 4µ 5µ 6µ FIGURE 12. Mode III, Timing Diagram for M0 = 1 and M1 = 0. 16 ADS8361 www.ti.com SBOS230C 1 CLOCK 20 CONVST Conversion of Chx M1 = 1 and 1st CONVST Conversion M1 = 1 and 2nd CONVST No Conversion M1 = 1 and 1st CONVST Conversion M1 = 1 and 2nd CONVST No Conversion A0 M0 HIGH 4-Ch Operation Starts, A0 Ignored M0 M0 HIGH 4-Ch Operation Starts M0 = 1 and 1st Active CONVST Ch0 M0 = 1 and 2nd Active CONVST Ch1 M1 M1 HIGH Only Serial Data A Used as Output Starting with 1st Conversion RD RD Connected with CONVST CS LOW Output Active CS CC hh 0A CC h h M1 = 1 and 2nd CONVST 0B Data of ChB0 CC h h M1 = 1 and 1st CONVST 1A Data of ChA1 CC h h M1 = 1 and 2nd CONVST 1B Data of ChB1 Serial Data A 16-Bit Data of ChAx M1 = 1 and 1st CONVST Data of ChA0 Serial Data B 16-Bit Data of ChBx M1 = 1 Serial Data B in Tri-state BUSY Conversion of Chx M1 = 1 and 1st CONVST Conversion M1 = 1 and 2nd CONVST No Conversion M1 = 1 and 1st CONVST Conversion M1 = 1 and 2nd CONVST No Conversion TIME 0 5µ Time (seconds) 10µ FIGURE 13. Mode IV, Timing Diagram for M0 = 1 and M1 = 1. ADS8361 SERIAL DATA A CLOCK CONVST BVDD M1 M0 RD BUSY A0 CS MSP430x1xx/4xx MISO SCLK P3.5 P2.1(INT) P3.6 FIGURE 14. 2x2 Channel Using A Output. ADS8361 SBOS230C www.ti.com 17 ADS8361 SERIAL DATA A CONVST RD CLOCK BVDD BUSY M1 M0 A0 CS DR FSX FSR TMS320F28xx/ C54xx/C67xx CLKX CLKR EXT_INT DX FIGURE 15. 2x2 Channel Using A Output. ADS8361 SERIAL DATA A SERIAL DATA B CONVST RD DRA DRB TMS320C54xx/ C67xx FSXA FSRA FSRB CLKXA CLKRA CLKRB CLOCK BVDD M1 M0 CS FIGURE 16. 4-Channel Sequential Mode Using A and B Outputs. ADS8361 SERIAL DATA A CONVST RD CLOCK M0 M1 CS BVDD TMS320F28xx/ C54xx/C67xx DRX FSX FSR CLKX CLKR FIGURE 17. 4-Channel Sequential Mode Using A Output. 18 ADS8361 www.ti.com SBOS230C THERMAL PAD MECHANICAL DATA www.ti.com RHB (S-PQFP-N32) THERMAL INFORMATION This package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink. The thermal pad must be soldered directly to the printed circuit board (PCB). After soldering, the PCB can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to a ground plane or special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit (IC). For additional information on the Quad Flatpack No-Lead (QFN) package and how to take advantage of its heat dissipating abilities, refer to Application Report, Quad Flatpack No-Lead Logic Packages , Texas Instruments Literature No. SCBA017 and Application Report, 56-Pin Quad Flatpack No-Lead Logic Package , Texas Instruments Literature No. SCEA032. Both documents are available at www.ti.com. The exposed thermal pad dimensions for this package are shown in the following illustration. 1 8 32 9 Exposed Thermal Pad 3,15 +0,10 0,15 25 16 24 17 3,15 +0,10 0,15 Bottom View NOTE: All linear dimensions are in millimeters QFND028 Exposed Thermal Pad Dimensions PACKAGE OPTION ADDENDUM www.ti.com 30-Sep-2004 PACKAGING INFORMATION ORDERABLE DEVICE ADS8361IDBQ ADS8361IDBQR ADS8361IRHBR ADS8361IRHBT STATUS(1) ACTIVE ACTIVE ACTIVE ACTIVE PACKAGE TYPE SSOP SSOP QFN QFN PACKAGE DRAWING DBQ DBQ RHB RHB PINS 24 24 32 32 PACKAGE QTY 56 2500 3000 250 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. MECHANICAL DATA MSOI004E JANUARY 1995 − REVISED MAY 2002 DBQ (R−PDSO−G**) PLASTIC SMALL−OUTLINE PACKAGE 0.025 (0,64) 24 0.012 (0,30) 0.008 (0,20) 13 0.005 (0,13) 0.157 (3,99) 0.150 (3,81) 0.244 (6,20) 0.228 (5,80) 0.008 (0,20) NOM Gauge Plane 1 A 0°−8° 0.069 (1,75) MAX 12 0.010 (0,25) 0.035 (0,89) 0.016 (0,40) Seating Plane 0.010 (0,25) 0.004 (0,10) 0.004 (0,10) PINS ** DIM A MAX 16 0.197 (5,00) 0.189 (4,80) 20 0.344 (8,74) 0.337 (8,56) 24 0.344 (8,74) 0.337 (8,56) 28 0.394 (10,01) 0.386 (9,80) A MIN D M0−137 VARIATION AB AD AE AF 4073301/F 02/2002 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MO−137. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright  2004, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless