ADS8410
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SLAS493A – OCTOBER 2005 – REVISED MAY 2013
16-BIT, 2-MSPS, LVDS SERIAL INTERFACE,
SAR ANALOG-TO-DIGITAL CONVERTER
Check for Samples: ADS8410
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
2-MHz Sample Rate
16-Bit Resolution
SNR 87.5 dB at 10 kHz I/P
THD –98 dB at 10 kHz I/P
±1 LSB Typ, ±2.5 LSB INL Max
+0.8/–0.5 LSB Typ, +1.5/–1 LSB DNL Max
Unipolar Differential Input Range: 0 V
to 4 V
Internal Reference
Internal Reference Buffer
200-Mbps LVDS Serial Interface
Optional 200-MHz Internal Interface Clock
16-/8-Bit Data Frame
Zero Latency at Full Speed
Power Dissipation: 290 mW at 2 MSPS
Nap Mode (125 mW Power Dissipation)
Power Down (5 μW)
48-Pin QFN Package
Medical Instrumentation
HIgh-Speed Data Acquisiton Systems
High-Speed Close-Loop Systems
Communication
DESCRIPTION
The ADS8410 is a 16-bit, 2-MSPS, analog-to-digital
(A/D) converter with 4-V internal reference. The
device includes a capacitor based SAR A/D converter
with inherent sample and hold.
The ADS8410 also includes a 200-Mbps, LVDS,
serial interface. This interface is designed to support
daisy chaining or cascading of multiple devices. A
selectable 16-/8-bit data frame mode enables the use
of a single shift register chip (SN65LVDS152) for
converting the data to parallel format.
The ADS8410 unipolar single-ended input range
supports a differential input swing of 0 V to +Vref.
The nap feature provides substantial power saving
when used at lower conversion rates.
The ADS8410 is available in a 48-pin QFN package.
Table 1. High-Speed SAR Converter Family
Type/Speed
18-Bit Pseudo-Diff
500 kHz
ADS8383
~ 600 kHz
750 kHZ
1 MHz
1.25 MHz
2 MHz
3 MHz
4 MHz
ADS8381
ADS8380 (S)
18-Bit Pseudo-Bipolar, Fully Diff
ADS8382 (S)
16-Bit Pseudo-Diff
ADS8370 (S)
16-Bit Pseudo-Bipolar, Fully Diff
ADS8372 (S)
ADS8411
ADS8371
ADS8401/05
ADS8410
(S-LVDS)
ADS8412
14-Bit Pseudo-Diff
ADS8402/06
ADS7890 (S)
ADS8413
(S-LVDS)
ADS7891
12-Bit Pseudo-Diff
ADS7881
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
ADS8410
SLAS493A – OCTOBER 2005 – REVISED MAY 2013
www.ti.com
+ VA
+ VBD
AGND
Core Supply
BDGND
I/O Supply
SAR
CSTART
LVDS I/O
SYNC_I, CLK_I, SDI
+
+ IN
SYNC_O, CLK_O, SDO
CDAC
−
− IN
CONVST
Comparator
BUS BUSY
CMOS I/O
REFIN
Clock
CS
Mode
Selection
4 V Internal
Reference
REFOUT
RD
BUSY
Conversion
and
Control Logic
LAT_Y/N
BYTE,
MODE_C/D,
CLK_I/E, PD, NAP
ORDERING INFORMATION (1)
MODEL
MAXIMUM
INTEGRAL
LINEARITY
(LSB)
MAXIMUM
DIFFERENTIAL
LINEARITY
(LSB)
NO MISSING
CODES AT
RESOLUTION
(BIT)
PACKAGE
TYPE
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
ORDERING
INFORMATION
1.5/–1
16
RGZ
–40°C
to 85°C
250
±2.5
48 pin
QFN
ADS8410IBRGZT
ADS8410lB
ADS8410IBRGZR
2000
48 pin
QFN
–40°C
to 85°C
ADS8410IRGZT
250
RGZ
ADS8410IRGZR
2000
ADS8410l
(1)
±4
3/–1
16
TRANSPORT
MEDIA
QUANTITY
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
+IN to AGND
–0.3 V to +VA + 0.3 V
-IN to AGND
–0.3 V to +0.3 V
+VA to AGND
–0.3 to 7 V
+VBD to BDGND
–0.3 to 7 V
Digital input voltage to GND
–0.3 V to (+VBD + 0.3 V)
Digital output to GND
–0.3 V to (+VBD + 0.3 V)
Operating temperature range
–40°C to 85°C
Storage temperature range
–65°C to 150°C
Junction temperature (TJmax)
QFN package
Lead temperature, soldering
(1)
2
150°C
Power dissipation
θJA Thermal impedance
(TJ Max – TA)/ θJA
86°C/W
Vapor phase (60 sec)
215°C
Infrared (15 sec)
220°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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SPECIFICATIONS
TA = –40°C to 85°C, +VA = 5 V,+VBD = 5 V or 3.3 V, Vref = 4.096 V, f sample = 2 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Full-scale input voltage span
(1)
+IN – (–IN)
Absolute input voltage range
Ci
0
Vref
+IN
–0.2
Vref + 0.2
–IN
–0.2
+0.2
Input capacitance
Input leakage current
V
V
25
pF
500
pA
16
Bits
SYSTEM PERFORMANCE
Resolution
No missing codes
ADS8410IB
16
ADS8410I
16
Bits
ADS8410IB
–2.5
±1
2.5
ADS8410I
–4.0
±2.5
4.0
–1
0.8/–0.5
1.5
–1.0
1.5/–0.8
3
–0.75
±0.1
0.75
–1.5
±0.75
1.5
–0.05
±0.01
0.05
–0.15
±0.05
0.15
INL
Integral linearity (2)
DNL
Differential linearity
EO
Offset error
EG
Gain error (4)
CMMR
Common-mode rejection ratio
With common mode input signal = 200
mVp-p at 1 MHz
60
dB
PSRR
Power supply rejection ratio
At FFF0H output code
80
dB
ADS8410IB
ADS8410I
ADS8410IB
ADS8410I
ADS8410IB
ADS8410I
External reference
External reference
LSB (3)
LSB (3)
mV
% of FS
SAMPLING DYNAMICS
+VBD = 5 V
Conversion time
360
+VBD = 3 V
Acquisition time
391
391
+VBD = 5 V
100
+VBD = 3 V
100
ns
ns
Maximum throughput rate with or without latency
2.0
MHz
Aperture delay
20
ns
Aperture jitter
10
psec
Step response
50
ns
Overvoltage recovery
50
ns
DYNAMIC CHARACTERISTICS
THD
Total harmonic distortion (5)
SNR
Signal-to-noise ratio
SINAD
Signal-to-noise and distortion
SFDR
Spurious free dynamic range
VIN 0.5 dB below FS at 10 kHz
–98
VIN 0.5 dB below FS at 100 kHz
–92.5
VIN 0.5 dB below FS at 10 kHz
87.5
VIN 0.5 dB below FS at 100 kHz
86
VIN 0.5 dB below FS at 10 kHz
87
VIN 0.5 dB below FS at 100 kHz
85
VIN 0.5 dB below FS at 10 kHz
–101
VIN 0.5 dB below FS at 100 kHz
–93
–3 dB Small signal bandwidth
dB
dB
dB
dB
37.5
MHz
EXTERNAL REFERENCE INPUT
Input voltage range, VREF
Resistance (6)
3.9
To internal reference voltage
4.096
4.2
500
V
kΩ
INTERNAL REFERENCE OUTPUT
(1)
(2)
(3)
(4)
(5)
(6)
Ideal input span; does not include gain or offset error.
This is endpoint INL, not best fit.
Least significant bit
Measured relative to actual measured reference.
Calculated on the first nine harmonics of the input frequency.
Can vary ±20%
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SPECIFICATIONS (continued)
TA = –40°C to 85°C, +VA = 5 V,+VBD = 5 V or 3.3 V, Vref = 4.096 V, f sample = 2 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
25
UNIT
Start-up time
From 95% (+VA), with 1-μF storage
capacitor on REFOUT to AGND
Reference voltage range, Vref
At room temperature
Source current
Static load
Line regulation
+VA = 4.75 V to 5.25 V
0.6
mV
Drift
IOUT = 0 V
36
PPM/°C
4.080
4.096
ms
4.112
V
10
μA
POWER SUPPLY REQUIREMENTS
Power supply voltage
+VBD
+VA
2.7
3.3
5.25
4.75
5
5.25
Supply current, 2-MHz sample rate +VA
Power dissipation, 2-MHz sample rate
+VA = 5 V
V
58
64
mA
290
320
mW
NAP MODE
Supply current
+VA
25
mA
POWER DOWN
Supply current
+VA
1
Powerdown time
With 1-μF storage capacitor on
REFOUT to AGND
Powerup time
Invalid conversions after power up or reset
2.5
μA
10
μs
25
ms
3
Numbers
TEMPERATURE RANGE
Operating free air
–40
85
°C
LOGIC FAMILY CMOS
VIH
High-level input voltage
IIH = 5 μA
+VBD –1
+VBD +0.3
V
VIL
Low-level input voltage
IIL = 5 μA
–0.3
0.8
V
VOH
High-level output voltage
IOH = 2 TTL loads
+VBD – 0.6
+VBD
V
VOL
Low-level output voltage
IOL = 2 TTL loads
0
0.4
V
LOGIC FAMILY LVDS (7)
DRIVER
Steady-state differential output voltage
magnitude
|VOD(SS)|
247
∆|VOD(SS)|
Change in steady-state differential output voltage
magnitude between logic states
VOC(SS)
Steady-state common-mode output voltage
∆|VOC(SS)|
Change in steady-state common-mode output
voltage between logic states
VOC(pp)
Peak to peak change in common-mode output
voltage
IOS
Short circuit output current
IOZ
High impedance output current
(7)
4
340
454
RL = 100 Ω, See Figure 52, Figure 53
mV
-50
1.125
See Figure 54
50
1.2
–50
1.375
50
mV
50
150
VOY or VOZ = 0 V
3
10
VOD = 0 V
3
10
VO = 0 V or +VBD
V
–5
5
mA
μA
All min max values ensured by design.
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SPECIFICATIONS (continued)
TA = –40°C to 85°C, +VA = 5 V,+VBD = 5 V or 3.3 V, Vref = 4.096 V, f sample = 2 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RECEIVER
VITH+
Positive going differential voltage threshold
VITH-
Negative going differential voltage threshold
–50
50
VIC
Common mode input voltage
0.2
CI
Input capacitance
1.2
mV
2.2
V
5
pF
TIMING REQUIREMENTS
TA = –40°C to 85°C, +VA = 5 V, +VBD = 5 V or 3.3 V (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
REF
ns
Figure 1,
Figure 2
ns
Figure 1,
Figure 2
SAMPLING AND CONVERSION RELATED
tacq
Acquisition time
tcnv
Conversion time
tw1
Pulse duration, CONVST high
tw2
Pulse duration, CONVST low
td1
Delay time, CONVST rising edge to sample start
100
391
100
40
5
5
ns
Figure 1
ns
Figure 1,
Figure 2
ns
Figure 1
ns
Figure 1,
Figure 2
ns
Figure 1,
Figure 2
ns
Figure 1,
Figure 2
td2
Delay time, CONVST falling edge to conversion start
td3
Delay time, CONVST falling edge to busy high
td4
Delay time, conversion end to busy low
tw3
Pulse duration, CSTART high
100
ns
Figure 1,
Table 3
tw4
Pulse duration, CSTART low
45
ns
Figure 1,
Figure 2,
Table 3
td5
Delay time, CSTART rising edge to sample start
7.5
ns
Figure 1,
Table 3
td6
Delay time, CSTART falling edge to conversion start
7.5
ns
Figure 1,
Figure 2,
Table 3
td7
Delay time, CSTART falling edge to busy high
ns
Figure 1,
Figure 2,
Table 3
ns
Figure 5
ns
Figure 5
ns
Figure 6
ns
Figure 6
ns
Figure 6
ns
Figure 5
ns
Figure 11
ns
Figure 5,
Figure 6
ns
Figure 7,
Figure 12
+VBD = 3.3 V
14
+VBD = 5 V
13
+VBD = 3.3 V
8
+VBD = 5 V
7
+VBD = 3.3 V
16.5
+VBD = 5 V
15.5
I/O RELATED
td8
Delay time, RD falling edge while CS low to BUS_BUSY high
td9
Delay time, RD falling edge while CS low to SYNC_O and SDO out of
3-state condition (for device with LAT_Y/N pulled low)
td10
Delay time, pre_conversion end (point A) to SYNC_O and SDO out of 3-state condition
22
+VBD = 3.3 V
8
+VBD = 5 V
7
td11
Delay time, pre_conversion end (point A) to BUS_BUSY high
td12
Delay time, conversion phase end to SYNC_O high
td13
Delay time, RD falling edge while CS low to SYNC_O high
tw5
Pulse duration, RD low for device in no latency mode
16
+VBD = 3.3 V
29
+VBD = 5 V
28
+VBD = 3.3 V
6
9 + tCLK
5.5 + 4*tCLK
8.5 + 5*tCLK
5 + 4*tCLK
8 + 5*tCLK
+VBD = 5 V
5
td14
Delay time, CLK_O rising edge to data valid
td15
Delay time, BUS_BUSY low to SYNC_O high in daisy chain mode
indicating receiving device to output data
+VBD = 3.3 V
1.4
+VBD = 5 V
1.3
+VBD = 3.3 V
4*tCLK – 6.5
4*tCLK – 3
4*tCLK – 6
4*tCLK – 2.5
+VBD = 5 V
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TIMING REQUIREMENTS (continued)
TA = –40°C to 85°C, +VA = 5 V, +VBD = 5 V or 3.3 V (unless otherwise noted)
PARAMETER
MIN
td16
Delay time, CLK_O to SDO and SYNC_O 3-state
tpd1
Propagation delay time, SYNC_I to SYNC_O in daisy chain mode
td17
Delay time, SYNC_O and SDO 3-state to BUS_BUSY low in cascade mode
0
TYP
MAX
UNIT
REF
4
ns
Figure 7,
Figure 8,
Figure 12,
Figure 15
11 + 0.5*tCLK
ns
Figure 12
2
ns
Figure 8
ns
Figure 11,
Figure 14
ns
Figure 6
td18
Delay time, RD rising edge to BUS_BUSY high for device with
LAT_Y/N = 1
+VBD = 3.3 V
8
+VBD = 5 V
7
td19
Delay time, point A indicating clear for bus 3-state release to BUSY
falling edge
+VBD = 3.3 V
tr
Rise time, differential LVDS output signal
950
ps
Figure 53
tf
Fall time, differential LVDS output signal
950
ps
Figure 53
210
MHz
40.5
+VBD = 5 V
CLK frequency (serial data rate)
40
190
td20
Delay time, from PD falling edge to SDO 3-state
10
ns
Figure 22,
Figure 23
td21
Delay time, from PD falling edge to device powerdown
10
μs
Figure 22,
Figure 23
td22
Delay time, from PD rising edge to device powerup
25
ms
Figure 22,
Figure 23
ts1
Settling time, internal reference after first three conversions
4
ms
Figure 22
td23
Delay time, CONVST falling edge to start of restricted zone for start of data read cycle
ns
Figure 9
td24
Delay time, CONVST falling edge to end of restricted zone for start of data read cycle
ns
Figure 9
6
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406
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DEVICE INFORMATION
NAP
7
6
5
CS
MODE_C/D
8
CONVST
CLK_I/E
9
PD
LAT_Y/N
11 10
BYTE
+VA
AGND
12
REFM
REFM
RGZ PACKAGE
(TOPVIEW)
4
3
2
1
REFIN
13
48
BUS_BUSY
REFOUT
NC
+VA
14
47
RD
15
46
BUSY
16
45
BDGND
AGND
17
44
+VBD
+IN
18
43
SYNC_O +
+VA
+VA
21
40
SDO −
22
39
CLK_O +
AGND
23
38
AGND
24
37
CLK_O −
+VA
35 36
AGND
32 33 34
(M1 −) SYNC_I −
30 31
CSTART+
26 27 28 29
CSTART−
25
CLK_I −
SDO +
(M2+) SDI +
(M2−) SDI −
CLK_I +
SYNC_O −
41
(M1 +) SYNC_I +
42
20
+VA
AGND
19
AGND
−IN
AGND
NC − No internal connection
TERMINAL FUNCTIONS
TERMINAL
NO.
NAME
I/O
DESCRIPTION
ANALOG PINS
11, 12
REFM
I
Reference ground. Connect to analog ground plane.
13
REFIN
I
Reference (positive) input. Decouple with REFM pin using 0.1-μF bypass capacitor and 1-μF storage
capacitor.
14
REFOUT
O
Internal reference output. Short to REFIN pin when the internal reference is used. Do not connect to
the REFIN pin when an external reference is used. Always decouple with AGND using a 0.1-μF
bypass capacitor.
18
+IN
I
Noninverting analog input channel
19
–IN
I
Inverting analog input channel (supports ±0.2 V i/p range)
LVDS I/O PINS (1)
28,
29
(1)
CSTART+
CSTART–
I
Device sample and convert control input. Device enters sample phase with the rising edge of
CSTART and the conversion phase starts with the falling edge of CSTART (provided other conditions
are satisfied). Set CSTART = 0 when the CONVST input is used.
All LVDS inputs and outputs are differential with signal+ and signal– lines. Whenever only the 'signal' is mentioned it refers to the
signal+ line and the signal– line is the compliment. For example CLK_O refers to CLK_O+ and CLK_O is the compliment.
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TERMINAL FUNCTIONS (continued)
TERMINAL
NO.
NAME
SYNC_I +
SYNC_I–
30,
31
M1+
M1–
SDI+
SDI–
32,
33
M2+
M2–
I/O
I
Dasiy
Chain
DESCRIPTION
Connect to previous device SYNC_O with same polarity, while the device is selected to operate in
daisy chain mode.
Mode 1 (valid in cascade mode only). CLK_O is available while M1=1 (LVDS) or M1+ is pulled up to
I
+VBD and M1– is grounded (AGND). CLK_O o/p goes to 3-state when M1 = 0 (LVDS) or M1+ is
Cascade
grounded (AGND) and M1– is pulled up to +VBD. Do not allow these pins to float.
I
Daisy
Chain
Serial data input. Connect to previous device SDO with same polarity, while the device is selected to
operate in daisy chain mode.
Mode 2 (valid in cascade mode only). Doubles LVDS o/p current while M2 = 1 (LVDS) or M2+ is
I
pulled up to +VBD and M2– is grounded (AGND). LVDS o/p current is normal (3.4 mA typ) when M2
Cascade = 0 (LVDS) or M2+ is grounded (AGND) and M2 – is pulled up to +VBD. Do not allow these pins to
float.
34,
35
CLK_I+
CLK_I–
I
Serial external clock input. Set CLK_I/E (pin 7) = 0 to select an external clock source.
38,
39
CLK_O–
CLK_O+
O
Serial clock out. Data is latched out on the rising edge of CLK_O and can be captured on the next
falling edge.
40,
41
SDO–
SDO+
O
Serial data out. Data is latched out on the rising edge of CLK_O with MSB first format.
42,
43
SYNC_O –
SYNC_O +
O
Synchronizes the data frame.
(2)
CMOS I/O PINS
1
CS
I
Chip select, active low signal. All of the LVDS o/p except CLK_O are 3-state if this pin is high.
2
CONVST
I
CMOS equivalent of CSTART input. So functionality is the same as the CSTART input. Set CONVST
= 0 when the CSTART input is used.
3
BYTE
I
Controls the data frame (3) duration. The frame duration is 16 CLKs if BYTE = 0 or 8 CLKs if BYTE =
1.
4
PD
I
Active low input, acts as device power down.
5
NAP
I
Selects nap mode while high. Device enters the nap state at conversion end and remains so until the
next acquisition phase begins.
6
MODE_C/D
I
Selects cascade (MODE_C/D = 1) or daisy chain mode (MODE_C/D = 0).
7
CLK_I/E
I
Selects the source of the I/O clock.
CLK_I/E = 1 selects internally generated clock with 200-MHz typ frequency.
CLK_I/E = 0 selects CLK_I as the I/O clock.
8
LAT_Y/N
I
Controls the data read with latency (LAT_Y/N = 1) or without latency ((LAT_Y/N = 0). It is essential to
set LAT_Y/N = 0 for the first device in daisy chain or cascade.
46
BUSY
O
Active high signal, indicates a conversion is in progress.
47
RD
I
Data read request to the device, also acts as a handshake signal for daisy chain and cascade
operation.
48
BUS_BUSY
O
Status output. Indicates that the bus is being used by the device. Connect to RD of the next device
for daisy chain or cascade operation.
POWER SUPPLY PINS
10, 16,
21, 22,
26, 37
+VA
9, 17, 20,
23, 24,
AGND
25, 27,
36
(2)
(3)
8
–
Analog power supply and LVDS input buffer power supply.
–
Analog ground pins. Short to the analog ground plane below the device.
44
+VBD
–
Digital power supply for all CMOS digital inputs and CMOS LVDS outputs.
45
BDGND
–
Digital ground for all digital inputs and outputs. Short to the analog ground plane below the device.
The duration from the first rising edge of SYNC_O to the second rising edge of SYNC_O is one data frame. The data frame duration is
16 CLKs if BYTE = 0 or 8 CLKs if BYTE = 1.
The duration from the first rising edge of SYNC_O to the second rising edge of SYNC_O is one data frame. The data frame duration is
16 CLKs if BYTE = 0 or 8 CLKs if BYTE = 1.
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TERMINAL FUNCTIONS (continued)
TERMINAL
NO.
I/O
NAME
DESCRIPTION
NOT CONNECTED PINS
15
NC
–
No connection pins
Table 2. Device Configuration for Various Modes of Operation
DEVICE PINS AND RECOMMENDED LOGIC LEVELS
COMMENTS
FOR
SAMPLING
AND
CONVERSION
OPERATION MODE
MODE_C/D
CLK_I/E
LAT_Y/N
M1+
+VBD
1
1 or 0
M1–
M2+
M2–
AGND
AGND
+VBD
0
or M1 = 1 LVDS
or M2 = 0 LVDS
REFERENCE FIGURES
FOR DATA
READ
Recommended configuration
1 or 2
See Figures 3,4
and 5,6,8 for
more details
See Figures 3,4
and 5,6,7 for
more details
Single device
Multiple
devices
in daisy
chain
Multiple
devices
in
cascade
(1)
0
1 or 0
0
See comments
See comments
Set SYNC_I and SDI to logic 0
or + terminal to AGND and –ve
terminal to +VBD
1 or 2
1st Device
0
1 or 0
0
See comments
See comments
Set SYNC_I and SDI to logic 0
or + terminal to AGND and –ve
terminal to +VBD
1 or 2
2nd To last
device
0
0
1
See comments
See comments
Maximum 4 devices supported
at 2 MSPS with 200-MHz CLK
1 or 2
+VBD
AGND
Maximum 3 devices supported
at 2 MSPS
1 or 2
1st Device
2nd To last
device
1
0
1
0
AGND
0
+VBD
or M1 = 1 LVDS
or M2 = 0 LVDS (1)
+VBD
AGND
AGND
1
or M1 = 0 LVDS
See Figures
3,4,11 and 6,12
for more details
+VBD
See Figures
3,4,14 and 6,15
for more details
or M2 = 0 LVDS (1)
Specified polarity is suitable for a 100-Ω differential load across the LVDS outputs. However, polarity can be reversed to double the
output current in order to support two 100-Ω loads on both ends of the transmission lines, resulting in 50-Ω net load.
DETAILED DESCRIPTION
SAMPLE AND CONVERT
The sampling and conversion process is controlled by the CSTART (LVDS) or CONVST (CMOS) signal. Both
signals are functionally identical. The following diagrams show control with CONVST. The rising edge of
CONVST (or CSTART) starts the sample phase, if the conversion has completed and the device is in the wait
state. Figure 2 shows the case when the device is in the conversion phase at the rising edge of CONVST. In this
case, the sample phase starts immediately at the end of the conversion phase and there is no wait state.
CONVST
tw1
tw2
td2
td1
td4
BUSY
td3
Wait
Sample Phase
Conversion Phase
tacq
Wait
tcnv
Figure 1. Sample and Convert With Wait (Less Than 2 MSPS Throughput)
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tw2
Not less than td1 to
avoid device entering
wait state
CONVST
td4
td2
BUSY
td3
Sample Phase
Conversion Phase
tacq
Sample Phase
tcnv
Figure 2. Sample and Convert With No Wait or Back to Back (2 MSPS Throughput)
The device ends the sample phase and enters the conversion phase on the falling edge of CONVST (CSTART).
A high level on the BUSY output indicates an ongoing conversion. The device conversion time is fixed. The
falling edge of CONVST (CSTART) during the conversion phase aborts the ongoing conversion. A data read
after a conversion abort fetches invalid data. Valid data is only available after a sample phase and a conversion
phase has completed. The timing diagram for control with CSTART is similar to Figure 1 and Figure 2. Table 3
shows the equivalent timing for control with CONVST and CSTART.
Table 3. CONVST and CSTART Timing Control
TIMING CONTROL WITH CONVST
TIMING CONTROL WITH CSTART
tw1
tw3
tw2
tw4
td1
td5
td2
td6
td3
td7
DATA READ OPERATION
The ADS8410 supports a 200-MHz serial LVDS interface for data read operation. The three signal LVDS
interface (SDO, CLK_O, and SYNC_O) is well suited for high-speed data transfers. An application with a single
device or multiple devices can be implemented with a daisy chain or cascade configuration. The following
sections discuss data read timing when a single device is used.
DATA READ FOR A SINGLE DEVICE (See Table 1 for Device Configuration)
For a single device, there are two possible read cycle starts: a data read cycle start during a wait or sample
phase or a data read cycle start at the end of a conversion phase. Read cycle end conditions can change
depending on MODE C/D selection. Figure 3 explains the data read cycle. The details of a read frame start with
the two previous listed conditions and a read cycle end with MODE C/D selection are explained in Figure 5 and
Figure 6 and Figure 7 and Figure 8, respectively.
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See Figures 5 and 6
See Figures 7 and 8
RD
SYNC_O
CLK_O
1F
1R
18F 18R
2R
SDO
D15
D0
D14
BUS BUSY
Figure 3. Data Read With CS Low and BYTE = 0
As shown in Figure 3, a new data read cycle is initiated with the falling edge of RD, if CS is low and the device is
in a wait or sample phase. The device releases the LVDS o/p (SYNC_O, SDO) from 3-state and sets
BUS_BUSY high at the start of the read cycle. The SYNC_O cycle is 16 clocks wide (rising edge to rising edge)
if BYTE i/p is held low and can be used to synchronize a data frame. The clock count begins with the first CLK_O
falling edge after a SYNC_O rising edge. The MSB is latched out on the second rising edge (2R) and each
subsequent data bit is latched out on the rising edge of the clock. The receiver can shift data bits on the falling
edges of the clock. The next rising edge of SYNC_O coincides with the 16th rising edge of the clock. D0 is
latched out on the 17th rising edge of the clock. The receiver can latch the de-serialized 16-bit word on the 18th
rising edge (18R, or the second rising edge after a SYNC_O rising edge).
CS high during a data read 3-states SYNC_O and SDO. These signals remain in 3-state until the start of the
next data read cycle.
DATA READ IN BYTE MODE
Byte mode is selected by setting BYTE = 1; this mode is allowed for any condition listed in Table 2. Figure 4
shows a data read operation in byte mode.
RD
SYNC_O
CLK_O
1F
1R
9F
2R
9R
10R
18F 18R
SDO
D15
D14
D8
D7
D0
BUS BUSY
Figure 4. Data Read Timing Diagram with CS Low and BYTE = 1
Similar to Figure 3, a new data read cycle is initiated with the falling edge of RD, if CS is low and the device is in
a wait or sample phase. The device releases the LVDS o/p (SYNC_O, SDO) from 3-state and sets BUS_BUSY
high at the start of the read cycle. The SYNC_O cycle is 8 clocks wide (rising edge to rising edge) if BYTE i/p is
held high and can be used to synchronize a data frame. The clock count begins with the first falling edge of
CLK_O after the rising edge of SYNC_O. The MSB is latched out on the second rising edge (2R) and each
subsequent data bit is latched out on the rising edge of the clock. The receiver can shift data bits on the falling
edges of clock. The next rising edge of SYNC_O coincides with the 8th rising edge of the clock. D8 is latched out
on the 9th rising edge of the clock. The receiver can latch the de-serialized higher byte on the 10th rising edge
(10R, or second rising edge after a SYNC_O rising edge). The de-serialized lower byte can be latched on the
18th rising edge (18R).
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CS high during a data read 3-states SYNC_O and SDO. These signals remain in 3-state until the start of the
next data read cycle.
DATA READ CYCLE START DURING WAIT OR SAMPLE PHASE
As shown in Figure 5, the falling edge of RD, with CS low and the device is in a wait or sample phase, triggers
the start of a read cycle. The cycle starts when BUS_BUSY goes high and SYNC_O and SDO are released from
3-state. SYNC_O is low at the start and rises to a high level td13 ns after the falling edge of RD . As shown in
Figure 5, the MSB is shifted on the 2nd rising edge of the clock (2R). Other details about the data read cycle are
discussed in the previous section (see Figure 3).
td9
RD
td13
td8
BUSY
BUS_BUSY
0R
1F
1R
2R
3R
CLK_O
SYNC_O
td14
SDO_O
MSB
MSB − 1
Figure 5. Start of Data Read Cycle with RD with CS Low and Device in Wait or Sample Phase
DATA READ CYCLE START AT END OF CONVERSION PHASE (Read Without Latency, Back-to-Back)
This mode is optimized for a data read immediately after the end of a conversion phase and ensures the data
read is complete before the sample end while running at 2 MSPS. Point A in Figure 6 indicates a
'pre_conversion_end'; it occurs td19 ns before the falling edge of BUSY or [(td2 + tcnv + td4) – td19] ns after the
falling edge of CONVST. A read cycle is initiated at point A if RD is issued before point A while CS is low.
Alternately, RD and CS can be held low. At the start of the read cycle, BUS_BUSY rises to a high level and the
LVDS outputs are released from 3-state. The rising edge of SYNC_O occurs td12 ns after the conversion end. As
shown in Figure 6, the MSB is shifted on the 2nd rising edge of the clock (2R). Other details about the data read
cycle are discussed in the previous section (see Figure 3).
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Conversion Phase
Conversion End
A
td19
RD_REQ (Int)
td11
td4
BUSY
td10
BUS_BUSY O/P
0R
1F
1R
2R
3R
CLK_O
td12
SYNC_O
td14
SDO_O
MSB
MSB − 1
Figure 6. Start of Data Read Cycle with End of Conversion
DATA READ CYCLE END (With MODE C/D = 0)
A data read cycle ends after all 16 bits have been serially latched out. Figure 7 shows the timing of the falling
edge of BUS_BUSY and the rising edge of SYNC_O with respect to SDO. SYNC_O rises on the 16th rising edge
of CLK_O. As shown in Figure 5 and Figure 6, the MSB is shifted out on the 2nd rising edge of CLK_O.
Therefore, the LSB-1 is shifted out on the 16th rising edge of CLK_O.
CONVST
CS = 0
BUS_BUSY
td15
SYNC_O
15R
16R
17R
18R
CLK_O
td16
SDO
LSB − 1
LSB
Figure 7. Data Read Cycle End with MODE C/D = 0
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The next two rising edges of CLK_O are shown as 17R and 18R in Figure 7. On 17R the LSB is latched out, and
on 18R SDO and SYNC_O go to 3-state. Note that BUS_BUSY falls td15 ns before the rising edge of SYNC_O
when MODE C/D = 0. Care must be taken not to allow LVDS bus usage by any other device until the end of the
read cycle or (td15 + 2/fclk + td16) ns after the falling edge of BUS_BUSY.
DATA READ CYCLE END (With MODE C/D = 1)
A data read cycle ends after all 16 bits have been serially latched out. Figure 8 shows the timing of the falling
edge of BUS_BUSY and the rising edge of SYNCO with respect to SDO. SYNC_O rises on the 16th rising edge
of CLK_O. As shown in Figure 5 and Figure 6, the MSB is shifted out on the 2nd rising edge of CLK_O.
Therefore, the LSB-1 is shifted out on the 16th rising edge of CLK_O.
CONVST
CS = 0
BUS_BUSY
td17
SYNC_O
16R
15R
17R
18R
CLK_O
td16
LSB − 1
SDO
LSB
Figure 8. Data Read Cycle End with MODE C/D = 1
The next two rising edges of CLK_O are shown as 17R and 18R in Figure 8. On 17R the LSB is latched out and
on 18R SDO and SYNC_O go to 3-state. In cascade mode (with MODE C/D = 1), unlike daisy chain mode, the
falling edge of BUS_BUSY occurs after the LVDS outputs are 3-stated. One can use the falling edge of
BUS_BUSY to allow LVDS bus usage by any other device.
RESTRICTIONS ON READ CYCLE START
CONVST
td23
td24
BUSY
Read cycle not allowed
to start in this region
Figure 9. Read Cycle Restriction Region
The start of a data read cycle is not allowed in the region bound by td23 and td24. Previous conversion results are
available for a data read cycle start before this region, and current conversion results are available for a read
cycle start after this region.
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MULTIPLE DEVICES IN DAISY CHAIN OR CASCADE
Multiple devices can be connected in either a daisy chain or cascade configuration. The following sections
describe detailed timing diagrams and electrical connections. The ADS8410 provides all of the handshake
signals required for both of these modes. CONVST or CSTART is the only external signal needed for operation.
DAISY CHAIN
Figure 10 shows the first two devices in daisy chain. The signals shown by double lines are LVDS and the others
are CMOS. Daisy chain mode is selected by setting MODE_C/D = 0. The first device in the chain is identified by
selecting LAT_Y/N = 0.
Device 1
See Table 1
External Clock
(Optional)
See Table 1
Last_Device
BUS_BUSY
Device 2
SD0
SDI
CLK_0
CLK_I
BUS_BUSY
RD
+V
MODE_C/D
CLK_I/E
LAT_Y/N
+V
CLK_I/E
MODE_C/D
CS
To Next Device
or Receiver
SYNC_0
SYNC_I
BUS_BUSY
RD
CLK_0
CLK_I
SYNC_0
SYNC_I
SD0
SDI
LAT_Y/N
CS
From Controller
Figure 10. Connecting Multiple Devices in Daisy Chain
For all other devices in the chain LAT_Y/N = 1. See Table 2 for more details on device configurations. SDO,
CLK_O, and SYNC_O of device n are connected to SDI, CLK_I, and SYNC_I of device n+1. SDO, CLK_O, and
SYNC_O of the last device in the chain go to the receiver. BUS_BUSY of device n is connected to RD of device
n+1 and so on. Finally, BUS_BUSY of the last device in the chain is connected to RD of device 1. This ensures
the necessary handshake to seamlessly propagate the data of all devices through the chain (it is also allowed to
tie RD = 0 for device 1).
TIMING DIAGRAMS FOR DAISY CHAIN OPERATION
The conversion speed for n devices in the chain must be selected such that:
1/conversion speed > read startup delay + n*(data frame duration) + td16
Read startup delay = 10 ns + (td19 - td4) + td12 + 2/fCLK
Data frame duration = 16/fCLK Note that it is not necessary for all devices in the chain to sample the data
simultaneously. But all of the devices must operate with the same exact conversion speed.
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n + 1 Tracking
n + 1 Conversion
CONVST #1
See Figure 6 for details
CS
tw5
RD #1
BUS_BUSY #n
(Last device)
BUS_BUSY #1
RD #2
SDO #1
SDI #2
16−Bit Data
nth conversion
See Figure 12 for details
SYNC_O #1
SYNC_I #2
td18
BUS_BUSY #2
RD #3
#1 16−Bits
nth conversion
SDO #2
SDI #3
#2 16−Bits
nth conversion
SYNC_O #2
SYNC_I #3
Figure 11. Data Read Operation for Devices in Daisy Chain
DATA READ OPERATION
On power up, BUS_BUSY of all of the devices is low. The devices receive CONVST or CSTART to sample and
start the conversion. The first device in the chain starts the data read cycle at the end of its conversion.
BUS_BUSY of device 1 (connected to RD of device 2) goes high on the read cycle start. Device 2 BUS_BUSY
goes high on the rising edge of RD. This propagates until the last device in the chain. Device 2 receives CLK_I,
SDI, and SYNC_I from device 1 and it passes all of these signals to the next device. Device 2 (and every
subsequent device in the chain) passes the received signals to its output until it sees the falling edge of RD
(same as BUS_BUSY of the previous device). In daisy chain mode, BUS_BUSY for any device falls when it has
passed all of the previous device data followed by its own data. The falling edge of BUS_BUSY occurs before
the rising edge of SYNC_O. This indicates to the receiving device that the previous data chain is over and it is its
own turn to output the data. The device outputs the data from the last completed conversion. BUS_BUSY of the
last device in the chain is fed back to RD of the first device as shown in Figure 10 (or device 1 RD tied to 0). This
makes sure that RD of device 1 is low before its conversion is over. The chain continues with only one external
signal (CONVST or CSTART) when CS is held low. Every device LVDS output goes to 3-state once all data
transfer through the device has been completed.
CS going high during the data read cycle of any device 3-states its SYNC_O and SDO. This halts the
propagation of data through the chain. To reset this condition it is necessary to assert CS high for all devices.
The new read sequence starts only after CS for all devices is low before point A shown in Figure 6. The high
pulse on CS must be at least 20 ns wide. It is better to connect CS of all of the devices together to avoid
undesired halting of the daisy chain.
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CS = 0
BUS_BUSY #1
RD #2
td15
SYNC_O #1
SYNC_I #2
td16
15R
16R
17R
18R
CLK_O #1
CLK_I #2
SDO #1
SDO #2
LSB − 1
#1
LSB #1
BUSY_BUS #2 = 1
18R
17F 17R
CLK_O #2
tpd1
SYNC_O #2
#1 DATA
LSB − 1
#1
LSB #1
MSB
MSB − 1
#2 DATA
Figure 12. Data Propagation from Device n to Device n+1 in Daisy Chain Mode
As shown in Figure 12 there is a propagation delay of tpd1 from SYNC_I to SYNC_O or SDI to SDO. Note that
the data frames of all devices in the chain appear seamless at the last device output. The rising edge of SYNC
occurs at an interval of 16 clocks (or 8 clocks in BYTE mode); this can be used as a data frame sync. The
deserializer at the output of the last device can shift the data on every falling edge of the clock and it can latch
the parallel 16-bit word on the second rising edge of CLK_O (shown as 18R) after every rising edge of SYNC_O.
CASCADE
Figure 13 shows the cascade connection. The signals shown by double lines are LVDS and the others are
CMOS. Cascade mode is selected by setting MODE_C/D = 1. Similar to daisy chain, the first device in the chain
is identified by selecting LAT_Y/N = 0. For all other devices in the chain LAT_Y/N = 1. See Table 2 for more
details on device configuration. SDO, CLK_O, and SYNC_O are connected to the common bus. This means only
one device occupies the bus at a time while the LVDS drivers for all other devices 3-state. Unlike SDO and
SYNC_O, the clock cannot be switched out from device to device as the receiver requires a continuous clock. So
only device 1 outputs the clock and CLK_O of all other devices is 3-stated by appropriately setting M1+ and M1as listed in Table 2.
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Device 1
SD0
External Clock
CLK_0
CLK_I
SYNC_0
BUS_BUSY
Last Device
BUS_BUSY
+V
To Receiver
M1+,M2−
RD
CLK_I/E,
LAT_Y/N,
+V
MODE_C/D
CS M1−,M2+
From Controller
Device 2
RD
SD0
CLK_I
CLK_0
SYNC_0
BUS_BUSY
+V
+V
M1−,LAT_Y/N, M2−
M1+,M2+,
MODE_C/D
CLK_I/E
CS
To Next Device
From Controller
Figure 13. Cascade Connection
CLOCK SOURCE
In this mode it is very critical to control the skew between the three LVDS o/p signals. It is recommended to use
external clock mode only for all of the devices in cascade. BUS_BUSY of device n is connected to RD of device
n + 1 and so on. Finally BUS_BUSY of the last device in the chain is to be connected to RD of device 1. This
ensures the necessary handshake to control the sequence of data reads for all of the devices in cascade. (It is
also allowed to tie RD to 0 for device 1.)
TIMING DIAGRAMS FOR CASCADE OPERATION
The conversion rate for n devices in cascade must be selected such that:
1/conversion speed > first device read cycle duration + (n - 1) next device read cycle duration
First device read cycle duration = read startup delay_1 + data frame duration + (td16 + td17)
Next device read cycle duration = read startup delay_n + data frame duration + (td16 + td17)
Read startup delay_1 = 10 ns + (td19 - td4 + td12) + 2/fclk
Read startup delay_n = (td13 + 2/fclk)
Data frame duration = 16/fclk Note that it is not necessary that all devices in the chain sample the data
simultaneously. But all of the devices must operate with the same exact conversion speed.
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nth CONV
n + 1 Tracking
n + 1 Conversion
CONVST
See Figure 6 for details
CS
RD #1
BUS_BUSY #n
(Last device)
See Figure 15 for details
BUS_BUSY #1
RD #2
td18
BUS_BUSY #2
SDO
#1 16−Bits
nth conversion
#2 16−Bits
nth conversion
SYNC_O #1
SYNC_O #2
SYNC_O
Figure 14. Data Read Operation for Devices in Cascade Mode
DATA READ OPERATION
On power up, BUS_BUSY for all of the devices is low. The devices receive CONVST or CSTART to sample and
start the conversion. The first device starts the data read cycle at the end of its conversion. BUS_BUSY of device
1 (connected to RD of device 2) goes high on the read cycle start indicating that it wants to occupy the bus.
Device 2 BUS_BUSY goes high on the rising edge of RD. This propagates until the last device.
Device 1 BUS_BUSY goes low after it outputs its data; at this time SDO and SYNC_O for device 1 go to 3-state.
The falling edge of BUS_BUSY (RD of the next device) indicates to the next device that it is its turn to output the
data. The next device outputs the data from the last completed conversion. BUS_BUSY of the last device goes
low and its SYNC_O and SDO go to 3-state after it outputs its data. BUS_BUSY of the last device is fed back to
RD of the first device as shown in Figure 13 (RD can also be tied to 0 for device 1). This ensures that RD of
device 1 is low before its conversion is over. The data read sequence continues with only one external signal,
CONVST or CSTART, when CS = 0. For any device, CS high during the data read cycle 3-states SYNC_O and
SDO of the device and halts the data read sequence. To reset this condition it is necessary to assert CS high for
all of the devices. The new read sequence starts only after CS for all of the devices is low before point A shown
in Figure 6. The high pulse on CS must be at least 20 ns wide. It is better to connect CS for all of the devices
together to avoid undesired halting of the data read sequence.
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CS = 0
BUS_BUSY #1
RD #2
td17
SYNC_O #1
15R
16R
17R
18R
CLK_O #1
td16
LSB − 1
#1
SDO #1
BUSY_BUS #2 = 1
LSB #1
td13
1F #2
2R #2
SYNC_O #2
SDO #2
MSB
MSB − 1
Figure 15. Device n Read Cycle End and Device n+1 Read Cycle Start
Unlike daisy chain, the data frames of all the devices in cascade are not seamless and there is a loss of time
between one device 3-state to other device data valid due to wakeup time from 3-state and a two clock phase
shift between SYNC and data (see Figure 15 for details). As a result, the number of data frames per second in
this mode are less than in daisy chain mode. Also, a maximum of 4 devices can be cascaded on the same bus.
But, I/O power per device is considerably lower in cascade as compared to daisy chain as each device LVDS o/p
goes to 3-state after its data transfer. The deserializer at the output of the last device can shift the data on every
clock falling edge, and it can latch the parallel 16-bit word on the second CLK_O rising edge (shown as 18R)
after every SYNC_O rising edge.
THEORY OF OPERATION
The ADS8410 is a member of the high-speed successive approximation register (SAR) analog-to-digital
converters family. The architecture is based on charge redistribution, which inherently includes a sample/hold
function. The device includes a built-in conversion clock, internal reference, and 200-MHz LVDS serial interface.
The device can be operated at maximum throughput of 2 MSPS.
ANALOG INPUT
An analog input is provided to two input pins: +IN and -IN. When a conversion is initiated, the voltage difference
between these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are
disconnected from any internal function.
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+VA
ADS8410
170 W
+IN
−IN
+
_
170 W
25 pF
25 pF
AGND
AGND
Figure 16. Simplified Input Circuit
When the converter enters hold mode, the voltage difference between the +IN and -IN inputs is captured on the
internal capacitor array. The input current on the analog inputs depends upon a number of factors: sample rate,
input voltage, signal frequency, and source impedance. Essentially, the current into the ADS8410 charges the
internal capacitor array during the sample period. After this capacitance has been fully charged, there is no
further input current (this may not happen when the signal is moving continuously). The source of the analog
input voltage must be able to charge the input capacitance (25 pF) to better than a 16-bit settling level with a
step input within the acquisition time of the device. For calculation, the step size can be selected equal to the
maximum voltage difference between two consecutive samples at the maximum signal frequency (see the
TYPICAL ANALOG INPUT CIRCUIT section). When the converter goes into hold mode, the input impedance is
greater than 1GΩ.
7
INPUT+
3
1 mF
+
VCC+
2
0.1 mF
REF
−
6
THS4031
+
REFIN
15 W
18 +IN
8
4
19
1
1000 pF
15 W
NULL
NULL
VCC−
A
11
REFM
10 mF
A
REFM
12
49.9 W
−IN
ADS8410
A
Figure 17. Typical Analog Input Schematic
Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, both IN and +IN inputs should be within the limits specified. Outside of these ranges, the converter linearity may not
meet specifications. Care should be taken to ensure that +IN and -IN see the same impedance to the respective
sources. If this is not observed, the two inputs could have different setting times. This may result in offset error,
gain error, and linearity error which changes with temperature and input voltage.
REFERENCE
The ADS8410 has a built-in 4.096-V (nominal value) reference. The ADS8410 can also operate with an external
reference. When the internal reference is used, pin 14 (REFOUT) should be connected to pin 13 (REFIN), and a
0.1-μF decoupling capacitor and 1-μF storage capacitor must be connected between pin 14 (REFOUT) and pins
11 and 12 (REFM) (see Figure 18). The internal reference of the converter is buffered.
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ADS8410
REFOUT
REFIN
1 mF
0.1 mF
REFM
AGND
Figure 18. Using Internal Reference
The REFIN pin is also internally buffered. This eliminates the need to put a high bandwidth buffer onboard to
drive the ADC reference and saves system area and power. When an external reference is used, the reference
must be low noise, which can be achieved by the additional bypass capacitor from the REFIN pin to the REFM
pin (see Figure 19). REFM must be connected to the analog ground plane.
ADS8410
REFOUT
0.1 mF
50 W
REF3040
REFIN
0.1 mF
22 mF
1 mF
REFM
AGND
AGND
Figure 19. Using External Reference
DIGITAL INTERFACE
TIMING AND CONTROL
Refer to the timing diagrams and TIMING REQUIREMENTS table for detailed information.
SAMPLING AND CONVERSION
Sampling and conversion is controlled by the CONVST pin. For higher noise performance it is essential to have
low jitter on the falling edge of CONVST. The device uses the internally generated clock for conversion, hence it
has a fixed conversion time.
READING DATA
The ADS8410 includes a high-speed LVDS serial interface. As discussed prior, an external clock (CLK_I, less
than 200 MHz) or an internal 200-MHz clock can be used for a data read. The device outputs data in two’s
compliment format. Table 4 lists the ideal output codes.
Table 4. Ideal Input Voltages and Output Codes
DESCRIPTION
22
ANALOG VALUE (+IN – (–IN))
HEX CODE
Full-scale range
+Vref
–
Least significant bit (LSB)
+Vref/216
–
Full scale
Vref – 1 LSB
FFFF
Midscale
+Vref/2
8000
Midscale – 1 LSB
Vref /2 – 1 LSB
7FFF
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Table 4. Ideal Input Voltages and Output Codes (continued)
DESCRIPTION
Zero
ANALOG VALUE (+IN – (–IN))
HEX CODE
0V
0000
The restrictions on read cycle start are described in the section RESTRICTIONS ON READ CYCLE START (see
Figure 9).
ADS8410
SN65LVDS152 #1
SDO+
GND
DI+
100 W
BYTE
SDO−
LVI
VCC
EN
DI−
SYNC_O+
LCI+
CO_EN
D15−D6
100 W
D9−D0
SYNC_O−
LCI−
CLK_O+
MCI+
100 W
CLK_O−
MCI−
CO−
CO+
SN65LVDS152 #2
DI+
100 W
LVI
VCC
EN
DI−
LCI+
D5−D0
D9−D4
LCI−
MCI+
MCI−
CO−
CO+
CO_EN
Figure 20. 16-Bit Data De-Serialization While BYTE = 0
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ADS8410
+VBD
SN65LVDS152
SDO+
DI+
100 W
BYTE
SDO−
VCC
LVI
EN
DI−
SYNC_O+
LCI+
D7−D0
100 W
D9−D2
LCI−
SYNC_O−
CLK_O+
MCI+
100 W
CLK_O−
MCI−
CO−
CO_EN
CO+
Figure 21. 8-Bit Data De-Serialization While BYTE = 1, Data
POWER SAVING
The converter provides two power saving modes, full powerdown and nap. Table 5 lists information on the
activation/deactivation and resumption times for both modes.
Table 5. Powerdown Modes
POWERDOWN
MODE
SDO
POWER
CONSUMPTION
ACTIVATED BY
ACTIVATION TIME
RESUME POWER
BY
Normal operation
Refer to DATA READ
OPERATION section
58 mA
NA
NA
NA
Full powerdown
(internal reference)
3 Stated
1 μA
PD = 0
td21
PD = 1
Full powerdown
(external reference)
3 Stated
1 μA
PD = 0
td21
PD = 1
Nap powerdown
Not 3 stated
25 mA
Nap = 1
150 ns
Sample start
FULL POWERDOWN MODE
Full powerdown mode is activated by deasserting PD = 0; the device takes td21 ns to reach the full powerdown
state. The device can return to normal mode from full powerdown by asserting PD = 1. The powerup sequence is
different for device operation with an internal reference or external reference as shown in Figure 22 and
Figure 23.
24
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PD
tw6
td20
SDO
td22
1
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Invalid Conversion
2
3
Valid Conversion
BUSY
td21
VREF
ts1
Full ICC
ICC PD
Full ICC
Figure 22. Device Full Powerdown and Powerup Sequence with Device Operation in Internal Reference
Mode
When an internal reference is used, a conversion can be started td22 ns after asserting PD = 1. After the first
three conversions, ts1 ns are required for reference voltage settling to the trimmed value. Any conversions after
this provide data at the specified accuracy.
PD
tw6
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
Î
Î
Î
Î
Invalid Conversion
td20
SDO
td22
1
2
Valid Conversion
3
BUSY
td21
Full ICC
ICC PD
Full ICC
Figure 23. Device Full Powerdown and Powerup Sequence with Device Operation in External Reference
Mode
When an external reference is used, a conversion can be started td22 n after asserting PD = 1. The first three
conversions are required for internal circuit stabilization. Any conversions after this provide data at the specified
accuracy.
NAP MODE
The device automatically enters the nap state if nap = 1 at end of a conversion, and it remains in the nap state
until the start of the sampling phase. A minimum of 150 ns is required after a sample start for the device to come
out of the nap state and to perform normal sampling. So the minimum sampling time needed for nap mode is
tacq(min) + 150 ns, or the maximum conversion speed in nap mode is 1.5 MHz.
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LAYOUT
For optimum performance, care should be taken with the physical layout of the ADS8410 circuitry. The device
offers single-supply operation, and it is often used in close proximity with digital logic, FPGA, microcontrollers,
microprocessors, and digital signal processors. The more digital logic present in the design and the higher the
switching speed, the more difficult it is to achieve good performance from the converter.
The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground
connections, and digital inputs that occur just prior to the end of sampling and just prior to latching the output of
the analog comparator during the conversion phase. Such glitches might originate from switching power supplies,
nearby digital logic, or high power devices. Noise during the end of sampling and the later half of a conversion
must be kept to a minimum (the former half of a conversion is not very sensitive since the device uses a
proprietary error correction algorithm to correct for transient errors during this period).
The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the
external event. On average, the device draws very little current from an external reference as the reference
voltage is internally buffered. If the reference voltage is external and originates from an op amp, make sure that it
can drive the bypass capacitor or capacitors without oscillation. A 0.1-μF bypass capacitor and 1-μF storage
capacitor are recommended from REFIN directly to REFM.
The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the
analog ground. Avoid connections that are too close to the grounding point of a microcontroller or digital signal
processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal
layout consists of an analog ground plane dedicated to the converter and associated analog circuitry.
As with the AGND connections, +VA should be connected to a +5-V power supply plane that is separate from the
connection for +VBD and digital logic until they are connected at the power entry point onto the PCB. Power to
the ADC should be clean and well bypassed. A 0.1-μF ceramic bypass capacitor should be placed as close to
the device as possible. See Table 6 for the placement of the capacitor. In addition to the 0.1-μF capacitor, a 1-μF
capacitor is recommended. In some situations, additional bypassing may be required, such as a 100-μF
electrolytic capacitor or even a Pi filter made up of inductors and capacitors; all designed to essentially low-pass
filter the +5-V supply, thus removing the high frequency noise.
Table 6. Power Supply Decoupling Capacitor Placement
POWER SUPPLY PLANE
CONVERTER ANALOG SIDE
SUPPLY PINS
Pair of pins require a shortest path to
decoupling capacitors
CONVERTER DIGITAL SIDE
(9,10) (16,17) (20,21) (22,23) (26,27 or 25,26)
(36,37)
(44,45)
TYPICAL CHARACTERISTICS
HISTOGRAM (DC CODE SPREAD
AT THE CENTER OF CODE)
60000
+VA = 5 V,
TA = 25°C,
fs = 2 MSPS,
Vref = 4.096 V
48373
50000
40069
Number of Hits
Number of Hits
50000
40000
30000
26605
20000
14.25
+VA = 5 V,
TA = 25°C,
fs = 2 MSPS,
Vref = 4.096 V
48042
40000
33712
32556
30000
20000
11438
10382
10000
10000
5277
3462
3
278
828
16
32767
32769
32771
32773
32775
32768
32770
32772
32774
Code
Figure 24.
26
ENOB − Effective Number of Bits − Bits
60000
0
EFFECTIVE NUMBER OF BITS
vs
FREE-AIR TEMPERATURE
HISTOGRAM (DC CODE SPREAD
WITH I/P CLOSE TO FS)
0
7
458
621
17
65343
65345
65347
65349
65351
65344
65346
65348
65350
Code
Figure 25.
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14.15
14.05
13.95
13.85
13.75
−40
+VA = 5 V,
fi = 1 kHz,
fs = 2 MSPS,
Vref = 4.096 V
−20
20
40
60
80
0
TA − Free-Air Temperature − °C
Figure 26.
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TYPICAL CHARACTERISTICS (continued)
+VA = 5 V,
fi = 1 kHz,
fs = 2 MSPS,
Vref = 4.096 V
87.2
86.8
86.4
86
−40
+VA = 5 V,
fi = 1 kHz,
fs = 2 MSPS,
Vref = 4.096 V
88.6
88.2
87.8
87.4
87
−40
−90
+VA = 5 V,
fi = 1 kHz,
fs = 2 MSPS,
Vref = 4.096 V
−92
−94
−96
−98
−100
−40
TA − Free-Air Temperature − 5C
−20
0
20
40
60
TA − Free-Air Temperature − °C
Figure 27.
Figure 28.
Figure 29.
TOTAL HARMONIC DISTORTION
vs
FREE-AIR TEMPERATURE
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY
SIGNAL-TO-NOISE AND DISTORTION
vs
INPUT FREQUENCY
80
−94
−96
−98
−100
−40
−20
0
20
40
60
TA − Free-Air Temperature − °C
40
60
80
14.15
14.05
13.95
13.85
+VA = 5 V,
TA = 25°C,
fs = 2 MSPS,
Vref = 4.096 V
10
1
fI − Input Frequency − kHz
100
80
88
87
86
+VA = 5 V,
TA = 25°C,
fs = 2 MSPS,
Vref = 4.096 V
85
84
0.1
1
10
fI − Input Frequency − kHz
100
Figure 30.
Figure 31.
Figure 32.
SIGNAL-TO-NOISE RATIO
vs
INPUT FREQUENCY
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
SFDR − Spurious Free Dynamic Range − dB
88
87
86
+VA = 5 V,
TA = 25°C,
fs = 2 MSPS,
Vref = 4.096 V
85
0.1
20
14.25
13.75
0.1
80
0
1
10
fI − Input Frequency − kHz
100
Figure 33.
−90
−90
−93
+VA = 5 V,
TA = 25°C,
fs = 2 MSPS,
Vref = 4.096 V
THD − Total Harmonic Distortion − dB
−92
+VA = 5 V,
fi = 1 kHz,
fs = 2 MSPS,
Vref = 4.096 V
−20
SINAD − Signal−to− Noise and Distortion − dB
−20
0
20
40
60
TA − Free-Air Temperature − 5C
ENOB − Effective Number of Bits − Bits
THD − Total Harmonic Distortion − dB
SFDR − Spurious Free Dynamic Range − dB
87.6
SPURIOUS FREE DYNAMIC RANGE
vs
FREE-AIR TEMPERATURE
89
88
−90
SNR − Signal-to-Noise Ratio − dB
SIGNAL-TO-NOISE RATIO
vs
FREE-AIR TEMPERATURE
SNR − Signal-to-Noise Ratio − dB
SINAD − Signal−to−Noise and Distortion − dB
SIGNAL-TO-NOISE AND DISTORTION
vs
FREE-AIR TEMPERATURE
−96
−99
−102
−105
0.1
1
10
fI − Input Frequency − kHz
Figure 34.
100
−92
+VA = 5 V,
TA = 25°C,
fs = 2 MSPS,
Vref = 4.096 V
−94
−96
−98
−100
0.1
1
10
fI − Input Frequency − kHz
Figure 35.
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TYPICAL CHARACTERISTICS (continued)
OFFSET ERROR
vs
SUPPLY VOLTAGE
GAIN ERROR
vs
SUPPLY VOLTAGE
0.1
0.15
0.01
TA = 25°C,
fs = 2 MSPS,
Vref = 4.096 V
TA = 25°C,
fs = 2 MSPS,
Vref = 4.096 V
0.02
−0.02
0.1
Offset Error − mV
0.006
Gain Error − % FS
0.06
Offset Error − mV
OFFSET ERROR
vs
FREE-AIR TEMPERATURE
0.002
−0.002
−0.006
−0.06
−0.1
4.75
4.85
4.95
5.05
5.15
VCC − Supply Voltage − +VA in V
4.85
4.95
5.05
5.15
VCC − Supply Voltage − +VA in V
40
60
POWER DISSIPATION
vs
SAMPLE RATE (NAP MODE)
POWER DISSIPATION
vs
SUPPLY VOLTAGE
80
320
300
+VA = 5 V,
fs = 2 MSPS,
Vref = 4.096 V
−0.005
PD − Power Dissipation − mW
Normal
PD − Power Dissipation − mW
250
NAP
200
+VA = 5 V,
TA = 25°C,
Vref = 4.096 V
150
0
80
0.5
1
1.5
Sample Rate − MSPS
TA = 25°C,
fs = 2 MSPS,
Vref = 4.096 V
310
300
290
280
270
4.75
100
−20
0
20
40
60
TA − Free-Air Temperature − °C
2
4.85
4.95
5.05
5.15
VCC − Supply Voltage − +VA in V
Figure 39.
Figure 40.
Figure 41.
POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
1.5
DNL − Differential Nonlinearity − LSB
+VA = 5 V,
fs = 2 MSPS,
Vref = 4.096 V
310
300
290
−20
0
20
40
60
TA − Free-Air Temperature − °C
80
Figure 42.
1
+VA = 5 V,
fs = 2 MSPS,
Vref = 4.096 V
max
0.5
0
min
−0.5
−1
−40
5.25
2.5
INL − Integral Nonlinearity − LSB
Gain Error − % FS
20
GAIN ERROR
vs
FREE-AIR TEMPERATURE
320
PD − Power Dissipation − mW
0
TA − Free-Air Temperature − °C
Figure 38.
−0.01
28
−20
Figure 37.
0
280
−40
−0.05
Figure 36.
0.005
−0.015
−40
0
−0.15
−40
5.25
0.015
0.01
0.05
−0.1
−0.01
4.75
5.25
+VA = 5 V,
fs = 2 MSPS,
Vref = 4.096 V
−20
0
20
40
60
TA − Free-Air Temperature − °C
Figure 43.
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80
2
1.5
+VA = 5 V,
fs = 2 MSPS,
Vref = 4.096 V
max
1
0.5
0
−0.5
−1
min
−1.5
−2
−2.5
−40
−20
0
20
40
60
TA − Free-Air Temperature − °C
80
Figure 44.
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TYPICAL CHARACTERISTICS (continued)
10
9
9
8
8
7
6
5
4
4.108
7
6
5
4
3
3
2
2
1
1
0
4.112
Internal Reference Output − V
10
Number of Devices
Number of Devices
INTERNAL REFERENCE OUTPUT
vs
SUPPLY VOLTAGE
NEGATIVE INTEGRAL
NONLINEARITY
DISTRIBUTION OVER 25 UNITS
POSITIVE INTEGRAL NONLINEARITY
DISTRIBUTION OVER 25 UNITS
−1.6
−1.4
−1.2
−1
−0.8
INL − Integral Nonlinearity min − LSB
Figure 45.
Figure 46.
4.104
4.1
4.096
4.092
4.088
4.084
4.08
4.75
0
0.7
0.9
1
1.2
1.3
INL − Integral Nonlinearity max − LSB
TA = 25°C,
fs = 2 MSPS,
Vref = 4.096 V
4.85
4.95
5.05
5.15
VCC − Supply Voltage − +VA in V
5.25
Figure 47.
INTERNAL REFERENCE OUTPUT
vs
FREE-AIR TEMPERATURE
4.112
Internal Reference Output − V
4.108
+VA = 5 V,
fs = 2 MSPS,
Vref = 4.096 V
4.104
4.1
4.096
4.092
4.088
4.084
4.08
−40
−20
0
20
40
60
TA − Free-Air Temperature − °C
80
Figure 48.
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PARAMETER MEASUREMENT INFORMATION
DRIVER
IOY
Driver Enable
Y
II
VOD
IOZ
Z
VOY + VOZ
2
VOY
VI
VOC
VOZ
Driver Enable
Y
100 W
+ 1%
VOD
Input
Z
CL = 10 pF
(2 Places)
Figure 52. Driver Voltage and Current Definitions
100%
80%
VOD(H)
Differential
Output
0V
VOD(L)
20%
0%
tf
tr
Figure 53. Timing and Voltage Definitions of the Differential Output Signal
49.9 Ω, ±1% (2 Places)
Driver Enable
3V
Y
Input
0V
Z
VOC
VOC(PP)
CL = 10 pF
(2 Places)
VOC(SS)
VOC
Figure 54. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
30
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PARAMETER MEASUREMENT INFORMATION (continued)
A
V
IA
)V
IB
VID
2
R
VIA
VIC
B
VO
VIB
Figure 55. Receiver Voltage Definitions
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REVISION HISTORY
Changes from Original (October 2005) to Revision A
Page
•
Added min spec for td23 paramenter in the Timing Requirements table (used to be max spec for this parameter) ............. 6
•
Deleted max spec for td23 paramenter in the Timing Requirements table (this spec is now the min spec for this
parameter) ............................................................................................................................................................................ 6
32
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PACKAGE OPTION ADDENDUM
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15-Feb-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
ADS8410IRGZT
NRND
Package Type Package Pins Package
Drawing
Qty
VQFN
RGZ
48
250
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
ADS8410I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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