ADS8412
SLAS384A – JUNE 2003 – REVISED DECEMBER 2004
16-BIT, 2 MSPS, UNIPOLAR DIFFERENTIAL INPUT, MICROPOWER SAMPLING
ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2-MHz Sample Rate
16-Bit NMC Ensured Over Temperature
Zero Latency
Unipolar Differential Input Range: Vref to -Vref
Onboard Reference
Onboard Reference Buffer
High-Speed Parallel Interface
Power Dissipation: 175 mW at 2 MHz Typ
Wide Digital Supply
8-/16-Bit Bus Transfer
48-Pin TQFP Package
ESD Sensitive - HBM Capability of 500 V,
1000 V at All Input Pins
•
•
•
DWDM
Instrumentation
High-Speed, High-Resolution, Zero Latency
Data Acquisition Systems
Transducer Interface
Medical Instruments
Communication
DESCRIPTION
The ADS8412 is a 16-bit, 2 MHz A/D converter with
an internal 4.096-V reference. The device includes a
16-bit capacitor-based SAR A/D converter with inherent sample and hold. The ADS8412 offers a full
16-bit interface and an 8-bit option where data is read
using two 8-bit read cycles.
The ADS8412 has a unipolar differential input. It is
available in a 48-lead TQFP package and is
characterized over the industrial -40°C to 85°C temperature range.
SAR
+IN
-IN
+
_
Output
Latches
and
3-State
Drivers
CDAC
BYTE
16-/8-Bit
Parallel DATA
Output Bus
Comparator
RESET
REFIN
REFOUT
4.096-V
Internal
Reference
Clock
Conversion
and
Control Logic
CONVST
BUSY
CS
RD
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2004, Texas Instruments Incorporated
ADS8412
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SLAS384A – JUNE 2003 – REVISED DECEMBER 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
MODEL
MAXIMUM
INTEGRAL
LINEARITY
(LSB)
MAXIMUM
DIFFERENTIAL
LINEARITY
(LSB)
NO MISSING
CODES
RESOLUTION
(BIT)
PACKAGE
TYPE
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
ADS8412I
–6 ~ 6
–2~+3
15
48 Pin
TQFP
PFB
–40°C to 85°C
48 Pin
TQFP
PFB
ADS8412IB
(1)
–2.5 ~ 2.5
–1~+2
16
ORDERING
INFORMATION
TRANSPORT
MEDIA
QUANTITY
ADS8412IPFBT
Tape and
reel 250
ADS8412IPFBR
Tape and
reel 1000
ADS8412IBPFBT
Tape and
reel 250
ADS8412IBPFBR
Tape and
reel 1000
–40°C to 85°C
For the most current specifications and package information, refer to our website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
UNIT
Voltage
Voltage range
+IN to AGND
–0.4 V to +VA + 0.1 V
–IN to AGND
–0.4 V to +VA + 0.1 V
+VA to AGND
–0.3 V to 7 V
+VBD to BDGND
–0.3 V to 7 V
+VA to +VBD
–0.3 V to 2.55 V
Digital input voltage to BDGND
–0.3 V to +VBD + 0.3 V
Digital output voltage to BDGND
–0.3 V to +VBD + 0.3 V
Operating free-air temperature range, TA
–40°C to 85°C
Storage temperature range, Tstg
–65°C to 150°C
Junction temperature (TJ max)
TQFP package
2
(TJMax - TA)/θJA
θJA thermal impedance
Lead temperature, soldering
(1)
150°C
Power dissipation
86°C/W
Vapor phase (60 sec)
215°C
Infrared (15 sec)
220°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
ADS8412
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SLAS384A – JUNE 2003 – REVISED DECEMBER 2004
SPECIFICATIONS
TA = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 2 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Full-scale input voltage (1)
Absolute input voltage
Common-mode input
range
+IN – (–IN)
–Vref
Vref
+IN
–0.2
Vref + 0.2
–IN
–0.2
Vref + 0.2
ADS8412I
(Vref/2) – 0.2
Vref/2
(Vref/2) + 0.2
V
V
V
Input capacitance
25
pF
Input leakage current
0.5
nA
16
Bits
SYSTEM PERFORMANCE
Resolution
No missing codes
(2) (3)
ADS8412I
15
ADS8412IB
16
–6
±4
6
–2.5
±1.5
2.5
ADS8412I
–2
±1
3
ADS8412IB
–1
±0.8
2
ADS8412I
INL
Integral linearity
DNL
Differential linearity
EO
Offset error
EG
Gain error (4) (5)
CMRR
Common-mode rejection ratio
(4)
ADS8412IB
ADS8412I
ADS8412IB
ADS8412I
ADS8412IB
–3
±1
3
–1.5
±0.5
1.5
–0.15
0.15
–0.098
0.098
At dc (±0.2 V around Vref/2)
80
+IN – (–IN) = 1 Vpp at 1 MHz
80
Noise
PSRR
Bits
DC Power supply rejection ratio
At 7FFFh output code,
+VA = 4.75 V to 5.25 V,
Vref = 4.096 V (4)
LSB
LSB
mV
%FS
dB
60
µV RMS
1
LSB
SAMPLING DYNAMICS
Conversion time
340
Acquisition time
100
400
ns
ns
Throughput rate
2
MHz
Aperture delay
2
ns
Aperture jitter
25
ps
Step response
100
ns
Overvoltage recovery
100
ns
DYNAMIC CHARACTERISTICS
VIN = 8 Vpp at 100 kHz
–95
VIN = 8 Vpp at 500 kHz
–90
Signal-to-noise ratio
VIN = 8 Vpp at 100 kHz
90
Signal-to-noise + distortion
VIN = 8 Vpp at 100 kHz
88
VIN = 8 Vpp at 100 kHz
95
VIN = 8 Vpp at 500 kHz
93
THD
Total harmonic distortion (6)
SNR
SINAD
SFDR
Spurious free dynamic range
–3 dB Small signal bandwidth
(1)
(2)
(3)
(4)
(5)
(6)
5
dB
dB
dB
MHz
Ideal input span, does not include gain or offset error.
LSB means least significant bit
This is endpoint INL, not best fit
Measured relative to an ideal full-scale input [+IN – (–IN)] of 8.192 V
This specification does not include the internal reference voltage error and drift.
Calculated on the first nine harmonics of the input frequency
3
ADS8412
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SLAS384A – JUNE 2003 – REVISED DECEMBER 2004
SPECIFICATIONS (continued)
TA = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 2 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3.9
4.096
4.2
UNIT
EXTERNAL VOLTAGE REFERENCE INPUT
Vref
Reference voltage at REFIN
Reference
resistance (7)
500
V
kΩ
INTERNAL REFERENCE OUTPUT
Vref
Internal reference start-up time
From 95% (+VA), with 1 µF
storage capacity
Reference voltage
IOUT = 0
Source current
Static load
Line regulation
+VA = 4.75 ~ 5.25 V
0.6
mV
Drift
IOUT = 0
36
PPM/°C
120
4.065
4.096
ms
4.13
V
10
µA
DIGITAL INPUT/OUTPUT
Logic family — CMOS
VIH
High level input voltage
IIH = 5 µA
+VBD – 1
VIL
Low level input voltage
IIL = 5 µA
–0.3
+VBD + 0.3
0.8
VOH
High level output voltage
IOH = 2 TTL loads
+VBD – 0.6
+VBD
VOL
Low level output voltage
IOL = 2 TTL loads
0
0.4
V
Data format – 2's complement
POWER SUPPLY REQUIREMENTS
Power supply voltage
PD
+VBD
+VA
2.7
3
5.25
4.75
5
5.25
V
+VA Supply current (8)
fs = 2 MHz
35
40
mA
Power dissipation (8)
fs = 2 MHz
175
200
mW
85
°C
TEMPERATURE RANGE
TA
(7)
(8)
4
Operating free-air
–40
Can vary ±20%
This includes only +VA current. +VBD current is typically 1 mA with 5-pF load capacitance on output pins.
ADS8412
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SLAS384A – JUNE 2003 – REVISED DECEMBER 2004
TIMING CHARACTERISTICS
All specifications typical at –40°C to 85°C, +VA = +VBD = 5 V (1) (2) (3)
PARAMETER
MIN
tCONV
Conversion time
340
tACQ
Acquisition time
100
tpd1
CONVST low to BUSY high
tpd2
Propagation delay time, end of conversion to BUSY low
tw1
Pulse duration, CONVST low
tsu1
Setup time, CS low to CONVST low
tw2
Pulse duration, CONVST high
TYP
MAX
UNIT
400
ns
ns
30
ns
5
ns
20
ns
0
ns
20
ns
CONVST falling edge jitter
10
tw3
Pulse duration, BUSY signal low
tw4
Pulse duration, BUSY signal high
th1
Hold time, first data bus data transition (RD low, or CS low for read
cycle, or BYTE input changes) after CONVST low
td1
tsu2
tw5
Pulse duration, RD low
ten
Enable time, RD low (or CS low for read cycle) to data valid
td2
Delay time, data hold from RD high
0
td3
Delay time, BYTE rising edge or falling edge to data valid
2
tw6
Pulse duration, RD high
20
ns
tw7
Pulse duration, CS high
20
ns
th2
Hold time, last RD (or CS for read cycle ) rising edge to CONVST
falling edge
50
ns
tsu3
Setup time, BYTE transition to RD falling edge
0
ns
th3
Hold time, BYTE transition to RD falling edge
0
tdis
Disable time, RD high (CS high for read cycle) to 3-stated data bus
20
ns
td5
Delay time, end of conversion to MSB data valid
10
ns
tsu4
Byte transition setup time, from BYTE transition to the next BYTE
transition
50
ns
td6
Delay time, CS rising edge to BUSY falling edge
50
ns
td7
Delay time, BUSY falling edge to CS rising edge
50
ns
tsu(AB)
Setup time, from the falling edge of CONVST (used to start the valid
conversion) to the next falling edge of CONVST (when CS = 0 and
CONVST used to abort) or to the next falling edge of CS (when CS is
used to abort)
60
tsu5
Setup time, falling edge of CONVST to read valid data (MSB) from
current conversion
th4
Hold time, data (MSB) from previous conversion hold valid from falling
edge of CONVST
(1)
(2)
(3)
Min(tACQ)
ps
ns
370
ns
40
ns
Delay time, CS low to RD low (or BUSY low to RD low)
0
ns
Setup time, RD high to CS high
0
ns
50
ns
20
ns
ns
20
ns
ns
340
MAX(tCONV) + MAX(td5)
ns
ns
MIN(tCONV)
ns
All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2.
See timing diagrams.
All timings are measured with 20 pF equivalent loads on all data bits and BUSY pins.
5
ADS8412
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SLAS384A – JUNE 2003 – REVISED DECEMBER 2004
TIMING CHARACTERISTICS
All specifications typical at –40°C to 85°C, +VA = 5 V, +VBD = 3 V
(1) (2) (3)
PARAMETER
MIN
TYP
MAX
UNIT
400
ns
tCONV
Conversion time
340
tACQ
Acquisition time
100
tpd1
CONVST low to conversion started (BUSY high)
40
ns
tpd2
Propagation delay time, end of conversion to BUSY low
10
ns
tw1
Pulse duration, CONVST low
tsu1
Setup time, CS low to CONVST low
tw2
Pulse duration, CONVST high
ns
20
ns
0
ns
20
ns
CONVST falling edge jitter
10
tw3
Pulse duration, BUSY signal low
tw4
Pulse duration, BUSY signal high
th1
Hold time, first data bus transition (RD low, or CS low for read cycle, or
BYTE input changes) after CONVST low
td1
tsu2
tw5
Pulse duration, RD low
ten
Enable time, RD low (or CS low for read cycle) to data valid
td2
Delay time, data hold from RD high
0
td3
Delay time, BYTE rising edge or falling edge to data valid
2
tw6
Pulse duration, RD high
20
ns
tw7
Pulse duration, CS high
20
ns
th2
Hold time, last RD (or CS for read cycle ) rising edge to CONVST
falling edge
50
ns
tsu3
Setup time, BYTE transition to RD falling edge
0
ns
th3
Hold time, BYTE transition to RD falling edge
0
tdis
Disable time, RD high (CS high for read cycle) to 3-stated data bus
td5
Delay time, end of conversion to MSB data valid
tsu4
Byte transition setup time, from BYTE transition to next BYTE transition
50
ns
td6
Delay time, CS rising edge to BUSY falling edge
50
ns
td7
Delay time, BUSY falling edge to CS rising edge
50
ns
tsu(AB)
Setup time, from the falling edge of CONVST (used to start the valid
conversion) to the next falling edge of CONVST (when CS = 0 and
CONVST used to abort) or to the next falling edge of CS (when CS is
used to abort)
70
tsu5
Setup time, falling edge of CONVST to read valid data (MSB) from
current conversion
th4
Hold time, data (MSB) from previous conversion hold valid from falling
edge of CONVST
(1)
(2)
(3)
6
Min(tACQ)
ps
ns
370
ns
40
ns
Delay time, CS low to RD low (or BUSY low to RD low)
0
ns
Setup time, RD high to CS high
0
ns
50
ns
30
ns
ns
30
ns
ns
30
ns
20
ns
350
MAX(tCONV) + MAX(td5)
ns
ns
MIN(tCONV)
All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2.
See timing diagrams.
All timings are measured with 20 pF equivalent loads on all data bits and BUSY pins.
ns
ADS8412
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SLAS384A – JUNE 2003 – REVISED DECEMBER 2004
PIN ASSIGNMENTS
BUSY
BDGND
+VBD
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
BDGND
PFB PACKAGE
(TOP VIEW)
36 35 34 33 32 31 30 29 28 27 26 25
37
24
38
23
39
22
40
21
41
20
42
19
43
18
44
17
45
16
46
15
47
14
48
3
4 5
6 7 8
13
9 10 11 12
REFIN
REFOUT
NC
+VA
AGND
+IN
-IN
AGND
+VA
+VA
1 2
+VBD
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
AGND
AGND
+VA
AGND
AGND
+VBD
RESET
BYTE
CONVST
RD
CS
+VA
AGND
AGND
+VA
REFM
REFM
NC - No connection
7
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SLAS384A – JUNE 2003 – REVISED DECEMBER 2004
Terminal Functions
NAME
NO.
I/O
5, 8, 11, 12,
14, 15, 44,
45
-
Analog ground
25, 35
-
Digital ground for bus interface digital supply
BUSY
36
O
Status output. High when a conversion is in progress.
BYTE
39
I
Byte select input. Used for 8-bit bus reading. 0: No fold back 1: Low byte D[7:0] of the 16 most
significant bits is folded back to high byte of the 16 most significant pins DB[15:8].
CONVST
40
I
Convert start. The falling edge of this input ends the acquisition period and starts the hold period.
CS
42
I
Chip select. The falling edge of this input starts the acquisition period.
AGND
BDGND
DESCRIPTION
8-Bit Bus
Data Bus
BYTE = 0
16-Bit Bus
BYTE = 1
BYTE = 0
DB15
16
O
D15 (MSB)
D7
D15 (MSB)
DB14
17
O
D14
D6
D14
DB13
18
O
D13
D5
D13
DB12
19
O
D12
D4
D12
DB11
20
O
D11
D3
D11
DB10
21
O
D10
D2
D10
DB9
22
O
D9
D1
D9
DB8
23
O
D8
D0 (LSB)
D8
DB7
26
O
D7
All ones
D7
DB6
27
O
D6
All ones
D6
DB5
28
O
D5
All ones
D5
DB4
29
O
D4
All ones
D4
DB3
30
O
D3
All ones
D3
DB2
31
O
D2
All ones
D2
DB1
32
O
D1
All ones
D1
DB0
33
O
D0 (LSB)
All ones
D0 (LSB)
–IN
7
I
Inverting input channel
+IN
6
I
Non inverting input channel
NC
3
-
No connection
REFIN
1
I
Reference input
REFM
47, 48
I
Reference ground
REFOUT
2
O
Reference output. Add 1 µF capacitor between the REFOUT pin and REFM pin when internal reference
is used.
RESET
38
I
Current conversion is aborted and output latches are cleared (set to zeros) when this pin is asserted
low. RESET works independantly of CS.
RD
41
I
Synchronization pulse for the parallel output. When CS is low, this serves as the output enable and puts
the previous conversion result on the bus.
+VA
4, 9, 10, 13,
43, 46
-
Analog power supplies, 5-V dc
24, 34, 37
-
Digital power supply for bus
+VBD
8
ADS8412
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SLAS384A – JUNE 2003 – REVISED DECEMBER 2004
TIMING DIAGRAMS
tw2
tw1
CONVST
(used in normal
conversion)
tcycle
CONVST
(used in ABORT)
tsu(AB)
tpd1
tsu(AB)
tpd2
tw4
tpd1
tw3
BUSY
tsu1
tw7
td7
CS
td6
CONVERT†
tCONV
tCONV
SAMPLING†
(When CS Toggle)
tACQ
BYTE
tsu4
th1
tsu2
td1
th2
RD
Data to
be read†
Invalid
Previous Conversion
th4
tdis
ten
tsu5
DB[15:8]
Invalid
Current Conversion
Hi−Z
Hi−Z
D [15:8]
DB[7:0]
Hi−Z
D [7:0]
Hi−Z
D [7:0]
†Signal
internal to device
Figure 1. Timing for Conversion and Acquisition Cycles With CS and RD Toggling
9
ADS8412
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SLAS384A – JUNE 2003 – REVISED DECEMBER 2004
tw1
CONVST
(used in normal
conversion)
tw2
tcycle
CONVST
(used in ABORT)
tsu(AB)
tpd1
tsu(AB)
tpd2
tw4
tw3
BUSY
tw7
tsu1
td7
CS
td6
CONVERT†
tCONV
tCONV
SAMPLING†
(When CS Toggle)
tACQ
BYTE
th1
RD = 0
Data to
be read†
tdis
ten
DB[15:8]
DB[7:0]
†Signal
tsu5
Hi−Z
Previous
D [7:0]
Hi−Z
internal to device
Invalid
Current Conversion
Previous
Hi−Z
D [15:8]
Hi−Z
tdis
Invalid
Previous Conversion
th4
tsu4
th2
ten
D [15:8]
D [7:0]
D [7:0]
Hi−Z
Repeated
D [15:8]
Hi−Z
Repeated
D [7:0]
ten
Figure 2. Timing for Conversion and Acquisition Cycles With CS Toggling, RD Tied to BDGND
10
ADS8412
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SLAS384A – JUNE 2003 – REVISED DECEMBER 2004
tw1
tw2
CONVST
(used in normal
conversion)
tcycle
CONVST
(used in ABORT)
tsu(AB)
tpd1
tsu(AB)
tpd2
tw4
tpd1
tw3
BUSY
CS = 0
CONVERT†
tCONV
tCONV
t(ACQ)
SAMPLING†
(When CS = 0)
BYTE
tsu4
th1
th2
RD
tdis
ten
Data to
be read†
th4
DB[15:8]
DB[7:0]
†Signal
Invalid
Invalid
Previous Conversion
Current Conversion
tsu5
Hi−Z
Hi−Z
D [15:8]
D [7:0]
D [7:0]
Hi−Z
Hi−Z
internal to device
Figure 3. Timing for Conversion and Acquisition Cycles With CS Tied to BDGND, RD Toggling
11
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SLAS384A – JUNE 2003 – REVISED DECEMBER 2004
tw1
CONVST
(used in normal
conversion)
tw2
tcycle
CONVST
(used in ABORT)
tsu(AB)
tpd1
tsu(AB)
tpd2
tw4
tpd1
tpd2
tw3
BUSY
CS = 0
CONVERT†
tCONV
tCONV
tACQ
SAMPLING†
(When CS Toggle)
th1
th1
BYTE
RD = 0
td3
td3
td5
th4
tsu5
Previous
MSB
Invalid
DB[15:8]
Previous Previous
LSB
LSB
Invalid
DB[7:0]
†Signal
td5
th4
td3
tsu5
Invalid
MSB
LSB
MSB
MSB
LSB
MSB
Invalid
internal to device
Figure 4. Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGND—Auto Read
CS
RD
tsu4
BYTE
ten
tdis
tdis
ten
DB[15:0]
td3
Hi−Z
Valid
Hi−Z
Valid
Valid
Figure 5. Detailed Timing for Read Cycles
12
Hi−Z
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SLAS384A – JUNE 2003 – REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS
SIGNAL-TO-NOISE RATIO
vs
FREE-AIR TEMPERATURE
HISTOGRAM (DC Code Spread)
HALF SCALE 131071 CONVERSIONS
80000
90.4
+VA = 5 V,
+VBD = 3.3 V,
TA = 25°C,
Code = 65292
60000
SNR − Signal-to-Noise Ratio − dB
70000
50000
40000
30000
20000
10000
90.2
90.1
90
89.9
89.8
89.7
89.6
89.5
−40
65295
65292
65289
0
Figure 7.
EFFECTIVE NUMBER OF BITS
vs
FREE-AIR TEMPERATURE
SIGNAL-TO-NOISE AND DISTORTION
vs
FREE-AIR TEMPERATURE
80
86.2
SINAD − Signal-to-Nois and Distortion − dB
14.015
14.01
14.005
14
13.995
fi = 50 kHz,
+VA = 5 V,
+VBD = 3.3 V,
TA = 25°C,
Internal
Reference
13.99
13.985
13.98
−40
−20
0
20
40
60
TA − Free-Air Temperature − °C
Figure 6.
14.02
ENOB − Effective Number of Bits − Bits
fi = 50 kHz,
+VA = 5 V,
+VBD = 3.3 V,
TA = 25°C,
Internal
Reference
90.3
−20
0
20
40
60
TA − Free-Air Temperature − °C
Figure 8.
80
86.15
86.1
86.05
fi = 50 kHz,
+VA = 5 V,
+VBD = 3.3 V,
Internal
Reference
86
85.95
85.9
−40
−20
0
20
40
60
TA − Free-Air Temperature − °C
80
Figure 9.
At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and fsample = 2 MHz
(unless otherwise noted)
13
ADS8412
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SLAS384A – JUNE 2003 – REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS (continued)
SPURIOUS FREE DYNAMIC RANGE
vs
FREE-AIR TEMPERATURE
TOTAL HARMONIC DISTORTION
vs
FREE-AIR TEMPERATURE
100.5
100
−93.8
fi = 100 kHz,
+VA = 5 V,
+VBD = 3.3 V,
Internal
Reference
99.5
99
98.5
98
97.5
97
96.5
−40
−20
0
20
40
60
−94.4
−94.6
−94.8
−95
−95.2
−95.4
TA − Free-Air Temperature − °C
−95.8
−40
80
−20
0
20
40
60
TA − Free-Air Temperature − °C
Figure 10.
Figure 11.
SIGNAL-TO-NOISE RATIO
vs
INPUT FREQUENCY
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY
80
14.45
+VA = 5 V,
+VBD = 3.3 V,
TA = 25°C,
Internal
Reference
91
90.8
ENOB − Effective Number of Bits − Bits
SNR − Signal-to-Noise Ratio − dB
−94.2
−95.6
91.2
90.6
90.4
90.2
90
89.8
+VA = 5 V,
+VBD = 3.3 V,
TA = 25°C,
Internal
Reference
14.4
14.35
14.3
14.25
14.2
14.15
14.1
14.05
14
13.95
13.9
0
20
40
60
80
fi − Input Frequency − kHz
Figure 12.
14
fi = 100 kHz,
+VA = 5 V,
+VBD = 3.3 V,
Internal
Reference
−94
THD − Total Harmonic Distortion − dB
SFDR − Spurious Free Dynamic Range − dB
101
100
0
20
40
60
80
fi − Input Frequency − kHz
Figure 13.
100
ADS8412
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SLAS384A – JUNE 2003 – REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS (continued)
SIGNAL-TO-NOISE AND DISTORTION
vs
INPUT FREQUENCY
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY
103
+VA = 5 V,
+VBD = 3.3 V,
TA = 25°C,
Internal
Reference
88.5
88
SFDR − Spurious Free Dynamic Range − dB
SINAD − Signal-to-Nois and Distortion − dB
89
87.5
87
86.5
86
85.5
0
20
40
60
80
fi − Input Frequency − kHz
100
99
98
97
0
20
40
60
80
fi − Input Frequency − kHz
Figure 15.
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
SUPPLY CURRENT
vs
SAMPLE RATE
100
34
+VA = 5 V,
+VBD = 3.3 V,
TA = 25°C,
Internal
Reference
−95
33.5
ICC − Supply Current − mA
−94
THD − Total Harmonic Distortion − dB
101
Figure 14.
−93
−96
−97
−98
−99
−100
33
+VA = 5 V,
+VBD = 3.3 V,
TA = 25°C,
Internal
Referance
32.5
32
31.5
31
30.5
30
−101
−102
102
96
100
+VA = 5 V,
+VBD = 3.3 V,
TA = 25°C,
Internal
Reference
29.5
0
20
40
60
80
fi − Input Frequency − kHz
Figure 16.
100
29
500
1000
1500
Samply Rate − KSPS
2000
Figure 17.
15
ADS8412
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SLAS384A – JUNE 2003 – REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS (continued)
GAIN ERROR
vs
SUPPLY VOLTAGE (VA+)
OFFSET ERROR
vs
SUPPLY VOLTAGE (VA+)
0.6
0.14
+VBD = 3.3 V,
TA = 25°C,
External
Reference
0.12
EO − Offset Error − mV
E G − Gain Error − mV
0.5
0.4
0.3
0.2
0.1
0
4.75
0.08
0.06
0.04
+VBD = 3.3 V,
TA = 25°C,
External
Reference
0.02
4.85
4.95
5.05
5.15
VDD − Supply Voltage − V
0
4.75
5.25
4.85
4.95
5.05
5.15
5.25
VDD − Supply Voltage − V
Figure 18.
Figure 19.
INTERNAL VOLTAGE REFERENCE
vs
FREE-AIR TEMPERATURE
GAIN ERROR
vs
FREE-AIR TEMPERATURE
1
4.091
+VA = 5 V,
+VBD = 3.3 V
4.090
+VA = 5 V,
+VBD = 3.3 V,
External
Reference
0.8
0.6
E G − Gain Error − mV
Internal Voltage Reference − V
0.10
4.089
4.088
4.087
0.4
0.2
0
−0.2
−0.4
4.086
−0.6
4.085
−0.8
4.084
−40
−20
0
20
40
60
TA − Free-Air Temperature − °C
Figure 20.
16
80
−1
−40
−20
0
20
40
60
TA − Free-Air Temperature − °C
Figure 21.
80
ADS8412
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SLAS384A – JUNE 2003 – REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS (continued)
OFFSET ERROR
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
34.8
0.1
+VA = 5 V,
+VBD = 3.3 V,
External
Reference
EO − Offset Error − mV
0.06
ICC − Supply Current − mA
0.08
0.04
0.02
0
−0.02
−0.04
34.2
34
33.8
33.6
33.2
−0.08
−20
0
20
40
60
TA − Free-Air Temperature − °C
33
−40
80
−20
0
20
40
60
TA − Free-Air Temperature − °C
Figure 22.
Figure 23.
DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
1.5
80
2
Max
INL − Integral Nonlinearity − LSBs
DNL − Differential Nonlinearity − LSBs
34.4
33.4
−0.06
−0.1
−40
+VA = 5 V,
+VBD = 3.3 V
34.6
+VA = 5 V,
+VBD = 3.3 V,
Internal
Reference
1
0.5
0
−0.5
Min
−1
−1.5
−40
−20
0
20
40
60
TA − Free-Air Temperature − °C
Figure 24.
80
1.5
MAX
1
0.5
0
−0.5
MIN
−1
−1.5
−2
−40
−25
−10
5
20
35
50
65
80
TA − Free-Air Temperature − °C
Figure 25.
17
ADS8412
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SLAS384A – JUNE 2003 – REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS (continued)
4
3
DNL − LSBs
2
1
0
−1
−2
−3
−4
0
16384
32768
Code
Figure 26.
49152
65536
0
16384
32768
Code
Figure 27.
49152
65536
4
INL − LSBs
3
2
1
0
−1
−2
−3
−4
Magnitude - dB
FFT
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
0
100
200
300
400
500
600
Frequency - kHz
Figure 28.
18
700
800
900
1000
ADS8412
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SLAS384A – JUNE 2003 – REVISED DECEMBER 2004
APPLICATION INFORMATION
MICROCONTROLLER INTERFACING
ADS8412 to 8-Bit Microcontroller Interface
Figure 29 shows a parallel interface between the ADS8412 and a typical microcontroller using the 8-bit data bus.
The BUSY signal is used as a falling-edge interrupt to the microcontroller.
Analog 5 V
0.1 µF
AGND
10 µF
Ext Ref Input
0.1 µF
1 µF
Micro
Controller
-IN
REFM
AGND
+IN
+VA
REFIN
Analog Input
Digital 3 V
GPIO
CS
BYTE
GPIO
P[7:0]
ADS8412
DB[15:8]
RD
CONVST
BUSY
RD
GPIO
INT
0.1 µF
BDGND
BDGND
+VBD
Figure 29. ADS8412 Application Circuitry (using external reference)
Analog 5 V
0.1 µF
AGND
10 µF
0.1 µF
AGND
REFM
REFIN
REFOUT
+VA
1 µF
AGND
ADS8412
Figure 30. Use Internal Reference
19
ADS8412
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SLAS384A – JUNE 2003 – REVISED DECEMBER 2004
PRINCIPLES OF OPERATION
The ADS8412 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The
architecture is based on charge redistribution, which inherently includes a sample/hold function. See Figure 29
for the application circuit for the ADS8412.
The conversion clock is generated internally. The conversion time of 400 ns is capable of sustaining a 2-MHz
throughput.
The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential input
on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are
disconnected from any internal function.
REFERENCE
The ADS8412 can operate with an external reference with a range from 3.9 V to 4.2 V. A 4.096-V internal
reference is included. When internal reference is used, pin 2 (REFOUT) should be connected to pin 1 (REFIN)
with an 0.1 µF decoupling capacitor and 1 µF storage capacitor between pin 2 (REFOUT) and pins 47 and 48
(REFM) (see Figure 33). The internal reference of the converter is double buffered. If an external reference is
used, the second buffer provides isolation between the external reference and the CDAC. This buffer is also
used to recharge all of the capacitors of the CDAC during conversion. Pin 2 (REFOUT) can be left unconnected
(floating) if external reference is used.
ANALOG INPUT
When the converter enters the hold mode, the voltage difference between the +IN and -IN inputs is captured on
the internal capacitor array. Both +IN and -IN input has a range of –0.2 V to Vref + 0.2 V. The input span(+IN –
(–IN)) is limited to –Vref to Vref.
The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and source
impedance. Essentially, the current into the ADS8412 charges the internal capacitor array during the sample
period. After this capacitance has been fully charged, there is no further input current. The source of the analog
input voltage must be able to charge the input capacitance (25 pF) to an 16-bit settling level within the acquisition
time (100 ns) of the device. When the converter goes into the hold mode, the input impedance is greater than 1
GΩ.
Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the
+IN and –IN inputs and the span (+IN – (–IN)) should be within the limits specified. Outside of these ranges, the
converter's linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass
filters should be used.
Care should be taken to ensure that the output impedance of the sources driving +IN and –IN inputs are
matched. If this is not observed, the two inputs could have different setting time. This may result in offset error,
gain error and linearity error which varies with temperature and input voltage.
A typical input circuit using TI's THS4503 is shown Figure 31. Input from a single-ended source may be
converted into differential signal for ADS8412 as shown in the figure. In case the source itself is differential then
THS4503 may be used in differential input and differential output mode.
20
ADS8412
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SLAS384A – JUNE 2003 – REVISED DECEMBER 2004
PRINCIPLES OF OPERATION (continued)
68 pF
RS
RG
RT
1 kΩ
50 Ω
VCC+
+ _
20 pF
THS4503
_ +
+
_
INADS8412
IN+
OCM
VCC1 kΩ
RG, RS, and RT should be chosen such that
RG + RS || RT = 1 k Ω
VOCM = 2 V, +VCC = 7 V, and -VCC = -7 V
1 kΩ
50 Ω
68 pF
Figure 31. Using THS4503 With ADS8412
DIGITAL INTERFACE
Timing And Control
See the timing diagrams in the specifications section for detailed information on timing signals and their
requirements.
The ADS8412 uses an internal oscillator generated clock which controls the conversion rate and in turn the
throughput of the converter. No external clock input is required.
Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum
requirement has been met, the CONVST pin can be brought high), while CS is low. The ADS8412 switches from
the sample to the hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge of
this signal is important to the performance of the converter. The BUSY output is brought high after CONVST
goes low. BUSY stays high throughout the conversion process and returns low when the conversion has ended.
Sampling starts when CS is tied low or starts with the falling edge of CS when BUSY is low.
Both RD and CS can be high during and before a conversion with one exception (CS must be low when
CONVST goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the
parallel output bus with the conversion.
Reading Data
The ADS8412 outputs full parallel data in two's complement format as shown in Table 1. The parallel output is
active when CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of
CONVST. This is 50 ns prior to the falling edge of CONVST and 40 ns after the falling edge. No data read should
be attempted within this zone. Any other combination of CS and RD sets the parallel output to 3-state. BYTE is
used for multiword read operations. BYTE is used whenever lower bits of the conversion result are output on the
higher byte of the bus. Refer to Table 1 for ideal output codes.
21
ADS8412
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SLAS384A – JUNE 2003 – REVISED DECEMBER 2004
Table 1. Ideal Input Voltages and Output Codes
DESCRIPTION
DIGITAL OUTPUT – TWOS COMPLEMENT
ANALOG VALUE
BINARY CODE
HEX CODE
Full Scale Range
2(+Vref)
Least significant bit (LSB)
2(+Vref)/65536
+Full scale
(+Vref) – 1 LSB
0111 1111 1111 1111
7FFF
Midscale
0V
0000 0000 0000 0000
0000
Midscale – 1 LSB
0 V – 1 LSB
1111 1111 1111 1111
FFFF
–Full scale
(–Vref)
1000 0000 0000 0000
8000
The output data is a full 16-bit word (D15-D0) on DB15-DB0 pins (MSB-LSB) if BYTE is low.
The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB15-DB8. In this
case two reads are necessary: the first as before, leaving BYTE low and reading the 8 most significant bits on
pins DB15-DB8, then bringing BYTE high. When BYTE is high, the low bits (D7-D0) appears on pins DB15-D8.
These multiword read operations can be done with multiple active RD (toggling) or with RD tied low for simplicity.
Table 2. Conversion Data Readout
BYTE
DATA READ OUT
DB15–DB8 Pins
DB7–DB0 Pins
High
D7–D0
All one's
Low
D15–D8
D7–D0
RESET
RESET is an asynchronous active low input signal (that works independantly of CS). Minimum RESET low time
is 25 ns. Current conversion will be aborted no later than 50 ns after the converter is in the reset mode. In
addition, all output latches are cleared (set to zero's) after RESET. The converter goes back to normal operation
mode no later than 20 ns after RESET input is brought high.
The converter starts the first sampling period 20 ns after the rising edge of RESET. Any sampling period except
for the one immediately after a RESET is started with the falling edge of the previous BUSY signal or the falling
edge of CS, whichever is later.
Another way to reset the device is through the use of the combination of CS and CONVST. This is useful when
the dedicated RESET pin is tied to the system reset but there is a need to abort only the conversion in a specific
converter. Since the BUSY signal is held high during the conversion, either one of these conditions triggers an
internal self-clear reset to the converter just the same as a reset via the dedicated RESET pin. The reset does
not have to be cleared as for the dedicated RESET pin. A reset can be started with either of the two following
steps.
• Issue a CONVST when CS is low and a conversion is in progress. The falling edge of CONVST must satisfy
the timing as specified by the timing parameter tsu(AB) mentioned in the timing characteristics table to ensure
a reset. The falling edge of CONVST starts a reset. Timing is the same as a reset using the dedicated
RESET pin except the instance of the falling edge is replaced by the falling edge of CONVST.
• Issue a CS while a conversion is in progress. The falling edge of CS must satisfy the timing as specified by
the timing parameter tsu(AB) mentioned in the timing characteristics table to ensure a reset. The falling edge of
CONVST starts a reset. The falling edge of CS causes a reset. Timing is the same as a reset using the
dedicated RESET pin except the instance of the falling edge is replaced by the falling edge of CS.
POWER-ON INITIALIZATION
RESET is not required after power on. An internal power-on reset circuit generates the reset. To ensure that all
of the registers are cleared, three conversion cycles must be given to the converter after power on.
22
ADS8412
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SLAS384A – JUNE 2003 – REVISED DECEMBER 2004
LAYOUT
For optimum performance, care should be taken with the physical layout of the ADS8412 circuitry.
As the ADS8412 offers single-supply operation, it is often used in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and
the higher the switching speed, the more difficult it is to achieve good performance from the converter.
The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground
connections and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving
any single conversion for an n-bit SAR converter, there are at least n windows in which large external transient
voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby
digital logic, or high power devices.
The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the
external event.
On average, the ADS8412 draws very little current from an external reference, as the reference voltage is
internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive
the bypass capacitor or capacitors without oscillation. A 0.1-µF bypass capacitor and 1-µF storage capacitor are
recommended from pin 1 (REFIN) directly to pin 48 (REFM). REFM and AGND should be shorted on the same
ground plane under the device.
The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the
analog ground. Avoid connections which are close to the grounding point of a microcontroller or digital signal
processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal
layout consists of an analog ground plane dedicated to the converter and associated analog circuitry.
As with the AGND connections, +VA should be connected to a 5-V power supply plane or trace that is separate
from the connection for digital logic until they are connected at the power entry point. Power to the ADS8412
should be clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to the device
as possible. See Table 3 for the placement of the capacitor. In addition, a 1-µF to 10-µF capacitor is
recommended. In some situations, additional bypassing may be required, such as a 100-µF electrolytic capacitor
or even a Pi filter made up of inductors and capacitors—all designed to essentially low-pass filter the 5-V supply,
removing the high frequency noise.
Table 3. Power Supply Decoupling Capacitor Placement
POWER SUPPLY PLANE
SUPPLY PINS
CONVERTER ANALOG SIDE
CONVERTER DIGITAL SIDE
Pin pairs that require shortest path to decoupling capacitors
(4,5), (8,9), (10,11), (13,15), (43,44),
(45,46)
(24,25), (34, 35)
Pins that require no decoupling
12, 14
37
23
PACKAGE OPTION ADDENDUM
www.ti.com
27-Feb-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS8412IBPFBR
ACTIVE
TQFP
PFB
48
1000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8412I
B
ADS8412IBPFBT
ACTIVE
TQFP
PFB
48
250
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8412I
B
ADS8412IBPFBTG4
ACTIVE
TQFP
PFB
48
250
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8412I
B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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