ADS8482IBRGZRG4

Burr Brown Products from Texas Instruments ADS8482 SLAS386A – JULY 2005 – REVISED JUNE 2006 18-BIT, 1-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE, REFERENCE FEATURES • • • • • • • • • • • • • • • • • • APPLICATIONS • Medical Instruments 0 to 1-MHz Sample Rate • Optical Networking ±1.2 LSB Typ, ±2.5 LSB Max INL • Transducer Interface +0.75/-0.6 LSB Typ, +1.5/-1 LSB Max DNL • High Accuracy Data Acquisition Systems 18-Bit NMC Ensured Over Temperature • Magnetometers ±0.05-mV Offset Error ±0.05-PPM/°C Offset Error Drift DESCRIPTION ±0.035 %FSR Gain Error The ADS8482 is an 18-bit, 1-MSPS A/C converter ±0.5-PPM/°C Gain Error Drift with an internal 4.096-V reference and a 99dB SNR, -121dB THD, 123dB SFDR pseudo-bipolar, fully differential input. The device includes a 18-bit capacitor-based SAR A/D converter Zero Latency with inherent sample and hold. The ADS8482 offers Low Power: 225 mW at 1 MSPS a full 18-bit interface, a 16-bit option where data is Unipolar Differential Input Range: Vref to –Vref read using two read cycles, or an 8-bit bus option using three read cycles. Onboard Reference with 6 PPM/°C Drift Onboard Reference Buffer The ADS8482 is available in a 48-lead 7x7 QFN package and is characterized over the industrial High-Speed Parallel Interface –40°C to 85°C temperature range. Wide Digital Supply 2.7 V to 5.25 V 8-/16-/18-Bit Bus Transfer 48-Pin 7x7 QFN Package HIGH SPEED SAR CONVERTER FAMILY TYPE/SPEED 500 kHz ADS8383 ~600 kHz ADS8381 ADS8380 (s) 750 kHz 1 MHz ADS8481 1.25 MHz 2 MHz 3 MHz 4MHz 18-Bit Pseudo-Diff 18-Bit Pseudo-Bipolar, Fully Diff ADS8327 16-Bit Pseudo-Diff ADS8328 16-Bit Pseudo-Bipolar, Fully Diff ADS8406 14-Bit Pseudo-Diff 12-Bit Pseudo-Diff ADS7886 ADS7890 (s) ADS7883 ADS8413 (s) ADS7891 ADS7881 ADS8372 (s) ADS8472 ADS8405 ADS8402 ADS8410 (s) ADS8412 ADS8422 ADS8382 (s) ADS8370 (s) ADS8371 ADS8482 ADS8471 ADS8401 ADS8411 SAR +IN −IN REFIN 4.096-V Internal Reference + _ CDAC Comparator Output Latches and 3-State Drivers BYTE 16-/8-Bit Parallel DA TA Output Bus BUS 18/16 CONVST BUSY CS RD REFOUT Clock Conversion and Control Logic Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2006, Texas Instruments Incorporated ADS8482 www.ti.com SLAS386A – JULY 2005 – REVISED JUNE 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) MODEL MAXIMUM INTEGRAL LINEARITY (LSB) MAXIMUM DIFFERENTIAL LINEARITY (LSB) NO MISSING CODES RESOLUTION (BIT) PACKAGE TYPE PACKAGE DESIGNATOR TEMPER-ATURE RANGE ORDERING INFORMATION TRANS-PORT MEDIA QTY. Tape and reel 250 Tape and reel 1000 Tape and reel 250 Tape and reel 1000 ADS8482IRGZT ADS8482I ±4 –1 to +1.5 18 7x7 48 Pin QFN RGZ –40°C to 85°C ADS8482IRGZR ADS8482IBRGZT ADS8482IB ±2.5 –1 to +1.5 18 7x7 48 Pin QFN RGZ –40°C to 85°C ADS8482IBRGZR (1) For the most current specifications and package information, refer to our website at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE +IN to AGND –IN to AGND Voltage +VA to AGND +VBD to BDGND +VA to +VBD Digital input voltage to BDGND Digital output voltage to BDGND TA Tstg Operating free-air temperature range Storage temperature range Junction temperature (TJ max) QFN package Lead temperature, soldering (1) Power dissipation θJA thermal impedance Vapor phase (60 sec) Infrared (15 sec) –0.4 to +VA + 0.1 –0.4 to +VA + 0.1 –0.3 to 7 –0.3 to 7 –0.3 to 2.55 –0.3 to +VBD + 0.3 –0.3 to +VBD + 0.3 –40 to 85 –65 to 150 150 (TJMax – TA)/θJA 22 215 220 °C/W °C °C UNIT V V V V V V V °C °C °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 Submit Documentation Feedback ADS8482 www.ti.com SLAS386A – JULY 2005 – REVISED JUNE 2006 SPECIFICATIONS TA = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1 MSPS (unless otherwise noted) PARAMETER ANALOG INPUT Full-scale input voltage (1) Absolute input voltage Common-mode input range Input capacitance Input leakage current SYSTEM PERFORMANCE Resolution No missing codes (2) TEST CONDITIONS MIN TYP MAX UNIT +IN – (–IN) +IN –IN –Vref –0.2 –0.2 (Vref)/2 – 0.2 (Vref)/2 65 1 Vref Vref + 0.2 Vref + 0.2 (Vref)/2 + 0.2 V V V pF nA 18 ADS8482I ADS8482IB ADS8482I ADS8482IB ADS8482I ADS8482IB ADS8482I ADS8482IB ADS8482I ADS8482IB ADS8482I ADS8482IB ADS8482I ADS8482IB At dc (±0.2 V around Vref/2) +IN – (–IN) = 1 Vpp at 1 MHz Vref = 4.096 V Vref = 4.096 V –0.1 –0.1 18 18 –4 –2.5 –1 –1 –0.5 –0.5 ±1.2 ±1.2 –0.6/0.75 –0.6/0.75 ±0.05 ±0.05 ±0.05 ±0.05 ±0.035 ±0.035 ±0.5 ±0.5 60 55 25 At 1FFFFh output code 60 0.1 0.1 4 2.5 1.5 1.5 0.5 0.5 Bits Bits LSB (18 bit) (3) LSB (18 bit) mV ppm/°C %FS %FS ppm/°C dB µV RMS dB Integral linearity Differential linearity Offset error (4) Offset error temperature drift Gain error (4) (5) Gain error temperature drift Common-mode rejection ratio Noise Power supply rejection ratio SAMPLING DYNAMICS Conversion time Acquisition time Throughput rate Aperture delay Aperture jitter Step response Over voltage recovery 625 320 350 650 ns ns 1 4 5 150 150 MHz ns ps ns ns (1) (2) (3) (4) (5) Ideal input span, does not include gain or offset error. This is endpoint INL, not best fit. LSB means least significant bit Measured relative to an ideal full-scale input [+IN – (–IN)] of 8.192 V This specification does not include the internal reference voltage error and drift. Submit Documentation Feedback 3 ADS8482 www.ti.com SLAS386A – JULY 2005 – REVISED JUNE 2006 SPECIFICATIONS (Continued) TA = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1 MSPS (unless otherwise noted) PARAMETER DYNAMIC CHARACTERISTICS ADS8482I ADS8482IB Total harmonic distortion (THD) (1) ADS8482I ADS8482IB ADS8482I ADS8482IB ADS8482I ADS8482IB Signal to noise ratio (SNR) (1) ADS8482I ADS8482IB ADS8482I ADS8482IB ADS8482I ADS8482IB Signal to noise + distortion (SINAD) (1) ADS8482I ADS8482IB ADS8482I ADS8482IB ADS8482I ADS8482IB Spurious free dynamic range (SFDR) (1) ADS8482I ADS8482IB ADS8482I ADS8482IB –3dB Small signal bandwidth VIN = 8 Vpp at 2 kHz VIN = 8 Vpp at 20 kHz VIN = 8 Vpp at 100 kHz VIN = 8 Vpp at 2 kHz VIN = 8 Vpp at 20 kHz VIN = 8 Vpp at 100 kHz VIN = 8 Vpp at 2 kHz VIN = 8 Vpp at 20 kHz VIN = 8 Vpp at 100 kHz VIN = 8 Vpp at 2 kHz VIN = 8 Vpp at 20 kHz VIN = 8 Vpp at 100 kHz 96 97.5 96 97.5 –120 –121 –105 –110 –100 –103 98.6 99 98 98.5 95 97 98.5 99 97 98 93 95 120 123 107 113 102 105 15 MHz dB dB dB dB TEST CONDITIONS MIN TYP MAX UNIT (1) Calculated on the first nine harmonics of the input frequency. 4 Submit Documentation Feedback ADS8482 www.ti.com SLAS386A – JULY 2005 – REVISED JUNE 2006 SPECIFICATIONS (Continued) TA = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1 MSPS (unless otherwise noted) PARAMETER VOLTAGE REFERENCE INPUT Reference voltage at REFIN, Vref Reference resistance (1) Reference current drain INTERNAL REFERENCE OUTPUT Internal reference start-up time Reference voltage range, Vref Source current Line regulation Drift DIGITAL INPUT/OUTPUT Logic family –CMOS VIH Logic level VIL VOH VOL Data format – Straight Binary POWER SUPPLY REQUIREMENTS Power supply voltage Supply current (2) Power dissipation (2) TEMPERATURE RANGE Operating free-air –40 85 °C +VBD +VA fs = 1 MHz fs = 1 MHz 2.7 4.75 3.3 5 45 225 5.25 5.25 50 250 V V mA mW IIH = 5 µA IIL = 5 µA IOH = 2 TTL loads IOL = 2 TTL loads +VBD – 1 –0.3 +VBD – 0.6 +VBD + 0.3 0.8 V From 95% (+VA), with 1-µF storage capacitor IO = 0 Static load +VA = 4.75 V ~ 5.25 V IO = 0 60 ±6 4.081 4.096 120 4.111 10 ms V µA µV PPM/°C fs = 1 MHz 3.0 4.096 500 1 +VA – 0.8 V kΩ mA TEST CONDITIONS MIN TYP MAX UNIT (1) (2) Can vary ±20% This includes only +VA current. +VBD current is typical 1 mA with 5 pF load capacitance on all output pins. Submit Documentation Feedback 5 ADS8482 www.ti.com SLAS386A – JULY 2005 – REVISED JUNE 2006 TIMING CHARACTERISTICS All specifications typical at –40°C to 85°C, +VA =+VBD = 5 V PARAMETER t(CONV) t(ACQ) t(HOLD) tpd1 tpd2 tpd3 tw1 tsu1 tw2 tw3 tw4 th1 td1 tsu2 tw5 ten td2 td3 tw6 tw7 th2 tpd4 td4 tsu3 th3 tdis td5 td6 td7 tsu5 Conversion time Acquisition time Sample capacitor hold time CONVST low to BUSY high Propagation delay time, end of conversion to BUSY low Propagation delay time, start of convert state to rising edge of BUSY Pulse duration, CONVST low Setup time, CS low to CONVST low Pulse duration, CONVST high CONVST falling edge jitter Pulse duration, BUSY signal low Pulse duration, BUSY signal high Hold time, first data bus transition (RD low, or CS low for read cycle, or BYTE or BUS18/16 input changes) after CONVST low Delay time, CS low to RD low Setup time, RD high to CS high Pulse duration, RD low Enable time, RD low (or CS low for read cycle) to data valid Delay time, data hold from RD high Delay time, BUS18/16 or BYTE rising edge or falling edge to data valid Pulse duration, RD high Pulse duration, CS high Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edge Delay time, BYTE edge to BUS18/16 edge skew Setup time, BYTE or BUS18/16 transition to RD falling edge Hold time, BYTE or BUS18/16 transition to RD falling edge Disable time, RD high (CS high for read cycle) to 3-stated data bus Delay time, BUSY low to MSB data valid delay Delay time, CS rising edge to BUSY falling edge Delay time, BUSY falling edge to CS rising edge BYTE transition setup time, from BYTE transition to next BYTE transition, or BUS18/16 transition setup time, from BUS18/16 to next BUS18/16. 50 50 50 60 550 5 10 20 20 50 0 0 10 10 20 0 20 40 0 0 50 20 t(ACQ)min 650 40 20 20 10 320 25 40 15 15 (1) (2) (3) MIN TYP MAX 650 UNIT ns ns ns ns ns ns ns ns ns ps ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tsu(ABORT) Setup time from the falling edge of CONVST (used to start the valid conversion) to the next falling edge of CONVST (when CS = 0 and CONVST are used to abort) or to the next falling edge of CS (when CS is used to abort). (1) (2) (3) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2. See timing diagrams. All timing are measured with 20 pF equivalent loads on all data bits and BUSY pins. 6 Submit Documentation Feedback ADS8482 www.ti.com SLAS386A – JULY 2005 – REVISED JUNE 2006 TIMING CHARACTERISTICS All specifications typical at –40°C to 85°C, +VA = 5 V +VBD = 3 V PARAMETER t(CONV) t(ACQ) t(HOLD) tpd1 tpd2 tpd3 tw1 tsu1 tw2 tw3 tw4 th1 td1 tsu2 tw5 ten td2 td3 tw6 tw7 th2 tpd4 td4 tsu3 th3 tdis td5 td6 td7 tsu5 Conversion time Acquisition time Sample capacitor hold time CONVST low to BUSY high Propagation delay time, end of conversion to BUSY low Propagation delay time, start of convert state to rising edge of BUSY Pulse duration, CONVST low Setup time, CS low to CONVST low Pulse duration, CONVST high CONVST falling edge jitter Pulse duration, BUSY signal low Pulse duration, BUSY signal high Hold time, first data bus transition (RD low, or CS low for read cycle, or BYTE or BUS18/16 input changes) after CONVST low Delay time, CS low to RD low Setup time, RD high to CS high Pulse duration, RD low Enable time, RD low (or CS low for read cycle) to data valid Delay time, data hold from RD high Delay time, BUS18/16 or BYTE rising edge or falling edge to data valid Pulse duration, RD high Pulse duration, CS high Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edge Delay time, BYTE edge to BUS18/16 edge skew Setup time, BYTE or BUS18/16 transition to RD falling edge Hold time, BYTE or BUS18/16 transition to RD falling edge Disable time, RD high (CS high for read cycle) to 3-stated data bus Delay time, BUSY low to MSB data valid delay Delay time, CS rising edge to BUSY falling edge Delay time, BUSY falling edge to CS rising edge BYTE transition setup time, from BYTE transition to next BYTE transition, or BUS18/16 transition setup time, from BUS18/16 to next BUS18/16. 50 50 50 70 550 5 10 20 20 50 0 0 10 10 30 0 30 40 0 0 50 30 t(ACQ)min 650 40 20 20 10 310 25 40 25 25 (1) (2) (3) MIN TYP MAX 650 UNIT ns ns ns ns ns ns ns ns ns ps ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tsu(ABORT) Setup time from the falling edge of CONVST (used to start the valid conversion) to the next falling edge of CONVST (when CS = 0 and CONVST are used to abort) or to the next falling edge of CS (when CS is used to abort). (1) (2) (3) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2. See timing diagrams. All timing are measured with 20 pF equivalent loads on all data bits and BUSY pins. Submit Documentation Feedback 7 ADS8482 www.ti.com SLAS386A – JULY 2005 – REVISED JUNE 2006 PIN ASSIGNMENTS RGZ PACKAGE (TOP VIEW) +VBD BUS18/16 BYTE CONVST RD CS +VA AGND AGND +VA REFM REFM 48 47 46 45 44 43 42 41 40 39 38 37 36 1 35 2 3 34 4 33 5 32 31 6 30 7 29 8 28 9 27 10 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 REFOUT REFIN AGND +VA +VA AGND AGND AGND NC +VA +IN −IN BUSY DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 BDGND +VBD DB10 DB11 DB12 DB13 DB14 DB15 DB16 DB17 AGND AGND +VA NC − No internal connection NOTE: The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. TERMINAL FUNCTIONS NAME AGND BDGND BUSY NO 8, 9, 17, 20, 23, 24, 26, 27 37 48 I/O – – O Analog ground Digital ground for bus interface digital supply Status output. High when a conversion is in progress. Bus size select input. Used for selecting 18-bit or 16-bit wide bus transfer. 0: Data bits output on the 18-bit data bus pins DB[17:0]. 1: Last two data bits D[1:0] from 18-bit wide bus output on: a) the low byte pins DB[9:2] if BYTE = 0 b) the high byte pins DB[17:10] if BYTE = 1 Byte select input. Used for 8-bit bus reading. 0: No fold back 1: Low byte D[9:2] of the 16 most significant bits is folded back to high byte of the 16 most significant pins DB[17:10]. Convert start. The falling edge of this input ends the acquisition period and starts the hold period. Chip select. The falling edge of this input starts the acquisition period. 8-BIT BUS Data Bus BYTE = 0 BUS18/16 = 0 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 28 29 30 31 32 33 34 35 38 O O O O O O O O O D17 (MSB) D16 D15 D14 D13 D12 D11 D10 D9 BYTE = 1 BUS18/16 = 0 D9 D8 D7 D6 D5 D4 D3 D2 All ones BYTE = 1 BUS18/16 = 1 All ones All ones All ones All ones All ones All ones D1 D0 (LSB) All ones 16-BIT BUS BYTE = 0 BUS18/16 = 0 D17 (MSB) D16 D15 D14 D13 D12 D11 D10 D9 BYTE = 0 BUS18/16 = 1 All ones All ones All ones All ones All ones All ones All ones All ones All ones 18-BIT BUS BYTE = 0 BUS18/16 = 0 D17 (MSB) D16 D15 D14 D13 D12 D11 D10 D9 DESCRIPTION BUS18/16 2 I BYTE CONVST CS 3 4 6 I I I 8 Submit Documentation Feedback ADS8482 www.ti.com SLAS386A – JULY 2005 – REVISED JUNE 2006 TERMINAL FUNCTIONS (continued) NAME DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 –IN +IN NC REFIN REFOUT REFM RD +VA +VBD NO 39 40 41 42 43 44 45 46 47 19 18 15 13 14 11, 12 5 7, 10, 16, 21, 22, 25 1, 36 I O I I – – I/O O O O O O O O O O I I D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) All ones All ones All ones All ones All ones All ones All ones All ones All ones All ones All ones All ones All ones All ones All ones All ones All ones All ones DESCRIPTION D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) All ones All ones All ones All ones All ones D1 D0 (LSB) All ones All ones D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) Inverting input channel Noninverting input channel No connection Reference input Reference output. Add 1-µF capacitor between the REFOUT pin and REFM pin when internal reference is used. Reference ground Synchronization pulse for the parallel output. When CS is low, this serves as output enable and puts the previous conversion results on the bus. Analog power supplies, 5-V DC Digital power supply for bus TYPICAL CHARACTERISTICS DC HISTOGRAM (8192 Conversion Outputs) 4000 3500 3000 +VA = 5 V, +VBD = 5 V, TA = 25C, fi = 1 MSPS, Vref = 4.096 V, Input = Midscale 3615 INTERNAL REFERENCE VOLTAGE vs FREE-AIR TEMPERATURE 4.098 4.0975 +VA = 5 V, +VBD = 5 V Reference Voltage - V INTERNAL REFERENCE VOLTAGE vs SUPPLY VOLTAGE 4.0972 TA = 25°C 4.09719 4.09718 4.09717 4.09716 4.09715 4.09714 4.09713 4.75 Reference Voltage - V 481 36 1 0 Frequency 2500 2000 1474 2383 4.097 4.0965 1500 1000 500 0 6 196 4.096 4.0955 4.095 -40 0 -4 -3 -2 -1 0 1 2 Output Code 3 4 5 -25 -10 5 20 35 50 65 80 4.85 TA - Free-Air Temperature - °C 4.95 5.05 5.15 Supply Voltage - V 5.25 Figure 1. Figure 2. Figure 3. Submit Documentation Feedback 9 ADS8482 www.ti.com SLAS386A – JULY 2005 – REVISED JUNE 2006 TYPICAL CHARACTERISTICS (continued) SUPPLY CURRENT vs FREE-AIR TEMPERATURE 46 46 SUPPLY CURRENT vs SUPPLY VOLTAGE 46 SUPPLY CURRENT vs SAMPLE RATE +VA = 5 V, +VBD = 5 V, TA = 25°C, Vref = 4.096 V 45.6 Supply Current - mA Supply Current - mA Supply Current - mA +VA = 5 V, +VBD = 5 V, fi = 1 MSPS, Vref = 4.096 V 45.6 TA = 25C, fi = 1 MSPS, Vref = 4.096 V 45 44 43 42 41 40 45.2 45.2 44.8 44.8 44.4 44.4 44 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 80 44 4.75 4.85 4.95 5.05 Supply Voltage - V 5.15 5.25 39 250 750 500 Sample Rate - KSPS 1000 Figure 4. DIFFERENTIAL NONLINEARITY vs FREE-AIR TEMPERATURE 1.50 Figure 5. INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE 2.5 2 1.5 Max 1.50 Figure 6. DIFFERENTIAL NONLINEARITY vs SUPPLY VOLTAGE 1 +VA = 5 V, +VBD = 5 V, fi = 1 MSPS, Vref = 4.096 V Max INL - LSBs 1 0.5 0 -0.5 1 Max DNL - LSBs 0.50 DNL - LSBs 0 +VA = 5 V, +VBD = 5 V, fi = 1 MSPS, Vref = 4.096 V Min 0.50 0 Min -0.50 -1 -1.5 -2 +VA = 5 V, +VBD = 5 V, TA = 25°C, fi = 1 MSPS, Vref = 4.096 V, Min -0.50 -1 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 80 -2.5 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 80 -1 4.75 4.95 5.15 Supply Voltage - V Figure 7. INTEGRAL NONLINEARITY vs SUPPLY VOLTAGE 2.50 2 1.50 1 Max 1.50 Figure 8. DIFFERENTIAL NONLINEARITY vs REFERENCE VOLTAGE 2.50 2 1.50 Max 1 Figure 9. INTEGRAL NONLINEARITY vs REFERENCE VOLTAGE VDD = 5 V, TA = 25°C, 1 f = 1 MSPS i DNL - LSBs INL - LSBs Max INL - LSBs 0.50 0 -0.50 -1 -1.50 -2 -2.50 4.75 +VA = 5 V, +VBD = 5 V, TA = 25°C, fi = 1 MSPS, Vref = 4.096 V, Min 0.50 0.50 0 -0.50 -1 VDD = 5 V, TA = 25°C, fi = 1 MSPS Min 0 Min -0.50 -1.50 -2 4.85 4.95 5.05 5.15 Supply Voltage - V 5.25 -1 3 -2.50 3.2 3.4 3.6 3.8 4.2 4 3 3.2 Reference Voltage - V 3.4 3.6 3.8 4 Reference Voltage - V 4.2 Figure 10. Figure 11. Figure 12. 10 Submit Documentation Feedback ADS8482 www.ti.com SLAS386A – JULY 2005 – REVISED JUNE 2006 TYPICAL CHARACTERISTICS (continued) OFFSET ERROR vs FREE-AIR TEMPERATURE 0 -0.01 -0.02 -0.03 0 OFFSET ERROR vs SUPPLY VOLTAGE 0 -0.01 -0.02 OFFSET ERROR vs REFERENCE VOLTAGE -0.01 -0.02 +VA = 5 V, +VBD = 5 V, fi = 1 MSPS, Vref = 4.096 V Offset Error - mV TA = 25°C, fi = 1 MSPS, Vref = 4.096 V Offset Error - mV VDD = 5 V, TA = 25°C, fi = 1 MSPS Offset Error - mV -0.03 -0.04 -0.05 -0.06 -0.07 -0.08 -0.09 -0.03 -0.04 -0.05 -0.06 -0.07 -0.08 -0.09 -0.1 -0.04 -0.05 -0.06 -0.07 -0.08 -0.09 -0.1 -40 -25 -10 5 20 35 50 65 80 TA - Free-Air Temperature - °C -0.1 4.75 4.85 4.95 5.05 5.15 Supply Voltage - V 5.25 3 3.2 3.4 3.6 3.8 Reference Voltage - V 4 4.2 Figure 13. GAIN ERROR vs SUPPLY VOLTAGE -0.01 -0.02 -0.02 Figure 14. GAIN ERROR vs FREE-AIR TEMPERATURE -0.025 -0.03 Figure 15. GAIN ERROR vs REFERENCE VOLTAGE 0.1 0.08 0.06 VDD = 5 V, TA = 25°C, fi = 1 MSPS Gain Error - %FS TA = 25°C, fi = 1 MSPS, Vref = 4.096 +VA = 5 V, +VBD = 5 V, fi = 1 MSPS, Vref = 4.096 V Gain Error - %FS Gain Error - %FS -0.03 -0.04 -0.05 -0.06 -0.07 -0.035 -0.04 -0.045 -0.05 -0.055 -0.06 -0.065 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.1 -0.08 4.75 4.85 4.95 5.05 5.15 Supply Voltage - V 5.25 -0.07 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 80 3 3.2 3.4 3.6 3.8 4 4.2 Reference Voltage - V Figure 16. Figure 17. Figure 18. TOTAL HARMONIC DISTORTION vs REFERENCE VOLTAGE -119 OFFSET ERROR TEMPERATURE DRIFT DISTRIBUTION (35 Samples) 14 GAIN ERROR TEMPERATURE DRIFT DISTRIBUTION (35 Samples) 10 9 +VA = 5 V, +VBD = 5 V, 12 fi = 1 MSPS, Vref = 4.096 V 10 Frequency 8 6 13 11 9 8 7 8 7 +VA = 5 V, +VBD = 5 V, fi = 1 MSPS, Vref = 4.096 V 6 -120 +VA = 5 V, +VBD = 5 V, fs = 1 MSPS, TA = 25°C, fi = 2 kHz Frequency THD - dB 6 5 -121 4 4 3 4 4 2 0 4 3 -122 2 1 0 0.01 0.03 0.04 0.05 0.07 Offset Drift - ppm/C 0.08 1 0 0.03 0.19 0.35 0.50 0.66 Gain Error Drift - ppm/C 0.90 -123 3 3.2 3.4 3.6 3.8 4 Vref - Reference Voltage - V 4.2 Figure 19. Figure 20. Figure 21. Submit Documentation Feedback 11 ADS8482 www.ti.com SLAS386A – JULY 2005 – REVISED JUNE 2006 TYPICAL CHARACTERISTICS (continued) SIGNAL-TO-NOISE RATIO vs REFERENCE VOLTAGE SINAD - Signal-to-noise + Distortion - dB 99.5 SIGNAL-TO-NOISE + DISTORTION vs REFERENCE VOLTAGE 99.5 TOTAL HARMONIC DISTORTION vs FREE-AIR TEMPERATURE -115 THD - Total Harmonic Distortion - dB SNR- Signal-to-Noise Ratio - dB 99 98.5 +VA = 5 V, +VBD = 5 V, fs = 1 MSPS, TA = 25°C, fi = 2 kHz 99 98.5 +VA = 5 V, +VBD = 5 V, fs = 1 MSPS, TA = 25°C, fi = 2 kHz -116 -117 -118 -119 -120 -121 +VA = 5 V, +VBD = 5 V, fs = 1 MSPS, Vref = 4.096 V, fi = 2 kHz 98 98 97.5 97.5 97 96.5 3 3.2 3.4 3.6 3.8 4 Vref - Reference Voltage - V 4.2 97 96.5 3 3.2 3.4 3.6 3.8 4 Vref - Reference Voltage - V 4.2 -122 -40 -25 -10 5 20 35 50 65 80 TA - Free-Air Temperature - °C Figure 22. SPURIOUS FREE DYNAMIC RANGE vs FREE-AIR TEMPERATURE SFDR - Spurious Free Dynamic Range - dB 123.5 98.9 123 122.5 122 121.5 121 120.5 120 119.5 119 118.5 -40 -25 -10 5 20 35 50 65 80 Figure 23. SIGNAL-TO-NOISE RATIO vs FREE-AIR TEMPERATURE SINAD - Signal-to-Noise + Distortion - dB Figure 24. SIGNAL-TO-NOISE + DISTORTION vs FREE-AIR TEMPERATURE 98.9 SNR - Signal-to-Noise Ratio - dB +VA = 5 V, +VBD = 5 V, fs = 1 MSPS, Vref = 4.096 V, fi = 2 kHz 98.8 98.7 98.6 98.5 98.4 98.3 98.2 98.1 -40 +VA = 5 V, +VBD = 5 V, fs = 1 MSPS, Vref = 4.096 V, fi = 2 kHz 98.8 98.7 98.6 98.5 98.4 98.3 98.2 +VA = 5 V, +VBD = 5 V, fs = 1 MSPS, Vref = 4.096 V, fi = 2 kHz TA - Free-Air Temperature - °C -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 80 98.1 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 80 Figure 25. Figure 26. DNL Figure 27. 1.5 1 +VA = 5 V, +VBD = 5 V, TA = 25C, fi = 1 MSPS, Vref = 4.096 V DNL - LSBs 0.5 0 -0.5 -1 -1.5 -131072 -65536 0 Output Code 65536 131072 Figure 28. 12 Submit Documentation Feedback ADS8482 www.ti.com SLAS386A – JULY 2005 – REVISED JUNE 2006 TYPICAL CHARACTERISTICS (continued) INL 2.5 2 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 -131072 +VA = 5 V, +VBD = 5 V, TA = 25C, fi = 1 MSPS, Vref = 4.096 V INL - LSBs -65536 0 Output Code 65536 131072 Figure 29. Submit Documentation Feedback 13 ADS8482 www.ti.com SLAS386A – JULY 2005 – REVISED JUNE 2006 TIMING DIAGRAMS tw1 CONVST tpd1 BUSY tsu1 CS tpd3 CONVERT† t(CONV) t(HOLD) SAMPLING† (When CS Toggle) t(ACQ) tsu(ABORT) BYTE th1 BUS 18/16 tpd4 RD td1 tsu5 tsu2 th2 tsu5 tsu(ABORT) t(CONV) td7 td6 tpd2 tw3 tw7 tw2 tw4 ten DB[17:12] Hi−Z D[17:12] D[9:4] tdis Hi−Z MSB Hi−Z Hi−Z DB[11:10] D[11:10] D[3:2] D[1:0] DB[9:0] †Signal Hi−Z D[9:0] Hi−Z internal to device Figure 30. Timing for Conversion and Acquisition Cycles With CS and RD Toggling 14 Submit Documentation Feedback ADS8482 www.ti.com SLAS386A – JULY 2005 – REVISED JUNE 2006 tw1 CONVST tpd1 BUSY tsu1 CS tpd3 CONVERT† t(CONV) t(HOLD) SAMPLING† (When CS Toggle) tpd2 tw2 tw4 tw3 tw7 td7 td6 t(CONV) t(ACQ) tsu(ABORT) BYTE th1 BUS 18/16 tpd4 tsu5 tsu(ABORT) th2 RD = 0 ten DB[17:12] Previous Hi−Z D[17:12] tdis Hi−Z ten MSB D[17:12] D[9:4] tdis ten Hi−Z Repeated D[17:12] DB[11:10] Hi−Z Previous D[11:10] Hi−Z D[11:10] D[3:2] D[1:0] Hi−Z Repeated D[11:10] DB[9:0] †Signal Hi−Z Previous D [9:0] Hi−Z D[9:0] Hi−Z Repeated D [9:0] internal to device Figure 31. Timing for Conversion and Acquisition Cycles With CS Toggling, RD Tied to BDGND Submit Documentation Feedback 15 ADS8482 www.ti.com SLAS386A – JULY 2005 – REVISED JUNE 2006 tw1 CONVST tpd1 BUSY tpd2 tw2 tw4 tw3 CS = 0 CONVERT† t(CONV) t(HOLD) t(CONV) SAMPLING† (When CS = 0) tsu(ABORT) BYTE th1 BUS 18/16 tpd4 RD ten t(ACQ) tsu(ABORT) tsu5 tsu5 th2 tdis MSB D[17:12] D[9:4] DB[17:12] Hi−Z Hi−Z DB[11:10] Hi−Z D[11:10] D[3:2] D[1:0] Hi−Z DB[9:0] Hi−Z D[9:0] Hi−Z †Signal internal to device Figure 32. Timing for Conversion and Acquisition Cycles With CS Tied to BDGND, RD Toggling 16 Submit Documentation Feedback ADS8482 www.ti.com SLAS386A – JULY 2005 – REVISED JUNE 2006 tw1 CONVST tpd1 BUSY tw4 tpd2 tw2 tw3 CS = 0 CONVERT† tpd3 t(HOLD) t(CONV) tpd3 t(HOLD) t(ACQ) t(CONV) SAMPLING† (When CS = 0) tsu(ABORT) BYTE tsu5 BUS 18/16 tsu5 th1 RD = 0 td5 DB[17:12] D[17:12] D[9:4] tsu(ABORT) tsu5 tsu5 th1 Next D[17:12] DB[11:10] Previous LSB D[11:10] D[3:2] D[1:0] Next D[11:10] DB[9:0] †Signal D[9:0] Next D[9:0] internal to device Figure 33. Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGND - Auto Read Submit Documentation Feedback 17 ADS8482 www.ti.com SLAS386A – JULY 2005 – REVISED JUNE 2006 CS RD BYTE tsu5 BUS 18/16 ten ten Hi−Z Valid tdis Hi−Z td3 Valid td3 tdis Hi−Z DB[17:0] Valid Figure 34. Detailed Timing for Read Cycles 18 Submit Documentation Feedback ADS8482 www.ti.com SLAS386A – JULY 2005 – REVISED JUNE 2006 APPLICATION INFORMATION MICROCONTROLLER INTERFACING ADS8482 to 8-Bit Microcontroller Interface Figure 35 shows a parallel interface between the ADS8482 and a typical microcontroller using the 8-bit data bus. The BUSY signal is used as a falling-edge interrupt to the microcontroller. Analog 5 V 0.1 µF AGND 10 µF 0.1 µF Ext Ref Input Analog Input +VA REFIN REFM AGND +IN −IN Micro Controller GPIO GPIO GPIO GPIO RD AD[7:0] Digital 3 V CS AD8482 BYTE BUS18/16 CONVST RD DB[17:10] 0.1 µF BDGND BDGND +VBD Data Bus D[17:0] Figure 35. ADS8482 Application Circuitry Analog 5 V 0.1 µF 10 µF AGND 0.1 µF 1 µF REFOUT REFM +VA REFIN AGND AGND ADS8482 Figure 36. ADS8482 Using Internal Reference Submit Documentation Feedback 19 ADS8482 www.ti.com SLAS386A – JULY 2005 – REVISED JUNE 2006 PRINCIPLES OF OPERATION The ADS8482 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The architecture is based on charge redistribution which inherently includes a sample/hold function. See Figure 35 for the application circuit for the ADS8482. The conversion clock is generated internally. The conversion time of 650 ns is capable of sustaining a 1 MHz throughput. The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function. REFERENCE The ADS8482 can operate with an external reference with a range from 3.0 V to 4.2 V. The reference voltage on the input pin #13 (REFIN) of the converter is internally buffered. A clean, low noise, well-decoupled reference voltage on this pin is required to ensure good performance of the converter. A low noise band-gap reference like the REF3240 can be used to drive this pin. A 0.1-µF decoupling capacitor is required between REFIN and REFM pins (pin #13 and pin #12) of the converter. This capacitor should be placed as close as possible to the pins of the device. Designers should strive to minimize the routing length of the traces that connect the terminals of the capacitor to the pins of the converter. An RC network can also be used to filter the reference voltage. A 100-Ω series resistor and a 0.1-µF capacitor, which can also serve as the decoupling capacitor can be used to filter the reference voltage. REFM 0.1 mF 100 W REF3240 REFIN ADS8482 Figure 37. ADS8482 Using External Reference The ADS8482 also has limited low pass filtering capability built into the converter. The equivalent circuitry on the REFIN input ia as shown in Figure 38. 10 kW REFIN + _ 300 pF REFM To CDAC 830 pF To CDAC Figure 38. Simplified Reference Input Circuit The REFM input of the ADS8482 should always be shorted to AGND. A 4.096-V internal reference is included. When internal reference is used, pin 14 (REFOUT) is connected to pin 13 (REFIN) with an 0.1-µF decoupling capacitor and 1-µF storage capacitor between pin 14 (REFOUT) and pins 11 and 12 (REFM) (see Figure 36). The internal reference of the converter is double buffered. If an external reference is used, the second buffer provides isolation between the external reference and the CDAC. This buffer is also used to recharge all of the capacitors of the CDAC during conversion. Pin 14 (REFOUT) can be left unconnected (floating) if external reference is used. 20 Submit Documentation Feedback ADS8482 www.ti.com SLAS386A – JULY 2005 – REVISED JUNE 2006 PRINCIPLES OF OPERATION (continued) ANALOG INPUT When the converter enters the hold mode, the voltage difference between the +IN and –IN inputs is captured on the internal capacitor array. Both +IN and –IN input has a range of –0.2 V to Vref + 0.2 V. The input span [+IN – (–IN)] is limited to –Vref to Vref. The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and source impedance. Essentially, the current into the ADS8482 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input must be able to charge the input capacitance (65 pF) to an 18-bit settling level within the acquisition time (320 ns) of the device. When the converter goes into the hold mode, the input impedance is greater than 1 GΩ. Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the +IN and –IN inputs and the span [+IN – (–IN)] must be within the limits specified. Outside of these ranges, the converter's linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass filters are used. Care must be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are matched. If this is not observed, the two inputs could have different setting times. This may result in offset error, gain error, and linearity error which varies with temperature and input voltage. The analog input to the converter needs to be driven with a low noise, high-speed op-amp like the THS4031. An RC filter is recommended at the input pins to low-pass filter the noise from the source. The input to the converter is a uni-polar input voltage in the range 0 to Vref. The THS4031 can be used in the source follower configuration to drive the converter. Submit Documentation Feedback 21 ADS8482 www.ti.com SLAS386A – JULY 2005 – REVISED JUNE 2006 PRINCIPLES OF OPERATION (continued) +12 V 1 mF R +VIN +0V to +4V C THS4031 5W (+)IN 1 mF 1 mF -12 V 75 W 2200 pF 300 W +12 V 1 mF 300 W 5W THS4031 +2.048 V 1 mF 1 mF (-)IN -12 V Figure 39. Single-Ended Input, Differential Output Configuration In systems, where the input is differential, the THS4031 can be used in the inverting configuration with an additional DC bias applied to its + input so as to keep the input to the ADS8482 within its rated operating voltage range. The DC bias can be derived from the REF3220 or the REF3240 reference voltage ICs. The input configuration shown below is capable of delivering better than 97dB SNR and -103db THD at an input frequency of 100 kHz. In case band-pass filters are used to filter the input, care should be taken to ensure that the signal swing at the input of the band-pass filter is small so as to keep the distortion introduced by the filter minimal. In such cases, the gain of the circuit shown below can be increased to keep the input to the ADS8482 large to keep the SNR of the system high. Note that the gain of the system from the + input to the output of the THS4031 in such a configuration is a function of the gain of the AC signal. A resistor divider can be used to scale the output of the REF3220 or REF3240 to reduce the voltage at the DC input to THS4031 to keep the voltage at the input of the converter within its rated operating range. 22 Submit Documentation Feedback ADS8482 www.ti.com SLAS386A – JULY 2005 – REVISED JUNE 2006 PRINCIPLES OF OPERATION (continued) +12 V 1 mF +2.048 V 300 W +VIN 1 mF THS4031 12 W (+)IN 1 mF AP Cascade Two System -12V 2200 pF 300 W 300 W AP Cascade Two System Pattern Generator Platform fi = 1 kHz SNR: 99 dB SINAD: 99 dB THD: -121 dB SFDR: 123 dB ENOB(SINAD): 16.15 -VIN +12V 1 mF 300 W 12 W THS4031 (-)IN +2.048 V 1 mF 1 mF -12 V Figure 40. Differential Input, Differential Output Configuration DIGITAL INTERFACE Timing and Control See the timing diagrams in the specifications section for detailed information on timing signals and their requirements. The ADS8482 uses an internal oscillator generated clock which controls the conversion rate and in turn the throughput of the converter. No external clock input is required. Submit Documentation Feedback 23 ADS8482 www.ti.com SLAS386A – JULY 2005 – REVISED JUNE 2006 PRINCIPLES OF OPERATION (continued) Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum requirement has been met, the CONVST pin can be brought high), while CS is low. The ADS8482 switches from the sample to the hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge of this signal is important to the performance of the converter. The BUSY output is brought high immediately following CONVST going low. BUSY stays high throughout the conversion process and returns low when the conversion has ended. Sampling starts with the falling edge of the BUSY signal when CS is tied low or starts with the falling edge of CS when BUSY is low. Both RD and CS can be high during and before a conversion with one exception (CS must be low when CONVST goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the parallel output bus with the conversion. Reading Data The ADS8482 outputs full parallel data in straight binary format as shown in Table 1. The parallel output is active when CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of CONVST. This is 50 ns prior to the falling edge of CONVST and 40 ns after the falling edge. No data read should attempted within this zone. Any other combination of CS and RD sets the parallel output to 3-state. BYTE and BUS18/16 are used for multiword read operations. BYTE is used whenever lower bits on the bus are output on the higher byte of the bus. BUS18/16 is used whenever the last two bits on the 18-bit bus is output on either bytes of the higher 16-bit bus. Refer to Table 1 for ideal output codes. Table 1. Ideal Input Voltages and Output Codes DESCRIPTION Full scale range Least significant bit (LSB) +Full scale Midscale Midscale – 1 LSB Zero ANALOG VALUE +Vref 2 × (+Vref)/262144 (+Vref) – 1 LSB 0V 0 V – 1 LSB –Vref BINARY CODE 01 1111 1111 1111 1111 00 0000 0000 0000 0000 11 1111 1111 1111 1111 10 0000 0000 0000 0000 HEX CODE 1FFFF 00000 3FFFF 20000 DIGITAL OUTPUT STRAIGHT BINARY The output data is a full 18-bit word (D17–D0) on DB17–DB0 pins (MSB–LSB) if both BUS18/16 and BYTE are low. The result may also be read on an 16-bit bus by using only pins DB17–DB2. In this case two reads are necessary: the first as before, leaving both BUS18/16 and BYTE low and reading the 16 most significant bits (D17–D2) on pins DB17–DB2, then bringing BUS18/16 high while holding BYTE low. When BUS18/16 is high, the lower two bits (D1–D0) appear on pins DB3–DB2. The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB17–DB10. In this case three reads are necessary: the first as before, leaving both BUS18/16 and BYTE low and reading the 8 most significant bits on pins DB17–DB10, then bringing BYTE high while holding BUS18/16 low. When BYTE is high, the medium bits (D9–D2) appear on pins DB17–DB10. The last read is done by bringing BUS18/16 high while holding BYTE high. When BUS18/16 is high, the lower two bits (D1–D0) appear on pins DB11–DB10. The last read cycle is not necessary if only the first 16 most significant bits are of interest. All of these multiword read operations can be performed with multiple active RD (toggling) or with RD held low for simplicity. This is referred to as the AUTO READ operation. Table 2. Conversion Data Read Out DATA READ OUT BYTE High Low BUS18/16 High High PINS DB17–DB12 All One's All One's PINS DB11–DB10 D1–D0 All One's PINS DB9–DB4 All One's All One's PINS DB3–DB2 All One's D1–D0 PINS DB1–DB0 All One's All One's 24 Submit Documentation Feedback ADS8482 www.ti.com SLAS386A – JULY 2005 – REVISED JUNE 2006 Table 2. Conversion Data Read Out (continued) DATA READ OUT BYTE High Low BUS18/16 Low Low PINS DB17–DB12 D9–D4 D17–D12 PINS DB11–DB10 D3–D2 D11–D10 PINS DB9–DB4 All One's D9–D4 PINS DB3–DB2 All One's D3–D2 PINS DB1–DB0 All One's D1–D0 RESET On power-up, internal POWER-ON RESET circuitry generates the reset required for the device. The first three conversions after power-up are used to load factory trimming data for a specific device to assure high accuracy of the converter. The results of the first three conversions are invalid and should be discarded. The device can also be reset through the use of the combination fo CS and CONVST. Since the BUSY signal is held at high during the conversion, either one of these conditions triggers an internal self-clear reset to the converter. • Issue a CONVST when CS is low and the internal convert state is high. The falling edge of CONVST starts a reset. • Issue a CS (select the device) while the internal convert state is high. The falling edge of CS causes a reset. Once the device is reset, all output latches are cleared (set to zeroes) and the BUSY signal is brought low. A new sampling period is started at the falling edge of the BUSY signal immediately after the instant of the internal reset. LAYOUT For optimum performance, care must be taken with the physical layout of the ADS8482 circuitry. As the ADS8482 offers single-supply operation, it is often used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to achieve good performance from the converter. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving any single conversion for an n-bit SAR converter, there are at least n windows in which large external transient voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, or high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. On average, the ADS8482 draws very little current from an external reference as the reference voltage is internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive the bypass capacitor or capacitors without oscillation. A 0.1-µF capacitor is recommended from pin 13 (REFIN) directly to pin 12 (REFM). REFM and AGND must be shorted on the same ground plane under the device. The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the analog ground. Avoid connections which are too close to the grounding point of a microcontroller or digital signal processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal layout consists of an analog ground plane dedicated to the converter and associated analog circuitry. As with the AGND connections, +VA should be connected to a 5-V power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. Power to the ADS8482 should be clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to the device as possible. See Table 3 for the placement of the capacitor. In addition, a 1-µF to 10-µF capacitor is recommended. In some situations, additional bypassing may be required, such as a 100-µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors-all designed to essentially low-pass filter the 5-V supply, removing the high frequency noise. Submit Documentation Feedback 25 ADS8482 www.ti.com SLAS386A – JULY 2005 – REVISED JUNE 2006 Table 3. Power Supply Decoupling Capacitor Placement POWER SUPPLY PLANE SUPPLY PINS Pin pairs that require shortest path to decoupling capacitors Pins that require no decoupling 24, 26 CONVERTER ANALOG SIDE (7,8), (9,10), (16,17), (20,21), (22,23), (25,26) CONVERTER DIGITAL SIDE (36,37) 1 26 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 PACKAGING INFORMATION Orderable Device ADS8482IBRGZR ADS8482IBRGZRG4 ADS8482IBRGZT ADS8482IBRGZTG4 ADS8482IRGZR ADS8482IRGZRG4 ADS8482IRGZT ADS8482IRGZTG4 (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type QFN QFN QFN QFN QFN QFN QFN QFN Package Drawing RGZ RGZ RGZ RGZ RGZ RGZ RGZ RGZ Pins Package Eco Plan (2) Qty 48 48 48 48 48 48 48 48 1000 Green (RoHS & no Sb/Br) 1000 Green (RoHS & no Sb/Br) 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR 1000 Green (RoHS & no Sb/Br) 1000 Green (RoHS & no Sb/Br) 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 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