ADS8506I

Burr Brown Products from Texas Instruments ADS8506 SLAS484A – SEPTEMBER 2007 – REVISED OCTOBER 2007 12-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE 1 FEATURES 40-kHz Min Sampling Rate 4-V, 5-V, and ±10-V Input Ranges 73.9-dB SINAD with 10-kHz Input ±0.45 LSB Max INL ±0.45 LSB Max DNL, 12-Bit No Missing Codes ±5-mV BPZ, ±0.5 PPM/°C BPZ Drift SPI Compatible Serial Output With Daisy-Chain (TAG) Feature Single 5-V Analog Supply Pin-Compatible With ADS7806 and 16-Bit ADS7807/8507 Uses Internal or External 2.5-V Reference Low Power Dissipation – 24 mW Typ, 30 mW Max at 40 KSPS 50-μW Max Power Down Mode 28-Pin SO Package Full Parallel Interface 2's Comp or BTC Output Code APPLICATIONS • • • • • • Industrial Process Control Test Equipment Medical Equipment Data Acquisition Systems Digital Signal Processing Instrumentation • • • • • • • 2 DESCRIPTION The ADS8506 is a complete low power, single 5-V supply, 12-bit sampling analog-to-digital (A/D) converter. It contains a complete 12-bit capacitor-based, successive approximation register (SAR) A/D converter with sample and hold, clock, reference, and data interface. The converter can be configured for a variety of input ranges including ±10 V, 4 V, and 5 V. For most input ranges, the input voltage can swing to 25 V or –25 V without damage to the converter. A SPI compatible serial interface allows data to be synchronized to an internal or external clock. A full parallel interface with BYTE select is also provided to allow the maximum system design flexibility. The ADS8506 is specified at 40 kHz sampling rate over the industrial -40°C to 85°C temperature range. • • • • • • • • Successive Approximation Register Clock EXT/IN 39.8 kΩ R1IN R2IN 20 kΩ 40 kΩ 9.9 kΩ CDAC Parallel and Serial Data Out & Control Parallel Data PWRD BYTE BUSY CS R/C SB/BTC TAG SDATA DATACLK Comparator CAP Buffer 6 kΩ REF Internal +2.5 V Ref REFD 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. QSPI, SPI are trademarks of Motorola. Copyright © 2007, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. ADS8506 SLAS484A – SEPTEMBER 2007 – REVISED OCTOBER 2007 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PACKAGE/ORDERING INFORMATION (1) PRODUCT MINIMUM INL (LSB) ±0.45 NO MISSING CODE 12 FULLSCALE ERROR (%) ±0.25 SPECIFICATION TEMPERATURE RANGE -40°C to 85°C -40°C to 85°C PACKAGE LEAD PACKAGE DESIGNATOR ORDERING NUMBER ADS8506IBDW ADS8506IBDWR ADS8506IDW ADS8506IDWR TRANSPORT MEDIA, QTY Tube, 20 Tape and Reel, 1000 Tube, 20 Tape and Reel, 1000 ADS8506IB SO-28 DW ADS8506I ±0.45 12 ±0.5 SO-28 DW (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT R1IN Analog inputs R2IN REF DGND, AGND2 Ground voltage differences VANA VDIG to VANA VDIG Digital inputs Maximum junction temperature Storage temperature range Internal power dissipation Lead temperature (soldering, 1.6 mm from case 10 seconds) (1) All voltage values are with respect to network ground terminal. ±25 V ±25 V +VANA + 0.3 V to AGND2 - 0.3 V ±0.3 V 6V 0.3 V 6V -0.3 V to +VDIG + 0.3 V 165°C –65°C to 150°C 700 mW 260°C ELECTRICAL CHARACTERISTICS At TA = -40°C to 85°C, fS = 40 kHz, VDIG = VANA = 5 V, and using internal reference and fixed resistors, (see Figure 43) unless otherwise specified. PARAMETER Resolution ANALOG INPUT -10 Voltage ranges See Table 1 0 0 Impedance Capacitance THROUGHPUT SPEED Conversion time Complete cycle Throughput rate DC ACCURACY INL Integral linearity error -0.45 ±0.15 0.45 -0.45 ±0.15 0.45 LSB (1) Acquire and convert 40 15 25 15 25 kHz μs 45 45 pF 10 5 4 -10 0 0 10 5 4 V TEST CONDITIONS ADS8506IB MIN TYP MAX 12 MINADS8506I MIN TYP MAX 12 UNIT Bits (1) 2 LSB means Least Significant Bit. One LSB for the ±10-V input range is 305 μV. Submit Documentation Feedback Product Folder Link(s): ADS8506 Copyright © 2007, Texas Instruments Incorporated ADS8506 www.ti.com SLAS484A – SEPTEMBER 2007 – REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS (continued) At TA = -40°C to 85°C, fS = 40 kHz, VDIG = VANA = 5 V, and using internal reference and fixed resistors, (see Figure 43) unless otherwise specified. PARAMETER DNL Differential linearity error No missing codes Transition noise (2) Gain Error Full scale error (3) (4) Full scale error drift Full scale error (3) (4) Full scale error drift Bipolar zero error (3) Bipolar zero error drift Unipolar zero error (3) Unipolar zero error drift Recovery time to rated accuracy from power down (5) Power supply sensitivity (VDIG = VANA = VS) AC ACCURACY SFDR THD SINAD SNR Spurious-free dynamic range Total harmonic distortion Signal-to-(noise+distortion) Signal-to-noise Usable bandwidth (7) Full-power bandwidth (-3 dB) SAMPLING DYNAMICS Aperture delay Aperture jitter Transient response Overvoltage recovery (8) REFERENCE Internal reference voltage Internal reference source current (must use external buffer) Internal reference drift External reference voltage range for specified linearity External reference current drain DIGITAL INPUTS VIL VIH IIL IIH Low-level input voltage High-level input voltage Low-level input current High-level input current VIL = 0 V VIH = 5 V -0.3 2.0 +0.8 VD +0.3 V ±10 ±10 -0.3 2.0 +0.8 VD +0.3 V ±10 ±10 V V μA μA Ext. 2.5-V Ref 2.3 No load 2.48 2.5 1 8 2.5 2.7 100 2.3 2.52 2.48 2.5 1 8 2.5 2.7 100 2.52 V μA ppm/°C V μA FS Step 750 40 20 5 750 40 20 5 ns ps μs ns fIN = 10 kHz, ±10 V fIN = 10 kHz, ±10 V fIN = 10 kHz, ±10 V fIN = 10 kHz, ±10 V -60 dB Input 72 72 98 -96 73.9 32 74 130 600 72 -80 72 98 -96 73.9 32 74 130 600 -80 dB (6) dB dB dB kHz kHz Ext. 2.5-V Ref Ext. 2.5-V Ref ±10 V Range ±10 V Range 0 V to 5 V, 0 V to 4 V Ranges 0 V to 5 V, 0 V to 4 V Ranges 2.2-μF Capacitor to CAP +4.75 V < VS < +5.25 V -3 ±0.5 1 ±0.5 -10 ±0.5 3 -3 ±0.5 1 -0.25 ±0.5 10 -10 ±0.5 3 -0.25 ±5 0.25 -0.5 ±0.5 10 TEST CONDITIONS ADS8506IB MIN -0.45 12 0.1 ±0.1 0.25 -0.5 ±5 0.5 TYP ±0.15 MAX 0.45 12 0.1 ±0.1 0.5 MINADS8506I MIN TYP ±0.15 MAX 0.45 UNIT LSB Bits LSB % % ppm/°C % ppm/°C mV ppm/°C mV ppm/°C ms LSB ±0.5 DIGITAL OUTPUTS (2) (3) (4) (5) (6) (7) (8) Typical rms noise at worst case transitions. As measured with fixed resistors, see Figure 43. Adjustable to zero with external potentiometer. Full scale error is the worst case of -Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. This is the time delay after the ADS8506 is brought out of Power-Down mode until all internal settling occurs and the analog input is acquired to rated accuracy. A Convert command after this delay will yield accurate results. All specifications in dB are referred to a full-scale input. Usable bandwidth defined as full-scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60 dB. Recovers to specified performance after 2 x FS input overvoltage. Submit Documentation Feedback Product Folder Link(s): ADS8506 3 Copyright © 2007, Texas Instruments Incorporated ADS8506 SLAS484A – SEPTEMBER 2007 – REVISED OCTOBER 2007 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At TA = -40°C to 85°C, fS = 40 kHz, VDIG = VANA = 5 V, and using internal reference and fixed resistors, (see Figure 43) unless otherwise specified. PARAMETER Data format - Parallel 12-bits in 2-bytes Data coding - Serial binary 2s complement or straight binary VOL VOH Low-level output voltage High-level output voltage Leakage Current Output capacitance DIGITAL TIMING Bus access time Bus relinquish time POWER SUPPLIES VDIG VANA IDIG IANA Digital voltage Analog voltage Digital current Analog current VANA = VDIG = 5 V, fS = 40 kHz Power dissipation REFD High PWRD and REFD High TEMPERATURE RANGE Specified performance Derated performance Storage temperature SO Thermal resistance (ΘJA) -40 -55 -65 46 85 125 150 -40 -55 -65 46 85 125 150 °C °C °C °C/W Must be ≤ VANA 4.75 4.75 5 5 0.6 4.2 24 20 50 30 5.25 5.25 4.75 4.75 5 5 0.6 4.2 24 20 50 30 5.25 5.25 V V mA mA mW mW μW RL = 3.3 kΩ, CL = 50 pF RL = 3.3 kΩ, CL = 10 pF 83 83 83 83 ns ns ISINK = 1.6 mA ISOURCE = 500 μA High-Z state, VOUT = 0 V to VDIG High-Z state 4 ±5 15 0.4 4 ±5 15 0.4 V V μA pF TEST CONDITIONS ADS8506IB MIN TYP MAX MINADS8506I MIN TYP MAX UNIT DEVICE INFORMATION R1IN 1 AGND1 2 R2IN 3 CAP 4 REF 5 AGND2 6 SB/BTC 7 EXT/INT 8 D7 9 D6 10 D5 11 D4 12 D3 13 DGND 14 ADS8506 28 VDIG 27 V ANA 26 REFD 25 PWRD 24 BUSY 23 CS 22 R/C 21 BYTE 20 TAG 19 SDATA 18 DATACLK 17 D0 16 D1 15 D2 4 Submit Documentation Feedback Product Folder Link(s): ADS8506 Copyright © 2007, Texas Instruments Incorporated ADS8506 www.ti.com SLAS484A – SEPTEMBER 2007 – REVISED OCTOBER 2007 Terminal Functions TERMINAL NO. 1 2 3 4 5 6 7 8 NAME R1IN AGND1 R2IN CAP REF AGND2 SB/BTC EXT/INT I I DIGITAL I/O Analog Input. Analog sense ground. Used internally as ground reference point. Minimal current flow Analog Input. Reference buffer output. 2.2-μF Tantalum capacitor to ground. Reference input/output. Outputs internal 2.5-V reference. Can also be driven by external system reference. In both cases, bypass to ground with a 2.2-μF tantalum capacitor. Analog ground Selects straight binary or binary 2's complement for output data format. if high, data is output in a straight binary format. If low, data is output in a binary 2's complement format. Selects external/Internal data clock for transmitting data. If high, data is output synchronized to the clock input on DATACLK. If low, a convert command initiates the transmission of the data from the previous conversion, along with 12-clock pulses output on DATACLK. Data bit 3 if BYTE is high. Data bit 11 (MSB) if BYTE is low. Hi-Z when CS is high and/or R/C is low. Leave unconnected when using serial output. Data bit 2 if BYTE is high. Data bit 10 if BYTE is low. Hi-Z when CS is high and/or R/C is low. Data bit 1 if BYTE is high. Data bit 9 if BYTE is low. Hi-Z when CS is high and/or R/C is low. Data bit 0 (LSB) if BYTE is high. Data bit 8 if BYTE is low. Hi-Z when CS is high and/or R/C is low. Ground if BYTE is high. Data bit 7 if BYTE is low. Hi-Z when CS is high and/or R/C is low. Digital ground O O O I/O Ground if BYTE is high. Data bit 6 if BYTE is low. Hi-Z when CS is high and/or R/C is low. Ground if BYTE is high. Data bit 5 if BYTE is low. Hi-Z when CS is high and/or R/C is low. Ground if BYTE is high. Data bit 4 if BYTE is low. Hi-Z when CS is high and/or R/C is low. Either an input or an output depending on the EXT/INT level. Output data is synchronized to this clock. If EXT/INT is low, DATACLK transmits 12 pulses after each conversion, and then remains low between conversions. Serial data output. Data is synchronized to DATACLK, with the format determined by the level of SB/BTC. In the external clock mode, after 12 bits of data, the ADC outputs the level input on TAG as long as CS is low and R/C is high. If EXT/INT is low, data is valid on both the rising and falling edges of DATACLK, and between conversions SDATA stays at the level of the TAG input when the conversion was started. Tag input for use in the external clock mode. If EXT is high, digital data input from TAG is output on DATA with a delay that is dependent on the external clock mode. Selects 8 most significant bits (low) or 8 least significant bits (high) on parallel output pins. Read/convert input. With CS low, a falling edge on R/C puts the internal sample-and-hold into the hold state and starts a conversion. When EXT/INT is low, this also initiates the transmission of the data results from the previous conversion. Internally ORed with R/C. If R/C is low, a falling edge on CS initiates a new conversion. If EXT/INT is low, this same falling edge will start the transmission of serial data results from the previous conversion. At the start of a conversion, BUSY goes low and stays low until the conversion is completed and the digital outputs have been updated. Power down input. If high, conversions are inhibited and power consumption is significantly reduced. Results from the previous conversion are maintained in the output shift register. REFD High shuts down the internal reference. External reference will be required for conversions. Analog Supply. Nominally +5 V. Decouple with 0.1-μF ceramic and 10-μF tantalum capacitors. Digital Supply. Nominally +5 V. Connect directly to pin 27. Must be ≤ VANA. DESCRIPTION 9 10 11 12 13 14 15 16 17 18 D7 D6 D5 D4 D3 DGND D2 D1 D0 DATACLK O O O O O 19 SDATA O 20 21 22 TAG BYTE R/C I I I 23 CS I 24 25 26 27 28 BUSY PWRD REFD VANA VDIG O I I Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS8506 5 ADS8506 SLAS484A – SEPTEMBER 2007 – REVISED OCTOBER 2007 www.ti.com Table 1. Input Range Connections (see Figure 42 and Figure 43) ANALOG INPUT RANGE ±10 V 0 V to 5 V 0 V to 4 V CONNECT R1IN VIA 200 Ω TO VIN AGND VIN CONNECT R2IN VIA 100 Ω TO CAP VIN VIN IMPEDANCE 45.7 kΩ 20.0 kΩ 21.4 kΩ TYPICAL CHARACTERISTICS POWER SUPPLY CURRENT vs FREE-AIR TEMPERATURE 5.5 INTERNAL REFERENCE vs FREE-AIR TEMPERATURE 2.520 Vref - Internal Reference Voltage - V POWER SUPPLY CURRENT vs SAMPLING FREQUENCY 5.5 ICC - Power Supply Current - mA ICC - Power Supply Current - mA 2.515 2.510 2.505 2.500 2.495 2.490 2.485 2.480 -40 -25 -10 5 20 35 50 65 80 95 110 125 TA - Free-Air Temperature - ºC 5 5 4.5 4.5 4 4 3.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 TA - Free-Air Temperature - ºC 3.5 10 20 30 fs - Sampling Frequency - kHz 40 Figure 1. BIPOLAR OFFSET ERROR vs FREE-AIR TEMPERATURE Bipolar Positive Full-Scale Error - %FSR 3 20 V Bipolar Range Figure 2. BIPOLAR POSITIVE FULL-SCALE ERROR vs FREE-AIR TEMPERATURE 0.2 20 V Bipolar Range Bipolar Negative Full-Scale Error - %FSR Figure 3. BIPOLAR NEGATIVE FULL-SCALE ERROR vs FREE-AIR TEMPERATURE 0 Bipolar Offset Error - mV 2 0.15 -0.05 1 0.1 -0.1 0 0.05 -0.15 -1 -2 -45 -30 -15 0 15 30 45 60 75 90 105120 TA - Free-Air Temperature - ºC 0 -45 -30 -15 0 15 30 45 60 75 90 105120 TA - Free-Air Temperature - ºC -0.2 -45 -30 -15 0 15 30 45 60 75 90 105120 TA - Free-Air Temperature - ºC Figure 4. Figure 5. Figure 6. 6 Submit Documentation Feedback Product Folder Link(s): ADS8506 Copyright © 2007, Texas Instruments Incorporated ADS8506 www.ti.com SLAS484A – SEPTEMBER 2007 – REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (continued) UNIPOLAR OFFSET ERROR vs FREE-AIR TEMPERATURE 3 UNIPOLAR FULL-SCALE ERROR vs FREE-AIR TEMPERATURE 0.2 UNIPOLAR FULL-SCALE ERROR vs FREE-AIR TEMPERATURE 0 Unipolar Full-Scale Error - %FSR Unipolar Offset Error - mV 2 Unipolar Full-Scale Error - %FSR Unipolar Range Unipolar Range, 4 V Input Range 0.1 Unipolar Range, 5 V Input Range -0.1 1 0 -0.2 0 -1 -0.1 -0.3 -2 -45 -30 -15 0 15 30 45 60 75 90 105120 TA - Free-Air Temperature - ºC -0.2 -45 -30 -15 0 15 30 45 60 75 90 105120 TA - Free-Air Temperature - ºC -0.4 -45 -30 -15 0 15 30 45 60 75 90 105120 TA - Free-Air Temperature - ºC Figure 7. SPURIOUS FREE DYNAMIC RANGE vs FREE-AIR TEMPERATURE SFDR - Spurious Free Dynamic Range - dB Figure 8. TOTAL HARMONIC DISTORTION vs FREE-AIR TEMPERATURE -80 Figure 9. SIGNAL-TO-NOISE RATIO vs FREE-AIR TEMPERATURE 90 110 THD - Total Harmonic Distortion - dB fi = 10 kHz, 0 dB 105 SNR - Signal-to-Noise Ratio - dB fi = 10 kHz, 0 dB -85 -90 fi = 10 kHz, 0 dB 85 80 75 70 65 60 -50 100 95 -95 -100 90 85 80 -50 -105 -110 -50 -25 0 25 50 75 100 TA - Free-Air Temperature - ºC 125 -25 0 25 50 75 100 TA - Free-Air Temperature - ºC 125 -25 0 25 50 75 100 TA - Free-Air Temperature - ºC 125 Figure 10. SIGNAL-TO-NOISE AND DISTORTION vs FREE-AIR TEMPERATURE SINAD - Signal-to-Noise and Distortion - dB SINAD - Signal-to-Noise and Distortion - dB 90 fi = 10 kHz, 0 dB 85 80 75 70 65 60 -50 Figure 11. SIGNAL-TO-NOISE AND DISTORTION vs FREQUENCY SINAD - Signal-to-Noise and Distortion - dB 90 80 70 60 50 40 30 20 10 0 0 2 4 6 8 10 12 14 16 18 20 f - Frequency - kHz G = -60 dB G = -20 dB G = 0 dB Figure 12. SIGNAL-TO-NOISE AND DISTORTION vs FREE-AIR TEMPERATURE 85 fi = 10kHz, 0 dB 80 fs = 10 kHz 75 fs = 40 kHz fs = 30 kHz 65 fs = 20 kHz 70 -25 0 25 50 75 100 TA - Free-Air Temperature - ºC 125 60 -50 -25 0 25 50 75 100 TA - Free-Air Temperature - ºC 125 Figure 13. Figure 14. Figure 15. Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS8506 7 ADS8506 SLAS484A – SEPTEMBER 2007 – REVISED OCTOBER 2007 www.ti.com TYPICAL CHARACTERISTICS (continued) SIGNAL-TO-NOISE RATIO vs FREQUENCY fi = 0 dB SNR - Signal-to-Noise Ratio - dB SIGNAL-TO-NOISE AND DISTORTION vs FREQUENCY SINAD - Signal-to-Noise and Distortion - dB 90 SFDR - Spurious Free Dynamic Range - dB SPURIOUS FREE DYNAMIC RANGE vs FREQUENCY 100 90 fi = 0 dB 80 fi = 0 dB 90 80 70 70 80 60 60 70 50 0 1 100 10 f - Frequency - kHz 1000 50 0 1 10 100 f - Frequency - kHz 1000 60 0 1 10 100 f - Frequency - kHz 1000 Figure 16. TOTAL HARMONIC DISTORTION vs FREQUENCY fi = 0 dB -70 SFDR - Spurious Free Dynamic Range - dB Figure 17. SPURIOUS FREE DYNAMIC RANGE vs EQUIVALENT SERIES RESISTOR 115 110 105 100 95 90 85 80 75 0 1 2 3 456 ESR - W 7 8 9 10 THD - Total Harmonic Distortion - dB Figure 18. TOTAL HARMONIC DISTORTION vs EQUIVALENT SERIES RESISTOR -80 -60 THD - Total Harmonic Distortion - dB fi = 10 kHz, 0 dB fi = 10 kHz, 0 dB -85 -90 -95 -100 -80 -90 -100 -105 -110 0 1 2 3 4 56 ESR - W 7 8 9 10 -110 0 1 10 100 f - Frequency - kHz 1000 Figure 19. SIGNAL-TO-NOISE RATIO vs EQUIVALENT SERIES RESISTOR SNR - Signal-to-Noise Ratio - dB 90 85 80 75 70 65 60 55 0 1 2 3 4 56 ESR - W 7 8 9 10 Figure 20. SIGNAL-TO-NOISE AND DISTORTION vs EQUIVALENT SERIES RESISTOR SINAD - Signal-to-Noise and Distortion - dB 95 90 85 80 75 70 65 60 55 0 1 2 3 4 56 ESR - W 7 8 9 10 Figure 21. OUTPUT REJECTION vs POWER-SUPPLY RIPPLE FREQUENCY -20 Silicon Tested Under 5 V Unipolar Range 95 fi = 10 kHz, 0 dB fi = 10 kHz, 0 dB -30 Output Rejection - dB -40 -50 -60 -70 -80 10 100 1k 10 k 100 k 1M Power-Supply Ripple Frequency - Hz Figure 22. Figure 23. Figure 24. 8 Submit Documentation Feedback Product Folder Link(s): ADS8506 Copyright © 2007, Texas Instruments Incorporated ADS8506 www.ti.com SLAS484A – SEPTEMBER 2007 – REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (continued) CONVERSION TIME vs FREE-AIR TEMPERATURE 13.6 tCONVERT - Conversion Time - ms 13.5 13.4 13.3 13.2 13.1 13 -50 -25 0 25 50 75 100 TA - Free-Air Temperature - ºC 125 Figure 25. INL 0.3 0.2 0.1 INL - LSBs 0 -0.1 -0.2 -0.3 0 512 1024 1536 2048 Code 2560 3072 3584 4095 Figure 26. DNL 0.3 0.2 0.1 DNL - LSBs 0 -0.1 -0.2 -0.3 0 512 1024 1536 2048 Code 2560 3072 3584 4095 Figure 27. Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS8506 9 ADS8506 SLAS484A – SEPTEMBER 2007 – REVISED OCTOBER 2007 www.ti.com TYPICAL CHARACTERISTICS (continued) FFT 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 5 10 f - Frequency - kHz 15 20 8192 Point FFT, fi = 10 kHz, 0 dB Amplitude - dB Figure 28. FFT 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 8192 Point FFT, fi = 20 kHz, 0 dB Amplitude - dB -100 -110 -120 -130 0 5 10 f - Frequency - kHz 15 20 Figure 29. FFT 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 5 10 f - Frequency - kHz 15 20 8192 Point FFT, fi = 1 kHz, 0 dB Amplitude - dB Figure 30. BASIC OPERATION PARALLEL OUTPUT Figure 31 shows a basic circuit to operate the ADS8506 with a ±10-V input range and parallel output. Taking R/C (pin 22) LOW for a minimum of 40 ns (12 μs max) will initiate a conversion. BUSY (pin 24) will go LOW and stay 10 Submit Documentation Feedback Product Folder Link(s): ADS8506 Copyright © 2007, Texas Instruments Incorporated ADS8506 www.ti.com SLAS484A – SEPTEMBER 2007 – REVISED OCTOBER 2007 LOW until the conversion is completed and the output register is updated. If BYTE (pin 21) is LOW, the eight most significant bits (MSBs) will be valid when BUSY rises; if BYTE is HIGH, the four least significant bits (LSBs) will be valid when BUSY rises. Data will be output in binary 2's complement (BTC) format. BUSY going HIGH can be used to latch the data. After the first byte has been read, BYTE can be toggled allowing the remaining byte to be read. All convert commands will be ignored while BUSY is LOW. The ADS8506 begins tracking the input signal at the end of the conversion. Allowing 25 μs between convert commands assures accurate acquisition of a new signal. The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors compensate for this adjustment and can be left out if the offset and gain will be corrected in software (refer to the Calibration section). Parallel Output 200 Ω ± 10 V 66.5 kΩ 100 Ω 2.2 µF +5 V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ADS8506 28 27 26 25 24 23 22 21 20 19 NC(1) 18 17 16 15 B6 B5 B4 B2 R/C BYTE 40 ns Min BUSY Convert Pulse + 0.1 µF + +5 V 10 µF + 2.2 µF Pin 21 LOW Pin 21 HIGH B11 B10 B9 B8 B7 (MSB) B3 B2 B1 B0 (LSB) Figure 31. Basic ±10-V Operation, Both Parallel and Serial Output SERIAL OUTPUT Figure 32 shows a basic circuit to operate the ADS8506 with a ±10-V input range and serial output. Taking R/C (pin 22) LOW for 40 ns (12 μs max) will initiate a conversion and output valid data from the previous conversion on SDATA (pin 19) synchronized to 12 clock pulses output on DATACLK (pin 18). BUSY (pin 24) will go LOW and stay LOW until the conversion is completed and the serial data has been transmitted. Data will be output in BTC format, MSB first, and will be valid on both the rising and falling edges of the data clock. BUSY going HIGH can be used to latch the data. All convert commands will be ignored while BUSY is LOW. The ADS8506 begins tracking the input signal at the end of the conversion. Allowing 25 μs between convert commands assures accurate acquisition of a new signal. The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors compensate for this adjustment and can be left out if the offset and gain are corrected in software (refer to the Calibration section). Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS8506 11 ADS8506 SLAS484A – SEPTEMBER 2007 – REVISED OCTOBER 2007 www.ti.com Serial Output 200 Ω ± 10 V 66.5 kΩ +5V 100 Ω 2.2 µF 22 µF 1 2 3 4 5 6 7 8 NC(1) 9 NC(1) 10 NC(1) 11 NC(1) 12 NC(1) 13 28 27 26 25 24 23 ADS8506 22 21 20 19 18 17 NC(1) 16 NC(1) 15 NC(1) SDATA DATACLK 40 ns Min R/C BUSY Convert Pulse + 0.1 µF + +5 V 10 µF + + 14 Figure 32. Basic ±10-V Operation With Serial Output STARTING A CONVERSION The combination of CS (pin 23) and R/C (pin 22) low for a minimum of 40 ns puts the sample-and-hold of the ADS8506 in the hold state and starts conversion N. BUSY (pin 24) goes low and stays low until conversion N is completed and the internal output register has been updated. All new convert commands during BUSY low are ignored. CS and/or R/C must go high before BUSY goes high, or a new conversion is initiated without sufficient time to acquire a new signal. The ADS8506 begins tracking the input signal at the end of the conversion. Allowing 25 μs between convert commands assures accurate acquisition of a new signal. Refer to Table 2 and Table 3 for a summary of CS, R/C, and BUSY states, and Figure 33, Figure 34, Figure 35, Figure 36, Figure 37, Figure 38, and Figure 39 for timing diagrams. Table 2. Control Functions When Using Parallel Output (DATACLK Tied Low, EXT/INT Tied High) CS 1 ↓ 0 0 ↓ ↓ 0 0 X (1) R/C X 0 ↓ 1 1 1 ↑ 0 X BUSY X 1 1 ↑ 1 0 0 ↑ 0 None. Data bus is in Hi-Z state. Initiates conversion N. Data bus remains in Hi-Z state. Initiates conversion N. Databus enters Hi-Z state. Conversion N completed. Valid data from conversion N on the databus. Enables databus with valid data from conversion N. Enables databus with valid data from conversion N–1 (1). Conversion N in progress. Enables databus with valid data from conversion N–1 (1). Conversion N in progress. New conversion initiated without acquisition of a new signal. Data will be invalid. CS and/or R/C must be HIGH when BUSY goes HIGH. New convert commands ignored. Conversion N in progress. OPERATION See Figure 33 and Figure 34 for constraints on data valid from conversion N–1. CS and R/C are internally ORed and level triggered. It is not a requirement which input goes low first when initiating a conversion. If, however, it is critical that CS or R/C initiates conversion N, be sure the less critical input is low at least tsu2 ≥ 10 ns prior to the initiating input. If EXT/INT (pin 8) is low when initiating conversion N, serial data from conversion N–1 is output on SDATA (pin 19) following the start of conversion N. See Internal Data Clock in the Reading Data section. 12 Submit Documentation Feedback Product Folder Link(s): ADS8506 Copyright © 2007, Texas Instruments Incorporated ADS8506 www.ti.com SLAS484A – SEPTEMBER 2007 – REVISED OCTOBER 2007 To reduce the number of control pins, CS can be tied low using R/C to control the read and convert modes. This has no effect when using the internal data clock in the serial output mode. The parallel output and the serial output (only when using an external data clock), however, is affected whenever R/C goes high and the external clock is active. Refer to the Reading Data section. In the internal clock mode data is clocked out every convert cycle regardless of the states of CS and R/C. The conversion result is available as soon as BUSY returns to high therefore, data always represents the conversion previously completed even when it is read during a conversion. READING DATA The ADS8506 outputs serial or parallel data in straight binary (SB) or binary 2's complement data output format. If SB/BTC (pin 7) is high, the output is in SB format, and if low, the output is in BTC format. Refer to Table 4 for ideal output codes. The first conversion immediately following a power-up does not produce a valid conversion result. The parallel output can be read without affecting the internal output registers; however, reading the data through the serial port shifts the internal output registers one bit per data clock pulse. As a result, data can be read on the parallel port prior to reading the same data on the serial port, but data cannot be read through the serial port prior to reading the same data on the parallel port. Table 3. Control Functions When Using Serial Output (1) CS ↓ 0 ↓ 0 ↓ ↓ 0 0 X (1) R/C 0 ↓ 0 ↓ 1 1 ↑ 0 X BUSY 1 1 1 1 1 0 0 ↑ 0 EXT/INT 0 0 1 1 1 1 1 X X Input Input Input Input X DATACLK Output Output Input OPERATION Initiates conversion N. Valid data from conversion N–1 clocked out on SDATA. Initiates conversion N. Valid data from conversion N–1 clocked out on SDATA. Initiates conversion N. Internal clock still runs conversion process. Initiates conversion N. Internal clock still runs conversion process. Conversion N completed. Valid data from conversion N clocked out on SDATA synchronized to external data clock. Valid data from conversion N–1 output on SDATA synchronized to external data clock. Conversion N in progress. Valid data from conversion N–1 output on SDATA synchronized to external data clock. Conversion N in progress. New conversion initiated without acquisition of a new signal. Data will be invalid. CS and/or R/C must be HIGH when BUSY goes HIGH. New convert commands ignored. Conversion N in progress.. See Figure 37, Figure 38, and Figure 39 for constraints on data valid from conversion N–1. Table 4. Output Codes and Ideal Input Voltages DIGITAL OUTPUT DESCRIPTION ANALOG INPUT BINARY 2's COMPLEMENT (SB/BTC LOW) 0 V to 4 V 61 μV 3.999939 V 2V 1.999939 V 0V 0111 1111 1111 0000 0000 0000 1111 1111 1111 1000 0000 0000 BINARY CODE HEX CODE 7FF 000 FFF 800 STRAIGHT BINARY (SB/BTC HIGH) Full-scale range Least significant bit (LSB) +Full-Scale (FS - 1LSB) Midscale One LSB Below Midscale -Full-Scale ±10 305 μV 9.999695 V 0V 305 μV -10 V 0 V to 5 V 76 μV 4.999924 V 2.5 V 2.499924 V 0V BINARY CODE 1111 1111 1111 1000 0000 0000 0111 1111 1111 0000 0000 0000 HEX CODE FFF 800 7FF 000 PARALLEL OUTPUT To use the parallel output, tie EXT/INT (pin 8) high and DATACLK (pin 18) low. SDATA (pin 19) should be left unconnected. The parallel output is active when R/C (pin 22) is high and CS (pin 23) is low. Any other combination of CS and R/C 3-states the parallel output. Valid conversion data can be read in two 8-bit bytes on D7-D0 (pins 9-13 and 15-17). When BYTE (pin 21) is low, the 8 most significant bits will be valid with the MSB on D7. When BYTE is high, the 4 least significant bits are valid with the LSB on D4. BYTE can be toggled to read both bytes within one conversion cycle. Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS8506 13 ADS8506 SLAS484A – SEPTEMBER 2007 – REVISED OCTOBER 2007 www.ti.com Upon initial power up, the parallel output contains indeterminate data. PARALLEL OUTPUT (After a Conversion) After conversion N is completed and the output registers have been updated, BUSY (pin 24) goes high. Valid data from conversion N is available on D7-D0 (pin 9-13 and 15-17). BUSY going high can be used to latch the data. Refer to Table 5 and Figure 33 and Figure 34 for timing specifications. t1 R/C t3 BUSY t6 t7 MODE Acquire Convert t1 t4 t3 t5 t8 Acquire t6 Convert t12 t11 Parallel Data Bus Previous High Byte Valid Hi-Z Previous High Previous Low Byte Valid Byte Valid Not Valid t10 High Byte Valid Low Byte Valid Hi-Z t12 High Byte Valid t2 t9 BYTE t12 t12 t12 t9 t12 Figure 33. Conversion Timing With Parallel Output (CS and DATACLK Tied Low, EXT/INT Tied High) t21 R/C t21 CS t3 BUSY t21 BYTE t21 Data Bus Hi-Z State High Byte Hi-Z State t1 t21 t21 t21 t21 t4 t21 t21 Low Byte Hi-Z State t21 t9 t21 t9 Figure 34. CS to Control Conversion and Read Timing With Parallel Outputs 14 Submit Documentation Feedback Product Folder Link(s): ADS8506 Copyright © 2007, Texas Instruments Incorporated ADS8506 www.ti.com SLAS484A – SEPTEMBER 2007 – REVISED OCTOBER 2007 PARALLEL OUTPUT (During a Conversion) After conversion N has been initiated, valid data from conversion N–1 can be read and is valid up to 12 μs after the start of conversion N. Do not attempt to read data beyond 12 μs after the start of conversion N until BUSY (pin 24) goes high; this may result in reading invalid data. Refer to Table 5 and Figure 33 and Figure 34 for timing constraints. Table 5. Parallel Conversion and Data Timing, TA = -40°C to 85°C SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t21 t7 + t8 Convert pulse width Data valid delay after R/C low BUSY delay from start of conversion BUSY Low BUSY delay after end of conversion Aperture delay Conversion time Acquisition time Bus relinquish time BUSY delay after data valid Previous data valid after start of conversion Bus access time and BYTE delay R/C to CS setup time Throughput time 10 25 10 20 60 13.5 10 15 83 13.5 90 40 13.5 11.5 83 15 DESCRIPTION MIN 0.04 13.5 TYP MAX 12 15 85 15 UNITS μs μs ns μs ns ns μs μs ns ns μs ns ns μs SERIAL OUTPUT Data can be clocked out with the internal data clock or an external data clock. When using serial output, be careful with the parallel outputs, D7-D0 (pins 9-13 and 15-17), as these pins come out of Hi-Z state whenever CS (pin 23) is low and R/C (pin 22) is high. The serial output cannot be 3-stated and is always active. Refer to the Applications Information section for specific serial interfaces. If external clock is used, the TAG input can be used to daisy-chain multiple ADS8506 data pins together. INTERNAL DATA CLOCK (During a Conversion) To use the internal data clock, tie EXT/INT (pin 8) low. The combination of R/C (pin 22) and CS (pin 23) low initiates conversion N and activates the internal data clock (typically 900-kHz clock rate). The ADS8506 outputs 12 bits of valid data, MSB first, from conversion N–1 on SDATA (pin 19), synchronized to 12 clock pulses output on DATACLK (pin 18). The data is valid on both the rising and falling edges of the internal data clock. The rising edge of BUSY (pin 24) can be used to latch the data. After the 12th clock pulse, DATACLK remains low until the next conversion is initiated, while SDATA returns to the state of the TAG pin input sensed at the start of transmission. Refer to Table 6 and Figure 36. EXTERNAL DATA CLOCK To use an external data clock, tie EXT/INT (pin 8) high. The external data clock is not and cannot be synchronized with the internal conversion clock; care must be taken to avoid corrupting the data. To enable the output mode of the ADS8506, CS (pin 23) must be low and R/C (pin 22) must be high. DATACLK must be high for 20% to 70% of the total data clock period; the clock rate can be between DC and 10 MHz. Serial data from conversion N can be output on SDATA (pin 19) after conversion N is completed or during conversion N+1. An obvious way to simplify control of the converter is to tie CS low and use R/C to initiate conversions. While this is perfectly acceptable, there is a possible problem when using an external data clock. At an indeterminate point from 12 μs after the start of conversion N until BUSY rises, the internal logic shifts the results of conversion N into the output register. If CS is low, R/C high, and the external clock is high at this point, data is lost. So, with CS low, either R/C and/or DATACLK must be low during this period to avoid losing valid data. Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS8506 15 ADS8506 SLAS484A – SEPTEMBER 2007 – REVISED OCTOBER 2007 www.ti.com EXTERNAL DATA CLOCK (After a Conversion) After conversion N is completed and the output registers have been updated, BUSY (pin 24) goes high. With CS low and R/C high, valid data from conversion N is output on SDATA (pin 19) synchronized to the external data clock input on DATACLK (pin 18). The MSB is valid on the first falling edge and the second rising edge of the external data clock. The LSB is valid on the 12th falling edge and 13th rising edge of the data clock. TAG (pin 20) inputs a bit of data for every external clock pulse. The first bit input on TAG is valid on SDATA on the 13th falling edge and the 14th rising edge of DATACLK; the second input bit is valid on the 14th falling edge and the 15th rising edge, etc. With a continuous data clock, TAG data is output on SDATA until the internal output registers are updated with the results from the next conversion. Refer to Table 6 and Figure 38. EXTERNAL DATA CLOCK (During a Conversion) After conversion N has been initiated, valid data from conversion N–1 can be read and is valid up to 12 μs after the start of conversion N. Do not attempt to clock out data from 12 μs after the start of conversion N until BUSY (pin 24) rises; this results in data loss. NOTE: For the best possible performance when using an external data clock, data should not be clocked out during a conversion. The switching noise of the asynchronous data clock can cause digital feedthrough degrading the converter's performance. Refer to Table 6 and Figure 39. 16 Submit Documentation Feedback Product Folder Link(s): ADS8506 Copyright © 2007, Texas Instruments Incorporated ADS8506 www.ti.com SLAS484A – SEPTEMBER 2007 – REVISED OCTOBER 2007 Table 6. Serial Timing Requirements, TA = –40°C to 85°C PARAMETER tw1 td1 tw2 td2 td3 tconv tacq tconv + tacq td4 tc1 td5 td6 tc2 tw3 tw4 tsu1 tsu2 td8 td9 td10 tsu3 td11 tsu3 th1 Pulse duration, convert Delay time, BUSY from R/C low Pulse duration, BUSY low Delay time, BUSY, after end of conversion Delay time, aperture Conversion time Acquisition time Cycle time Delay time, R/C low to internal DATACLK output Cycle time, internal DATACLK Delay time, data valid to internal DATACLK high Delay time, data valid after internal DATACLK low Cycle time, external DATACLK Pulse duration, external DATACLK high Pulse duration, external DATACLK low Setup time, R/C rise/fall to external DATACLK high Setup time, R/C transition to CS transition Delay time, data valid from external DATCLK high Delay time, CS rising edge to external DATACLK rising edge Delay time, previous data available after CS, R/C low Setup time, BUSY transition to first external DATACLK Delay time, final external DATACLK to BUSY rising edge Setup time, TAG valid Hold time, TAG valid 0 2 600 150 150 35 15 15 15 10 2 10 2 5 1 20 204 820 204 208 850 10 MIN 0.04 12 13.5 5 5 13.5 11.5 25 15 TYP MAX 12 20 15 UNIT μs ns μs ns ns μs μs μs ns ns ns ns ns ns ns ns ns ns ns μs ns μs ns ns CS R/C tsu1 External DATACLK tsu1 R/C CS tsu1 External DATACLK tsu1 CS Set Low, Discontinuous Ext DATACLK CS tsu2 R/C tsu2 R/C Set Low, Discontinuous Ext DATACLK BUSY tsu3 External DATACLK 1 2 CS Set Low, Discontinuous Ext DATACLK Figure 35. Critical Timing Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS8506 17 ADS8506 SLAS484A – SEPTEMBER 2007 – REVISED OCTOBER 2007 www.ti.com tw1 R/C td1 BUSY td3 STATUS Nth Conversion Error Correction tw1 tw2 td1 tw2 td2 td11 (N+1)th Accquisition td3 Error (N+1)th Conversion Correction td2 td11 (N+2)th Accquisition tconv td4 Internal DATACLK td5 SDATA TAG = 0 D 11 1 2 12 tacq td4 tconv tacq tc1 1 2 12 td6 D 0 TAG = 0 D 11 8 starts READ D 0 TAG = 0 (N− 1)th Conversion Data CS, EXT/INT, and TAG are tied low Nth Conversion Data Figure 36. Basic Conversion Timing - Internal DATACLK (Read Previous Data During Conversion) tw1 R/C td1 BUSY td3 STATUS Nth Conversion tw1 tw2 td1 tw2 td2 td11 Error Correction (N+1)th Accquisition td3 (N+1)th Conversion td2 td11 Error Correction (N+2)th Accquisition tconv tsu1 External DATACLK 1 12 tacq tsu3 1 2 12 tconv tsu1 1 12 tacq tsu3 1 2 12 SDATA TAG = 0 No more data to shift out TAG = 0 Nth Data TAG = 0 No more data to shift out TAG = 0 (N+1)th Data TAG = 0 EXT/INT tied high, CS and TAG are tied low tw1 + tsu1 starts READ Figure 37. Basic Conversion Timing - External DATACLK 18 Submit Documentation Feedback Product Folder Link(s): ADS8506 Copyright © 2007, Texas Instruments Incorporated ADS8506 www.ti.com SLAS484A – SEPTEMBER 2007 – REVISED OCTOBER 2007 tw1 R/C td1 BUSY td3 STATUS Nth Conversion tw2 tsu1 td1 td2 td11 Error Correction (N+1) th Accquisition td3 tconv tc2 External DATACLK tw3 0 tsu3 tw4 1 2 3 4 5 tacq tsu1 8 9 10 11 12 td8 SDATA tsu3 TAG EXT/INT tied high, CS tied low T00 D11 D10 D9 D8 D7 D6 Nth Conversion Data D03 D02 D01 td8 D00 Null T00 Txx th1 T01 T02 T03 T04 T05 T06 T8 T9 T10 T11 Null T13 Tyy tw1 + tsu1 starts READ Figure 38. Read After Conversion (Discontinuous External DATACLK) tw1 R/C td1 tw2 BUSY td3 STATUS tsu3 tc2 External DATACLK tsu1 tw3 0 1 td10 Nth Conversion td2 Error Correction tconv tw4 2 3 4 5 7 8 9 10 11 td11 td8 SDATA D11 D10 D9 D8 D7 D6 Nth Conversion Data D03 D02 D01 td8 D00 EXT/INT tied high, CS and TAG tied low Rising DATACLK change DATA, tw1 + tsu1 Starts READ TAG is not recommended for this mode. There is not enough time to do so without violating td11. Figure 39. Read During Conversion (Discontinuous External DATACLK) TAG FEATURE The TAG feature allows the data from multiple ADS8506 converters to be read on a single serial line. The converters are cascaded together using the DATA pins as outputs and the TAG pins as inputs as illustrated in Figure 40. The DATA pin of the last converter drives the processor's serial data input. Data is then shifted through each converter, synchronous to the externally supplied data clock, onto the serial data line. The internal clock cannot be used for this configuration. Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS8506 19 ADS8506 SLAS484A – SEPTEMBER 2007 – REVISED OCTOBER 2007 www.ti.com The preferred timing uses the discontinuous, external, data clock during the sampling period. Data must be read during the sampling period because there is not sufficient time to read data from multiple converters during a conversion period without violating the td11 constraint (see the EXTERNAL DATACLOCK section). The sampling period must be sufficiently long to allow all data words to be read before starting a new conversion. Note, in Figure 40, that a NULL bit separates the data word from each converter. The state of the DATA pin at the end of a READ cycle reflects the state of the TAG pin at the start of the cycle. This is true in all READ modes, including the internal clock mode. For example, when a single converter is used in the internal clock mode the state of the TAG pin determines the state of the DATA pin after all 12 bits have shifted out. When multiple converters are cascaded together this state forms the NULL bit that separates the words. Thus, with the TAG pin of the first converter grounded as shown in Figure 40 the NULL bit becomes a zero between each data word. Processor ADS8506A TAG DATA CS R/C DATACLK ADS8506B TAG DATA CS R/C DATACLK TAG(A) D Null Q D A00 Q D A11 Q D A12 Q SDATA (A) SCLK GPIO GPIO SDI TAG(B) DATACLK Null D Q D B00 Q D B11 Q D B12 Q SDATA (B) R/C (both A & B) BUSY (both A & B) SYNC (both A & B) External DATACLK 1 2 3 4 12 13 14 15 16 17 26 27 28 SDATA ( A ) A11 B11 A10 A9 A01 A00 B00 SDATA ( B ) B10 B9 B01 Null TAG(A) = 0 A Nth Conversion Data Null A11 A10 A9 B A01 A00 Null A TAG(A) = 0 EXT/INT tied high, CS of both converter A and B, TAG input of converter A are tied low. . Figure 40. Timing of TAG Feature With Single Conversion (Using External DATACLK) INPUT RANGES The ADS8506 offers three input ranges: standard ±10-V and 0-V to 5-V ranges, and a 0-V to 4-V range for complete, single-supply systems. See Figure 42 and Figure 43 for the necessary circuit connections for implementing each input range and optional offset and gain adjust circuitry. Offset and full-scale error specifications are tested with the fixed resistors, see Figure 43 (full-scale error includes offset and gain errors measured at both +FS and -FS). Adjustments for offset and gain are described in the Calibration section of this data sheet. The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors compensate for this adjustment and can be left out if the offset and gain are corrected in software (refer to the Calibration section). The input impedance, summarized in Table 1, results from the combination of the internal resistor network (see the front page of this product data sheet) and the external resistors used for each input range (see Figure 44). The input resistor divider network provides inherent over-voltage protection to at least ±5.5 V for R2IN and ±12 V for R1IN. Analog inputs above or below the expected range yields either positive full-scale or negative full-scale digital outputs, respectively. Wrapping or folding over for analog inputs outside the nominal range does not occur. 20 Submit Documentation Feedback Product Folder Link(s): ADS8506 Copyright © 2007, Texas Instruments Incorporated ADS8506 www.ti.com SLAS484A – SEPTEMBER 2007 – REVISED OCTOBER 2007 +15V 2.2 mF 22 pF 200 W 2 kW Pin 7 2 kW Vin 22 pF Pin3 Pin 2 Pin 1 100 W − OPA 627 or OPA 132 + Pin4 R2IN Pin 6 GND 33.2 kW R3IN CAP GND 2.2 mF 2.2 mF 100 nF GND 2.2 mF AGND2 −V 15 GND REF DGND GND AGND1 ADS8506 R1IN 100 nF GND Figure 41. Typical Driving Circuit (±10 V, No Trim) CALIBRATION Hardware Calibration To calibrate the offset and gain of the ADS8506 in hardware, install the resistors shown in Figure 42. Table 7 lists the hardware trim ranges relative to the input for each input range. Table 7. Offset and Gain Adjust Ranges for Hardware Calibration (see Figure 42) INPUT RANGE ±10 V 0 V to 5 V 0 V to 4 V ±10 V 200 Ω 1 2 OFFSET ADJUST RANGE (mV) ±15 ±4 ±3 0 V to 5 V 200 Ω R1IN AGND1 33.2 kΩ VIN +5 V CAP 50 kΩ REF AGND2 50 kΩ 1 R1IN 2 3 R2IN 100 Ω + 4 5 6 AGND1 R2IN GAIN ADJUST RANGE (mV) ±60 ±30 ±30 0 V to 4 V 33.2 kΩ 200 Ω 2 VIN 3 +5 V 100 Ω 50 kΩ 2.2 µF + 4 5 6 1 R1IN AGND1 R2IN CAP REF AGND2 VIN 3 33.2 kΩ 100 Ω + 5 V 2.2 µF 50 kΩ 1 MΩ 2.2 µF + 6 + 5 50 kΩ 4 2.2 µF CAP REF AGND2 + 1 MΩ 2.2 µF 50 kΩ + 1 MΩ 2.2 µF +5V Figure 42. Circuit Diagrams (With Hardware Trim) Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS8506 21 ADS8506 SLAS484A – SEPTEMBER 2007 – REVISED OCTOBER 2007 www.ti.com Software Calibration To calibrate the offset and gain in software, no external resistors are required. However, to get the data sheet specifications for offset and gain, the resistors shown in Figure 43 are necessary. See the No Calibration section for more details on the external resistors. Refer to Table 8 for the range of offset and gain errors with and without the external resistors. ±10 V 200 Ω 1 2 66.5 kΩ +5V 100 Ω 2.2 µF + 2.2 µF 6 + 5 0 V to 5 V 200 Ω R1IN AGND1 33.2 kΩ VIN 1 R1IN 2 3 R2IN CAP 2.2 µF REF AGND2 2.2 µF 100 Ω + 5 + 6 4 AGND1 R2IN CAP 0 V to 4 V 33.2 kΩ 200 Ω 2 VIN 3 100 Ω 2.2 µF REF AGND2 2.2 µF + 5 + 6 4 1 R1IN AGND1 R2IN CAP REF AGND2 VIN 3 4 Figure 43. Circuit Diagrams (Without Hardware Trim) Table 8. Range of Offset and Gain Errors With and Without External Resistors INPUT RANGE (V) ±10 0 to 5 0 to 4 (1) High grade OFFSET ERROR WITH RESISTORS RANGE (mV) -10 ≤ BPZ ≤ 10 -3 ≤ UPO ≤ 3 -3 ≤ UPO ≤ 3 WITHOUT RESISTORS RANGE (mV) 0 ≤ BPZ ≤ 35 -12 ≤ UPO ≤ -3 -10.5 ≤ UPO ≤ -1.5 TYP (mV) 15 -7.5 -6 WITH RESISTORS RANGE (% FS) -0.4 ≤ G ≤ 0.4 0.15 ≤ G (1) GAIN ERROR WITHOUT RESISTORS RANGE (% FS) -0.3 ≤ G ≤ 0.5 -0.1 ≤ G (1) TYP 0.05 0.05 -0.2 -0.2 -0.2 -0.2 ≤ 0.15 ≤ 0.2 -0.4 ≤ G ≤ 0.4 0.15 ≤ G (1)≤ 0.1 -0.4 ≤ G ≤ 0.4 -0.15 ≤ G (1)≤ 0.15 -1.0 ≤ G ≤ 0.1 -0.55 ≤ G (1)≤ -0.05 -1.0 ≤ G ≤ 0.1 -0.55 ≤ G (1)≤ -0.05 No Calibration Figure 43 shows circuit connections. Note that the actual voltage dropped across the external resistors is at least two orders of magnitude lower than the voltage dropped across the internal resistor divider network. This should be considered when choosing the accuracy and drift specifications of the external resistors. In most applications, 1% metal-film resistors are sufficient. The external resistors, see Figure 43, may not be necessary in some applications. These resistors provide compensation for an internal adjustment of the offset and gain which allows calibration with a single supply. Not using the external resistors results in offset and gain errors in addition to those listed in the electrical characteristics section. Offset refers to the equivalent voltage of the digital output when converting with the input grounded. A positive gain error occurs when the equivalent output voltage of the digital output is larger than the analog input. Refer to Table 8 for nominal ranges of gain and offset errors with and without the external resistors. Refer to Figure 44 for typical shifts in the transfer functions which occur when the external resistors are removed. 22 Submit Documentation Feedback Product Folder Link(s): ADS8506 Copyright © 2007, Texas Instruments Incorporated ADS8506 www.ti.com SLAS484A – SEPTEMBER 2007 – REVISED OCTOBER 2007 (a) Bipolar Digital Output + Full-Scale (b) Unipolar Digital Output + Full-Scale Analog Input − Full-Scale Analog Input − Full-Scale Typical Transfer Functions With External Resistors. Typical Transfer Functions Without External Resistors. Figure 44. Typical Transfer Functions With and Without External Resistors To further analyze the effects of removing any combination of the external resistors, consider Figure 45. The combination of the external and the internal resistors form a voltage divider which reduces the input signal to a 0.3125-V to 2.8125-V input range at the capacitor digital-to-analog converter (CDAC). The internal resistors are laser trimmed to high relative accuracy to meet full-scale specifications. The actual input impedance of the internal resistor network looking into pin 1 or pin 3 however, is only accurate to ±20% due to process variations. This should be taken into account when determining the effects of removing the external resistors. 200 Ω VIN 33.5 kΩ +5V 100 Ω + 2.5 V 200 Ω 33.5 kΩ VIN 100 Ω + 2.5 V 200 Ω VIN 33.5 kΩ 100 Ω + 2.5 V 9.9 kΩ 20 kΩ 40 kΩ 39.8 kΩ CDAC (0.3125 V to 2.8125 V) 39.8 kΩ 9.9 kΩ CDAC (0.3125 V to 2.8125 V) 20 kΩ 40 kΩ 9.9 kΩ 20 kΩ 40 kΩ 39.8 kΩ CDAC (0.3125 V to 2.8125 V) + 2.5 V + 2.5 V + 2.5 V Figure 45. Circuit Diagrams Showing External and Internal Resistors Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS8506 23 ADS8506 SLAS484A – SEPTEMBER 2007 – REVISED OCTOBER 2007 www.ti.com REFERENCE The ADS8506 can operate with its internal 2.5-V reference or an external reference. By applying an external reference to pin 5, the internal reference can be bypassed. The reference voltage at REF is buffered internally with the output on CAP (pin 4). The internal reference has an 8 ppm/°C drift (typical) and accounts for approximately 20% of the full-scale error (FSE = ±0.5% for low grade, ±0.25% for high grade). The ADS8506 also has an internal buffer for the reference voltage. Figure 46 shows characteristic impedances at the input and output of the buffer with all combinations of powerdown and reference down. ZCAP CAP (Pin 4) CDAC Buffer ZREF REF (Pin 5) PWRD 0 REFD 0 1 6k PWRD 0 REFD 1 1 100 M Internal Reference ZCAP Ω ZREF Ω PWRD 1 REFD 0 200 6k PWRD 1 REFD 1 200 100 M Figure 46. Characteristic Impedances of the Internal Buffer REF REF (pin 5) is an input for an external reference or the output for the internal 2.5-V reference. A 2.2-μF tantalum capacitor should be connected as close as possible to the REF pin from ground. This capacitor and the output resistance of REF create a low-pass filter to bandlimit noise on the reference. Using a smaller value capacitor will introduce more noise to the reference, degrading the SNR and SINAD. The REF pin should not be used to drive external AC or DC loads, as shown in Figure 46. The range for the external reference is 2.3 V to 2.7 V and determines the actual LSB size. Increasing the reference voltage increases the full-scale range and the LSB size of the converter which can improve the SNR. CAP CAP (pin 4) is the output of the internal reference buffer. A 2.2-μF tantalum capacitor should be placed as close as possible to the CAP pin from ground to provide optimum switching currents for the CDAC throughout the conversions cycle. This capacitor also provides compensation for the output of the buffer. Using a capacitor any smaller than 1 μF can cause the output buffer to oscillate and may not have sufficient charge for the CDAC. Capacitor values larger than 2.2 μF have little affect on improving performance. ESR is the total equivalent series resistance of the compensation capacitor (CAP pin). See Figure 46 and Figure 47. 24 Submit Documentation Feedback Product Folder Link(s): ADS8506 Copyright © 2007, Texas Instruments Incorporated ADS8506 www.ti.com SLAS484A – SEPTEMBER 2007 – REVISED OCTOBER 2007 7000 6000 Power−Up Time − ms 5000 4000 3000 2000 1000 0 0.1 1 10 CAP − Pin Value − mF 100 Figure 47. Power-Down to Power-Up Time vs Capacitor Value on CAP The output of the buffer is capable of driving up to 1 mA of current to a DC load. Using an external buffer allows the internal reference to be used for larger DC loads and AC loads. Do not attempt to directly drive an AC load with the output voltage on CAP. This causes performance degradation of the converter. REFERENCE AND POWER-DOWN The ADS8506 has analog power-down and reference power down capabilities via PWRD (pin 25) and REFD (pin 26), respectively. PWRD and REFD high powers down all analog circuitry maintaining data from the previous conversion in the internal registers, provided that the data has not already been shifted out through the serial port. Typical power consumption in this mode is 50 μW. Power recovery is typically 1 ms, using a 2.2-μF capacitor connected to CAP. Figure 47 shows power-down to power-up recovery time relative to the capacitor value on CAP. With +5 V applied to VDIG, the digital circuitry of the ADS8506 remains active at all times, regardless of PWRD and REFD states. PWRD PWRD high powers down all of the analog circuitry except for the reference. Data from the previous conversion is maintained in the internal registers and can still be read. With PWRD high, a convert command yields meaningless data. REFD REFD high powers down the internal 2.5-V reference. All other analog circuitry, including the reference buffer, is active. REFD should be high when using an external reference to minimize power consumption and the loading effects on the external reference. See Figure 46 for the characteristic impedance of the reference buffer's input for both REFD high and low. The internal reference consumes approximately 5 mW. LAYOUT POWER For optimum performance, tie the analog and digital power pins to the same +5-V power supply and tie the analog and digital grounds together. As noted in the electrical characteristics, the ADS8506 uses 90% of its power for the analog circuitry. The ADS8506 should be considered as an analog component. The +5-V power for the A/D converter should be separate from the +5 V used for the system's digital logic. Connecting VDIG (pin 28) directly to a digital supply can reduce converter performance due to switching noise Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS8506 25 ADS8506 SLAS484A – SEPTEMBER 2007 – REVISED OCTOBER 2007 www.ti.com from the digital logic. For best performance, the +5-V supply can be produced from whatever analog supply is used for the rest of the analog signal conditioning. If +12-V or +15-V supplies are present, a simple +5-V regulator can be used. Although it is not suggested, if the digital supply must be used to power the converter, be sure to properly filter the supply. Either using a filtered digital supply or a regulated analog supply, both VDIG and VANA should be tied to the same +5-V source. GROUNDING Three ground pins are present on the ADS8506. DGND is the digital supply ground. AGND2 is the analog supply ground. AGND1 is the ground to which all analog signals internal to the A/D converter are referenced. AGND1 is more susceptible to current induced voltage drops and must have the path of least resistance back to the power supply. All the ground pins of the A/D converter should be tied to an analog ground plane, separated from the system's digital logic ground, to achieve optimum performance. Both analog and digital ground planes should be tied to the system ground as near to the power supplies as possible. This helps to prevent dynamic digital ground currents from modulating the analog ground through a common impedance to power ground. SIGNAL CONDITIONING The FET switches used for the sample hold on many CMOS A/D converters release a significant amount of charge injection which can cause the driving op amp to oscillate. The amount of charge injection due to the sampling FET switch on the ADS8506 is approximately 5% to 10% of the amount on similar A/D converters with the charge redistribution digital-to-analog converter (DAC) CDAC architecture. There is also a resistive front end which attenuates any charge which is released. The end result is a minimal requirement for the drive capability on the signal conditioning preceding the A/D converter. Any op amp sufficient for the signal in an application will be sufficient to drive the ADS8506. The resistive front end of the ADS8506 also provides a specified ±25-V overvoltage protection. In most cases, this eliminates the need for external over-voltage protection circuitry. INTERMEDIATE LATCHES The ADS8506 does have 3-state outputs for the parallel port, but intermediate latches should be used if the bus is active during conversions. If the bus is not active during conversion, the 3-state outputs can be used to isolate the A/D converter from other peripherals on the same bus. Intermediate latches are beneficial on any monolithic A/D converter. The ADS8506 has an internal LSB size of 38 μV. Transients from fast switching signals on the parallel port, even when the A/D converter is 3-stated, can be coupled through the substrate to the analog circuitry causing degradation of converter performance. 26 Submit Documentation Feedback Product Folder Link(s): ADS8506 Copyright © 2007, Texas Instruments Incorporated ADS8506 www.ti.com SLAS484A – SEPTEMBER 2007 – REVISED OCTOBER 2007 APPLICATION INFORMATION AVERAGING The noise of the converter can be compensated by averaging the digital codes. By averaging conversion results, transition noise is reduced by a factor of 1/√Hz where n is the number of averages. For example, averaging four conversion results reduces the TN by to 0.4 LSBs. Averaging should only be used for input signals with frequencies near DC. For AC signals, a digital filter can be used to low-pass filter and decimate the output codes. This works in a similar manner to averaging: for every decimation by 2, the signal-to-noise ratio improves 3 dB. QSPI™ INTERFACE Figure 48 shows a simple interface between the ADS8506 and any QSPI equipped microcontroller. This interface assumes that the convert pulse does not originate from the microcontroller and that the ADS8506 is the only serial peripheral. Convert Pulse QSPI R/C PCS0/SS MOSI SCK ADS8506 BUSY SDATA DATACLK CS EXT/INT BYTE CPOL = 0 (Inactive State is LOW) CPHA = 1 (Data Valid on Falling Edge) QSPI Port is in Slave Mode. Figure 48. QSPI Interface to the ADS8506 Before enabling the QSPI interface, the microcontroller must be configured to monitor the slave select line. When a transition from low to high occurs on slave select (SS) from BUSY (indicating the end of the current conversion), the port can be enabled. If this is not done, the microcontroller and the A/D converter may be out-of-sync. SPI™ INTERFACE The SPI interface is generally only capable of 8-bit data transfers. For some microcontrollers with SPI interfaces, it might be possible to receive data in a similar manner as shown for the QSPI interface in Figure 48. The microcontroller needs to fetch the 8 most significant bits before the contents are overwritten by the least significant bits. Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS8506 27 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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