ADS850Y/2K

ADS850 ADS 850 SBAS154C – OCTOBER 2000 – REVISED OCTOBER 2002 14-Bit, 10MSPS Self-Calibrating ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● ● ● ● ● ● ● ● ● The ADS850 is a high dynamic range, 14-bit Analog-to-Digital Converter (ADC) that utilizes a fully differential input, allowing for either single-ended or differential input interface over varying input spans. This converter features digital error correction techniques ensuring 14-bit linearity and a calibration procedure that corrects for capacitor and gain mismatches. The ADS850 also includes a high-bandwidth track-and-hold that provides excellent spurious performance up to and beyond the Nyquist rate. SELF-CALIBRATING HIGH SFDR: 85dB at NYQUIST HIGH SNR: 76dB LOW POWER: 250mW DIFFERENTIAL OR SINGLE-ENDED INPUTS +3V/+5V LOGIC I/O COMPATIBLE FLEXIBLE INPUT RANGE OVER-RANGE INDICATOR INTERNAL OR EXTERNAL REFERENCE The ADS850 provides an internal reference that can be programmed for a 2Vp-p input range for the best spurious performance and ease of driving. Alternatively, the 4Vp-p input range can be used for the lowest input referred noise, offering superior signal-to-noise performance for imaging applications. There is also the capability to set the range between 2Vp-p and 4Vp-p, or to use an external reference. The ADS850 also provides an over-range indicator flag to indicate if the input has exceeded the full-scale input range of the converter. APPLICATIONS ● ● ● ● IF AND BASEBAND DIGITIZATION CCD IMAGING SCANNERS TEST INSTRUMENTATION IR IMAGING The low distortion and high signal-to-noise performance provide the extra margin needed for communications, imaging, and test instrumentation applications. The ADS850 is available in a TQFP-48 package. +VS VDRV CLK ADS850 Timing Circuitry VIN IN 14-Bit Pipelined ADC Core T&H IN (Opt.) CM Error Correction Logic and Calibration Circuitry 3-State Outputs OVR Reference Ladder and Driver Reference and Mode Select REFT VREF SEL D0 • • • D13 REFB OE Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) +VS ....................................................................................................... +6V Analog Input ........................................................... (–0.3V) to (+VS +0.3V) Logic Input ............................................................. (–0.3V) to (+VS +0.3V) Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature ..................................................................... +150°C This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DEMO BOARD ORDERING INFORMATION PRODUCT DEMO BOARD ADS850Y ADS850Y-EVM PACKAGE/ORDERING INFORMATION SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS850Y/250 ADS850Y/2K Tape and Reel, 250 Tape and Reel, 2000 PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR(1) ADS850Y TQFP-48 PFB –40°C to +85°C ADS850Y " " " " " NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. ELECTRICAL CHARACTERISTICS At TA = full specified temperature range, VS = +5V, specified differential input range = 1.5V to 3.5V, internal reference input, sampling rate = 10MSPS after calibration, and VREF = 2V, unless otherwise specified. ADS850Y PARAMETER CONDITIONS MIN RESOLUTION SPECIFIED TEMPERATURE RANGE CONVERSION CHARACTERISTICS Sample Rate Data Latency ANALOG INPUT Single-Ended Input Range Differential Input Range Common-Mode Voltage Input Capacitance Analog Input Bandwidth DYNAMIC CHARACTERISTICS Differential Linearity Error (Largest Code Error) f = 4.8MHz No Missing Codes Spurious-Free Dynamic Range(1) f = 4.8MHz (–1dB input) f = 4.8MHz (–1dB input) Signal-to-Noise Ratio (SNR) f = 4.8MHz (–1dB input) f = 4.8MHz (–1dB input) Signal-to-(Noise + Distortion) (SINAD) f = 4.8MHz (–1dB input) f = 4.8MHz (–1dB input) Effective Number of Bits at 4.8MHz(3) Integral Nonlinearity Error f = 4.8MHz Aperture Delay Time Aperture Jitter Overvoltage Recovery Time Full-Scale Step Acquisition Time 2 TYP MAX Bits –40 to +85 °C 10k 10M Samples/s Clk Cycles 3.5 4.5 3.5 V V V V V pF MHz ±1.0 LSB 7 VREF = 1.0 VREF = 2.0 VREF = 2.0 1.5 0.5 1.5 2.5 1 20 270 –3dBFS Input UNITS 14 ±0.75 Tested 4Vp-p 2Vp-p 75 85 82 dBFS(2) dBFS 4Vp-p 2Vp-p 71 76 73 dBFS dBFS 4Vp-p 2Vp-p 70 75 72 12.2 dBFS dBFS Bits 1.5 • FS Input ±2.5 1 4 2 50 ±5.0 LSB ns ps rms ns ns ADS850 www.ti.com SBAS154C ELECTRICAL CHARACTERISTICS (Cont.) At TA = full specified temperature range, VS = +5V, specified differential input range = 1.5V to 3.5V, internal reference input, sampling rate = 10MSPS after calibration, and VREF = 2V, unless otherwise specified. ADS850Y PARAMETER DIGITAL INPUTS Logic Family Convert Command High Level Input Current (VIN = 5V)(4) Low Level Input Current (VIN = 0V) High Level Input Voltage Low Level Input Voltage Input Capacitance DIGITAL OUTPUTS Logic Family Logic Coding Low Output Voltage Low Output Voltage High Output Voltage High Output Voltage 3-State Enable Time 3-State Disable Time Output Capacitance ACCURACY (4Vp-p Input Range) Zero Error (Referred to –FS) Zero Error Drift (Referred to –FS) Gain Error(5) Gain Error Drift(5) Gain Error(6) Gain Error Drift(6) Power-Supply Rejection of Gain Reference Input Resistance Internal Voltage Reference Tolerance (VREF = 2.0V)(7) Internal Voltage Reference Tolerance (VREF = 1.0V)(7) POWER-SUPPLY REQUIREMENTS Supply Voltage: +VS Supply Voltage: VDRV Supply Current: +IS Power Dissipation VDRV = 3V VDRV = 5V VDRV = 3V VDRV = 5V CONDITIONS Start Conversion MIN TYP MAX +3V/+5V Logic Compatible CMOS Rising Edge of Convert Clock 100 ±10 +2.0 +1.0 5 +3V/+5V Logic Compatible CMOS Straight Offset Binary (IOL = 50µA) (IOL = 1.6mA) (IOH = 50µA) (IOH = 0.5mA) OE = LOW OE = HIGH +4.5 +2.4 20 2 5 At 25°C ∆VS = ±5% At 25°C At 25°C Thermal Resistance, θJA TQFP-48 40 10 ±0.2 ±5 ±0.7 ±15 ±0.042 ±15 82 1.6 ±13.5mV ±6mV At 25°C +4.7 +2.7 +5.0 53 240 245 250 255 20 56.5 µA µA V V pF V 0.1 0.4 At 25°C Operating Operating Operating External Reference External Reference Internal Reference Internal Reference Power-Down UNITS V V V V ns ns pF %FS ppm/°C %FS ppm/°C %FS ppm/°C dB kΩ mV mV +5.3 +5.3 275 V V mA mW mW mW mW mW °C/W NOTES: (1) Spurious-Free Dynamic Range refers to the difference in magnitude between the fundamental and the next largest harmonic. (2) dBFS means dB relative to full scale. (3) Effective number of bits (ENOB) is defined by (SINAD – 1.76)/6.02. (4) Internal 50kΩ pull-down resistor. (5) Includes internal reference. (6) Excludes internal reference. (7) Typical reference tolerance based on ±1 sigma of distribution. ADS850 SBAS154C www.ti.com 3 PIN CONFIGURATION IN GND IN GND CBP1 GND REFT CM REFB GND CBP2 TQFP GND Top View 48 47 46 45 44 43 42 41 40 39 38 37 +VS 1 36 +VS +VS 2 35 GND +VS 3 34 VREF +VS 4 33 SEL GND 5 32 GND CLK 6 NC 7 30 BTC MEM_RST 8 29 PD CAL 9 28 OE 31 GND ADS850Y OVR 10 27 GND CAL_BUSY 11 26 VDRV B4 B5 B6 B7 19 20 21 22 23 24 B13 18 B12 17 B11 16 B10 15 B9 14 B8 13 B3 25 B14 (LSB) B2 B1 (MSB) 12 PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 4 I/O I I I O O O O O O O O O O O O O O DESIGNATOR +VS +VS +VS +VS GND CLK NC MEM_RST CAL OVR CAL_BUSY B1 (MSB) B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 (LSB) VDRV DESCRIPTION PIN +5V Supply +5V Supply +5V Supply +5V Supply Ground Convert Clock Input No Connection Memory Reset. When pulsed HIGH, resets memory to zero. Not intended as a function pin, so should be permanently tied to ground. When Pulsed High, puts ADC into Calibration Mode (2 clock cycles). Over Range Indicator Indicates in Calibration Mode. Data Bit 1 (D13) (MSB) Data Bit 2 (D12) Data Bit 3 (D11) Data Bit 4 (D10) Data Bit 5 (D9) Data Bit 6 (D8) Data Bit 7 (D7) Data Bit 8 (D6) Data Bit 9 (D5) Data Bit 10 (D4) Data Bit 11 (D3) Data Bit 12 (D2) Data Bit 13 (D1) Data Bit 14 (D0) (LSB) Output Driver Voltage I/O DESIGNATOR 27 28 I GND OE 29 I PD 30 I BTC I/O GND GND SEL VREF GND +VS CBP2 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 I/O O I/O I I GND REFB CM REFT GND CBP1 GND IN GND IN GND DESCRIPTION Ground Output Enable: HI = High Impedance; LO = Normal Operation (50kΩ Internal Pull-Down Resistor) Power Down: HI = Power Down; LO = Normal Operation (50kΩ Internal Pull-Down Resistor) HI = Binary Two’s Complement (BTC); LO = Straight Offset Binary (SOB) Ground Ground Input Range Select Reference Voltage Select Ground +5V Supply Calibration Reference Bypass 2 (0.1µF ceramic capacitor recommended for decoupling.) Ground Bottom Reference Voltage Bypass Common-Mode Voltage (mid-scale). Not intended for driving a load. Top Reference Voltage Bypass Ground Calibration Reference Bypass 1 (0.1µF ceramic capacitor recommended for decoupling.) Ground Complementary Analog Input (–) Ground Analog Input (+) Ground ADS850 www.ti.com SBAS154C TIMING DIAGRAMS N+2 N+1 Analog In N+4 N+3 N tD N+5 tL tCONV N+6 N+7 tH CLK 7 Clock Cycles t2 Data Out N–7 N–6 N–5 N–4 N–3 N–2 N–1 Data Invalid SYMBOL t CONV tL tH tD t1 t2 N t1 DESCRIPTION MIN Convert Clock Period Clock Pulse LOW Clock Pulse HIGH Aperture Delay Data Hold Time, CL = 0pF New Data Delay Time, CL = 15pF max 100 48 48 TYP MAX UNITS 100µs ns ns ns ns ns ns t CONV /2 t CONV /2 2 3.9 12 TIMING DIAGRAM 1. Pipeline Delay Timing. tS VREF 7 Clock Cycles 32,768 Cycles CLK BUSY Delay Time = 221 Clocks Data Out Data Invalid tS = Time for reference to settle (< 200ms). TIMING DIAGRAM 2. Power-On Calibration Mode Timing. 7 Clock Cycles 32,768 Cycles CLK tP CAL BUSY Data Out Data Invalid Data Valid Calibrated ADC tP = 2 • tCONV TIMING DIAGRAM 3. Calibration-On-Demand Mode Timing. CLK tP RST Data Out Uncalibrated ADC TIMING DIAGRAM 4. Reset Mode Timing. ADS850 SBAS154C www.ti.com 5 TYPICAL CHARACTERISTICS At TA = full specified temperature range, VS = +5V, specified input range = 1.5V to 3.5V, differential internal reference input and sampling rate = 10MSPS after calibration, VREF = 2V, –1dB input, unless otherwise specified. SPECTRAL PERFORMANCE (2Vp-p, Differential, fIN = 4.8MHz) SPECTRAL PERFORMANCE (4Vp-p, Differential, fIN = 4.8MHz) 0 0 SFDR = 89dBFS SNR = 76dBFS –10 –30 Amplitude (dB) Amplitude (dB) –30 –50 –70 –110 –110 –130 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 5 0.5 1 1.5 2 2.5 3 3.5 Frequency (MHz) Frequency (MHz) SPECTRAL PERFORMANCE (2Vp-p, Single-Ended, fIN = 4.8MHz) SPECTRAL PERFORMANCE (4Vp-p, Differential, fIN = 1MHz) 0 4 4.5 5 0 SFDR = 85dBFS SNR = 73dBFS –10 SFDR = 82dBFS SNR = 76dBFS –10 –30 –30 Amplitude (dB) Amplitude (dB) –70 –90 0 –50 –70 –90 –110 –50 –70 –90 –110 –130 –130 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 Frequency (MHz) Frequency (MHz) SPECTRAL PERFORMANCE (2Vp-p, Single-Ended, fIN = 1MHz) UNDERSAMPLING (Differential, 4Vp-p) 0 3.5 4 4.5 5 0 SFDR = 87dBFS SNR = 73dBFS –10 fS = 3.2MHz fIN = 10MHz SFDR = 87dBFS SNR = 73dBFS –20 Amplitude (dBFS) –30 Amplitude (dB) –50 –90 –130 –50 –70 –90 –110 –40 –60 –80 –100 –120 –130 –140 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 Frequency (MHz) 6 SFDR = 88dBFS SNR = 73dBFS –10 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Frequency (MHz) ADS850 www.ti.com SBAS154C TYPICAL CHARACTERISTICS (Cont.) At TA = full specified temperature range, VS = +5V, specified input range = 1.5V to 3.5V, differential internal reference input and sampling rate = 10MSPS after calibration, VREF = 2V, –1dB input, unless otherwise specified. DIFFERENTIAL LINEARITY ERROR INTEGRAL LINEARITY ERROR 1 4 fIN = 4.8MHz 3 0.5 2 0.25 1 ILE (LSB) DLE (LSB) fIN = 4.8MHz 0.75 0 –0.25 0 –1 –0.5 –2 –0.75 –3 –1 –4 0 4096 8192 12288 16384 0 4096 8192 Code 12288 16384 Code OUTPUT NOISE HISTOGRAM (4Vp-p) SFDR vs TEMPERATURE 9k 95 8k fIN = 4.8MHz 7k SFDR (dB) Counts 6k 5k 4k 3k 90 85 2k fIN = 500kHz 1k 0k 80 N–1 N –45 N+1 –25 –5 15 35 55 75 95 Temperature (°C) Codes THD vs INPUT FREQUENCY SINAD vs TEMPERATURE 110 85 90 80 THD (dB) SINAD (dB) 100 fIN = 4.8MHz 80 70 75 fIN = 500kHz 60 50 70 –45 –25 –5 15 35 55 75 0 95 2 3 4 5 Input Frequency (MHz) Temperature (°C) ADS850 SBAS154C 1 www.ti.com 7 TYPICAL CHARACTERISTICS (Cont.) At TA = full specified temperature range, VS = +5V, specified input range = 1.5V to 3.5V, differential internal reference input and sampling rate = 10MSPS after calibration, VREF = 2V, –1dB input, unless otherwise specified. SINAD vs INPUT FREQUENCY 110 350 100 90 300 SINAD (dB) Power Dissipation (mW) POWER DISSIPATION vs TEMPERATURE 400 250 200 80 70 60 150 50 40 100 –45 –25 –5 15 35 55 75 95 0 1 2 Temperature (°C) 3 4 5 Input Frequency (MHz) SFDR vs INPUT FREQUENCY THD vs CLOCK FREQUENCY 100 110 100 90 80 80 THD (dB) SFDR (dB) 90 70 70 60 50 40 60 30 20 50 10 40 0 0 1 2 3 4 5 0 2 4 Input Frequency (MHz) 8 10 12 14 16 14 16 SFDR vs CLOCK FREQUENCY 110 110 100 100 90 90 80 80 70 70 SFDR (dB) SINAD (dB) SINAD vs CLOCK FREQUENCY 60 50 40 60 50 40 30 30 20 20 10 10 0 0 0 2 4 6 8 10 12 14 16 0 Clock Frequency (MSPS) 8 6 Clock Frequency (MSPS) 2 4 6 8 10 12 Clock Frequency (MSPS) ADS850 www.ti.com SBAS154C TYPICAL CHARACTERISTICS (Cont.) At TA = full specified temperature range, VS = +5V, specified input range = 1.5V to 3.5V, differential internal reference input and sampling rate = 10MSPS after calibration, VREF = 2V, –1dB input, unless otherwise specified. SWEPT POWER 110 dBFS fIN = 4.8MHz SFDR (dBc, dBFS) 100 90 80 70 dBc 60 50 40 30 –60 –50 –40 –30 –20 –10 0 Input Amplitude (dBFS) APPLICATION INFORMATION AC-COUPLED INPUT CONFIGURATION DRIVING THE ANALOG INPUT The ADS850 allows its analog inputs to be driven either single-ended or differentially. The focus of the following discussion is on the single-ended configuration. CALIBRATION PROCEDURE The calibration procedure (CAL) is started by a positive pulse, with a minimum width of 2 clock cycles. Once calibration is initiated, the clock must operate continuously and the power supplies and references must remain stable. The calibration registers are reset on the rising edge of the CAL signal. The actual calibration procedure begins at the falling edge of the CAL signal. Calibration is completed at the end of 32,775 cycles at 10MSPS, CAL = 3.28ms (see Timing Diagram 3 on page 5). During calibration, the CAL_BUSY signal stays HIGH and the digital output pins of the ADC are forced to zero. Also, during calibration, the inputs (IN and IN) are disabled. When the calibration procedure is complete, the CAL_BUSY goes LOW. Valid data appears at the output seven cycles later or after a total of 32,775 clock cycles. If there are any changes to the clock or the temperature changes more than ±20°C, the ADC should be re-calibrated to maintain performance. At power-on (see Timing Diagram 2 on page 5), the ADC calibrates itself. The power-on delay, tS, is the time it takes for the reference voltage to settle. Once the clock starts, the power-on delay operates for 221 clock cycles. Bypass capacitors should be selected to allow the reference to settle within 200ms. If the system is noisy or external references require a longer settling time, a CAL pulse may be required. See Figure 1 for the circuit example of the most common interface configuration for the ADS850. With the VREF pin connected to the SEL pin, the full-scale input range is defined to be 2Vp-p. This signal is ac-coupled in single-ended form to the ADS850 using the low distortion voltage-feedback amplifier OPA642. As is generally necessary for singlesupply components, operating the ADS850 with a full-scale input signal swing requires a level-shift of the amplifier’s zero-centered analog signal to comply with the ADC’s input range requirements. Using a DC blocking capacitor between the output of the driving amplifier and the converter’s input, a simple level-shifting scheme can be implemented. In this configuration, the top and bottom references (REFT, REFB) provide an output voltage of +3V and +2V, respectively. Here, two resistor pairs of 2 • 2kΩ are used to create a common-mode voltage of approximately +2.5V to bias the inputs of the ADS850 (IN, IN) to the required DC voltage. An advantage of ac-coupling is that the driving amplifier still operates with a ground-based signal swing. This will keep the distortion performance at its optimum since the signal swing stays centered within the linear region of the op amp and sufficient headroom to the supply rails can be maintained. Consider using the inverting gain configuration to eliminate CMR induced errors of the amplifier. The addition of a small series resistor (RS) between the output of the op amp and the input of the ADS850 will be beneficial in almost all interface configurations. This will decouple the op amp’s output from the capacitive load and avoid gain peaking, which can result in increased noise. For best spurious and distortion performance, the resistor value should be kept below 100Ω. Furthermore, the series resistor together with the 100pF capacitor establish a passive low-pass filter, limiting the bandwidth for the wideband noise, thus help improving the SNR performance. ADS850 SBAS154C www.ti.com 9 +5V –5V 2Vp-p VIN +VIN 2kΩ RS 24.9Ω 0.1µF REFT (+3V) 2kΩ IN OPA642 0V 100pF –VIN RF 402Ω ADS850 2kΩ RG 402Ω +2.5VDC IN 0.1µF (+2V) REFB 2kΩ (+1V) VREF SEL FIGURE 1. AC-Coupled Input Configuration for 2Vp-p Input Swing and Common-Mode Voltage at +2.5V Derived from Internal Top and Bottom Reference. DC-COUPLED WITHOUT LEVEL SHIFT In some applications the analog input signal may already be biased at a level which complies with the selected input range and reference level of the ADS850. In this case, it is only necessary to provide an adequately low source impedance to the selected input, IN or IN. Always consider wideband op amps since their output impedance will stay low over a wide range of frequencies. For those applications requiring the driving amplifier to provide a signal amplification, with a gain ≥ 3, consider using the decompensated voltage feedback op amp OPA686. DC-COUPLED WITH LEVEL SHIFT Several applications may require that the bandwidth of the signal path include DC, in which case the signal has to be DCcoupled to the ADC. In order to accomplish this, the interface circuit has to provide a DC-level shift. The circuit shown in Figure 2 employs an op amp, OPA681, to sum the ground centered input signal with a required DC offset. The ADS850 typically operates with a +2.5V common-mode voltage, which is established at the center tap of the ladder and connected to the IN input of the converter. The OPA681 operates in inverting configuration. Here resistors R1 and R2 set the DCbias level for the OPA691. Because of the op amp’s noise gain of +2V/V, assuming RF = RIN, the DC offset voltage applied to its noninverting input has to be divided down to +1.25V, resulting in a DC output voltage of +2.5V. DC voltage differences between the IN and IN inputs of the ADS850 effectively will produce an offset, which can be corrected for by adjusting the values of resistors R1 and R2. The bias current of the op amp may also result in an undesired offset. The selection criteria of the appropriate op amp should include the input bias current, output voltage swing, distortion and noise specification. Note that in this example the overall signal phase is inverted. To re-establish the original signal polarity, it is always possible to interchange the IN and IN connections. RF RIN +1V 0 +VS VIN REFT 2kΩ RS 24.9Ω IN OPA691 –1V 2Vp-p 100pF R1 ADS850 R2 +VS +2.5V + 0.1µF 10µF IN 0.1µF REFB (+1V) VREF SEL 2kΩ NOTE: RF = RIN, G = –1 FIGURE 2. DC-Coupled, Single-Ended Input Configuration with DC-level Shift. 10 ADS850 www.ti.com SBAS154C SINGLE-ENDED-TO-DIFFERENTIAL CONFIGURATION (TRANSFORMER COUPLED) REFERENCE OPERATION In order to select the best suited interface circuit for the ADS850, the performance requirements must be known. If an ac-coupled input is needed for a particular application, the next step is to determine the method of applying the signal; either single-ended or differentially. The differential input configuration may provide a noticeable advantage of achieving good SFDR performance based on the fact that in the differential mode, the signal swing can be reduced to half of the swing required for single-ended drive. Secondly, by driving the ADS850 differentially, the even-order harmonics will be reduced. Figure 3 shows the schematic for the suggested transformer-coupled interface circuit. The resistor across the secondary side (RT) should be set to get an input impedance match (e.g., RT = n2 • RG). Integrated into the ADS850 is a bandgap reference circuit including logic that provides either a +1V or +2V reference output, by simply selecting the corresponding pin-strap configuration. For more design flexibility, the internal reference can be shut off and an external reference voltage used. Table I provides an overview of the possible reference options and pin configurations. MODE INPUT RANGE SEL VREF REFB REFT NC Internal 2Vp-p VREF SEL NC Internal 4Vp-p GND NC NC NC External 2V < FSR < 4V +VS 1V < FSR < 2V NC NC +VS GND External (REFB – REFT) • 2 1.5V < REFB < 2V 2V < REFT