ADS8686SIPZAR

Order Now Product Folder Support & Community Tools & Software Technical Documents ADS8686S SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 ADS8686S 16-Channel, 16-Bit, 1-MSPS, Dual, Simultaneous Sampling ADC with Integrated Analog Front-End 1 Features 3 Description • The ADS8686S is a 16-channel data acquisition (DAQ) system based on a dual simultaneoussampling, 16-bit successive approximation register (SAR) analog-to-digital converter (ADC). The ADS8686S features a complete analog front-end for each channel with an input clamp, 1-MΩ input impedance, independently programmable gain amplifier (PGA), programmable low-pass filter, and an ADC input driver. The device also features a low-drift, precision reference with a buffer to drive the ADCs. A flexible digital interface supporting serial, parallel, and byte communication enables the device to be used with a variety of host controllers. 1 • • • • • • • • • • • • 16-channel, 16-bit ADC with integrated analog front-end Dual simultaneous sampling: 8x2 channels Supply: – Analog: 5 V – Digital: 1.8 V to 5 V Constant 1-MΩ input impedance front-end Independently programmable input ranges with 20% overrange Programmable low-pass filter: – 15 kHz, 39 kHz, 376 kHz Excellent DC and AC performance On-chip reference and reference buffer Excellent over temperature performance Overvoltage input clamp with 8-kV ESD Optional cyclic redundancy check (CRC) error checking On-chip self diagnostic function Temperature range: –40°C to +125°C The ADS8686S can be configured to accept ±10-V, ±5-V, or ±2.5-V bipolar inputs with a 20% overrange option using a single 5-V supply. The high input impedance allows direct connection with sensors and transformers, thus eliminating the need for external driver circuits. The ADS8686S has a highly configurable channel sequencer to reduce the sequencing overhead on the backend controller or processor. The high performance and accuracy, along with zero-latency conversions offered by this device make the ADS8686S a great choice for multiple industrial applications. 2 Applications • • • • Device Information(1) Multifunction relays Servo drive position sensors Analog input modules Data acquisition (DAQ) PART NUMBER ADS8686S PACKAGE LQFP (80) BODY SIZE (NOM) 14.00 mm x 14.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Device Block Diagram AVDD AIN_nA Clamp AIN_nAGND Clamp 1M PGA 1M 2nd Order PROG LPF REFCAP REFIO 2.5 V REF ADC Driver 9:1 MUX CH7A AIN_nB Clamp AIN_nBGND Clamp PGA 1M 2nd Order PROG LPF AGND ALDO DLDO Dual Simultaneous Sampling SER/BYTE/PAR Serial - Parallel Byte Interface SDOx/SDI Digital OSR Filter SER1W OSR Channel Sequencer RESET CH7B ADS8686S 16-BIT SAR ADC Driver CH0B AVDD ALDO DB[15:0] CH0A 1M REFSEL REGCAP REGCAPD DVDD 2:1 MUX 9:1 MUX 16-BIT SAR Burst Capture CONVST CRC BUSY Self Diagnosys DGND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADS8686S SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 7 1 1 1 2 3 6 Absolute Maximum Ratings ...................................... 6 ESD Ratings.............................................................. 6 Recommended Operating Conditions....................... 7 Thermal Information .................................................. 7 Electrical Characteristics........................................... 7 Timing Requirements .............................................. 14 Switching Characteristics ........................................ 15 Timing Specifications: Universal ............................ 17 Timing Requirements: Parallel Data Read.............. 19 Timing Requirements: Serial Data Read .............. 20 Typical Characteristics .......................................... 21 Detailed Description ............................................ 28 7.1 Overview ................................................................. 28 7.2 Functional Block Diagram ....................................... 28 7.3 Feature Description................................................. 29 7.4 Device Functional Modes........................................ 37 7.5 Programming........................................................... 56 7.6 Register Maps ......................................................... 62 8 Application and Implementation ........................ 90 8.1 Application Information............................................ 90 8.2 Typical Applications ................................................ 90 9 Power Supply Recommendations...................... 94 9.1 Power Supplies ....................................................... 94 10 Layout................................................................... 95 10.1 Layout Guidelines ................................................. 95 10.2 Layout Examples................................................... 95 11 Device and Documentation Support ................. 96 11.1 11.2 11.3 11.4 11.5 11.6 11.7 Device Support...................................................... Documentation Support ....................................... Receiving Notification of Documentation Updates Support Resources ............................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 96 96 96 96 96 96 96 12 Mechanical, Packaging, and Orderable Information ........................................................... 96 4 Revision History Changes from Revision B (May 2020) to Revision C • Changed AC performance parameters................................................................................................................................. 11 Changes from Revision A (March 2020) to Revision B • 2 Page Page Changed device status from advance information to production data .................................................................................. 1 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S ADS8686S www.ti.com SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 5 Pin Configuration and Functions AIN_3BGND AIN_3B AIN_2BGND AIN_2B AIN_1BGND AIN_1B AIN_0BGND AIN_0B AGND AVDD REGCAP REGGND CONVST BUSY CHSEL2 CHSEL1 CHSEL0 CS SCLK/RD WR/BURST PM Package: PZA 80-Pin LQFP Top View 80 7978 77 76 75 7473 72 71 70 69 68 6766 6564 63 62 61 AIN_4BGND AIN_4B AIN_5BGND AIN_5B AGND AVDD AIN_6B AIN_6BGND AIN_7B AIN_7BGND AIN_7AGND AIN_7A AIN_6AGND AIN_6A AVDD AGND AIN_5A AIN_5AGND AIN_4A AIN_4AGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ADS8686S TOP VIEW (Not to Scale) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 DB15/0S2 DB14/0S1 DB13/0S0 DB12/SDOA DB11/SDOB DB10/SDI DB9/BYTESEL DB8 REGCAPD REGGNDD DGND DVDD DB7 DB6 DB5/CRCEN DB4/SER1W DB3 DB2 DB1 DB0 AIN_3AGND AIN_3A AIN_2AGND AIN_2A AIN_1AGND AIN_1A AIN_0AGND AIN_0A AGND AVDD REFCAP REFGND REFIO REFIO_GND REFSEL RESET SEQEN HW_RNGSEL1 HW_RNGSEL0 SER/BYTE/PAR 21 22 23 24 25 26 27 28 29 30 31 32 3334 35 36 373839 40 Pin Functions NAME AGND NO. TYPE (1) DESCRIPTION 5, 16, 29, 72 P Analog supply ground pins AIN_0AGND 27 AI Analog input channel 0A: negative input AIN_0A 28 AI Analog input channel 0A: positive input AIN_0BGND 74 AI Analog input channel 0B: negative input AIN_0B 73 AI Analog input channel 0B: positive input AIN_1AGND 25 AI Analog input channel 1A: negative input AIN_1A 26 AI Analog input channel 1A: positive input AIN_1BGND 76 AI Analog input channel 1B: negative input AIN_1B 75 AI Analog input channel 1B: positive input AIN_2AGND 23 AI Analog input channel 2A: negative input AIN_2A 24 AI Analog input channel 2A: positive input AIN_2BGND 78 AI Analog input channel 2B: negative input AIN_2B 77 AI Analog input channel 2B: positive input AIN_3AGND 21 AI Analog input channel 3A: negative input AIN_3A 22 AI Analog input channel 3A: positive input AIN_3BGND 80 AI Analog input channel 3B: negative input AIN_3B 79 AI Analog input channel 3B: positive input AIN_4AGND 20 AI Analog input channel 4A: negative input (1) AI = analog input, AO = analog output, AIO = analog input/output, DI = digital input, DO = digital output, DIO = digital input/output, P = power supply. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S 3 ADS8686S SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 www.ti.com Pin Functions (continued) NAME NO. TYPE (1) DESCRIPTION AIN_4A 19 AI Analog input channel 4A: positive input AIN_4BGND 1 AI Analog input channel 4B: negative input AIN_4B 2 AI Analog input channel 4B: positive input AIN_5AGND 18 AI Analog input channel 5A: negative input AIN_5A 17 AI Analog input channel 5A: positive input AIN_5BGND 3 AI Analog input channel 5B: negative input AIN_5B 4 AI Analog input channel 5B: positive input AIN_6AGND 13 AI Analog input channel 6A: negative input AIN_6A 14 AI Analog input channel 6A: positive input AIN_6BGND 8 AI Analog input channel 6B: negative input AIN_6B 7 AI Analog input channel 6B: positive input AIN_7AGND 11 AI Analog input channel 7A: negative input AIN_7A 12 AI Analog input channel 7A: positive input AIN_7BGND 10 AI Analog input channel 7B: negative input AIN_7B 9 AI Analog input channel 7B: positive input AVDD 6, 15, 30, 71 P Analog supply pins. Decouple these pins to the closest AGND pins. See the Power Supply Recommendations section. BUSY 67 DO Logic output indicating an ongoing conversion; see the BUSY (Output) section. CHSEL0 64 DI Logic input pin to select the channel or program the hardware mode sequencer; see the CHSEL[2:0] (Input) section. CHSEL1 65 DI Logic input pin to select the channel or program the hardware mode sequencer; see the CHSEL[2:0] (Input) section. CHSEL2 66 DI Logic input pin to select the channel or program the hardware mode sequencer; see the CHSEL[2:0] (Input) section. CONVST 68 DI Logic input to control the conversion start input for channel group A and channel group B; see the CONVST (Input) section. CS 63 DI Active low logic input chip select; see the CS (Input) section. DB0 41 DIO This pin is the data input/output DB0 (LSB) in parallel and parallel byte interface modes. In serial mode, this pin must be connected to DGND. See the DB[3:0] (Input/Output) section. DB1 42 DIO This pin is the data input/output DB1 in parallel and parallel byte interface modes. In serial mode, this pin must be connected to DGND. See the DB[3:0] (Input/Output) section. DB2 43 DIO This pin is the data input/output DB2 in parallel and parallel byte interface modes. In serial mode, this pin must be connected to DGND. See the DB[3:0] (Input/Output) section. DB3 44 DIO This pin is the data input/output DB3 in parallel and parallel byte interface modes. In serial mode, this pin must be connected to DGND. See the DB[3:0] (Input/Output) section. DIO This pin is a multifunctional logic input/output pin. This pin is the data input/output DB4 in parallel and parallel byte interface modes. This pin is the logic input pin in serial mode to configure data capture using both SDOA and SDOB or just SDOA. The signal state is latched on the release of a full RESET, and requires an additional full RESET to be reconfigured. See the DB4/SER1W (Input/Output) section. DB4/SER1W 45 DB5/CRCEN 46 DIO This pin is a multifunctional logic input/output pin. This pin is the data input/output DB5 in parallel and parallel byte interface modes. This pin is the logic input pin in hardware serial mode to enable the cyclic redundancy check (CRC) word. The signal is latched on the release of a full reset, and requires an additional full RESET to be reconfigured. In software mode, this pin must be connected to DGND. See the DB5/CRCEN (Input/Output) section. DB6 47 DIO This pin is the data input/output DB6 in parallel and parallel byte interface modes. See the DB[7:6] (Input/Output) section. DB7 48 DIO This pin is the data input/output DB7 in parallel and parallel byte interface modes. See the DB[7:6] (Input/Output) section. DB8 53 DIO This pin is a multifunctional logic input/output pin. This pin is the data input/output DB8 in parallel interface mode. In serial mode, this pin must be connected to DGND. See the DB8 (Input/Output) section. 4 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S ADS8686S www.ti.com SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 Pin Functions (continued) NAME DB9/BYTESEL DB10/SDI DB11/SDOB DB12/SDOA DB13/OS0 DB14/OS1 NO. 54 55 56 57 58 59 TYPE (1) DESCRIPTION DIO This pin is a multifunctional logic input/output pin. This pin is the data input/output DB9 in parallel interface mode. This pin is the logic input pin that enables the parallel byte interface. The signal is latched on the release of a full RESET, and requires an additional full RESET to be reconfigured. See the DB9/BYTESEL (Input/Output) section. DIO This pin is a multifunctional logic input/output pin. This pin is the data input/output DB10 in parallel interface mode. This pin is the serial data input that programs the device in software serial mode. Tie this pin to DGND for parallel byte interface mode. See the DB10/SDI (Input/Output) section. DIO This pin is a multifunctional logic input/output pin. This pin is the data input/output DB11 in parallel interface mode. This pin is the serial data output port B in serial interface mode if enabled by the DB4/SER1W pin at full RESET. Tie this pin to DGND when in parallel byte interface mode. See the DB11/SDOB (Input/Output) section. DIO This pin is a multifunctional logic input/output pin. This pin is the data input/output DB12 in parallel interface mode. This pin is the serial data output port A in serial interface mode. Tie this pin to DGND when in parallel byte interface mode. See the DB12/SDOA (Input/Output) section. DIO This pin is a multifunctional logic input/output pin. This pin is the data input/output DB13 in parallel interface mode. This pin is the logic input pin for the oversampling rate (OSR) setting. The signal is latched on the release of a full RESET, and requires an additional full RESET to be reconfigured. See the DB13/OS0 (Input/Output) section. DIO This pin is a multifunctional logic input/output pin. This pin is the data input/output DB14 in parallel interface mode. This pin is the logic input pin for the OSR setting. The signal is latched on the release of a full RESET, and requires an additional full RESET to be reconfigured. See the DB14/OS1 (Input/Output) section. This pin is a multifunctional logic input/output pin. This pin is the data input/output DB15 in parallel interface mode. This pin is the logic input pin for the OSR setting. The signal is latched on the release of a full RESET, and requires an additional full RESET to be reconfigured. See the DB15/OS2 (Input/Output) section. DB15/OS2 60 DIO DGND 50 P Digital ground DVDD 49 P Digital supply pin. Decouple with DGND on pin 50 with a minimum 0.1-µF capacitor. 38, 39 DI Hardware and software mode selection inputs. Hardware and software mode selection is latched at full reset. In hardware mode, these pins select the input range and are not latched. In software mode, these pins are latched and ignored until the next RESET event. HW_RNGSELx = 00: software mode; the ADS8686S is configured via the software registers. HW_RNGSELx = 01: hardware mode; the analog input range is ±2.5 V. HW_RNGSELx = 10: hardware mode; the analog input range is ±5 V. HW_RNGSELx = 11: hardware mode; the analog input range is ±10 V. See the HW_RANGESEL[1:0] (Input) section. REFCAP 31 AO Reference amplifier output pin. This pin must be decoupled to REFGND using a low equivalent series resistance (ESR), 10-µF ceramic capacitor. Place this capacitor as close to the REFCAP pin as possible. Do not drive any external load from this pin. REFGND 32 P REFIO 33 AIO REFIO_GND 34 P REFIO ground. Connect this pin to the AGND plane with the shortest trace possible. REFSEL 35 DI Active high logic input to enable the internal reference. See the REFSEL (Input) section. REGCAP 70 P Voltage output from the internal analog regulator. Decouple this output pin separately to REGGND using a 10-µF capacitor. Place the capacitor close to the REGCAP pin. REGCAPD 52 P Voltage output from the internal digital regulator. Decouple this output pin separately to REGGNDD using a 10-µF capacitor. Place the capacitor close to the REGCAPD pin. REGGND 69 P Internal analog regulator GND. Connect this pin to the AGND plane with the shortest trace possible. REGGNDD 51 P Internal digital regulator GND. Connect this pin to the DGND plane with the shortest trace possible. RESET 36 DI Active low logic input to reset the device digital logic. The duration of the RESET pulse decides the partial or full RESET of the device. See the RESET (Input) section. HW_RNGSEL1, HW_RNGSEL0 Reference GND. Connect this pin to the AGND plane with the shortest trace possible. This pin acts as an internal reference output when REFSEL is high. This pin functions as an input pin for the external reference when REFSEL is low. Decouple this pin with REFIO_GND on pin 34 using a 0.1-µF capacitor. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S 5 ADS8686S SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 www.ti.com Pin Functions (continued) NAME NO. TYPE (1) DESCRIPTION SCLK/RD 62 DI This pin is a multifunctional logic input pin. This pin is the logic input pin for the Serial Clock in serial interface mode. This pin is the logic input pin in parallel and parallel byte interface modes. When both CS and RD are logic low in parallel and parallel byte modes, the output bus is enabled. See the SCLK/RD (Input) section. SEQEN 37 DI Active high logic input to enable the channel sequencer in hardware mode. The state is latched with a device full RESET. Tie this pin to DGND in software mode. See the SEQEN (Input) section. DI Logic input to select between serial, parallel byte, or parallel interface mode. Tie this pin to logic high and DB9/BYTESEL to logic low to select the serial interface mode. Tie this pin to logic high and DB9/BYTESEL to logic high to select the parallel BYTE interface mode. Tie this pin to logic low to select the parallel interface mode. The signal state is latched at full RESET, and requires an additional full RESET to be reconfigured. See the SER/BYTE/PAR (Input) section. DI This pin is a multifunctional logic input pin (see the WR/BURST (Input) section). WR is the logic input pin to write the register configuration in software parallel and parallel byte interface modes. BURST is the logic input pin to enable burst mode operation in the hardware mode of operation. The signal is latched on the release of a full RESET, and requires an additional full RESET to be reconfigured; see the Burst Sequencer section. Tie this pin to DGND when in software serial mode. SER/BYTE/PAR WR/BURST 40 61 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX AVDD to AGND –0.3 7 V DVDD to DGND –0.3 7 V AGND to DGND –0.3 0.3 V REFGND to AGND –0.3 0.3 V AINxP to AGND –15 15 V AINxGND to AGND –15 15 V REFCAPA, REFCAPB to REFGND –0.3 5.5 V REFIO to AGND –0.3 5.5 V Digital input to DGND –0.3 DVDD+0.3 V –0.3 DVDD+0.3 –10 10 mA Operating temperature –40 125 °C Storage temperature –65 150 °C Digital output to DGND Input current to any pin except supply pins (1) (2) (2) UNIT V Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Pin current input or output must be limited to 10 mA or less. 6.2 ESD Ratings VALUE V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) (1) (2) 6 All pins except analog inputs (1) Analog input pins (1) All pins (2) UNIT ±2000 ±8000 V ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S ADS8686S www.ti.com SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT POWER SUPPLY AVDD Analog supply voltage 4.75 5.25 V DVDD Digital supply voltage 1.71 AVDD V Software, hardware selectable range = ±10 V –10 10 Software, hardware selectable range = ±5 V –5 5 Software, hardware selectable range = ±2.5 V –2.5 2.5 Software selectable range = ±10 V with overrange –12 12 Software selectable range = ±5 V with overrange –6 6 Software selectable range = ±2.5 V with overrange –3 3 Software, hardware selectable range = ±10 V –10 10 Software, hardware selectable range = ±5 V –5 5 Software, hardware selectable range = ±2.5 V –2.5 2.5 Software selectable range = ±10 V with overrange –12 12 Software selectable range = ±5 V with overrange –6 6 Software selectable range = ±2.5 V with overrange –3 3 ANALOG INPUTS VFSR AIN_nX Full-scale input range (AIN_xx to AIN_xxGND) (1) Operating input voltage, positive input AIN_nXG Operating input voltage, ND negative input All input ranges V V –0.3 0 0.3 V 2.495 2.5 2.505 V 125 ℃ EXTERNAL REFERENCE VREF REFIO voltage TEMPERATURE RANGE TA (1) Ambient temperature –40 Ideal input span, does not include gain or offset error. 6.4 Thermal Information ADS8686S THERMAL METRIC (1) PZA (LQFP) UNIT 80 PINS RθJA Junction-to-ambient thermal resistance 33.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 5.3 °C/W RθJB Junction-to-board thermal resistance 14.4 °C/W ΨJT Junction-to-top characterization parameter 0.5 °C/W ΨJB Junction-to-board characterization parameter 13.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Electrical Characteristics at AVDD = 5 V, DVDD= 3.3 V, fSAMPLE = 1 MSPS, fIN = 1 kHz, internal or external VREF = 2.5 V, LPF option = 1; minimum and maximum values at TA = –40°C to +125°C; typical values at TA = +25°C, AVDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN (1) TYP MAX (1) 0.85 1 1.15 MΩ 1 1.2 1.4 MΩ 10 25 ppm/°C UNIT ANALOG INPUTS RIN Input impedance Input impedance temperature drift (1) Input ranges = ±10 V, ±5 V, ±2.5 V, TA = 25°C 20% overrange setting for ±10 V, ±5 V, ±2.5 V, TA = 25°C All input ranges Preliminary Specifications, subject to change based on characterization Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S 7 ADS8686S SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 www.ti.com Electrical Characteristics (continued) at AVDD = 5 V, DVDD= 3.3 V, fSAMPLE = 1 MSPS, fIN = 1 kHz, internal or external VREF = 2.5 V, LPF option = 1; minimum and maximum values at TA = –40°C to +125°C; typical values at TA = +25°C, AVDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN (1) Input capacitance IANL(IN) Analog input current MAX (1) 10 2.02 2.1 2.16 Software, hardware selectable range = ±5 V 1.72 1.8 1.88 1.37 1.45 1.53 2.36 2.45 2.54 Software selectable range = ±5 V with overrange 1.81 1.9 1.99 Software selectable range = ±2.5 V with overrange 1.46 1.55 1.64 All input ranges UNIT pF Software, hardware selectable range = ±10 V Software, hardware selectable range Internal bias voltage for analog front- = ±2.5 V end Software selectable range = ±10 V with overrange VBias TYP V (VIN – VBIAS) / RIN µA ANALOG INPUT FILTER BW(-3 dB) BW(-0.1 dB) tGROUP Analog input LPF bandwidth –3 dB Analog input LPF bandwidth –0.1 dB Group delay Filter option 1, range = ±10 V and overrange 39 Filter option 1, range = ±5 V, ±2.5 V and overrange 33 Filter option 2, all input ranges 15 Filter option 3, all input ranges 376 Filter option 1, range = ±10 V and overrange 6.9 Filter option 1, range = ±5 V, ±2.5 V and overrange 5.9 Filter option 2, all input ranges 3.1 Filter option 3, all input ranges 60 Filter option 1, range = ±10 V and overrange 5.2 Filter option 1, range = ±5 V and overrange 6.2 Filter option 1, range = ± 2.5V and overrange 6.2 Filter option 2, range = ±10 V and overrange 13.2 Filter option 2, range = ±5 V and overrange 13.2 Filter option 2, range = ±2.5 V and overrange 13.3 Filter option 3, range = ±10 V and overrange 0.9 Filter option 3, range = ±5 V and overrange 0.9 Filter option 3, range = ±2.5 V and overrange Group delay temperature drift 8 kHz kHz 6 15.1 µs 1.1 0.94 Filter option 1, range = ±10 V 0.3 5 Filter option 2, range = ±10 V 0.6 2 Filter option 3, range = ±10 V 0.2 1 Submit Documentation Feedback ns/°C Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S ADS8686S www.ti.com SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 Electrical Characteristics (continued) at AVDD = 5 V, DVDD= 3.3 V, fSAMPLE = 1 MSPS, fIN = 1 kHz, internal or external VREF = 2.5 V, LPF option = 1; minimum and maximum values at TA = –40°C to +125°C; typical values at TA = +25°C, AVDD = 5 V (unless otherwise noted) PARAMETER TYP MAX (1) Filter option 1, range = ±10 V and overrange 20 131 Filter option 1, range = ±5 V and overrange 24 Filter option 1, range = ±2.5 V and overrange 38 Filter option 2, range = ±10 V and overrange 52 Filter option 2, range = ±5 V and overrange 50 Filter option 2, range = ±2.5 V and overrange 56 Filter option 3, range = ±10 V and overrange 10 Filter option 3, range = ±5 V and overrange 12 Filter option 3, range = ±2.5 V and overrange 24 TEST CONDITIONS Group delay matching MIN (1) UNIT 357 ns 104 DC CHRACTERISTICS NMC Resolution 16 No missing codes 16 All input ranges DNL Differential nonlinearity (2) –0.5 ±0.2 0.5 –0.6 ±0.25 0.6 –0.65 ±0.35 0.65 –2 ±0.7 2 Range = ±10 V, TA = 0℃ to 70℃ –1.2 ±0.6 1.2 Range = ±5 V, TA = 0℃ to 70℃ –1.5 ±0.7 1.5 Range = ±2.5 V, TA = 0℃ to 70℃ –1.6 ±0.75 1.6 Range = ±10 V with overrange EG Total unadjusted error Gain error (3) ±2.5 Range = ±5 V ±2.5 Range = ±2.5 V with overrange ±2 Range = ±2.5 V ±2 Gain error matching –80 ±6 80 Range = ±10 V, ±5 V, ±2.5 V, external reference –64 ±4 64 Range = ±10 V, internal reference ±3 Range = ±10 V with overrange 20 Range = ±5 V Range = ±2.5 V with overrange Range = ±2.5 V (2) (3) LSB 20% overrange setting, external reference Range = ±5 V with overrange LSB ±3 Range = ±5 V with overrange Range = ±10 V LSB ±3.5 Range = ±10 V TUE 0.85 Range = ±5 V, TA = 0℃ to 70℃ All input ranges Integral nonlinearity Bits ±0.2 Range = ±10 V, TA = 0℃ to 70℃ Range = ±2.5 V, TA = 0℃ to 70℃ INL –0.85 Bits 5 12 5 LSB 20 LSB 12 6 This parameter is the endpoint INL, not best-fit INL. Gain error calculated after adjusting for offset error, which implies that positive full-scale error = negative full-scale error = gain error ÷ 2. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S 9 ADS8686S SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 www.ti.com Electrical Characteristics (continued) at AVDD = 5 V, DVDD= 3.3 V, fSAMPLE = 1 MSPS, fIN = 1 kHz, internal or external VREF = 2.5 V, LPF option = 1; minimum and maximum values at TA = –40°C to +125°C; typical values at TA = +25°C, AVDD = 5 V (unless otherwise noted) PARAMETER Gain error temperature drift TYP MAX (1) All ranges, external reference 1 10 All ranges, internal reference 8 20 TEST CONDITIONS Range = ±10 V with overrange EO Offset error MIN (1) –4 ±0.4 4 Range = ±10 V –2.4 ±0.3 2.4 Range = ±5 V with overrange –1.8 ±0.18 1.8 Range = ±5 V –1.5 ±0.15 1.5 Range = ±2.5 V with overrange –1.4 ±0.24 1.4 Range = ±2.5 V –1.1 ±0.2 1.1 Range = ±10 V with overrange Range = ±10 V Offset error matching Range = ±5 V with overrange Range = ±5 V Range = ±2.5 V with overrange Range = ±2.5 V Offset error temperature drift 10 All ranges Submit Documentation Feedback UNIT ppm/°C mV ±0.45 –3 ±0.4 3 ±0.3 mV ±0.25 ±0.3 ±0.25 0.3 1.5 ppm/°C Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S ADS8686S www.ti.com SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 Electrical Characteristics (continued) at AVDD = 5 V, DVDD= 3.3 V, fSAMPLE = 1 MSPS, fIN = 1 kHz, internal or external VREF = 2.5 V, LPF option = 1; minimum and maximum values at TA = –40°C to +125°C; typical values at TA = +25°C, AVDD = 5 V (unless otherwise noted) PARAMETER MIN (1) TYP Filter option 1, range = ±10 V with overrange 89 91.3 Filter option 1, range = ±10 V 89 91 TEST CONDITIONS MAX (1) UNIT AC CHARACTERISTICS Filter option 1, range = ±5 V with overrange Filter option 1, range = ±5 V 90.7 88 Filter option 1, range = ±2.5 V with overrange Filter option 1, range = ±2.5 V 88.2 85.5 Filter option 2, range = ±10 V with overrange Filter option 2, range = ±10 V SNR Signal-to-noise ratio, no oversampling (–0.5 dBFS input, 1 kHz) 90.35 89.25 SNROSR Signal-to-noise ratio (–0.5 dBFS input, 1 kHz) 86.8 88.9 85 82 85 Filter option 3, range = ±5 V with overrange 82 Filter option 3, range = ±5 V 82 Filter option 3, range = ±2.5 V with overrange 77 Filter option 3, range = ±2.5 V 77 Filter option 1, range = ±10 V, OSR =2 92.5 Filter option 1, range = ±10 V, OSR =4 93.5 dB Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S dB 91.4 89.1 Filter option 3, range = ±10 V with overrange Filter option 3, range = ±10 V 91.9 91.6 Filter option 2, range = ±2.5 V with overrange Filter option 2, range = ±2.5 V 88 92.2 Filter option 2, range = ±5 V with overrange Filter option 2, range = ±5 V 90.5 11 ADS8686S SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 www.ti.com Electrical Characteristics (continued) at AVDD = 5 V, DVDD= 3.3 V, fSAMPLE = 1 MSPS, fIN = 1 kHz, internal or external VREF = 2.5 V, LPF option = 1; minimum and maximum values at TA = –40°C to +125°C; typical values at TA = +25°C, AVDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN (1) Filter option 1, range = ±10 V with overrange Filter option 1, range = ±10 V 88.5 87.5 SINAD Signal-to-noise distortion ratio, no oversampling (–0.5 dBFS input, 1 kHz) 85 90 89 86.5 82 THD SFDR Total harmonic distortion Spurious-free dynamic range (–0.5 dBFS input, 1 kHz) Isolation crosstalk IMD (4) (5) 12 (4) (5) Intermodulation distortion 88 85 82 79 Filter option 3, range = ±2.5 V with overrange Filter option 3, range = ±2.5 V dB 90.5 85 Filter option 3, range = ±5 V with overrange Filter option 3, range = ±5 V 91 88.2 Filter option 3, range = ±10 V with overrange Filter option 3, range = ±10 V 87.5 90.7 Filter option 2, range = ±2.5 V with overrange Filter option 2, range = ±2.5 V 90 91.3 Filter option 2, range = ±5 V with overrange Filter option 2, range = ±5 V 90.5 87.7 Filter option 2, range = ±10 V with overrange Filter option 2, range = ±10 V UNIT 90.2 Filter option 1, range = ±2.5 V with overrange Filter option 1, range = ±2.5 V MAX (1) 90.8 Filter option 1, range = ±5 V with overrange Filter option 1, range = ±5 V TYP 82 78 75 78 Range = ±10 V with overrange –110 Range = ±10 V –110 Range = ±5 V with overrange –110 Range = ±5 V –110 Range = ±2.5 V with overrange –110 Range = ±2.5 V –110 All input ranges –108 dB fIN on unselected channel up to 5 kHz –112 dB fa = 1 kHz, fb = 1.1 kHz, 2nd-order terms –105 fa = 1 kHz, fb = 1.1 kHz, 3rd-order terms –113 –95 dB dB Calculated on the first nine harmonics of the input frequency. Isolation crosstalk is measured by applying a full-scale sinusoidal signal up to 160 kHz to a channel, not selected in the multiplexing sequence, and measuring the effect on the output of any selected channel. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S ADS8686S www.ti.com SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 Electrical Characteristics (continued) at AVDD = 5 V, DVDD= 3.3 V, fSAMPLE = 1 MSPS, fIN = 1 kHz, internal or external VREF = 2.5 V, LPF option = 1; minimum and maximum values at TA = –40°C to +125°C; typical values at TA = +25°C, AVDD = 5 V (unless otherwise noted) TEST CONDITIONS MIN (1) TYP MAX (1) UNIT 0.1-µF capacitor on REFIO pin, TA = 25°C 2.4975 2.5 2.5025 V 7 20 4 4.004 PARAMETER INTERNAL REFERENCE OUTPUT VREF (6) Voltage on REFIO pin (configured as output) Reference temperature drift V(REFCAP) Reference buffer output voltage (REFCAP pin) TA = 25°C tON Reference turn-on time 10-µF capacitor on REFCAP pin 3.996 ppm/°C 15 V ms EXTERNAL REFERENCE INPUT REFLKG Reference input leakage current –1 1 µA 55 69 mA 59 72 mA POWER-SUPPLY REQUIREMENTS Static AVDD current with internal reference Dynamic, fSAMPLE = 1 MSPS Power-down IAVDD AVDD current with external reference IDVDD DVDD current 130 µA Static 54 68 mA Dynamic, fSAMPLE = 1 MSPS 59 72 mA Power-down 130 Static 0.06 0.1 mA 0.6 1 mA Dynamic, fSAMPLE = 1 MSPS Power-down µA 1 µA DIGITAL INPUTS VIH High-level input voltage 0.7 x DVDD DVDD + 0.3 V VIL Low-level input voltage –0.3 0.3 x DVDD V ILKG Input leakage current Input capacitance 100 nA 5 pF DIGITAL OUTPUTS VOH High-level output voltage IO = 500-µA source VOL Low-level output voltage IO = 500-µA sink (6) 0.8 x DVDD DVDD V 0 0.2 x DVDD V 20 µA Floating state leakage current 1 Floating state output capacitance 5 pF Does not include the variation in voltage resulting from solder shift effects. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S 13 ADS8686S SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 www.ti.com 6.6 Timing Requirements at AVDD = 5 V, DVDD = 1.71 V to 5.25 V, VIL and VIH at datasheet limits, and fSAMPLE = 1 MSPS (unless otherwise noted); minimum and maximum values are at TA = –40°C to +125°C; typical values are at TA = 25°C MIN NOM MAX UNIT DEVICE CONFIGURATION tD_CSCNV Delay time: CS rising edge to CONVST rising edge 75 ns tSU_CHXCNV Setup time: CHSELx to CONVST rising edge 50 ns tHT_BSYCHX Hold time: BUSY falling edge to CHSELx change 20 ns tPWRUP Power supplies settled to RESET rising edge 1 ms tDEV_WRITE tSU_RST tHT_RST Partial reset: RESET rising edge to first falling edge of CS 50 ns 240 µs Partial reset: setup time HW mode configuration inputs to RESET rising edge 10 ns Full reset: setup time HW mode configuration inputs to RESET rising edge 50 µs Partial reset: hold time RESET rising edge to HW mode configuration inputs 10 ns 240 µs 480 ns Full reset: RESET rising edge to first falling edge of CS Full reset: Hold time RESET rising edge to HW mode configuration inputs CONVST CONTROL tACQ Acquisition time: BUSY falling edge to rising edge of trailing CONVST tPH_CNV CONVST pulse high time 50 ns tPL_CNV CONVST pulse low time 50 ns Partial reset setup time: RESET rising edge to first rising edge of CONVST 50 ns Full reset setup time: RESET rising edge to first rising edge of CONVST 15 ms Partial reset 40 Full reset 1.2 µs tSU_BSYCS Setup time: BUSY falling edge to CS falling edge, start of data read operation after conversion 20 ns tDZ_CSCNV Delay between CS rising edge to CONVST rising edge, end of data read operation after conversion 50 ns tDEV_STRTUP tPL_RST 500 ns DATA READ PARALLEL AND BYTE DATA READ tSU_CSRD Setup time: CS falling edge to RD falling edge 10 ns tHT_RDCS Hold time: RD rising edge to CS rising edge 10 ns tPH_RD RD high time 10 ns tPL_RD RD low time 30 ns 14 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S ADS8686S www.ti.com SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 Timing Requirements (continued) at AVDD = 5 V, DVDD = 1.71 V to 5.25 V, VIL and VIH at datasheet limits, and fSAMPLE = 1 MSPS (unless otherwise noted); minimum and maximum values are at TA = –40°C to +125°C; typical values are at TA = 25°C MIN NOM MAX UNIT SERIAL DATA READ tSCLK SCLK time period, 1.71 V ≤ DVDD ≤ 2.3 V 50 ns SCLK time period, 2.3 V < DVDD ≤ 3 V 25 ns SCLK time period, DVDD > 3 V 20 ns tPH_SCLK SCLK high time 0.45 0.55 tSCLK tPL_SCLK SCLK low time 0.45 0.55 tSCLK Setup time: CS falling edge to SCLK falling edge DVDD > 3V 10.5 ns Setup time: CS falling edge to SCLK falling edge 2.3 V < DVDD ≤ 3 V 13.5 ns Setup time: CS falling edge to SCLK falling edge 1.71 V ≤ DVDD ≤ 2.3 V 20 ns Hold time: SCLK to CS rising time 10 ns tSU_CSCK tHT_CKCS PARALLEL AND BYTE DATA WRITE tSU_CSWR Setup time: CS falling edge to WR falling edge 10 ns tHT_WRCS Hold time: WR rising edge to CS rising edge 10 ns tPH_WR WR high time 20 ns tPL_WR WR low time 30 ns tSU_DINWR Setup time: DIN change to WR rising edge 30 ns tHT_WRDIN Hold time: WR rising edge to DIN change 10 ns tDZ_CONFIG Device configuration time: WR rising edge to CONVST rising edge 20 ns 10 ns 8 ns SERIAL DATA WRITE tSU_DINCK Setup time: DIN to SCLK falling edge tHT_CKDIN Hold time: SCLK falling edge to DIN change 6.7 Switching Characteristics at AVDD = 5 V, DVDD = 1.71 V to 5.25 V, VIL and VIH at datasheet limits, and fSAMPLE = 1 MSPS (unless otherwise noted); minimum and maximum values are at TA = –40°C to +125°C; typical values are at TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CONVST CONTROL tCYC tCONV ADC cycle time Conversion time: CONVST rising edge to BUSY falling edge time, input channels No oversampling, parallel or byte or serial 2-wire mode readback 1 µs No oversampling 475 Oversampling by 2 1.4 520 µs Oversampling by 4 3.2 µs Oversampling by 8 6.7 µs Oversampling by 16 13.7 µs Oversampling by 32 27.9 µs Oversampling by 64 55.9 µs Oversampling by 128 112 µs Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S ns 15 ADS8686S SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 www.ti.com Switching Characteristics (continued) at AVDD = 5 V, DVDD = 1.71 V to 5.25 V, VIL and VIH at datasheet limits, and fSAMPLE = 1 MSPS (unless otherwise noted); minimum and maximum values are at TA = –40°C to +125°C; typical values are at TA = 25°C PARAMETER tCONV_DIAG tD_CNVBSY Conversion time: CONVST rising edge to BUSY falling edge time, diagnostic channels Delay between CONVST rising edge to BUSY rising edge TYP MAX UNIT No oversampling TEST CONDITIONS MIN 525 570 ns Oversampling by 2 1.4 µs Oversampling by 4 3.2 µs Oversampling by 8 6.7 µs Oversampling by 16 13.7 µs Oversampling by 32 27.9 µs Oversampling by 64 55.9 µs Oversampling by 128 112 µs Manual mode 32 ns 30 ns 20 ns 12 ns 16 ns 9 ns PARALLEL AND BYTE DATA READ Delay time: RD falling edge to new data on DB[15:0] tD_RDDB Delay time: CS rising edge to DB[15:0] becoming tri-state tDHZ_CSDB Delay time: CS rising edge to DB[15:0] becoming tri-state 1.71 V ≤ DVDD ≤ 2.3 V DVDD > 2.3 V SERIAL DATA READ tD_CSDO tH_CKDO tD_CKDO tDHZ_CSDO 16 Delay time: CS falling edge to SDOA and SDOB becoming valid (out of tri-state) 1.71 V ≤ DVDD ≤ 2.3 V Delay time: CS falling edge to SDOA and SDOB becoming valid (out of tri-state) DVDD > 2.3 V Hold time: SCLK rising edge to data hold on SDOA and SDOB 1.71 V ≤ DVDD ≤ 2.3 V Hold time: SCLK rising edge to data hold on SDOA and SDOB 2.3 V ≤ DVDD ≤ 3 V Hold time: SCLK rising edge to data hold on SDOA and SDOB DVDD > 3 V Delay time: SCLK rising edge to valid data on SDOA and SDOB 1.71 V ≤ DVDD ≤ 2.3 V Delay time: SCLK rising edge to valid data on SDOA and SDOB 2.3 V < DVDD ≤ 3 V Delay time: SCLK rising edge to valid data on SDOA and SDOB DVDD > 3 V Delay time: CS rising edge to SDOA and SDOB becoming tri-state 1.71 V ≤ DVDD ≤ 2.3 V Delay time: CS rising edge to SDOA and SDOB becoming tri-state DVDD > 2.3 V Submit Documentation Feedback 3 ns 3 ns 2.8 ns 20 ns 12 ns 10 ns 20 ns 10 ns Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S ADS8686S www.ti.com SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 6.8 Timing Specifications: Universal All figures in this section are at AVDD = 4.75 V to 5.25 V, DVDD = 1.71 V to AVDD, VREFIO = 2.5 V external reference and internal reference, and TA = −40°C to +125°C (unless otherwise noted); the interface timing tested used a load capacitance of 30 pF, dependent on DVDD and load capacitance for the serial interface (see Table 10). tCYC tPH_CNV tPL_CNV tD_CSCNV CONVST tD_CNVBSY BUSY tACQ tCONV tSU_BSYCS CS tSU_CHSCNV tHT_BSYCHS HARDWARE MODE CHSEL[2:0] DONT CARE CHX DONT CARE CHy Figure 1. Universal Timing Diagram Across All Interfaces Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S 17 ADS8686S SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 www.ti.com Timing Specifications: Universal (continued) tPWRUP tDEV_STRTUP AVDD DVDD RESET tPL_RST CONVST BUSY tDEV_WRITE CS tSU_RST tHT_RST REFSEL, BYTESEL SER/BYTE/PAR, SER1W DONT CARE HW_RNGSEL[1:0] DONT CARE CRCEN, BURST SEQEN, OS[2:0] DONT CARE CHSEL[2:0] DONT CARE DONT CARE ALL MODES HARDWARE MODE ONLY ACTION MODE RANGE SETTING IN HW MODE DONT CARE CHx DONT CARE ACQx CHy DONT CARE CONVx ACQy CHz DONT CARE CONVy Figure 2. Reset Timing 18 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S ADS8686S www.ti.com SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 6.9 Timing Requirements: Parallel Data Read CONVST BUSY tHT_RDCS tDHZ_CSDB tPH_RD CS RD DB[15:0] DATA Bx DATA Ax tSU_CSRD tPL_RD tD_RDDB Figure 3. Parallel Read Timing Diagram tDZ_CONFIG tSU_CSWR CONVST CS tHT_WRCS tPH_WR WR tPL_WR tHT_WRDIN WRITE REG 1 DB[15:0] WRITE REG 2 tSU_DINWR Figure 4. Parallel Write Timing Diagram Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S 19 ADS8686S SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 www.ti.com 6.10 Timing Requirements: Serial Data Read CONVST BUSY tPH_SCLK tD_CSDO tPL_SCLK tD_CKDO tSU_CSCK tSCLK tHT_CKCS tDOUT_HOLD CS SCLK DONT CARE 1 2 3 14 15 16 SDOA DB15 DB14 DB13 DB2 DB1 DB0 SDOB DB15 DB14 DB13 DB2 DB1 DB0 SDI DB15 DB14 DB13 DB2 DB1 tHT_CKDIN tSU_DINCK DONT CARE DB0 tDHZ_CSDO Figure 5. Serial Timing Diagram 20 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S ADS8686S www.ti.com SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 6.11 Typical Characteristics 0 0 -40 -40 Magnitude (dB) Magnitude (dB) At TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 2.5 V, and fS = 1 MSPS (unless otherwise noted). -80 -120 -80 -120 -160 -160 -200 -200 0 100 200 300 Frequency (kHz) 400 0 500 Number of points = 256k, SNR = 90.73 dB, SINAD = 90.65 dB, THD = –110 dB, SFDR = 112.2 dB 400 500 D002 Figure 7. Typical FFT Plot (±5 V, Normal Mode, Filter Option 1) 0 0 -40 -40 Magnitude (dB) Magnitude (dB) 200 300 Frequency (kHz) Number of points = 256k, SNR = 89.56 dB, SINAD = 89.47 dB, THD = –110.83 dB, SFDR = 110.69 dB Figure 6. Typical FFT Plot (±10 V, Normal Mode, Filter Option 1) -80 -120 -160 -80 -120 -160 -200 -200 0 100 200 300 Frequency (kHz) 400 500 0 12.5 D003 Number of points = 256k, SNR = 89.03 dB, SINAD = 88.89 dB, THD = –107.25 dB, SFDR = 110.46 dB 25 37.5 Frequency (kHz) 50 62.5 D004 Number of points = 256k, SNR = 90.27 dB, SINAD = 90.24 dB, THD = –111.9 dB, SFDR = 116.04 dB Figure 8. Typical FFT Plot (±2.5 V, Normal Mode, Filter Option 1) Figure 9. Typical FFT Plot (±10 V, Burst Mode, Filter Option 1) 0 0 -40 -40 Magnitude (dB) Magnitude (dB) 100 D001 -80 -120 -160 -80 -120 -160 -200 -200 0 100 200 300 Frequency (kHz) 400 500 0 D005 Number of points = 256k, SNR = 91.93 dB, SINAD = 91.82 dB, THD = –110.04 dB, SFDR = 111.95 dB 100 200 300 Frequency (kHz) 400 500 D006 Number of points = 256k, SNR = 90.99 dB, SINAD = 90.87 dB, THD = –111.91 dB, SFDR = 111.1 dB Figure 10. Typical FFT Plot (±10 V, Normal Mode, Filter Option 2) Figure 11. Typical FFT Plot (±5 V, Normal Mode, Filter Option 2) Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S 21 ADS8686S SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 www.ti.com Typical Characteristics (continued) 0 0 -40 -40 Magnitude (dB) Magnitude (dB) At TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 2.5 V, and fS = 1 MSPS (unless otherwise noted). -80 -120 -160 -80 -120 -160 -200 -200 0 100 200 300 Frequency (kHz) 400 500 0 100 Number of points = 256k, SNR = 84.29 dB, SINAD = 84.27 dB, THD = –110 dB, SFDR = 113.6 dB 92 Signal-to-Noise Ratio (dB) Signal-to-Noise Ratio (dB) D008 94.5 ± 10V ± 5V ± 2.5V 90 88 86 0 50 100 Free-Air Temperature (°C) ± 10V ± 5V ± 2.5V 93 91.5 90 88.5 87 -50 150 0 D009 Figure 14. SNR vs Free-Air Temperature (Filter Option 1) 50 100 Free-Air Temperature (°C) 150 D010 Figure 15. SNR vs Free-Air Temperature (Filter Option 2) 90 94 ± 10V ± 5V ± 2.5V 87 Signal to Noise+Distortion Ratio (dB) Signal-to-Noise Ratio (dB) 500 Figure 13. Typical FFT Plot (±5 V, Normal Mode, Filter Option 3) 94 84 81 78 75 -50 400 Number of points = 256k, SNR = 81.10 dB, SINAD = 81.01 dB, THD = –110.8 dB, SFDR = 113.56 dB Figure 12. Typical FFT Plot (±10 V, Normal Mode, Filter Option 3) 84 -50 200 300 Frequency (kHz) D007 0 50 100 Free-Air Temperature (°C) 150 ± 10V ± 5V ± 2.5V 92 90 88 86 84 -50 0 D011 50 100 Free-Air Temperature (°C) 150 D012 (Update) Figure 16. SNR vs Free-Air Temperature (Filter Option 3) 22 Figure 17. SINAD vs Free-Air Temperature (Filter Option 1) Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S ADS8686S www.ti.com SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 Typical Characteristics (continued) At TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 2.5 V, and fS = 1 MSPS (unless otherwise noted). 90 ± 10V ± 5V ± 2.5V 93 Signal to Noise + Distortion Ratio (dB) Signal to Noise + Distortion Ratio (dB) 94.5 91.5 90 88.5 87 -50 0 50 100 Free-Air Temperature (°C) 87 84 81 78 75 -50 150 D014 Total Harmonic Distortion (dB) -106 -108 -110 0 50 100 Free-Air Temperature (°C) 150 ± 10 V ±5V ± 2.5 V -104 -106 -108 -110 -112 -50 D015 Figure 20. THD vs Free-Air Temperature (Filter Option 1) 0 50 100 Free-Air Temperature (°C) 150 D016 Figure 21. THD vs Free-Air Temperature (Filter Option 2) -102 2 ± 10V ± 5V ± 2.5V -104 Integral Nonlinearity (LSB) Total Harmonic Distortion (dB) 150 -102 ± 10 V ±5V ± 2.5 V -104 -106 -108 -110 -112 -50 50 100 Free-Air Temperature (°C) Figure 19. SINAD vs Free-Air Temperature (Filter Option 3) -102 Total Harmonic Distortion (dB) 0 D013 Figure 18. SINAD vs Free-Air Temperature (Filter Option 2) -112 -50 ± 10V ± 5V ± 2.5V 0 50 100 Free-Air Temperature (°C) 150 1 0 -1 -2 -32768 D017 Figure 22. THD vs Free-Air Temperature (Filter Option 3) -16384 0 Codes (LSB) 16384 32767 D018 Figure 23. Typical INL for All Codes (±10 V) Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S 23 ADS8686S SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 www.ti.com Typical Characteristics (continued) At TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 2.5 V, and fS = 1 MSPS (unless otherwise noted). 1 Differential Nonlinearity (LSB) Integral Nonlinearity (LSB) 2 1 0 -1 -2 -32768 -16384 0 Codes (LSB) 16384 0 -0.5 -1 -32768 32768 -16384 D019 Figure 24. Typical INL for All Codes (±5 V) 0 Codes (LSB) 16384 32768 D020 Figure 25. Typical DNL for All Codes (±10 V) 175000 1 150000 0.5 125000 Number of Hits Differential Nonlinearity (LSB) 0.5 0 100000 75000 50000 -0.5 25000 Output Codes 3 2 0 32768 1 16384 0 0 Codes (LSB) -1 -16384 -2 -1 -32768 D021 D022 Mean = 0.83, sigma = 0.62, number of hits = 256k, VIN = 0 V Figure 27. Typical Offset Error Histogram (±10 V) 160000 120000 120000 90000 Number of Hits 80000 40000 60000 30000 D023 Mean = –0.78, sigma = 0.7, number of hits = 256k, VIN = 0 V Figure 28. Typical Offset Error Histogram (±5 V) 24 3 2 1 Output Codes 0 -1 -2 -3 -4 -6 2 1 Output Codes 0 -1 -2 -3 0 -4 0 -5 Number of Hits Figure 26. Typical DNL for All Codes (±5 V) D024 Mean = -1.91, sigma = 0.97, number of hits = 256k, VIN = 0 V Figure 29. Typical Offset Error Histogram (±2.5 V) Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S ADS8686S www.ti.com SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 Typical Characteristics (continued) At TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 2.5 V, and fS = 1 MSPS (unless otherwise noted). 20 20 ± 10V ± 5V ± 2.5V 12 Gain Error (LSB) Gain Error (LSB) 12 4 -4 -12 4 -4 0 50 100 Free-Air Temperature (°C) -20 -50 150 0 D025 Figure 30. Gain Error vs Free-Air Temperature 50 100 Free-Air Temperature (°C) 150 D026 Figure 31. Gain Error vs Free-Air Temperature (±10 V, Across Channels) 20 20 Ch 0 Ch 1 Ch 2 Ch 3 Ch 4 Ch 5 Ch 6 Ch 7 Ch 0 Ch 1 Ch 2 Ch 3 12 Gain Error (LSB) 12 4 -4 -12 Ch 4 Ch 5 Ch 6 Ch 7 4 -4 -12 -20 -50 0 50 100 Free-Air Temperature (°C) -20 -50 150 0 D027 Figure 32. Gain Error vs Free-Air Temperature (±5 V, Across Channels) 50 100 Free-Air Temperature (°C) 150 D028 Figure 33. Gain Error vs Free-Air Temperature (±2.5 V, Across Channels) 8 800 ± 10V ± 5V ± 2.5V 700 4.8 Offset Error (LSB) 600 Number of Hits Ch 4 Ch 5 Ch 6 Ch 7 -12 -20 -50 Gain Error (LSB) Ch 0 Ch 1 Ch 2 Ch 3 500 400 300 1.6 -1.6 200 -4.8 100 0 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 Gain Error Drift ppm/°C 5 6 7 -8 -50 8 D029 Figure 34. Gain Error Drift Histogram -10 30 70 Free-Air Temperature (°C) 110 150 D031 Figure 35. Offset Error vs Free-Air Temperature Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S 25 ADS8686S SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 www.ti.com Typical Characteristics (continued) At TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 2.5 V, and fS = 1 MSPS (unless otherwise noted). 8 8 Ch 0 Ch 1 Ch 2 Ch 3 1.6 -1.6 -4.8 -8 -50 Ch 4 Ch 5 Ch 6 Ch 7 1.6 -1.6 -4.8 0 50 100 Free-Air Temperature (°C) -8 -50 150 0 D032 Figure 36. Offset Error vs Free-Air Temperature (±10 V, Across Channels) 50 100 Free-Air Temperature (°C) 150 D033 Figure 37. Offset Error vs Free-Air Temperature (±5 V, Across Channels) 1200 8 Ch 0 Ch 1 Ch 2 Ch 3 Ch 4 Ch 5 Ch 6 Ch 7 900 Number of Hits 4.8 Offset Error (LSB) Ch 0 Ch 1 Ch 2 Ch 3 4.8 Offset Error (LSB) Offset Error (LSB) 4.8 Ch 4 Ch 5 Ch 6 Ch 7 1.6 -1.6 600 300 -4.8 -8 -50 0 0 50 100 Free-Air Temperature (°C) -5 150 -4 -3 -2 -1 0 1 2 Offset Error Drift (ppm/°C) 3 4 5 D034 D035 Figure 39. Offset Error Drift Histogram Figure 38. Offset Error vs Free-Air Temperature (±2.5 V, Across Channels) 58 0.65 Static Dynamic 0.64 DVDD Current (mA) AVDD Current (mA) 56 54 52 50 48 -50 0.62 0.61 0 50 100 Free-Air Temperature (°C) 150 0.6 -50 D050 Figure 40. AVDD Current vs Free-Air Temperature 26 0.63 0 50 100 Free-Air Temperature (°C) 150 D051 Figure 41. DVDD Current vs Free-Air Temperature Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S ADS8686S www.ti.com SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 Typical Characteristics (continued) At TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 2.5 V, and fS = 1 MSPS (unless otherwise noted). 2 2 ± 10 V ±5V ± 2.5 V 0 -2 Amplitude (dB) Amplitude (dB) 0 -4 -6 -8 -2 -4 -6 LPF = 39kHz LPF = 15kHz LPF = 376kHz -8 -10 1 2 3 4 5 6 7 8 10 20 Frequency (KHz) -10 0.1 0.2 30 40 50 70 100 0.5 1 D055 Figure 42. Frequency Response Across Ranges (Filter Option 1) 2 3 4 5 7 10 2030 50 100 200 Frequency (kHz) 5001000 D056 Figure 43. Frequency Response Across LPF Settings (±10 V) 7.5 ± 10 V ±5V ± 2.5 V Group Delay (us) 7 6.5 6 5.5 5 -50 0 50 100 Free-Air Temperature (°C) 150 D041 Figure 44. Group Delay vs Free-Air Temperature (Filter Option 1) Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S 27 ADS8686S SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 www.ti.com 7 Detailed Description 7.1 Overview The ADS8686S is a 16-bit data acquisition system (DAQ) with 16-channel analog inputs. Each analog input channel consists of an input clamp protection circuit, a programmable gain amplifier (PGA), a second-order programmable low-pass filter followed by an analog-to-digital (ADC) driver. The ADC driver outputs are connected through a dual 8:1 multiplexer (MUX) to a dual simultaneous sampling 16-bit ADC. The overall system can achieve a maximum throughput of 1 MSPS per ADC. The device features a 2.5-V internal reference with a fast-settling buffer, a programmable digital averaging filter to improve noise performance, a flexible channel sequencer, and high-speed parallel, byte, and serial interfaces for communication with a wide variety of digital hosts. The device operates from a single 5-V analog supply and can accommodate true bipolar input signals. The programmable analog signal range includes ±10-V, ±5-V, and ±2.5-V options with 20% overrange. The input clamp protection circuitry can tolerate voltages up to ±15 V. The device offers a constant 1-MΩ resistive input impedance irrespective of the sampling frequency or the selected input range. The device can be operated in hardware or software mode by controlling the HW_RNGSELx pins. In hardware mode, the device is configured by pin control. In software mode, the device is configured by the control registers accessed through the parallel, byte, or serial interface. 7.2 Functional Block Diagram AVDD AIN_0A AIN_0AGND REFCAP REFIO REFSEL REGCAP REGCAPD DVDD 2.5 V REF 1M Clamp PGA Clamp 1M 2nd -Order PROG LPF ADC Driver ALDO DLDO CRCEN 9:1 MUX 1M AIN_7A Clamp AIN_7AGND Clamp PGA 1M 2nd-Order PROG LPF SDOx/SDI 16-BIT SAR ADC Driver 16-BIT SAR OSR DIGITAL FILTER SERIAL/ PARALLEL/ BYTE INTERFACE SER/BYTE/PAR SER1W DB[15:0] 1M AIN_0B Clamp AIN_0BGND Clamp PGA 1M 2nd-Order PROG LPF ADC Driver OS[2:0] 9:1 MUX AIN_7B AIN_7BGND Clamp RESET 1M BURST PGA Clamp 1M 2nd-Order PROG LPF ADC Driver FLEXIBLE SEQUENCER SEQEN HW_RNGSEL[1:0] CONTROL INPUTS CHSEL[2:0] BYTESEL AVDD ADS8686S CLK OSC 2:1 MUX BUSY ALDO CONVST AGND 28 DGND Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S ADS8686S www.ti.com SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 7.3 Feature Description 7.3.1 Analog Inputs The ADS8686S incorporates dual, simultaneous sampling, 16-bit successive approximation register (SAR) analog-to-digital converters (ADCs). Each ADC is connected to eight analog input channels through a multiplexer. The device has a total of 16 analog inputs. Each analog input channel has two input pins, AIN_0A, AIN_0B and AIN_0AGND, AIN_0BGND to AIN_7A, AIN_7B and AIN_7AGND, AIN_7BGND. The positive inputs (AIN_nA, AIN_nB) are the single-ended analog inputs and the negative inputs (AIN_nAGND, AIN_nBGND) are tied to AGND. Figure 45 shows the simplified circuit schematic for each analog input channel, including the input clamp protection circuit, PGA, low-pass filter, high-speed ADC driver, multiplexer, and a precision 16-bit SAR ADC. 1 M: AIN_nA/B AIN_nA/BGND Clamp PGA 2nd -Order PROG LPF ADC Driver Clamp MUX 16-bit SAR ADC 1 M: Figure 45. Front-End Circuit Schematic for the Selected Analog Input Channel The device samples the voltage difference (AIN_nA, AIN_nB – AIN_nAGND, AIN_nBGND) between the selected analog input channel pins. The device allows a ±0.3-V range on the AIN_nAGND, AIN_nBGND pin for all analog input channels. Use this feature in modular systems where the sensor or signal conditioning block is further away from the ADC on the board and when a difference in the ground potential of the sensor or signal conditioner from the ADC ground is possible. In such cases, running separate wires from the AIN_nAGND, AIN_nBGND pin of the device to the sensor or signal conditioning ground is recommended The ADS8686S also has on-chip diagnostic channels to monitor the AVDD supply and an on-chip, low-dropout regulator (LDO). Channels can be selected for conversion by controlling the CHSELx pins in hardware mode or through the channel register control in software mode. The device supports dynamic channel selection or the onchip sequencer can be enabled to scan the channels in a preprogrammed manner. In hardware mode, simultaneous sampling is restricted to the corresponding A and B channel (that is, channel AIN_0A is always sampled with channel AIN_0B). The diagnostic channels cannot be sampled in the hardware mode of operation. Software mode is required to sample the diagnostic channels. In software mode, any AIN_nA channel can be selected with any AIN_nB channel for simultaneous sampling. 7.3.2 Analog Input Impedance Each analog input channel in the device presents a constant resistive impedance of 1 MΩ. The input impedance for each channel is independent of the configured range of the ADC, or the oversampling mode. The primary advantage of such high-impedance inputs is the ease of driving the ADC inputs without requiring driving amplifiers with low output impedance. Bipolar, high-voltage power supplies are not required in the system because this ADC does not require any high-voltage, front-end drivers. In most applications, the signal sources or sensor outputs can be directly connected to the ADC input, thus significantly simplifying the design of the signal chain. In order to maintain the dc accuracy of the system, matching the external source impedance on the AIN_nA, AIN_nB input pin with an equivalent resistance on the AIN_nAGND, AIN_nBGND pin is recommended (see Figure 48). This matching helps cancel any additional offset error contributed by the external resistance. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S 29 ADS8686S SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 www.ti.com Feature Description (continued) 7.3.3 Input Clamp Protection Circuit Figure 46 shows the analog input circuitry of the ADS8686S. The device features an internal clamp protection circuit on each of the 16 analog input channels. R FB 1M AIN_xx CLAMP + 2nd-ORDER LPF 1M AIN_xxGND ADC DRIVER MUX CLAMP R FB Figure 46. Analog Input Circuitry The input clamp protection circuit on the ADS8686S allows each analog input to swing up to a maximum voltage of ±15 V. Beyond an input voltage of ±15 V, the input clamp circuit turns on and still operates from the single 5-V supply. Figure 47 shows a typical current versus voltage characteristic curve for the input clamp. There is no current flow in the clamp circuit for input voltages up to ±15 V. Beyond this voltage, the input clamp circuit turns on. 50 Input Clamp Current (mA) 40 30 20 10 0 -10 -20 -30 -40 -50 -20 -15 -10 -5 0 5 Input Voltage (V) 10 15 20 D007 Figure 47. Input Protection Clamp Profile, Input Clamp Current vs Source Voltage For input voltages above the clamp threshold, make sure that the input current never exceeds the absolute maximum rating (see the Absolute Maximum Ratings table) of ±10 mA to prevent any damage to the device. Figure 48 shows that a small series resistor placed in series with the analog inputs is an effective way to limit the input current. In addition to limiting the input current, this resistor can also provide an antialiasing, low-pass filter (LPF) when coupled with a capacitor. To maintain the dc accuracy of the system, matching the external source impedance on the AIN_nA, AIN_nB input pin with an equal resistance on the AIN_nAGND AIN_nBGND pin is recommended. This matching helps cancel any additional offset error contributed by the external resistance. ADS8686S R ANALOG INPUT SIGNAL R AIN_nA/B R FB 1M CLAMP C + 1M CLAMP AIN_nA/BGND R FB Figure 48. Input Resistance Matching on the Analog Input 30 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S ADS8686S www.ti.com SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 Feature Description (continued) The input overvoltage protection clamp on the ADS8686S is intended to control transient excursions on the input pins. Leaving the device in a state where the clamp circuit is activated for extended periods of time in normal or power-down mode is not recommended because this fault condition can degrade device performance and reliability. Using external protection circuits is also recommended as a secondary protection scheme to protect the device. Using external protection devices helps protect against surges, electrostatic discharge (ESD), and electrical fast transient (EFT) conditions. 7.3.4 Programmable Gain Amplifier (PGA) The device offers a programmable gain amplifier (PGA) at each individual analog input channel that converts the input single-ended signal into a fully differential signal to drive the internal 16-bit ADC. The PGA also adjusts the common-mode level of the input signal before being fed into the ADC to provide the maximum usage of the ADC input dynamic range. The logic levels on the range select pins, HW_RNGSEL[1:0], determine the analog input range of all analog input channels (see the HW_RANGESEL[1:0] (Input) section). If both range select pins are tied to a logic low, the analog input range is determined in software mode through the input range registers (see the Register Maps section for details). In software mode, an individual analog input range can be configured per channel. The device also supports a 20% overrange feature on all input channels in software mode. Program the D[7:0] bits from the 0x08H and 0x0AH registers to individually enable the overrange feature for channels AIN_xA. Program the same value in both registers. Program the D[7:0] bits from the 0x09H and 0x0Bh registers to individually enable the overrange feature for channels AIN_xB. Program the same value in both registers. See the 0x0AH and 0x0BH register details for the programmed register values. The programmed range of the selected channel is increased by 20%. For example, if channel AIN_0A is programmed for a ±10-V range with the overrange feature, the resultant input range is ±12 V. In hardware mode, the range selected by the HW_RNGSEL[1:0] pins is applicable for all channels. A logic change on the HW_RNGSEL[1:0] pins has an immediate effect on the analog input range; however, there is typically a settling time of approximately 120 µs in addition to the normal acquisition time requirement for the lowpass filter option 2. Table 1 lists the various gain settings achievable with the HW_RNGSEL[1:0] pin settings. Table 1. Analog Input Range Selection HW_RNGSEL1 HW_RNGSEL0 ANALOG INPUT RANGE 0 0 Configured as per the input range register programming 0 1 ±2.5 V 1 0 ±5 V 1 1 ±10 V Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S 31 ADS8686S SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 www.ti.com 7.3.5 Second-Order, Programmable, Low-Pass Filter (LPF) In order to mitigate the noise of the front-end amplifiers and gain resistors of the PGA, each analog input channel of the ADS8686S features a second-order, programmable, antialiasing, low-pass filter (LPF) at the output of the PGA. Table 2 lists the various programmable LPF options available in the device. The programmable LPF options are available in the software mode of operation. Table 2. Programmable LPF Settings LPF OPTION REGISTER SETTING RANGE LPF CORNER FREQUENCY LPF 1 0x00b ±10 V, ±12 V 39 kHz LPF 1 0x00b ±5 V, ±2.5 V, ±6 V, ±3 V 33 kHz LPF 2 0x01b All ranges 15 kHz LPF 3 0x10b All ranges 376 kHz Figure 49 shows the magnitude response of the analog antialiasing filter for the various range and filter options. 2 Amplitude (dB) 0 -2 -4 -6 -8 -10 0.1 0.2 LPF = 39kHz LPF = 15kHz LPF = 376kHz 0.5 1 2 3 4 5 7 10 2030 50 100 200 Frequency (kHz) 5001000 D056 Figure 49. Second-Order LPF Magnitude Response 7.3.6 ADC Driver In order to meet the performance of a 16-bit, SAR ADC at the maximum sampling rate (1 MSPS), the capacitors at the input of the ADC must be successfully charged and discharged during the acquisition time window. The ADC inputs must settle to better than 16-bit accuracy before any sampled analog voltage is converted. This drive requirement at the ADC inputs necessitates the use of a high-bandwidth, low-noise, and stable amplifier buffer. The ADS8686S features an integrated input driver as part of the signal chain for each analog input, thus simplifying the signal chain design. 7.3.7 Multiplexer The ADS8686S features 16-channel analog inputs. The analog inputs are grouped in two sets of eight channels, AIN_xA and AIN_xB. These groups of eight channels are connected to two 16-bit SAR ADCs through a highly configurable 9:1 multiplexer (MUX). Apart from the eight channels, the MUX is also connected to an internal 2:1 MUX. The 2:1 MUX can be configured to monitor internal nodes for diagnostic purposes. In hardware mode, the multiplexer channel selection is controlled by the CHSEL[2:0] pin status. The CHSEL[2:0] pin status, when RESET is released, determines the initial channel pair to be configured. Consequently, the CHSEL[2:0] pin status is monitored during the device conversion time to decide the next state for the MUX connection. In hardware mode, the internal diagnostic channels cannot be accessed. In software mode, the multiplexer channel selection is controlled by programming the appropriate device register. In hardware and software modes, the sequencer and burst modes can be enabled to reduce the software overhead for cycling through the MUX; see the Sequencer section for more details. 32 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S ADS8686S www.ti.com SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 7.3.8 Digital Filter and Noise The ADS8686S features an optional digital second-order sinc filter that can be used in slower throughput applications requiring lower noise and higher dynamic range. As explained in Table 3, the oversampling ratio of the digital filter is determined by the configuration of the OS[2:0] pins in hardware mode or through the OS bits programming in software mode. When enabled, the oversampling is applicable for all channels. The overall throughput of the ADC decreases proportionally with the increase to the oversampling ratio. When the oversampling ratio increases, there is a proportional improvement in the SNR performance and decrease in the bandwidth of the input signal. In oversampling mode, the ADC takes the first sample for each channel at the rising edge of the CONVST signal. After converting the first sample, the subsequent samples are taken by an internally generated sampling control signal. The samples are then averaged to reduce the noise of the signal chain as well as to improve the SNR of the ADC. The final output is also decimated to provide a 16-bit output for each channel. If oversampling is enabled with the sequencer in burst mode, the extra samples are gathered for a given channel before the sequencer moves on to the next channel. Table 3. Oversampling Bit Decoding OSR 000 No OSR LPF 1 86.99 87.32 89.55 001 2 LPF 1 87.6 87.89 010 4 LPF 1 88.04 011 8 LPF 1 88.74 100 16 LPF 1 101 32 110 64 111 LPF OPTION −3-dB BANDWIDTH (kHz) TYPICAL SNR (dB) OSx PINS, OS BITS ±2.5-V RANGE ±10-V RANGE ±12-V RANGE ±10-V RANGE 89.69 90.69 90.53 39.4 90.25 90.4 91.53 91.35 39.4 88.36 90.89 91.01 92.37 92.17 37.5 89.07 91.65 97.79 93.29 93.08 32.0 89.97 90.28 92.76 92.92 94.4 94.21 22.4 LPF 1 91.98 92.21 94.33 94.45 95.65 95.53 12.9 LPF 1 93.61 93.95 95.68 95.83 96.8 96.69 6.8 128 LPF 1 95.53 95.9 97.27 97.42 97.97 98.01 3.4 000 No OSR LPF 2 89.05 89.35 90.98 91.11 91.92 91.85 15.4 001 2 LPF 2 89.94 90.18 91.91 92.01 92.94 92.84 15.4 010 4 LPF 2 90.4 90.65 92.62 92.73 93.82 93.72 15.3 011 8 LPF 2 90.81 91.08 93.2 93.31 94.53 94.42 14.8 100 16 LPF 2 91.39 91.7 93.82 93.95 95.19 95.07 13.3 101 32 LPF 2 92.74 92.96 94.84 94.95 95.99 95.87 10.1 110 64 LPF 2 93.85 94.2 95.91 96.04 96.88 96.85 6.2 111 128 LPF 2 95.62 95.94 97.28 97.47 98.04 98.02 3.4 000 No OSR LPF 3 77.29 77.33 81.12 81.25 84.33 83.58 399.9 001 2 LPF 3 80.11 80.34 83.79 83.95 86.77 86.26 210.3 010 4 LPF 3 82.97 83.24 86.52 86.67 89.25 88.87 108.8 011 8 LPF 3 85.82 86.1 89.14 89.31 91.58 91.28 55.0 100 16 LPF 3 88.53 88.81 91.56 91.73 93.59 93.38 27.6 101 32 LPF 3 91.26 91.5 93.78 93.89 95.28 95.12 13.8 110 64 LPF 3 93.29 93.64 95.49 95.6 96.62 96.52 6.9 111 128 LPF 3 95.46 95.79 97.1 97.27 97.94 97.89 3.5 ±3-V RANGE ±5-V RANGE ±6-V RANGE Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S 33 ADS8686S SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 www.ti.com 7.3.9 Reference The ADS8686S can operate with either an internal or external reference along with an internal gain amplifier. The internal or external reference selection is determined by an external REFSEL pin, as explained in the REFSEL (Input) section. The REFIO pin outputs the internal band-gap voltage (in internal reference mode) or functions as an input to the external reference voltage (in external reference mode). In both cases, the on-chip amplifier is always enabled. Use this internal amplifier to gain the reference voltage and drive the actual reference input of the internal ADC core for maximizing performance. The REFCAP (pin 31) must be decoupled with REFGND (pin 32) using a 10-µF, X5R, or X7R ceramic capacitor. 7.3.9.1 Internal Reference The device has an internal 2.5-V (nominal value) band-gap reference. In order to select the internal reference, the REFSEL pin must be tied high or connected to DVDD. When the internal reference is used, REFIO (pin 33) becomes an output pin with the internal reference value. A 100-nF (minimum) decoupling capacitor, as illustrated in Figure 50, is recommended to be placed between the REFIO pin and REFIO_GND (pin 34). The capacitor must be placed as close to the REFIO pin as possible. The output impedance of the internal band-gap creates a low-pass filter with this capacitor to band-limit the noise of the band-gap output. Using a smaller capacitor increases the reference noise in the system, thus degrading SNR and SINAD performance. Do not use the REFIO pin to drive external AC or DC loads because of the limited current output capability of the pin. The REFIO pin can be used as a reference source if followed by a suitable op amp buffer. REFIO + REFCAP BUF REFSEL ± 10 F 100 nF 2.5 V REF REFGND REFIO_GND Figure 50. Reference Circuitry 7.3.9.2 External Reference For applications that require a reference voltage with a lower temperature drift or a common reference voltage for multiple devices, the ADS8686S offers a provision to use an external reference by using the internal buffer to drive the ADC reference. To select external reference mode, either tie the REFSEL pin low or connect this pin to DGND. In this mode, an external 2.5-V reference must be applied at REFIO (pin 33), which becomes a highimpedance input pin. Any low-drift, small-size external reference can be used in this mode because the internal buffer is optimally designed to handle the dynamic loading on the ADC reference input. The output of the external reference must be filtered to minimize the resulting effect of the reference noise on system performance. Figure 51 shows a typical connection diagram for this mode. TI Device REFSEL DGND REFIO 100 nF AVDD REF5025 (Refer to Device Datasheet for Detailed Pin Configuration) REFIO_GND OUT RREF CREF REFIO_GND Figure 51. Device Connections for Using an External 2.5-V Reference 34 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S ADS8686S www.ti.com SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 7.3.9.3 Supplying One VREF to Multiple Devices For applications that require multiple ADS8686S devices, using the same reference voltage source for all the ADCs helps eliminate any potential errors in the system resulting from mismatch between multiple reference sources. Figure 52 shows the recommended connection diagram for an application that uses one device in internal reference mode and provides the reference source for other devices. The device used as the source of the voltage reference is bypassed by a 10-µF capacitor on the REFIO pin, whereas the other devices are bypassed with a 100-nF capacitor. DVDD TI Device TI Device TI Device REFSEL REFSEL REFSEL DGND REFIO Configured as Output REFIO Configured as Input REFIO Configured as Input 10 …F DGND 100 nF 100 nF REFIO_GND REFIO_GND REFIO_GND Figure 52. Multiple Devices Connected with an Internal Reference from One Device Figure 53 shows the recommended connection diagram for an application that uses an external voltage reference (such as the REF5025) to provide the reference source for multiple devices. TI Device TI Device TI Device REFSEL REFSEL REFSEL DGND REFIO AVDD REFIO_GND OUT DGND REFIO REFIO 100 nF REF5025 (Refer to Device Datasheet for Detailed Pin Configuration) DGND 100 nF 100 nF REFIO_GND REFIO_GND RREF CREF REFIO_GND Figure 53. Multiple Devices Connected Using an External Reference Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S 35 ADS8686S SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 www.ti.com 7.3.10 ADC Transfer Function The ADS8686S outputs 16 bits of conversion data in binary twos complement format for all ranges. The designed code transitions occur midway between successive integer LSB values (that is, 1/2 LSB and 3/2 LSB). The LSB size is the full-scale range ÷ 65,536 for the ADS8686S. Figure 54 and Table 4 show the ideal transfer characteristics for the ADS8686S. The LSB size is dependent on the analog input range selected. 011 «111 ADC OUTPUT CODE 011 «110 LSB FS ( FS) * 2N 000 «001 000 «000 111 «111 100 «010 100 «001 100 «000 ±FS+(0.5)LSB 0V±(0.5)LSB +FS±(1.5)LSB ANALOG INPUT Figure 54. Transfer Characteristics Table 4. ADC Full-Scale Range and LSB Size for Different Ranges 36 RANGE (V) +FS (V) MIDSCALE (V) –FS (V) LSB (µV) ±12 12 0 –12 366 ±10 10 0 –10 305 ±6 6 0 –6 183 ±5 5 0 –5 152 ±3 3 0 –3 92 ±2.5 2.5 0 –2.5 76 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S ADS8686S www.ti.com SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 7.4 Device Functional Modes 7.4.1 Device Interface: Pin Description Multiple digital pins of the ADS8686S are dual function. The pin functionality is decided by the status of the HW_RNGSELx pins at reset. Table 6 outlines the pin functionality in the different modes of operation and interface modes. 7.4.1.1 REFSEL (Input) The REFSEL pin is a digital input pin that enables selection between the internal or external reference mode of operation for the device. If the REFSEL pin is set to logic high, then the internal reference is enabled and selected. If this pin is set to logic low, then the internal band-gap reference circuit is disabled and powered down. In this mode, an external reference voltage must be provided to the REFIO pin. Under both conditions, the internal reference buffer is always enabled. The REFSEL pin status is latched when the RESET pin transitions from low to high. After the reference is configured the changes to the logic level of REFSEL signal are ignored. 7.4.1.2 RESET (Input) The RESET pin is an active-low digital input. A dedicated reset pin allows the device to be reset at any time in an asynchronous manner. The ADS8686S offers two reset modes: full and partial. The RESET pin must be held low to enter one of the reset modes. The duration of the pulled low time decides the reset mode. A partial reset does not affect the programmed values in the software mode or the latched values in the hardware mode of operation. The partial reset reinitializes the internal modules of the device. A full reset programs the device to operate in the default state. The device must always be reset after power-up as well as after recovery from shut-down mode when all the supplies and references have settled to the required accuracy. If the reset is issued during an ongoing conversion process, then the device aborts the conversion and output data are invalid. If the reset signal is applied during a data read operation, then the output data registers are all reset to zero. In order to initiate the next conversion cycle after deactivating a reset condition, allow for a minimum time delay between the rising edge of the RESET input and the rising edge of the CONVST input (see the Timing Requirements table). Any violation in this timing requirement can result in corrupting the results from the next conversion. 7.4.1.3 SEQEN (Input) The SEQEN pin is a digital input pin that enables the internal channel sequencer mode for data capture in the hardware mode of operation. If the SEQEN pin is set to logic high when the device exits the full reset, then the channel sequencer is enabled. The device cycles through the channel sequence with the CONVST signal based on the burst mode selection setting. See the Sequencer section for further details. 7.4.1.4 HW_RANGESEL[1:0] (Input) The HW_RNGSEL pins are digital input pins that select hardware or software mode of operation. The status of these pins are latched at full reset to choose between the software or hardware mode of operation. In hardware mode of operation, the pins also select the analog input range for all the input channels. See the Operation Mode section for further details. 7.4.1.5 SER/BYTE/PAR (Input) The SER/BYTE/PAR is a digital input pin that selects the digital interface option for device communication along with the DB9/BYTESEL pin. If the SER/BYTE/PAR pin is set to logic low at full reset, the parallel interface is selected. If the SER/BYTE/PAR pin is set to logic high at full reset, the serial or byte interface is selected based on the status of the DB9/BYTESEL pin. See the Programming section for further details. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S 37 ADS8686S SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 www.ti.com Device Functional Modes (continued) 7.4.1.6 DB[3:0] (Input/Output) The DB[3:0] are digital input/output pins. In software parallel interface mode (SER/BYTE/PAR = 0, HW_RNGSEL[1:0] = 00), use these pins to program the device during the write operation and read data during the read operation. See the Parallel Interface section for further details. In hardware parallel interface mode (SER/BYTE/PAR = 0, HW_RNGSEL[1:0] ≠ 00), use these pins to read data from the device. See the Parallel Interface section for further details. In software byte interface mode (SER/BYTE/PAR = 1, DB9/BYTESEL = 1, HW_RNGSEL[1:0] = 00), use these pins to program the device during the write operation and read data during the read operation. See the Parallel Byte Interface section for further details. In hardware byte interface mode (SER/BYTE/PAR = 1, DB9/BYTESEL = 1, HW_RNGSEL[1:0] ≠ 00), use these pins to read data from the device. See the Parallel Byte Interface section for further details. In serial interface mode (SER/BYTE/PAR = 1, DB9/BYTESEL = 0) tie these pins to DGND. 7.4.1.7 DB4/SER1W (Input/Output) DB4/SER1W is a dual-function digital input/output pin. In software parallel interface mode (SER/BYTE/PAR = 0, HW_RNGSEL[1:0] = 00), use this pin to program the device during the write operation and read data during the read operation. See the Parallel Interface section for further details. In hardware parallel interface mode (SER/BYTE/PAR = 0, HW_RNGSEL[1:0] ≠ 00), use this pin to read data from the device. See the Parallel Interface section for further details. In software byte interface mode (SER/BYTE/PAR = 1, DB9/BYTESEL = 1, HW_RNGSEL[1:0] = 00), use this pin to program the device during the write operation and read data during the read operation. See the Parallel Byte Interface section for further details. In hardware byte interface mode (SER/BYTE/PAR = 1, DB9/BYTESEL = 1, HW_RNGSEL[1:0] ≠ 00), use this pin to read data from the device. See the Parallel Byte Interface section for further details. In serial interface mode (SER/BYTE/PAR = 1, DB9/BYTESEL = 0) this pin determines if the device serial data output is available only on the SDOA pin or on both the SDOA and SDOB pins. The status is latched at the release of a full reset. If SER1W is low, the serial output is available on SDOA only. If SER1W is high, the serial output is available on SDOA and SDOB. See the Serial Interface section for further details. 7.4.1.8 DB5/CRCEN (Input/Output) DB5/CRCEN is a dual-function digital input/output pin. In software parallel interface mode (SER/BYTE/PAR = 0, HW_RNGSEL[1:0] = 00), use this pin to program the device during the write operation and read data during the read operation. See the Parallel Interface section for further details. In hardware parallel interface mode (SER/BYTE/PAR = 0, HW_RNGSEL[1:0] ≠ 00), use this pin to read data from the device. See the Parallel Interface section for further details. In software byte interface mode (SER/BYTE/PAR = 1, DB9/BYTESEL = 1, HW_RNGSEL[1:0] = 00), use this pin to program the device during the write operation and read data during the read operation. See the Parallel Byte Interface section for further details. In hardware byte interface mode (SER/BYTE/PAR = 1, DB9/BYTESEL = 1, HW_RNGSEL[1:0] ≠ 00), use this pin to read data from the device. See the Parallel Byte Interface section for further details. In serial interface mode (SER/BYTE/PAR = 1, DB9/BYTESEL = 0) this pin acts as the CRC enable input. The status is latched at the release of a full reset. If CRCEN is high, an additional CRC word is sent after the last conversion result. If CRCEN is low, the CRC word is not sent out. See the Interface Diagnosis: SELF TEST and CRC section for further details. 38 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S ADS8686S www.ti.com SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 Device Functional Modes (continued) 7.4.1.9 DB[7:6] (Input/Output) The DB[7:6] are digital input/output pins. In software parallel interface mode (SER/BYTE/PAR = 0, HW_RNGSEL[1:0] = 00), use these pins to program the device during the write operation and read data during the read operation. See the Parallel Interface section for further details. In hardware parallel interface mode (SER/BYTE/PAR = 0, HW_RNGSEL[1:0] ≠ 00), use these pins to read data from the device. See the Parallel Interface section for further details. In software byte interface mode (SER/BYTE/PAR = 1, DB9/BYTESEL = 1, HW_RNGSEL[1:0] = 00), use these pins to program the device during the write operation and read data during the read operation. See the Parallel Byte Interface section for further details. In hardware byte interface mode (SER/BYTE/PAR = 1, DB9/BYTESEL = 1, HW_RNGSEL[1:0] ≠ 00), use these pins read data from the device. See the Parallel Byte Interface section for further details. In serial interface mode (SER/BYTE/PAR = 1, DB9/BYTESEL = 0) tie these pins to DGND. 7.4.1.10 DB8 (Input/Output) In software parallel interface mode (SER/BYTE/PAR = 0, HW_RNGSEL[1:0] = 00), use this pin to program the device during the write operation and read data during the read operation. See the Parallel Interface section for further details. In hardware parallel interface mode (SER/BYTE/PAR = 0, HW_RNGSEL[1:0] ≠ 00), use this pin to read data from device. See the Parallel Interface section for further details. In byte and serial interface modes (SER/BYTE/PAR = 1), tie this pin to DGND. 7.4.1.11 DB9/BYTESEL (Input/Output) DB9/BYTESEL is a dual-function digital input/output pin. In software parallel interface mode (SER/BYTE/PAR = 0, HW_RNGSEL[1:0] = 00), use this pin to program the device during the write operation and read data during the read operation. See the Parallel Interface section for further details. In hardware parallel interface mode (SER/BYTE/PAR = 0, HW_RNGSEL[1:0] ≠ 00), use this pin to read data from the device. See the Parallel Interface section for further details. In byte and serial interface modes (SER/BYTE/PAR = 1), this pin is not used for device communication and is programmed as a device input. The status of this pin is latched at a full reset to determine the byte or serial interface modes. If BYTESEL is high, the byte interface mode is selected. If BYTESEL is low, the serial interface mode is selected. Any digital activity on this pin is ignored after the signal is latched. 7.4.1.12 DB10/SDI (Input/Output) DB10/SDI is a dual-function digital input/output pin. In software parallel interface mode (SER/BYTE/PAR = 0, HW_RNGSEL[1:0] = 00), use this pin to program the device during the write operation and read data during the read operation. See the Parallel Interface section for further details. In hardware parallel interface mode (SER/BYTE/PAR = 0, HW_RNGSEL[1:0] ≠ 00), use this pin to read data from the device. See the Parallel Interface section for further details. In byte interface mode (SER/BYTE/PAR = 1, DB9/BYTESEL = 1), tie this pin to DGND. In software serial interface mode (SER/BYTE/PAR = 1, DB9/BYTESEL = 0, HW_RNGSEL[1:0] = 00) this pin acts as the serial data input for device programmability. See the Serial Interface section for further details. In hardware serial interface mode (SER/BYTE/PAR = 1, DB9/BYTESEL = 0, HW_RNGSEL[1:0] ≠ 00), tie this pin to DGND. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S 39 ADS8686S SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 www.ti.com Device Functional Modes (continued) 7.4.1.13 DB11/SDOB (Input/Output) DB11/SDOB is a dual-function digital input/output pin. In software parallel interface mode (SER/BYTE/PAR = 0, HW_RNGSEL[1:0] = 00), use this pin to program the device during the write operation and read data during the read operation. See the Parallel Interface section for further details. In hardware parallel interface mode (SER/BYTE/PAR = 0, HW_RNGSEL[1:0] ≠ 00), use this pin to read data from the device. See the Parallel Interface section for further details. In byte interface mode (SER/BYTE/PAR = 1, DB9/BYTESEL = 1), tie this pin to DGND. In serial interface mode (SER/BYTE/PAR = 1, DB9/BYTESEL = 0) this pin acts as the serial data output B. See the Serial Interface section for further details. 7.4.1.14 DB12/SDOA (Input/Output) DB12/SDOA is a dual-function digital input/output pin. In software parallel interface mode (SER/BYTE/PAR = 0, HW_RNGSEL[1:0] = 00), use this pin to program the device during the write operation and read data during the read operation. See the Parallel Interface section for further details. In hardware parallel interface mode (SER/BYTE/PAR = 0, HW_RNGSEL[1:0] ≠ 00), use this pin to read data from the device. See the Parallel Interface section for further details. In byte interface mode (SER/BYTE/PAR = 1, DB9/BYTESEL = 1), tie this pin to DGND. In serial interface mode (SER/BYTE/PAR = 1, DB9/BYTESEL = 0) this pin acts as the serial data output A. See the Serial Interface section for further details. 7.4.1.15 DB13/OS0 (Input/Output) DB13/OS0 is a dual-function digital input/output pin. In software parallel interface mode (SER/BYTE/PAR = 0, HW_RNGSEL[1:0] = 00), use this pin to program the device during the write operation and read data during the read operation. See the Parallel Interface section for further details. In hardware parallel interface mode (SER/BYTE/PAR = 0, HW_RNGSEL[1:0] ≠ 00), use this pin to read data from the device. See the Parallel Interface section for further details. In byte interface mode (SER/BYTE/PAR = 1, DB9/BYTESEL = 1), tie this pin to DGND. In hardware serial interface mode (SER/BYTE/PAR = 1, DB9/BYTESEL = 0, HW_RNGSEL[1:0] ≠ 00) this pin acts as the oversampling selection bit 0. The status of this pin is latched at the release of a full reset. See the Digital Filter and Noise section for further details. 7.4.1.16 DB14/OS1 (Input/Output) DB14/OS1 is a dual-function digital input/output pin. In software parallel interface mode (SER/BYTE/PAR = 0, HW_RNGSEL[1:0] = 00), use this pin to program the device during the write operation and read data during the read operation. See the Parallel Interface section for further details. In hardware parallel interface mode (SER/BYTE/PAR = 0, HW_RNGSEL[1:0] ≠ 00), use this pin to read data from the device. See the Parallel Interface section for further details. In byte interface mode (SER/BYTE/PAR = 1, DB9/BYTESEL = 1), tie this pin to DGND. In hardware serial interface mode (SER/BYTE/PAR = 1, DB9/BYTESEL = 0, HW_RNGSEL[1:0] ≠ 00) this pin acts as the oversampling selection bit 1. The status of this pin is latched at the release of a full reset. See the Digital Filter and Noise section for further details. 40 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S ADS8686S www.ti.com SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 Device Functional Modes (continued) 7.4.1.17 DB15/OS2 (Input/Output) DB15/OS2 is a dual-function digital input/output pin. In software parallel interface mode (SER/BYTE/PAR = 0, HW_RNGSEL[1:0] = 00), use this pin to program the device during the write operation and read data during the read operation. See the Parallel Interface section for further details. In hardware parallel interface mode (SER/BYTE/PAR = 0, HW_RNGSEL[1:0] ≠ 00), use this pin to read data from the device. See the Parallel Interface section for further details. In byte interface mode (SER/BYTE/PAR = 1, DB9/BYTESEL = 1), tie this pin to DGND. In hardware serial interface mode (SER/BYTE/PAR = 1, DB9/BYTESEL = 0, HW_RNGSEL[1:0] ≠ 00) this pin acts as the oversampling selection bit 2. The status of this pin is latched at the release of a full reset. See the Digital Filter and Noise section for further details. 7.4.1.18 WR/BURST (Input) WR/BURST is dual-function digital input pin. In software parallel interface mode (SER/BYTE/PAR = 0, HW_RNGSEL[1:0] = 00), use this pin to control the device write operation. The CS and WR signals together enable DB[15:0] as the digital input to program the device. See the Parallel Interface section for further details. In software byte interface mode (SER/BYTE/PAR = 1, DB9/BYTESEL = 1, HW_RNGSEL[1:0] = 00), use this pin to control the device write operation. The CS and WR signals together enable DB[7:0] as the digital input to program the device. See the Parallel Byte Interface section for further details. In software serial interface mode (SER/BYTE/PAR = 1, DB9/BYTESEL = 0, HW_RNGSEL[1:0] = 00), tie this pin to DGND. In hardware mode (HW_RNGSEL[1:0] ≠ 00) this pin acts as the burst mode enable. The status of this pin is latched at the release of a full reset. If the BURST pin is set to logic high, then burst mode is enabled. If the BURST pin is set to logic low, then burst mode is disabled. See the Burst Sequencer section for further details. 7.4.1.19 SCLK/RD (Input) SCLK/RD is dual-function digital input pin. In serial interface mode (SER/BYTE/PAR = 1, DB9/BYTESEL = 0), all synchronous access to the device are timed with respect to rising edge of the SCLK signal. See the Serial Interface section for further details. In parallel interface mode (SER/BYTE/PAR = 0), use this pin to control the device read operation. The CS and RD signals together enable DB[15:0] as the digital output to read from the device. See the Parallel Interface section for further details. In byte interface mode (SER/BYTE/PAR = 1, DB9/BYTESEL = 1), use this pin to control the device read operation. The CS and RD signals together enable DB[7:0] as the digital output to read from the device. See the Parallel Byte Interface section for further details. 7.4.1.20 CS (Input) CS is active-low, chip-select digital input signal. A rising edge on the CS signal programs all data lines in tri-state mode. This function allows multiple devices to share the same output data lines. The falling edge of the CS signal marks the beginning of the output data transfer frame in any interface mode of operation for the device. In the parallel and byte interface modes, both the CS and WR or RD input pins must be driven low to enable the digital bus for writing to registers or reading the conversion data (DB[15:0] for parallel and DB[7:0] for byte interface). In serial mode, the falling edge of the CS signal initiates the data communication using a standard SPI interface in mode 00. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S 41 ADS8686S SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 www.ti.com Device Functional Modes (continued) 7.4.1.21 CHSEL[2:0] (Input) CHSEL[2:0] are digital input pins. In hardware mode (HW_RNGSEL[1:0] ≠ 00, SEQEN = 0), these input pins select the channel for the next conversion. See the Hardware Mode section for further details. In hardware sequence mode (HW_RNGSEL[1:0] ≠ 00, SEQEN = 1), these input pins select the last channel pair in the hardware sequence. See the Hardware Mode Sequencer section for further details. In software mode (HW_RNGSEL[1:0] = 00), tie these pin to DGND. 7.4.1.22 BUSY (Output) BUSY is an active-high digital output pin. BUSY is an active-high digital output signal. This pin goes to logic high after the rising edge of the CONVST signal, indicating that the front-end, track-and-hold circuits for the selected input channels are in hold mode and that the ADC conversion has started. When the BUSY signal goes high, any activity on the CONVST input has no effect on the device. The BUSY output remains high until the conversion process is complete and the conversion data are latched into the output data registers for read out. If the conversion data are read for the previous conversion when BUSY is high, make sure that the data read operation is complete before the falling edge of the BUSY output. In the burst mode of operation, the BUSY pin goes to logic high after the rising edge of the CONVST signal. The BUSY signal stays high until all conversions in the sequence are complete. See the Burst Sequencer section for further details. 7.4.1.23 CONVST (Input) CONVST is an active-high digital input pin. The rising edge of the CONVST pin, when BUSY is low, initiates a new conversion on the selected input channel pair from channel group A and channel group B. For normal mode and sequencer mode of operation, every CONVST signal performs one conversion of the selected channel pair based on the oversampling setting. For burst mode of operation only one CONVST signal is needed for the sequencer to cycle through the channel sequence. The BUSY signal is held high during this duration. 7.4.2 Device Modes of Operation The ADS8686S supports multiple modes of operation that can be enabled using the hardware or software modes of control. The device enters hardware or software mode based on the status of the HW_RNGSEL[1:0] pins at a full reset. In hardware mode, all device configurations are controlled by pin control and access to the internal registers is prohibited. In software mode, the interface and reference configurations are controlled by the respective pins. All other device configurations are enabled though register access only. To switch between hardware mode to software mode or vice-versa, a full reset is required. 7.4.2.1 Shutdown Mode The ADS8686S supports a low-power shutdown mode in which the entire internal circuitry is powered down and all registers are cleared and reset to the default values. In shutdown mode the total power consumption of the device is 700 µW. In order to enter shutdown mode, keep the RESET pin low for greater than 1.2 µs. The device exits shutdown mode when the RESET pin is set from low to high. At this time, the device exits shutdown mode and enters the hardware or software mode of operation based on the status of the HW_RNGSEL[1:0] pins. The power-up time to perform a register write in software mode is approximately 240 µs. A conversion can be initiated after 15 ms. 42 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S ADS8686S www.ti.com SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 Device Functional Modes (continued) 7.4.2.2 Operation Mode 7.4.2.2.1 Hardware Mode The device enters hardware mode if the HW_RNGSEL[1:0] pins are set to either 01, 10, or 11 at the time of a full reset. In hardware mode, the device operates with restricted functionality. All device functionality is configured through the pin control. The logic levels of the following signals at a full reset configure the functionality of the ADS8686S: CRC, BURST, SEQEN, SER/BYTE/PAR, DB9/BYESEL, DB8, and OSx. Table 5 provides a summary of the signals that are latched by the device on the release of a full reset. After the device is configured, a full reset through the RESET pin is required to exit the configuration and set up an alternate configuration. The data communication interface selected also dictates the functionality available in hardware mode. Table 6 provides a full list of the functionality available in hardware parallel, byte, or serial mode. Table 5. Summary of Hardware Pin Behavior LATCHED AT FULL RESET SIGNAL HW MODE SW MODE REFSEL Yes Yes SEQEN Yes HW_RNGSELx (range change) HW_RNGSELx (HW or SW mode) Yes Yes CRCEN Yes No OSx Yes No BURST Yes No SER1W Yes Yes SER/BYTE/PAR Yes Yes DB9/BYTESEL Yes Yes CHSELx READ AT RESET HW MODE SW MODE Yes Yes READ WHEN BUSY HW MODE EDGE DRIVEN SW MODE HW MODE SW MODE Yes Yes Yes Table 6. Pin Functionality Overview OPERATION MODE HARDWARE, HW_RNGSELx ≠ 00 SOFTWARE, HW_RNGSELx = 00 PIN NAME CHSELx SCLK/RD SERIAL, PARALLEL BYTE, SER/BYTE/PAR = 1, SER/BYTE/PAR = 1, DB9/BYTESEL = 0 DB9/BYTESEL = 1 No function, connect to DGND No function, connect to DGND PARALLEL, SER/BYTE/PAR = 0 SERIAL, SER/BYTE/PAR = 1, DB9/BYTESEL = 0 PARALLEL BYTE, SER/BYTE/PAR = 1, DB9/BYTESEL = 1 PARALLEL, SER/BYTE/PAR = 0 No function, connect to DGND CHSELx CHSELx CHSELx SCLK RD RD SCLK RD RD WR/BURST Connect to DGND WR WR BURST BURST BURST DB[15:13]/OS[0:2] Connect to DGND Connect to DGND DB15 to DB13 OSx Connect to DGND DB15 to DB13 DB12/SDOA SDOA Connect to DGND DB12 SDOA Connect to DGND DB12 DB11/SDOB SDOB, leave floating for serial 1-wire mode Connect to DGND DB11 SDOB Connect to DGND DB11 DB10 DB10/SDI SDI Connect to DGND DB10 Connect to DGND Connect to DGND Connect to DGND Connect to DVDD DB9 Connect to DGND Connect to DVDD DB9 DB8 to DB6, DB3 to DB0 Connect to DGND DB8 to DB6, DB3 to DB0 DB8 to DB6, DB3 to DB0 Connect to DGND DB8 to DB6, DB3 to DB0 DB8 to DB6, DB3 to DB0 DB5/CRCEN Connect to DGND DB5 DB5 CRCEN DB5 DB5 DB4/SER1W SER1W DB4 DB4 SER1W DB4 DB4 HW_RNGSELx Connect to DGND Connect to DGND Connect to DGND Configure analog input range Configure analog input range Configure analog input range SEQEN Connect to DGND Connect to DGND Connect to DGND SEQEN SEQEN SEQEN REFSEL REFSEL REFSEL REFSEL REFSEL REFSEL REFSEL DB9/BYTESEL Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S 43 ADS8686S SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 www.ti.com In hardware mode, the CHSELx and HW_RNGSELx control signals can change their state during device operation and have an immediate effect on the device configuration. The CHSELx pins are read at reset to determine the first analog input channel pair to be acquired for conversion. In the sequencer mode of operation, the CHSELx pins configure the settings for the sequencer. See the Sequencer section for additional details. The CHSELx pin status must be kept constant during the ADC conversion process (that is, between the CONVST rising edge and the BUSY falling edge). The status of the CHSELx pins is read during this time to select the next channel pair for conversion or to modify the hardware sequencer setting. The HW_RNGSELx signals program the analog input range. The selected input range is applied to all 16 analog input channels. A logic change on these pins has an immediate effect on the analog input range. Allow for a typical settling time of 120 µs, in addition to the normal acquisition time requirement after the range change. The recommended practice is to hardwire the range select pins according to the desired input range for the system signals. 7.4.2.2.2 Software Mode In software mode, all configuration settings can be controlled except for the reference and interface by programming the on-chip registers. All functionality of the ADS8686S is available when software mode is selected. Table 5 provides a summary of the signals that are latched by the device on the release of a full reset, depending on the mode of operation chosen. 7.4.2.3 Reset Functionality The ADS8686S supports two reset modes: full and partial. The reset mode selected is dependent on the length of the reset low pulse. A partial reset is applied when the RESET pin is held low between 40 ns and 500 ns. A partial reset reinitializes the sequencer, digital filter, SPI, and SAR ADC modules. The ongoing conversion result is discarded on completion of a partial reset. The partial reset does not affect the register values programmed in software mode or the user configuration latched in hardware and software modes. In software mode, a dummy conversion is required after a partial reset. After the release of a partial reset, the device is fully functional after 50 ns and a dummy conversion can be initiated. A full reset is applied when the RESET pin is held low for a minimum of 1.2 µs. A full reset configures the device to its default power-on state. Hardware or software mode, the internal or external reference, and the type of interface are configured when the ADS8686S is released from a full reset. At power-up, the RESET signal must be kept low until the AVDD and DVDD supplies are stable. The RESET signal can be released after the supplies ramp to stable operating conditions. The logic level of the HW_RNGSELx, REFSEL, SER/BYTE/PAR, DB9/BYTESEL, and DB4/SER1W pins are latched when the RESET pin is released to determine the device configuration. After 15 ms from releasing RESET, the device is completely reconfigured and a conversion can be initiated. In hardware mode, the DB8 CRCEN, OSx, BURST, and SEQEN pin status is also latched when the RESET pin transitions from low to high in full reset mode. The changes to these signals are ignored after they are latched until the next full reset. In hardware mode, the analog input range (HW_RNGSELx signals) can be configured during either a full or a partial reset or during normal operation, but hardware or software mode selection requires a full reset to reconfigure when this setting is latched. In hardware mode, the CHSELx and HW_RNGSELx pins are monitored at release from both a full and a partial reset to perform the following actions: • Select the first analog input channel pair to acquire for conversion • Configure the sequencer • Select the analog input voltage range The CHSELx signals are not latched at reset. The channel pair selected for next conversion, or the hardware sequencer, can be reconfigured during normal operation by setting and maintaining the CHSELx signal level before the CONVST rising edge, and holding the signal state constant until BUSY is held high by the device. See the Channel Selection section for further details. 44 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S ADS8686S www.ti.com SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 The HW_RNGSELx signals are not latched in hardware mode. A logic change on these pins has an immediate effect on the range selected. See the Programmable Gain Amplifier (PGA) section for additional details. In software mode, all device functionality is configured by controlling the on-chip registers. Figure 55 shows the device reset configuration and Table 6 lists an overview of the pin functionality. tPWRUP tDEV_STRTUP AVDD DVDD RESET tPL_RST CONVST BUSY tDEV_WRITE CS tSU_RST tHT_RST REFSEL, BYTESEL SER/BYTE/PAR, SER1W DONT CARE HW_RNGSEL[1:0] DONT CARE CRCEN, BURST SEQEN, OS[2:0] DONT CARE CHSEL[2:0] DONT CARE DONT CARE ALL MODES HARDWARE MODE ONLY MODE RANGE SETTING IN HW MODE DONT CARE CHx ACTION DONT CARE ACQx CHy DONT CARE CONVx CHz ACQy DONT CARE CONVy Figure 55. ADS8686S Configuration at Reset Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S 45 ADS8686S SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 www.ti.com 7.4.2.4 Channel Selection 7.4.2.4.1 Hardware Mode Channel Selection In hardware mode, the logic level of the CHSELx signals during an ongoing conversion determine the channel pair for next conversion. Table 7 lists the CHSELx signal decoding information. After a full or partial reset, the CHSELx signal status at the rising edge of the reset signal determines the initial channel pair to sample and convert when the first CONVST signal is available. Set the CHSELx signals to the required channel before CONVST goes from low to high and maintain the status until BUSY goes from high to low, indicating the conversion complete. The device samples the CHSELx status during conversion to select the channel pair for the next conversion. The multiplexer then establishes a relevant connection between the ADC driver of the selected channel and SAR ADC. Figure 56 shows a timing diagram of how this mode is selected. Table 7. CHSELx Pin Decoding CHANNEL SELECTION INPUT PIN ANALOG INPUT CHANNELS FOR CONVERSION CHSEL2 CHSEL1 CHSEL0 0 0 0 AIN_0A, AIN_0B 0 0 1 AIN_1A, AIN_1B 0 1 0 AIN_2A, AIN_2B 0 1 1 AIN_3A, AIN_3B 1 0 0 AIN_4A, AIN_4B 1 0 1 AIN_5A, AIN_5B 1 1 0 AIN_6A, AIN_6B 1 1 1 AIN_7A, AIN_7B RESET CONVST BUSY CHSEL[2:0] DONT CARE CHx DONT CARE DONT CARE CHy DONT CARE CHz A/Bx DATA BUS SETUP CHANNEL CONFIGURE CHANNEL CH... A/By CONFIGURE CHANNEL DONT CARE A/Bz CONFIGURE CHANNEL Figure 56. Hardware Mode Channel Conversion Setting 46 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S ADS8686S www.ti.com SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 7.4.2.4.2 Software Mode Channel Selection In software mode, the channels for conversion are selected by programming the relevant channel register. On power-up or after a reset, the default channels selected for conversion are channel AIN_0A and channel AIN_0B. See Figure 57, Figure 58, and Figure 59 for additional details regarding the channel selection. RESET CHX CONVERSION START CONVST BUSY CS DO NOT CARE SDI SDOA, SDOB CHX CHy CHZ CH.. INVALID A/B0 A/BX A/By Figure 57. Software Serial Mode Channel Conversion Setting RESET CHx CONVERSION START CONVST BUSY CS WR RD DB[7:0] CHX A0 B0 CHy AX BX CHz Figure 58. Software Parallel Byte Mode Channel Conversion Setting Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S 47 ADS8686S SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 www.ti.com RESET CHx CONVERSION START CONVST BUSY CS WR RD DB[15:0] CHX A0 B0 CHy AX BX CHZ Ay By Ch.. Figure 59. Software Parallel Mode Channel Conversion Setting 7.4.2.5 Sequencer The ADS8686S features a highly configurable sequencer functionality. The sequencer enables selection of the internal MUX connection in a predetermined order. This architecture helps reduce the software overhead on the host controller to configure the next channel for conversion. A complete set of sequencer functionality and configurability is available in software mode. The sequencer stack has 32 unique configurable sequence steps. All channels, including the diagnostic channel, can be randomly programmed in any order. Additionally, any channel AIN_nA input can be paired with any channel AIN_nB input or diagnostic channel. The sequencer can be operated with or without the burst function enabled. With the burst function enabled, only one CONVST pulse is required to convert every channel in a sequence. With burst mode disabled, one CONVST pulse is required for every conversion step in the sequence. See the Burst Sequencer section for additional details on operating in burst mode. 7.4.2.5.1 Hardware Mode Sequencer In hardware mode, the sequencer has limited functionality. The sequencer always selects a particular channel pair (for example, AIN_nA and AIN_nB). In hardware mode, the sequencer is controlled by the SEQEN pin and the CHSEL[2:0] pins. The logic level of the SEQEN pin is latched when RESET transitions from logic low to high after a full reset. Table 8 explains the sequencer setting based on the logic state of the SEQEN pin after a full reset. A full reset is required to exit sequencer mode and to setup an alternate configuration. Table 8. Hardware Mode Sequencer Configuration 48 SEQEN INTERFACE MODE 0 Sequencer disabled 1 Sequencer enabled Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S ADS8686S www.ti.com SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 When the sequencer is enabled, the logic levels of the CHSEL[2:0] pins determine the number of channel pairs selected for the conversion in the sequence. The CHSEL[2:0] pins at the time when RESET is released determine the initial settings for the channels to convert in the first sequence. To reconfigure the sequence channels selected for a conversion thereafter, set the CHSEL[2:0] pins to the required setting for the duration of the BUSY pulse for the final conversion in the sequence. Table 9 explains the relationship between the CHSEL[2:0] pin to the channel pairs selected in the sequence. See Figure 60 for further timing sequence details. Table 9. CHSELx Pin Decoding Sequencer CHANNEL SELECTION INPUT PIN ANALOG INPUT CHANNELS FOR SEQUENTIAL CONVERSION CHSEL2 CHSEL1 CHSEL0 0 0 0 AIN_0A, AIN_0B only 0 0 1 AIN_0A, AIN_0B to AIN_1A, AIN_1B 0 1 0 AIN_0A, AIN_0B to AIN_2A, AIN_2B 0 1 1 AIN_0A, AIN_0B to AIN_3A, AIN_3B 1 0 0 AIN_0A, AIN_0B to AIN_4A, AIN_4B 1 0 1 AIN_0A, AIN_0B to AIN_5A, AIN_5B 1 1 0 AIN_0A, AIN_0B to AIN_6A, AIN_6B 1 1 1 AIN_0A, AIN_0B to AIN_7A, AIN_7B RESET SEQEN DONT CARE DONT CARE DONT CARE CONVST BUSY CHSEL[2:0] DONT CARE CHX DATA A/B0 INITIAL SETUP DONT CARE CHY DONT CARE A/BX-1 A/BX A/B0 CHZ A/BY-1 DONT CARE A/BY A/B0 CONFIGURE SEQUENCE CONFIGURE SEQUENCE Figure 60. Hardware Mode Sequencer Configuration Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S 49 ADS8686S SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 www.ti.com 7.4.2.5.2 Software Mode Sequencer In software mode, the ADS8686S offers a 32-stack, fully configurable sequencer. The configuration register and sequencer stack registers can be programmed by using the parallel, byte, or serial interface. Each stack register has two 4-bit fields to control each individual MUX. This structure allows any input from channel AIN_nA to be paired with any input from channel AIN_nB, or to any diagnostic channel. The sequencer depth is programmable from 1 to 32. The sequencer depth is determined by setting the SSRENx bit in the sequencer stack register corresponding to the last step. The channels to convert are selected by programming the ASELx and BSELx bits in each sequence stack register for the depth required. The sequencer is activated by setting the SEQEN bit in the configuration register to 1. The recommended procedure to configure and enable the sequencer (see Figure 61 for additional information) is as follows: 1. Program the analog input range for the required analog input channels. 2. Program the sequencer stack registers (S0, S1,...Sn) to select the channels for the sequence. 3. Set the SSRENx bit in the last required sequence step. 4. Set the SEQEN bit in the configuration register. 5. Provide a dummy CONVST pulse. 6. Provide additional CONVST pulses and read the conversion results. After all sequence steps are cycled through, the sequence automatically restarts from the first element in the sequencer stack with the next CONVST pulse. Following a partial reset, the sequencer pointer is repositioned to the first layer of the stack, but the register programmed values remain unchanged. RESET DUMMY CONVERSION SEQUENCE START SEQUENCE START CONVST BUSY REGISTER SETUP DO NOT CARE DO NOT CARE DO NOT CARE A/B0 DATA S0 S1 Sn S0 Figure 61. Software Mode Sequencer Configuration 50 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S ADS8686S www.ti.com SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 7.4.2.6 Burst Sequencer The ADS8686S offers an additional feature for burst mode capture. This feature is applicable only if the sequencer feature is enabled. With the burst feature enabled, one CONVST pulse initiates conversion of all channels configured in the sequencer. Thus, for a sequencer configured for four channel pairs, only one CONVST pulse must be provided in BURST with the sequencer configuration instead of four CONVST pulses in the sequencer only configuration. When configured, the burst sequence is initiated at the rising edge of CONVST. The BUSY pin goes high and remains high until all conversions in the sequence are complete. If OSR mode is enabled, the sequencer captures the required samples for a given channel pair before moving to the next channel pair in sequencer. The conversion results are available for readback after the BUSY pin goes low. The number of data reads required in the burst sequence are dependent on the length of the sequence configured. The conversion results are presented on the data bus (parallel, byte, or serial) in the same order as the programmed sequence. The throughput rate of the ADS8686S is limited in burst mode because each channel pair requires an acquisition, conversion, and readback time. Equation 1 estimates the time taken to complete a sequence with the number of channel pairs, N. tBURST = (tCONV + 50 ns) + (N – 1) (tACQ + tCONV) + N(tRB) where • • • tCONV is the typical conversion time tACQ is the typical acquisition time tRB is the time required to read back the conversion results in either serial 1-wire, serial 2-wire, parallel byte, or parallel mode (1) Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S 51 ADS8686S SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 www.ti.com 7.4.2.6.1 Hardware Mode Burst Sequencer In hardware mode, set both the BURST and SEQEN pins to logic high to enable burst sequencer mode. The device latches these inputs when the RESET signal transitions from logic low to high after a full reset event. To exit the burst mode of operation, a full reset is needed. When the burst sequencer is enabled, the logic levels of the CHSEL[2:0] pins determine the channels selected for the conversion in the burst sequence. The CHSEL[2:0] pins at the time that RESET is released determines the initial settings for the channels to convert in the burst sequence. To reconfigure the channels selected for conversion after a reset, set the CHSEL[2:0] pins to the required setting for the duration of the next BUSY pulse. Figure 62 shows a timing diagram of this mode. RESET SEQEN DONT CARE DONT CARE BURST DONT CARE DONT CARE CONVST BUSY CHSEL[2:0] DONT CARE CHx DONT CARE CHy DATA DONT CARE A/B0 A/Bx-1 CHz A/Bx CONFIGURE SEQUENCER INITIAL SETUP DONT CARE A/B0 A/By-1 CHz DONT CARE A/B0 A/By A/Bz-1 CHz A/Bz CONFIGURE SEQUENCER CONFIGURE SEQUENCER Figure 62. Burst Sequencer, Hardware Mode 7.4.2.6.2 Software Mode Burst Sequencer In software mode, program the BURST bit in the configuration register to enable burst function. Enable this setting along with the SEQEN bit by programming the configuration register. Figure 63 shows a timing diagram for this mode. RESET CONVST BUSY REGISTER SETUP DONT CARE DONT CARE DONT CARE DATA A/B0 S0 S1 Sn-1 Sn DONT CARE S0 S1 Sn-1 Sn DUMMY CONVERSION Figure 63. Burst Sequencer, Software Mode 52 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S ADS8686S www.ti.com SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 7.4.2.7 Diagnostics 7.4.2.7.1 Analog Diagnosis The ADS8686S supports monitoring of the internal nodes AVDD and ALDO, respectively, along with the 16 analog inputs, AIN_nA and AIN_nB, by using the SAR ADCs. These channels can be monitored in the software mode of operation by programming the channel register (see the Register Maps section) to the corresponding channel identifier. The diagnostic channels can also be added to the sequencer stack. Equation 2 defines the expected output for each diagnostic channel. Figure 64 and Figure 65 show the transfer function for each diagnostic channel. AVDD Code = (:10 × ALDO; F :7 × VREFCAP ;) × 32,768 10 × VREFCAP (2) 29000 -5000 28000 -5800 Expected Output (Code) Expected Output (Code) ALDO Code = k:4 × AVDD; F VREFCAP o × 32,768 5 × VREFCAP 27000 26000 25000 24000 4.7 4.85 5 AVDD V 5.15 5.3 -6600 -7400 -8200 -9000 1.7 D061 Figure 64. AVDD vs Expected Output Code 1.8 1.9 ALDO (V) 2 2.1 D062 Figure 65. ALDO vs Expected Output Code 7.4.2.7.2 Interface Diagnosis: SELF TEST and CRC The ADS8686S features a communication self-test mode and a cyclic redundancy check (CRC) mode. These features help diagnose any issues with the digital interface between the host and the device. The communication self test can be enabled by programming the communication self-test channel in the channel register (see the Register Maps section). When enabled, the device forces the conversion result register to a known fixed output. When the conversion code is read, code 0xAAAA is output as the conversion code of ADC A, and code 0x5555 is output as the conversion code of ADC B. This feature can be accessed in the software mode of operation and is not supported in the hardware mode of operation. The ADS8686S supports a CRC checksum mode to improve interface robustness by detecting errors in data. The CRC feature is available in both software (serial, byte, and parallel) mode and hardware (serial only) mode. The CRC feature is not available in hardware parallel or hardware byte modes. The CRC result is stored in the status register. Enabling the CRC feature enables the status register and vice versa. In hardware mode, set the CRCEN pin to logic high when the ADS8686S is released from a full reset to enable the CRC feature. The logic level of the CRCEN pin is latched when the RESET pin is released. A full reset is required to exit the function and setup an alternative configuration. With CRC enabled, the content of the status register is appended to the conversion result (see the STATUS register in the Register Maps section for details regarding the CRC data structure). In software mode, the CRC function is enabled by setting either the CRCEN bit or the STATUSEN bit in the configuration register to 1. Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S 53 ADS8686S SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 www.ti.com If the CRC function is enabled, a CRC is calculated on the conversion results for channel AIN_nA and channel AIN_nB. The CRC is calculated and transferred on the serial, byte, or parallel interface after the conversion results are transmitted, depending on the configuration of the device. The hamming distance varies in relation to the number of bits in the conversion result. For conversions with less than or equal to 119 bits, the hamming distance is 4. For more than 119 bits, the hamming distance is 1 (that is, 1-bit errors are always detected). 54 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Product Folder Links: ADS8686S ADS8686S www.ti.com SBAS905C – NOVEMBER 2019 – REVISED JULY 2020 The following is a pseudocode description of how the CRC is implemented in the ADS8686S: crc = 8’b0; i = 0; x = number of conversion channel pairs; for (i=0, i