ADS900E/1KG4

ADS900 ADS 900 E SBAS058A – MAY 2001 10-Bit, 20MHz, +3V Supply ANALOG-TO-DIGITAL CONVERTER TM FEATURES DESCRIPTION ● ● ● ● ● ● The ADS900 is a high-speed pipelined Analog-to-Digital Converter (ADC). This complete converter includes a high bandwidth track-and-hold, a 10-bit quantizer, and an internal reference. The ADS900 employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications. Its low distortion and high SNR give the extra margin needed for telecommunications, video and test instrumentation applications. This high-performance ADC is specified for performance at a 20MHz sampling rate. The ADS900 is available in an SSOP-28 package. +2.7V TO +3.7V SUPPLY OPERATION INTERNAL REFERENCE LOW POWER: 52mW at +3V SINGLE-ENDED INPUT RANGE: 1V to 2V WIDEBAND TRACK/HOLD: 350MHz SSOP-28 PACKAGE APPLICATIONS ● ● ● ● ● ● PORTABLE INSTRUMENTATION IF AND BASEBAND COMMUNICATIONS CABLE MODEMS SET-TOP BOXES PORTABLE TEST EQUIPMENT COMPUTER SCANNERS CLK LVDD ADS900 Timing Circuitry 2V IN 1V T/H IN (Opt.) Pipeline A/D Error Correction 3-State Outputs 10-Bit Digital Data Internal Reference LpBy CM LnBy 1VREF Pwrdn OE Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC DISCHARGE SENSITIVITY +VS ....................................................................................................... +6V Analog Input ............................................................................... +VS +0.3V Logic Input ................................................................................. +VS +0.3V Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature ..................................................................... +150°C This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER ADS900E SSOP-28 324 –40°C to +85°C " " " " SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER(1) TRANSPORT MEDIA ADS900E ADS900E ADS900E ADS900E/1K Rails Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “ADS900E/1K” will get a single 1000-piece Tape and Reel. ELECTRICAL CHARACTERISTICS At TA = +25°C, VS = LVDD = +3V, Single-Ended Input, Sampling Rate = 20MHz, unless otherwise specified. ADS900E PARAMETER Resolution Specified Temperature Range ANALOG INPUT Single-Ended Full Scale Input Range Differential Full Scale Input Range Common-Mode Voltage Analog Input Bias Current Input Impedance CONDITIONS TEMP 2 TYP MAX UNITS Bits °C 10 Ambient Air –40 +85 (1Vp-p) (0.5Vp-pX 2) +1.0 +1.25 +2.0 +1.75 DIGITAL INPUTS Logic Family High Input Voltage, VIH Low Input Voltage, VIL High Input Current, IIH Low Input Current, IIL Input Capacitance CONVERSION CHARACTERISTICS Start Conversion Sample Rate Data Latency MIN Full 1.5 1 1.25 || 5 V V V µA MΩ || pF TTL/HCT COMPATIBLE CMOS 2.0 VDD 0.8 ±10 ±10 5 V V µA µA pF RISING EDGE OF CONVERT CLOCK 10k 20M 5 Samples/s Clk Cyc ADS900 SBAS058A ELECTRICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +3V, Single-Ended Input, Sampling Rate = 20MHz, unless otherwise specified. ADS900E PARAMETER DYNAMIC CHARACTERISTICS Differential Linearity Error f = 500kHz (Largest Code Error) f = 10MHz (Largest Code Error) No Missing Codes Integral Nonlinearity Error, f = 500kHz Spurious Free Dynamic Range(1) f = 500kHz (–1dBFS(2) input) f = 10MHz (–1dBFS(2) input) Two-Tone Intermodulation Distortion(3) f = 4.5MHz and 5.0MHz (–7dBFS each tone) Signal-to-Noise Ratio (SNR) f = 500kHz (–1dBFS input) f = 10MHz (–1dBFS input) Signal-to-(Noise + Distortion) (SINAD) f = 500kHz (–1dBFS input) f = 3.58MHz (–1dBFS input) f = 10MHz (–1dBFS input) Differential Gain Error Differential Phase Error Output Noise Aperture Delay Time Aperture Jitter Analog Input Bandwidth Small Signal Full Power Overvoltage Recovery Time(4) DIGITAL OUTPUTS Logic Family Logic Coding High Output Voltage, VOH Low Output Voltage, VOL 3-State Enable Time 3-State Disable Time Internal Pull-Down Power-Down Enable Time Power-Down Disable Time Internal Pull-Down ACCURACY Gain Error Input Offset Power Supply Rejection (Gain) Power Supply Rejection (Offset) Internal Positive Reference Voltage Internal Negative Reference Voltage POWER SUPPLY REQUIREMENTS Supply Voltage: +VS Supply Current: +IS Power Dissipation Power Dissipation (Power Down) Thermal Resistance, θJA SSOP-28 CONDITIONS TEMP MIN ±0.7 ±0.7 Guaranteed ±3.5 Full Full Full Full Full Full Full Full Full UNITS ±1.0 LSBs LSBs LSBs dBFS(2) dBFS 50 dBc 49 49 dB dB 48 48 48 2.3 1 0.2 2 7 dB dB dB % degrees LSBs rms ns ps rms 350 100 2 MHz MHz ns TTL/HCT COMPATIBLE CMOS Straight Offset Binary +2.4 LVDD +0.4 20 40 2 10 50 133 18 50 V V ns ns kΩ ns ns kΩ 45 44 NTSC, PAL NTSC, PAL Input Grounded –20dBFS Input 0dBFS Input 1.5X FS Input MAX 53 53 47 +25°C Full Full TYP +25°C +25°C +25°C CL = 15pF OE = L OE = H PwrDn = L PwrDn = H fS = 2.5MHz Referred to Ideal Midscale ∆ VS = +10% Operating Operating Operating, +3V +3V +25°C Full Full Full Full Full Full Full Full 25°C Full +2.7 8 15 55 62 +1.75 +1.25 ±10 ±60 %FS mV dB dB V V +3 18 54 52 10 +3.7 22 66 V mA mW mW mW 89 °C/W NOTES: (1) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to full scale. (3) Two-tone intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental envelope. (4) No rollover of bits. ADS900 SBAS058A 3 PIN CONFIGURATION PIN DESCRIPTIONS Top View SSOP +VS 1 28 +VS LVDD 2 27 IN LSB Bit 10 3 26 CM Bit 9 4 25 LnBy Bit 8 5 24 IN Bit 7 6 23 1VREF Bit 6 7 22 NC Bit 5 8 21 LpBy Bit 4 9 20 GND Bit 3 10 19 GND Bit 2 11 18 +VS MSB Bit 1 12 17 Pwrdn GND 13 16 OE GND 14 15 CLK ADS900 PIN DESIGNATOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 +VS LVDD Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 GND GND CLK OE Pwrdn +VS GND GND LpBy NC 1VREF IN LnBy CM IN +VS DESCRIPTION Analog Supply Output Logic Driver Supply Voltage Data Bit 10 (D0) (LSB) Data Bit 9 (D1) Data Bit 8 (D2) Data Bit 7 (D3) Data Bit 6 (D4) Data Bit 5 (D5) Data Bit 4 (D6) Data Bit 3 (D7) Data Bit 2 (D8) Data Bit 1 (D9) (MSB) Analog Ground Analog Ground Convert Clock Input Output Enable, Active Low Power Down Pin Analog Supply Analog Ground Analog Ground Positive Ladder Bypass No Connection 1V Reference Output Complementary Input Negative Ladder Bypass Common-Mode Voltage Output Analog Input Analog Supply TIMING DIAGRAM N+2 N+1 Analog In N+4 N+3 N tD N+5 tL tCONV N+6 N+7 tH Clock 5 Clock Cycles t2 Data Out N–5 N–4 N–3 N–2 N–1 N Data Invalid SYMBOL tCONV tL tH tD t1 t2 4 N+1 N+2 t1 DESCRIPTION MIN Convert Clock Period Clock Pulse Low Clock Pulse High Aperture Delay Data Hold Time, CL = 0pF New Data Delay Time, CL = 15pF max 50 24 24 TYP MAX UNITS 100µs ns ns ns ns ns ns 25 25 2 3.9 12 ADS900 SBAS058A TYPICAL CHARACTERISTICS At TA = +25°C, VS = LVDD = +3V, Single-Ended Input, Sampling Rate = 20MHz, unless otherwise specified. SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE 0 0 fIN = 500kHz fIN = 3MHz –20 Amplitude (dB) Amplitude (dB) –20 –40 –60 –80 –40 –60 –80 –100 –100 0 2 4 6 8 10 0 2 4 Frequency (MHz) SPECTRAL PERFORMANCE 10 0 fIN = 9MHz –20 f1 = 3.5MHz at –7dBFS f2 = 3.4MHz at –7dBFS Magnitude (dBFS) –20 –40 –60 –80 –40 –60 –80 –100 –100 0 2 4 6 8 10 0 2 4 Frequency (MHz) 6 8 10 Frequency (MHz) DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR 2.0 2.0 fIN = 500kHz fIN = 10MHz 1.0 Error (LSB) 1.0 DLE (LSB) 8 TWO-TONE INTERMODULATION 0 Amplitude (dB) 6 Frequency (MHz) 0.0 0.0 –1.0 –1.0 –2.0 –2.0 0 256 512 Output Code ADS900 SBAS058A 768 1024 0 256 512 768 1024 Output Code 5 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = LVDD = +3V, Single-Ended Input, Sampling Rate = 20MHz, unless otherwise specified. SWEPT POWER SFDR INTEGRAL LINEARITY ERROR 60 10.0 fIN = 500kHz 50 SFDR (dBFS, dBc) ILE (LSB) 5.0 0 40 dBFS 30 20 –5.0 dBc 10 0 –10.0 0 200 400 600 800 –80 1000 –60 –40 –20 –10 0 UNDERSAMPLING (With Differential Input) DYNAMIC PERFORMANCE vs INPUT FREQUENCY 0 54 fIN = 20MHz fS = 16MHz –20 Amplitude (dB) 53 SFDR, SNR (dB) –30 Input Amplitude Output Code SFDR 52 51 –40 –60 –80 SNR 50 –100 –120 49 0.1 1 10 0 100 2 4 6 8 Frequency (MHz) Frequency (MHz) DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE SPURIOUS FREE DYNAMIC RANGE (SFDR) vs TEMPERATURE 0.8 60 fIN = 500kHz SFDR (dBFS) DLE (LSBs) fIN = 500kHz 0.7 fIN = 10MHz 0.6 0.5 fIN = 10MHz 50 45 –50 –25 0 25 50 Temperature (°C) 6 55 75 100 –50 –25 0 25 50 75 100 Temperature (°C) ADS900 SBAS058A TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = LVDD = +3V, Single-Ended Input, Sampling Rate = 20MHz, unless otherwise specified. SIGNAL-TO-NOISE RATIO (SNR) vs TEMPERATURE POWER DISSIPATION vs TEMPERATURE 55 65 fIN = 10MHz fIN = 500kHz 45 40 –50 60 Power (mW) SNR (dB) 50 55 50 –25 0 25 50 75 100 –50 –25 0 Temperature (°C) GAIN ERROR vs TEMPERATURE 50 75 100 OFFSET ERROR vs TEMPERATURE 6.5 –25 6.0 –30 Offset Error (mV) Gain (%FSR) 25 Temperature (°C) 5.5 5.0 –35 –40 4.5 –45 –50 –25 0 25 50 75 100 –50 –25 Temperature (°C) 0 25 50 75 100 Temperature (°C) OUTPUT NOISE HISTOGRAM (DC Input) 500 Counts 400 300 200 100 0 N-3 N-2 N-1 N N+1 N+2 N+3 Output Code ADS900 SBAS058A 7 THEORY OF OPERATION Op Amp Bias The ADS900 is a high speed sampling ADC that utilizes a pipeline architecture. The fully differential topology and digital error correction guarantee 10-bit resolution. The track-and-hold circuit is shown in Figure 1. The switches are controlled by an internal clock which has a non-overlapping two phase signal, φ1 and φ2. At the sampling time the input signal is sampled on the bottom plates of the input capacitors. In the next clock phase, φ2, the bottom plates of the input capacitors are connected together and the feedback capacitors are switched to the op amp output. At this time the charge redistributes between CI and CH, completing one track-and-hold cycle. The differential output is a held DC representation of the analog input at the sample time. In the normal mode of operation, the complementary input is tied to the common-mode voltage. In this case, the track-andhold circuit converts a single-ended input signal into a fully differential signal for the quantizer. Consequently, the input signal gets amplified by a gain or two, which improves the signal-to-noise performance. Other parameters such as smallsignal and full-power bandwidth, and wideband noise are also defined in this stage. IN IN φ1 CH φ2 CI IN IN (Opt.) φ1 φ2 OUT φ1 OUT φ1 CI φ2 CH φ1 φ1 Input Clock (50%) Op Amp Bias VCM Internal Non-overlapping Clock φ1 φ2 φ1 FIGURE 1. Input Track-And-Hold Configuration with Timing Signals. Digital Delay Input T/H (Opt.) 2-Bit Flash STAGE 1 φ1 VCM 2-Bit DAC + Σ – x2 Digital Delay STAGE 2 B1 (MSB) 2-Bit DAC B2 Digital Error Correction 2-Bit Flash + Σ – x2 B3 B4 B5 B6 B7 B8 B9 Digital Delay 2-Bit Flash STAGE 8 B10 (LSB) 2-Bit DAC + Σ – x2 STAGE 9 2-Bit Flash Digital Delay FIGURE 2. Pipeline A/D Architecture. 8 ADS900 SBAS058A The pipelined quantizer architecture has 9 stages with each stage containing a two-bit quantizer and a two bit Digitalto-Analog Converter (DAC), as shown in Figure 2. Each two-bit quantizer stage converts on the edge of the subclock, which is the same frequency of the externally applied clock. The output of each quantizer is fed into its own delay line to time-align it with the data created from the following quantizer stages. This aligned data is fed into a digital error correction circuit which can adjust the output data based on the information found on the redundant bits. This technique provides the ADS900 with excellent differential linearity and guarantees no missing codes at the 10-bit level. The ADS900 includes an internal reference circuit that provides the bias voltages for the internal stages (for details see “Internal Reference”). A midpoint voltage is established by the built-in resistor ladder that is made available at pin 26 “CM”. This voltage can be used to bias the inputs up to the recommended common-mode voltage or used to level shift the input driving circuitry. The ADS900 can be used in both a single-ended or differential input configuration. When operated in single-ended mode, the reference midpoint (pin 26) should be tied to the inverting input, pin 24. To accommodate a bipolar signal swing, the ADS900 operates with a common-mode voltage (VCM) which is derived from the internal references. Due to the symmetric resistor ladder inside the ADS900, the VCM is situated between the top and bottom reference voltage. The following equation can be used for calculating the common-mode voltage level. VCM = (REFT +REFB)/2 SINGLE-ENDED INPUT (IN = 1.5V DC) +FS (IN = +2V) +FS –1LSB +FS –2LSB +3/4 Full Scale +1/2 Full Scale +1/4 Full Scale +1LSB Bipolar Zero (IN +1.5V) –1LSB –1/4 Full Scale –1/2 Full Scale –3/4 Full Scale –FS +1LSB –FS (IN = +1V) 1111111111 1111111111 1111111110 1110000000 1100000000 1010000000 1000000001 1000000000 0111111111 0110000000 0100000000 0010000000 0000000001 0000000000 APPLICATIONS DRIVING THE ANALOG INPUTS Figure 3 shows an example of an ac-coupled, single-ended interface circuit using high-speed op amps that operate on dual supplies (OPA650, OPA658, OPA680 and OPA681). The common-mode reference voltage (VCM), here +1.5V, biases the bipolar, ground-referenced input signal. The capacitor C1 and resistor R1 form a high-pass filter with the –3dB frequency set at f–3dB = 1/(2 π R1 C1) (2) +3V +5V VIN OPA65x OPA68x RS C1 0.1µF IN IN –5V R1 1kΩ ADS900 CM 1.5V 402Ω VCM 0.1µF 402Ω (1) DIGITAL OUTPUT DATA The 10-bit output data is provided at CMOS logic levels. There is a 5.0 clock cycle data latency from the start convert signal to the valid output data. The standard output coding is Straight Offset Binary where a full scale input signal corresponds to all “1’s” at the output. The digital outputs of the ADS900 can be set to a high impedance state by driving the OE (pin 16) with a logic “HI”. Normal operation is achieved with pin 16 “LO” or Floating due to internal pulldown resistor. This function is provided for testability STRAIGHT OFFSET BINARY (SOB) PIN 12 FLOATING or LO purposes but is not recommended to be used dynamically. The capacitive loading on the digital outputs should be kept below 15pF. FIGURE 3. AC-Coupled Driver. The values for C1 and R1 are not critical in most applications and can be set freely. The values shown correspond to a –3dB corner frequency of 1.6kHz. Figure 4 depicts a circuit that can be used in single-supply applications. The common-mode voltage biases the op amp up to the appropriate common-mode voltage, for example VCM = +1.5V. With the use of capacitor CG the DC gain for the non-inverting op amp input is set to +1V/V. As a result the transfer function is modified to VOUT = VIN {(1 + RF /RG) + VCM} (3) Again, the input coupling capacitor C1 and resistor R1 form a high-pass filter. At the same time the input impedance is defined by R1. Resistor RS isolates the op amp’s output from the capacitive load to avoid gain peaking or even oscillation. It can also be used to establish a defined roll-off for the wideband noise. Its value is usually between 10Ω and 100Ω. DIFFERENTIAL MODE OF OPERATION Some minor performance improvements in SFDR and THD can be realized by operating the ADS900 in its optional differential configuration. A RF-transformer with a center tap provides the best method of performing a single-ended to differential conversion and interface directly to the ADS900. TABLE I. Coding Table for the ADS900. ADS900 SBAS058A 9 As a passive component, a transformer can be used to stepup the signal amplitude without adding noise or distortion. At the same time it electrically isolates the front-end from the converter. In order to achieve optimum performance and to bias the converter inputs up to the correct common-mode voltage the mid-reference pin “CM” can be tied directly to the center tap of the transformer. input signal swings 1Vp-p centered around a typical common-mode voltage of +1.5V. This voltage can be derived from the internal bottom reference (REFB = +1.25V) and then fed back through a resistor divider (R1, R2) to level shift the driving op amp (OPA680). A capacitor across R2 will shunt most of the wideband noise to ground. Depending on the configured gain the values of resistors R1 and R2 must be adjusted since the offsetting voltage (VOS) is amplified by the non-inverting gain, 1+(RF/RIN). This example assumes the sum of R1 and R2 to be 5kΩ, drawing only 250µA from the bottom reference. Considerations for the selection of a Figure 6 shows an example for a single-ended DC-coupled interface circuit using one high-speed op amp to level-shift the ground-referenced input signal to condition it for the input requirements of the ADS900. With a +3V supply the +3V +5V C1 0.1µF RS 50Ω VIN IN OPA68x R1 1kΩ 22pF ADS900 IN CM VCM = 1.5V RF 402Ω 0.1µF RG 402Ω CG 0.1µF FIGURE 4. Driver Circuit Using Single Supply. +3V RS VIN T1 OPA65x 22pF RT R1 IN ADS900 IN CM 22pF R2 0.1µF RF Transformer: Minicircuits TT1-6 FIGURE 5. Single-Ended to Differential Drive Circuit Using a Transformer. +5V RF +3V VCM = 1.5V RIN RS VIN ADS900 IN OPA680 22pF IN CM REFB +1.25V VOS +1.5V 0.1µF R2 R1 0.1µF 0.1µF I = 250µA FIGURE 6. Single-Ended DC-Coupled Input Circuit. 10 ADS900 SBAS058A proper op amp should include its output swing, input common-mode range, and bias current. It should be noted that any DC voltage difference between the inputs, IN and IN, will show up as an offset at the output. At the same time an offset adjustment can be accomplished. mended to meet the rated performance specifications. However, the ADS900 performance is tolerant to duty cycle variations of as much as ±10% without degradation. For applications operating with input frequencies up to Nyquist or undersampling applications, special considerations must be made to provide a clock with very low jitter. Clock jitter leads to aperture jitter (tA) which can be the ultimate limitation in achieving good SNR performance. The following equation shows the relationship between aperture jitter, input frequency and the signal-to-noise ratio: INTERNAL REFERENCE The ADS900 features an internal pipeline reference that provides fixed reference voltages for the internal stages. As shown in Figure 7 a buffer for each the top and bottom reference is connected to the resistor ladder, which has a nominal resistance of 4kΩ (±15%). The two outputs of the buffers are brought out at pin 21 (LpBy) and pin 25 (LnBy), primarily to connect external bypass capacitors, typically 0.1µF, which will improve the performance. The buffers can drive limited external loads, for example for level shifting of the converter’s interface circuit, however, the current draw should be limited to approximately 1mA. SNR = 20log10 [1/(2 π fIN tA)] (4) For example, in the case of a 10MHz full-scale input signal and an aperture jitter of tA = 20ps the SNR is clock jitter limited to 58dB. DIGITAL OUTPUTS The digital outputs of the ADS900 are standard CMOS stages and designed to be compatible to both high speed TTL and CMOS logic families. The logic thresholds are for low-voltage CMOS: VOL = 0.4V, VOH = 2.4V, which allows the ADS900 to directly interface to 3V-logic. The digital outputs of the ADS900 uses a dedicated digital supply pin (pin 2, LVDD) see Figure 8. By adjusting the voltage on LVDD, the digital output levels will vary respectively. It is recommended to limit the fan-out to one to keep the capacitive loading on the data lines below the specified 15pF. If necessary, external buffers or latches may be used which provide the added benefit of isolating the ADC from any digital activities on the bus coupling back high frequency noise and degrading the performance. Derived from the top reference of +1.75V is an additional voltage of +1.0V. Note that this voltage, available on pin 23, is not buffered and care should be taken when external loads are applied. In normal operation, this pin is left unconnected and no bypassing components are required. CLOCK INPUT REQUIREMENTS The clock input of the ADS900 is designed to accommodate either +5V or +3V CMOS logic levels. To drive the clock input with a minimum amount of duty cycle variation and support maximum sampling rates (20Msps) high speed or advanced CMOS logic should be used (HC/HCT, AC/ACT). When digitizing at high sampling rates, a 50% duty cycle along with fast rise and fall times (2ns or less) are recom- ADS900 +1.75V 21 REFT LpBy 0.1µF 2kΩ CM 2.1kΩ 23 26 +1VREF 2.8kΩ 0.1µF 2kΩ +1.25V REFB 25 LnBy 0.1µF FIGURE 7. Internal Reference Structure and Recommended Reference Bypassing. ADS900 SBAS058A 11 POWER-DOWN MODE The ADS900’s low power consumption can be reduced even further by initiating a power down mode. For this, the Power Down Pin (Pin 17) must be tied to a logic “High” reducing the current drawn from the supply by about 70%. In normal operation the power-down mode is disabled by an internal pull-down resistor (50kΩ). During power-down the digital outputs are set in 3-state. With the clock applied, the converter does not accurately process the sampled signal. After removing the power-down condition the output data from the following 5 clock cycles is invalid (data latency). DECOUPLING AND GROUNDING CONSIDERATIONS The ADS900 has several supply pins, one of which is dedicated to only supply the output driver (LVDD). The remaining supply pins are not divided into analog and digital supply pins since they are internally connected on the chip. For this reason it is recommended to treat the converter as an analog component and to power it from the analog supply only. Digital supply lines often carry high levels of noise which can couple back into the converter and limit the performance. Because of its fast switching architecture, the converter also generates high frequency transients and noise that are fed back into the supply and reference lines. This requires that the supply and reference pins be sufficiently bypassed. Figure 9 shows the recommended decoupling scheme for the analog supplies. In most cases 0.1µF ceramic chip capacitors are adequate to keep the impedance low over a wide frequency range. Their effectiveness largely depends on the proximity to the individual supply pin. Therefore they should be located as close to the supply pins are possible. 12 +VS +LVDD Digital Output Stage ADS900 FIGURE 8. Independent Supply Connection for Output Stage. ADS900 +VS 1 GND 13 14 0.1µF +VS 18 0.1µF GND 19 20 +VS 28 0.1µF FIGURE 9. Recommended Bypassing for Analog Supply Pins. ADS900 SBAS058A PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS900E ACTIVE SSOP DB 28 50 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS900E ADS900E/1K ACTIVE SSOP DB 28 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ADS900E (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of