User's Guide
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ADS9110EVM-PDK
This user's guide describes the characteristics, operation, and use of the ADS9110 Evaluation Module
(EVM) performance demonstration kit (PDK). This kit is an evaluation platform for ADS9110, which is an
18-bit, 2-MSPS, fully-differential input, successive approximation register (SAR) analog-to-digital converter
(ADC) that features an enhanced serial multiSPI® digital interface. The EVM-PDK eases the evaluation of
the ADS9110 device with hardware, software, and computer connectivity through the universal serial bus
(USB) interface. This user's guide includes complete circuit descriptions, schematic diagrams, and a bill of
materials.
The following related documents are available through the Texas Instruments web site at www.ti.com.
Related Documentation
Device
Literature Number
ADS9110
SBAS629
OPA625
SBOS688
OPA376
SBOS406
OPA378
SBOS417
TPS7A4700
SBVS204
SN74LVC1G08
SCES217
SN74LVC1G17
SCES351
TLV3012
SBOS300
multiSPI is a registered trademark of Texas Instruments.
Microsoft, Windows are registered trademarks of Microsoft Corporation.
LabVIEW is a trademark of National Instruments.
All other trademarks are the property of their respective owners.
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Contents
Overview ...................................................................................................................... 4
1.1
ADS9110EVM-PDK Features ..................................................................................... 4
1.2
ADS9110EVM Features ........................................................................................... 4
Analog Interface.............................................................................................................. 5
2.1
Connectors for Differential Signal Source ....................................................................... 5
2.2
ADC Differential Input Signal Driver .............................................................................. 5
2.3
Onboard ADC Reference .......................................................................................... 8
Digital Interfaces ............................................................................................................. 8
3.1
multiSPI® for ADC Digital IO ...................................................................................... 8
Power Supplies .............................................................................................................. 9
ADS9110EVM-PDK Initial Setup .......................................................................................... 9
5.1
Default Jumper Settings ........................................................................................... 9
5.2
EVM Graphical User Interface (GUI) Software Installation .................................................... 9
ADS9110EVM-PDK Operation ........................................................................................... 14
6.1
EVM GUI Global Settings for ADC Control .................................................................... 16
6.2
Register Map Configuration Tool ................................................................................ 17
6.3
Time Domain Display Tool ....................................................................................... 17
6.4
Spectral Analysis Tool ............................................................................................ 18
6.5
Histogram Tool .................................................................................................... 19
6.6
Linearity Analysis Tool ............................................................................................ 21
Bill of Materials, PCB Layout, and Schematics......................................................................... 23
7.1
Bill of Materials .................................................................................................... 23
7.2
PCB Layout ........................................................................................................ 26
7.3
Schematic .......................................................................................................... 30
List of Figures
..................................................................................
1
OPA625 Differential Input Driving Path
2
Common Mode Selection Jumpers ........................................................................................ 7
3
Onboard Reference Signal Path ........................................................................................... 8
4
ADS9110 Software Installation Prompts ................................................................................ 10
5
Device Driver Installation Wizard Prompts .............................................................................. 11
6
LabVIEW Run-Time Engine Installation ................................................................................. 12
7
ADS9110 EVM Folder Post-Installation ................................................................................. 13
8
EVM-PDK Hardware Setup and LED Indicators ....................................................................... 14
9
Launch the EVM GUI Software ........................................................................................... 15
10
EVM GUI Global Input Parameters ...................................................................................... 16
11
Register Map Configuration ............................................................................................... 17
12
Time Domain Display Tool Options ...................................................................................... 18
13
Spectral Analysis Tool ..................................................................................................... 19
14
Histogram Analysis Tool................................................................................................... 20
15
Linearity Analysis Tool ..................................................................................................... 22
16
ADS9110EVM PCB Layer 1: Top Layer
17
ADS9110EVM PCB Layer 2: GND Plane ............................................................................... 27
18
ADS9110EVM PCB Layer 3: Power Planes ............................................................................ 28
19
ADS9110EVM PCB Layer 4: Bottom Layer
20
Schematic Diagram (Page 1) of the ADS9110EVM PCB ............................................................. 30
21
Schematic Diagram (Page 2) of the ADS9110EVM PCB ............................................................. 31
22
Schematic Diagram (Page 3) of the ADS9110EVM PCB ............................................................. 32
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29
List of Tables
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J7 and J3 SMA Connectors Description .................................................................................. 5
2
J4 and J6 Headers Description ............................................................................................ 5
3
J1 and J2 Configuration per Input Common Mode ...................................................................... 7
4
External Source Requirements for ADS9110 Evaluation ............................................................. 18
5
External Source Requirements for ADS9110 Evaluation ............................................................. 21
6
ADS9110EVM Bill of Materials
..........................................................................................
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3
Overview
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Overview
The ADS9110EVM-PDK is a platform for evaluating the performance of the ADS9110 SAR ADC, which is
a fully-differential input, 18-bit, 2-MSPS device. The evaluation kit includes the ADS9110EVM board and
the Precision Host Interface (PHI) controller board that enables the accompanying computer software to
communicate with the ADC over USB for data capture and analysis.
The ADS9110EVM board includes the ADS9110 SAR ADC, all the peripheral analog circuits and
components required to extract optimum performance from the ADC.
The PHI board primarily serves three functions:
• Provides a communication interface from the EVM to the computer through a USB port
• Provides the digital input and output signals necessary to communicate with the ADS9110EVM
• Supplies power to all active circuitry on the ADS9110EVM board
Along with the ADS9110EVM and PHI controller boards, this evaluation kit includes a microSD memory
card used by the PHI controller during power up and an A-to-micro-B USB cable to connect to a computer.
1.1
ADS9110EVM-PDK Features
The ADS9110EVM-PDK includes the following features:
• Hardware and software required for diagnostic testing as well as accurate performance evaluation of
the ADS9110 ADC
• USB powered - no external power supply is required
• The PHI controller that provides a convenient communication interface to the ADS9110 ADC over a
USB 2.0 (or higher) for power delivery as well as digital input and output
• Easy-to-use evaluation software for Microsoft® Windows® 7, Windows 8, 64-bit operating systems
• The software suite includes graphical tools for data capture, histogram analysis, spectral analysis, and
linearity analysis. It also has a provision for exporting data to a text file for post-processing
1.2
ADS9110EVM Features
The ADS9110EVM includes the following features:
• On-board low-noise and low distortion ADC input drivers optimized to meet ADC performance
• On-board precision 4.5-V voltage reference filtered and followed by a low-noise, low-offset and lowimpedance buffer. The reference driver circuit is optimized for 1-LSB voltage regulation under
maximum loading conditions at full device throughput of 2 MSPS.
• Jumper-selectable 0-V and 2.25-V input common mode options allow uni-polar and bi-polar inputs
• On-board ultra low noise low-dropout (LDO) regulator for excellent 5-V single supply regulation of all
operation amplifiers and voltage reference
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2
Analog Interface
As an analog interface, the evaluation board uses operational amplifiers in a variety of configurations to
drive the ADS9110 signal and reference inputs. This section covers driver details including jumper
configuration for different input signal common modes and board connectors for a differential signal
source.
2.1
Connectors for Differential Signal Source
The ADS9110EVM is designed for easy interfacing to external analog differential source via SMA
connector or 100-mil headers. J7 and J3 are SMA connectors that allow analog source connectivity
through coaxial cables. Also, 100-mil jumper cables or mini-grabbers can be used to connect analog
sources to J4:2 and J6:2 pins.
NOTE: The input does not support single-ended signals. The external source must be differential or
balanced keeping the negative and positive inputs to the board symmetric such that Vs(+) =
–Vs(–) at any given time.
Table 1. J7 and J3 SMA Connectors Description
Pin Number
Signal
Description
J3
Vs(–)
Negative Differential Board Input
1-kΩ Input Impedance
J7
Vs(+)
Positive Differential Board Input
1-kΩ Input Impedance
Table 2. J4 and J6 Headers Description
2.2
Pin Number
Signal
Description
J4 : 3
TEST 0.2V
DO NOT USE: Diagnostic use only
J4 : 2
Vs(–)
Negative Differential Board Input
1-kΩ Input Impedance
J4 : 1
AGND
Analog ground
J6 : 3
AGND
Analog ground
J6 : 2
Vs(+)
Positive Differential Board Input
1-kΩ Input Impedance
J6 : 1
TEST 4.3V
DO NOT USE: Diagnostic use only
ADC Differential Input Signal Driver
The differential signal inputs of the ADS9110 are not dynamically high impedance. SAR ADC inputs
terminate in switched-capacitor networks that create large instantaneous current loads when the switches
are closed that effectively make the ADC inputs dynamically low impedance. Thus, the evaluation board
has low impedance on board drivers that maintain ADC performance with maximum loading at the full
device throughput of 2 MSPS for signal and reference inputs.
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Input Signal Path
Figure 1 shows the signal path for the differential signal applied at the board inputs. The board input
impedance is 1-kΩ with 10-nF differential filtering that keeps noise in external cabling common. The
overall signal path bandwidth is limited to 160-kHz by the anti-aliasing filter formed from 1-kΩ resistor and
1-nF capacitor at the amplifier feedback. Finally, the two OPA625 operational amplifiers drive the
ADS9110 differential inputs with 2.2-Ω impedance up to 7-MHz that properly drives the low dynamic
impedance of the ADC inputs at 2 MSPS.
Figure 1. OPA625 Differential Input Driving Path
2.2.2
Input Common Mode Jumper Configuration
The ADS9110EVM board accommodates three external source common mode options: 0 V, 2.25 V, and
floating with jumpers J1 and J2 as shown in Figure 2.
J2 selects the OPA625 common mode as 2.25 V(J2:OPEN) or 1.25 V(J2:CLOSED). J1 increases the
OPA625 common mode by almost 100 mV to avoid amplifier output saturation with full-scale external
source signal amplitude. R1 is installed as 280 kΩ, allowing full-scale external source signals for external
source impedance (RS) between 0 Ω and 32 Ω, with 0-V common mode. R1 must be changed to
compensate for larger external source impedance (RS) values or for 2.25-V external source common mode
as explained in Section 2.2.3.
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Figure 2. Common Mode Selection Jumpers
Table 3. J1 and J2 Configuration per Input Common Mode
J1 Setting
(R1 Comp)
J2 Setting
CLOSED
CLOSED
CLOSED
2.2.3
External Signal
Common Mode
Differential Source Type
CLOSED
0V
Bipolar: If R1 = 280 kΩ, RS range is 0 Ω to 32 Ω
OPEN
2.25 V
Unipolar: Must change R1 to match RS
OPEN
Floating
AC-Coupled Bipolar: If R1 = 280 kΩ, no RS restriction
R1 Setting vs Source Impedance
The external source impedance ( RS) will add up to the 1 kΩ of the input resistor, thereby moving the
output common mode of the OPA625 amplifiers. To compensate for this, R1 can be modified according to
the particular external source impedance value used with the evaluation board to allow full-scale input
range without saturating the OPA625 amplifiers.
The board is shipped with R1 as 280 kΩ that allows an external source impedance ( RS) range between 0
Ω to 32 Ω for 0 V common mode configuration (J1:closed and J2:closed). For floating or AC-Coupled
signals, the input common mode is set by the OPA625 amplifiers themselves and R1 should remain at 280
kΩ for any given source impedance. The range of values of R1 for 0-V common mode is determined using
Equation 1.
2.6 u10 7
2.7 u10 7
9000 R1
9000
RS 96
RS 67
(1)
In the case of unipolar input signals, R1 must be replaced since 280 kΩ is not large enough to compensate
for any practical value of external source impedance (RS). The range of values of R1 for 2.25-V common
mode is determined using Equation 2.
1.9 u108
2.8 u108
177500 R1
270000
RS 1000
RS 1000
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Onboard ADC Reference
The EVM does not include a provision for driving the reference input of the ADS9110 from an external
source. The reference input signal path is entirely self-contained on the ADS9110EVM and consists of
REF5045, a 4.5-V precision voltage reference. The output of REF5025 is filtered and buffered by a
reference driver formed from two amplifiers: OPA625 and OPA378. This reference driver offers zerooffset, low-noise and is optimized for 1-LSB voltage regulation under maximum loading conditions at full
device throughput of 2 MSPS. The schematic for the reference driver circuit is shown in Figure 3.
Figure 3. Onboard Reference Signal Path
3
Digital Interfaces
As noted in Section 1, the EVM interfaces with the PHI that, in turn, communicates with the computer over
USB. There are three devices on the EVM with which the PHI communicates: the ADS9110 ADC (over
SPI or multiSPI), the EEPROM (over I2C), and the microSD memory card (via the SD/MMC/SDIO bus
protocol). The SD card and EEPROM come pre-programmed with the information required to configure
and initialize the ADS9110EVM-PDK platform. Once the hardware is initialized, the SD card and EEPROM
are no longer used.
3.1
multiSPI® for ADC Digital IO
The ADS9110EVM-PDK supports all the interface modes as detailed in the ADS9110 datasheet
(SBAS629). In addition to the standard SPI modes, (with single-, dual- and quad-SDO lanes), the multiSPI
modes support single- and dual-data output rates and the four possible clock source settings as well. The
PHI is capable of operating at a 1.8-V logic level and is directly connected to the digital I/O lines of the
ADC.
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Power Supplies
The PHI provides multiple power-supply options for the EVM, derived from the computer’s USB supply.
The EEPROM and microSD card on the ADS9110EVM use a 3.3-V power supply generated directly by
the PHI. The ADC and analog input drive circuits are powered by the TPS7A4700 onboard the EVM,
which is a low-noise linear regulator that uses the 5.5-V supply out of a switching regulator on the PHI to
generate a much cleaner 5-V output. The 1.8-V supply to the digital section of the ADC is provided directly
by an LDO on the PHI.
The power supply for each active component on the EVM is bypassed with a ceramic capacitor placed
close to that component. Additionally, the EVM layout uses thick traces or large copper fill areas where
possible between bypass capacitors and their loads to minimize inductance along the load current path.
5
ADS9110EVM-PDK Initial Setup
This section explains the initial hardware and software setup procedure that must be completed for the
proper operation of the ADS9110EVM-PDK.
5.1
Default Jumper Settings
Jumper settings are determined by common mode and source impedance of the external source that
provides a differential signal to the board. Remove shunts from J4 and J6 and set J2 and J1 according to
the external source as described in Section 2.
5.2
EVM Graphical User Interface (GUI) Software Installation
The EVM also comes with the microSD card pre-installed in slot J6. The microSD card contains the EVM
GUI installer that must be executed to install the EVM GUI software on the user’s computer.
CAUTION
Manually disable any antivirus software running on the computer before
connecting the SD card or downloading the EVM GUI installer onto the local
hard disk. Otherwise, depending on the antivirus settings, an error message
such as the one shown in Figure 4 may appear or the installer .exe file may be
deleted.
Download the latest version of the installer from the Tools and Software folder of the ADS9110 and run
the GUI installer. Accept the license agreements and follow the on-screen instructions to complete the
installation.
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Figure 4. ADS9110 Software Installation Prompts
As a part of the ADS9110 EVM GUI installation, a prompt with a Device Driver Installation will appear on
the screen. Click Next to proceed.
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Figure 5. Device Driver Installation Wizard Prompts
NOTE: A Notice may appear on the screen stating that Widows can’t verify the publisher of this
driver software; Select ‘Install this driver software anyway’.
The ADS9110EVM-PDK requires LabVIEW™ Run-Time Engine and may prompt for the installation of this
software, if it is not already installed.
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Figure 6. LabVIEW Run-Time Engine Installation
After these installations, verify that C:\Program Files (x86)\Texas Instruments\ADS9110 EVM is as shown
in Figure 7.
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Figure 7. ADS9110 EVM Folder Post-Installation
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ADS9110EVM-PDK Operation
The following instructions are a step-by-step guide to connecting the ADS9110EVM-PDK to the computer
and evaluating the performance of the ADS9110:
1. Connect the ADS9110EVM to the PHI. Install the two screws as indicated in Figure 8.
2. Use the USB cable provided to connect the PHI to the computer.
• LED D5 on the PHI lights up, indicating that the PHI is powered up.
• LEDs D1 and D2 on the PHI starts blinking to indicate that the PHI is booted up and
communicating with the PC. The resulting LED indicators are shown inFigure 8.
Figure 8. EVM-PDK Hardware Setup and LED Indicators
3. Launch the ADS9110EVM GUI software, as shown in Figure 9.
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Figure 9. Launch the EVM GUI Software
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EVM GUI Global Settings for ADC Control
Although the EVM GUI does not allow direct access to the levels and timing configuration of the ADC
digital interface, the EVM GUI does give users high-level control over virtually all functions of the
ADS9110 including interface modes, sampling rate, and number of samples to be captured.
Figure 10 identifies the input parameters of the GUI (as well as their default values) through which the
various functions of the ADS9110 can be exercised. These are global settings as they persist across the
GUI tools listed in the top left pane (or from one page to another).
Figure 10. EVM GUI Global Input Parameters
The host configuration options in this pane allow the user to choose from various SPI and multiSPI host
interface options available on the ADS9110. The host always communicates with the ADS9110 using the
standard SPI protocol over the single SDI lane, irrespective of the mode selected for Data Capture.
The drop-down boxes under the Device Modes sub-menu allows the user to select the data capture mode.
The Bus Width drop-down allows selection between Single-, Dual- and Quad-SDO lanes; Data Read
between Source and System Synchronous modes and Output Data Rate between SDR and DDR modes.
Detailed descriptions of each of these modes is available in the ADS9110 datasheet (SBAS629).
The user may select SCLK Frequency and Sampling Rate on this pane and this is dependent of the
Device Mode selected. The GUI allows the user to enter the targeted values for these two parameters and
the GUI computes the best values that can be achieved, considering the timing constraints of the selected
Device Mode.
The user may specify a target SCLK frequency (in Hz) and the GUI will try to match this as closely as
possible by changing the PHI PLL settings and the achievable frequency that may differ from the target
value displayed. Similarly, the sampling rate of the ADC can be adjusted by modifying the Target
Sampling Rate argument (also in Hz). The achievable ADC sampling rate may differ from the target value,
depending on the applied SCLK frequency and selected Device Mode and the closest match achievable is
displayed. This pane therefore allows the user to try various settings available on the ADS9110 in an
iterative fashion until the user converges to the best settings for the corresponding test scenario.
The final option in this pane is the selection for the Update Mode. The default value is “Immediate” which
indicates that the interface settings selection made by the user is applied to configure both the host and
the ADS9110 instantly. “Manual” indicates that the selection made will be made only when the user
finalizes his choices and is ready to configure the device. This is described in more detail in the following
section.
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6.2
Register Map Configuration Tool
The register map configuration tool allows the user to view and modify the registers of the ADS9110. This
can be selected by clicking on the Register Map Config radio button at the Pages section of the left pane
as indicated in Figure 11. On power up, the values on this page correspond to the reset values of the
device registers. The register values can be edited by double-clicking the corresponding value field. If
interface mode settings are affected by the change in register values, this change will reflect on the left
pane immediately. The impact of changes in the register value reflect on the ADS9110 device on
ADS9110EVM-PDK based on the Update Mode selection as described in Section 6.1.
Figure 11. Register Map Configuration
Section 6.3 through Section 6.6 describe the data collection and analysis features of the ADS9110EVMPDK GUI.
6.3
Time Domain Display Tool
The time domain display tool allows visualization of the ADC response to a given input signal. This tool is
useful for both studying the behavior and debugging any gross problems with the ADC or drive circuits.
The user can trigger a capture of the data of the selected number of samples from the ADS9110, as per
the current interface mode settings using the capture button as indicated on Figure 12. The sample
indices are on the x-axis and there are two y-axes showing the corresponding output codes as well as the
equivalent analog voltages based on the specified reference voltage. Switching pages to any of the
Analysis tools described in the subsequent sections, triggers calculations to be performed on the same set
of data.
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Figure 12. Time Domain Display Tool Options
6.4
Spectral Analysis Tool
The spectral analysis tool is intended to evaluate the dynamic performance (SNR, THD, SFDR, SINAD,
and ENOB) of the ADS9110 SAR ADC through single-tone sinusoidal signal FFT analysis using the 7term Blackman-Harris window setting. Also, the window setting of "None" can be used to look for noise
spurs over frequency in DC inputs.
For dynamic performance evaluation, the external differential source must have better specifications than
the ADC itself to ensure that the measured system performance is not limited by the performance of the
signal source. Therefore, it is critical that the external reference source meets the source requirements
mentioned in Table 4.
Table 4. External Source Requirements for ADS9110 Evaluation
18
Specification Description
Specification Value
Signal Frequency
2 kHz
External Source Type
Balanced Differential
External Source Common Mode
0 V or Floating
(Refer to Section 2.2.2 for jumper settings)
External Source Impedance (RS)
10 Ω–30 Ω
External Source Differential Impedance
(RS_DIFF = 2 × RS)
20 Ω–60 Ω
Source Differential Signal
(VPP Amplitude for –0.1 dBFS)
(2 × RS × 4.45 × 10–3) + 8.9 V
or
(RS_DIFF × 4.45 × 10–3) + 8.9 V
Maximum Noise
10 µVRMS
Maximum SNR
110 dB
Maximum THD
–130 dB
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For 2 kHz SNR and ENOB evaluation at maximum throughput of 2 MSPS, the number of samples should
be 32768 or 65536. More samples than these will bring noise floor so low that the external source phase
noise might dominate SNR and ENOB calculations. On the contrary, for THD and SFDR evaluation, much
large number of samples should be used to reduce the noise floor below –140 dBc to analyze noise-free
harmonics and spurs in the order of –120 dBc Such analysis will require at least 262144 samples.
NOTE: SNR for ADS9110 with 4.5-V reference is 1 dB lower than with 5-V reference and the ADC
typical SNR is expected to be 99 dB.
Figure 13. Spectral Analysis Tool
Finally, the FFT tool includes windowing options that are required to mitigate the effects of non-coherent
sampling (this discussion is beyond the scope of this document). The 7-Term Blackman Harris window is
the default option and has sufficient dynamic range to resolve the frequency components of up to a 24-bit
ADC. Note that the “None” option corresponds to not using a window (or using a rectangular window) and
is not recommended.
6.5
Histogram Tool
Noise degrades ADC resolution and the histogram tool can be used to estimate effective resolution, which
is an indicator of the number of bits of ADC resolution losses resulting from noise generated by the
various sources connected to the ADC when measuring a dc signal. The cumulative effect of noise
coupling to the ADC output from sources such as the input drive circuits, the reference drive circuit, the
ADC power supply, and the ADC itself is reflected in the standard deviation of the ADC output code
histogram that is obtained by performing multiple conversions of a dc input applied to a given channel.
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The histogram corresponding to a dc input is displayed on clicking on the Capture button as shown in
Figure 14:
Figure 14. Histogram Analysis Tool
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6.6
Linearity Analysis Tool
The linearity analysis tool measures and generates the DNL and INL plots over code for the specific
ADS9110 installed in the evaluation board. It requires a 2-kHz sinusoidal input signal, which is slightly
saturated (35 mV outside full scale range at each input or +0.13 dBFS) with very low distortion. It is critical
for the external source linearity to be better than the ADC linearity. This is important to ensure that the
measured system performance reflects the linearity errors of the ADC and is not limited by the
performance of the signal source. To make sure that the DNL and INL of the ADC are correctly measured,
the external source must meet the requirements in Table 5.
Table 5. External Source Requirements for ADS9110 Evaluation
Specification Description
Specification Value
Signal Frequency
2 kHz
External Source Type
Balanced Differential
External Source Common Mode
0 V or Floating
(Refer to Section 2.2.2 for jumper settings)
External Source Impedance (RS)
10 Ω–30 Ω
External Source Differential Impedance
(RS_DIFF = 2 × RS)
20 Ω–60 Ω
Source Differential Signal
(VPP Amplitude for –0.1 dBFS)
(2 × RS × 4.57 × 10–3) + 9.14 V
or
(RS_DIFF × 4.57 × 10–3) + 9.14 V
Maximum Noise
30 µVRMS
Maximum SNR
100 dB
Maximum THD
–130 dB
The number-of-hits setting depends on the external noise source. For a 110-dB SNR external source with
about 10 µVrms of noise, total number of hits should be 512. For a source with 100-dB SNR, the
recommended number of hits is 1024.
NOTE: This analysis can take a couple of minutes to run and it is extremely important that the
evaluation board remains undisturbed during the complete duration of the analysis.
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21
ADS9110EVM-PDK Operation
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Figure 15. Linearity Analysis Tool
22
ADS9110EVM-PDK
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Bill of Materials, PCB Layout, and Schematics
www.ti.com
7
Bill of Materials, PCB Layout, and Schematics
This section contains the ADS9110EVM bill of materials, PCB layout, and the EVM schematics.
7.1
Bill of Materials
Table 6 lists the ADS9110EVM BOM.
Table 6. ADS9110EVM Bill of Materials
Manufacturer Part Number
Manufacturer
Description
PA006
Qty
1
!PCB
Reference Designators
Any
Printed Circuit Board for Evaluation of ADS9110
PHI-EVM-CONTROLLER
(Edge# 6591636 rev. B)
1
!PCB2
Texas Instruments
USB Controller Board for ADC EVMs (Kit Item)
C3216X5R1E476M160AC
2
C1, C3
TDK
CAP, CERM, 47 µF, 25 V, +/- 20%, X5R, 1206
GRM188R71E105KA12D
10
C2, C5, C6, C8, C12, C32,
C38, C40, C43, C46
Murata
CAP, CERM, 1 µF, 25 V, +/- 10%, X7R, 0603
GRM21BR71A106KE51L
6
C4, C21, C26, C41, C44, C48
Murata
CAP, CERM, 10 µF, 10 V, +/- 10%, X7R, 0805
C0603C104J3RACTU
4
C7, C9, C10, C17
Kemet
CAP, CERM, 0.1 µF, 25 V, +/- 5%, X7R, 0603
GRM155R71C104KA88D
9
C11, C13, C14, C22, C25,
C30, C47, C49, C50
Murata
CAP, CERM, 0.1 µF, 16 V, +/- 10%, X7R, 0402
ZRB18AD71A106KE01L
6
C15, C27, C28, C29, C39,
C45
Murata
CAP, CERM, 10 µF, 10 V, +/- 10%, X7T, 0603
GRM1885C1H102FA01J
3
C16, C31, C42
Murata
CAP, CERM, 1000 pF, 50 V, +/- 1%, C0G/NP0, 0603
C0603C100F5GAC7867
1
C18
Kemet
CAP, CERM, 10 pF, 50 V, +/- 1%, C0G/NP0, 0603
C0603C224J3RAC7867
1
C19
Kemet
CAP, CERM, 0.22 µF, 25 V, +/- 5%, X7R, 0603
GRM155R71H103KA88D
1
C33
Murata
CAP, CERM, 0.01 µF, 50 V, +/- 10%, X7R, 0402
C0805C103F1GACTU
3
C34, C35, C37
Kemet
CAP, CERM, 0.01 µF, 100 V, +/- 1%, C0G/NP0, 0805
APT2012LZGCK
1
D1
Kingbright
LED, Green, SMD
CUS05S40,H3F
1
D2
Toshiba
Diode, Schottky, 40 V, 0.5 A, SOD-323
PMSSS 440 0025 PH
4
H1, H2, H3, H4
B&F Fastener Supply
MACHINE SCREW PAN PHILLIPS 4-40
1891
4
H5, H6, H7, H8
Keystone
3/16 Hex Female Standoff
9774050360R
2
H9, H10
Wurth Elektronik
ROUND STANDOFF M3 STEEL 5MM
AP4GMCSH4-B
1
H11
Apacer Technology
microSD Card, 4GB, Class 4
102-1092-BL-00100
1
H12
CNC Tech
CABLE USB A MALE-B MICRO MALE 1M (Kit Item)
RM3X4MM 2701
2
H14, H15
APM HEXSEAL
Machine Screw Pan PHILLIPS M3
87898-0204
2
J1, J2
Molex
Header, 2.54 mm, 2x1, Gold, R/A, SMT
142-0701-801
2
J3, J7
Johnson
Connector, End launch SMA, 50 ohm, SMT
TSM-103-01-L-SV
2
J4, J6
Samtec
Header, 100mil, 3x1, Gold, SMT
QTH-030-01-L-D-A
1
J5
Samtec
Header(Shrouded), 19.7mil, 30x2, Gold, SMT
502570-0893
1
J9
Molex
Connector, Micro SD, 1.1mm, R/A, SMT
THT-14-423-10
1
LBL1
Brady
Thermal Transfer Printable Labels, 0.650" W x 0.200" H - 10,000 per roll
NX3020NAKW,115
1
Q1
NXP Semiconductor
MOSFET, N-CH, 30 V, 0.18 A, SOT-323
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Bill of Materials, PCB Layout, and Schematics
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Table 6. ADS9110EVM Bill of Materials (continued)
Manufacturer Part Number
Manufacturer
Description
RG2012P-2803-B-T5
1
R1
Susumu Co Ltd
RES, 280 k, 0.1%, 0.125 W, 0805
ERJ-3RSFR10V
1
R2
Panasonic
RES, 0.1, 1%, 0.1 W, 0603
RG1608P-103-B-T5
3
R5, R25, R36
Susumu Co Ltd
RES, 10.0 k, 0.1%, 0.1 W, 0603
ERJ-2RKF1002X
11
R6, R18, R23, R56, R61, R62,
R63, R64, R65, R66, R67
Panasonic
RES, 10.0 k, 1%, 0.1 W, 0402
ERJ-3RQFR22V
1
R8
Panasonic
RES, 0.22, 1%, 0.1 W, 0603
RG1608P-203-B-T5
3
R10, R15, R20
Susumu Co Ltd
RES, 20.0 k, 0.1%, 0.1 W, 0603
ERJ-2GE0R00X
14
R11, R12, R32, R34, R35,
R37, R40, R42, R43, R46,
R47, R49, R51, R53
Panasonic
RES, 0, 5%, 0.063 W, 0402
RG1608P-102-B-T5
6
R16, R29, R41, R45, R54,
R55
Susumu Co Ltd
RES, 1.00 k, 0.1%, 0.1 W, 0603
RG1608P-4991-B-T5
1
R17
Susumu Co Ltd
RES, 4.99 k, 0.1%, 0.1 W, 0603
ERJ-3GEY0R00V
5
R19, R24, R57, R59, R60
Panasonic
RES, 0, 5%, 0.1 W, 0603
RG1608P-4990-B-T5
2
R21, R30
Susumu Co Ltd
RES, 499, 0.1%, 0.1 W, 0603
RG1608P-2491-B-T5
1
R22
Susumu Co Ltd
RES, 2.49 k, 0.1%, 0.1 W, 0603
RG1608P-3242-B-T5
1
R26
Susumu Co Ltd
RES, 32.4 k, 0.1%, 0.1 W, 0603
RG1608P-303-B-T5
1
R27
Susumu Co Ltd
RES, 30.0 k, 0.1%, 0.1 W, 0603
CRCW06034R75FKEA
1
R31
Vishay-Dale
RES, 4.75, 1%, 0.1 W, 0603
RG1608P-101-B-T5
2
R38, R44
Susumu Co Ltd
RES, 100, 0.1%, 0.1 W, 0603
RG1608P-2552-B-T5
1
R39
Susumu Co Ltd
RES, 25.5 k, 0.1%, 0.1 W, 0603
CRCW06032R21FKEA
2
R48, R50
Vishay-Dale
RES, 2.21, 1%, 0.1 W, 0603
CRCW0402100KFKED
1
R58
Vishay-Dale
RES, 100 k, 1%, 0.063 W, 0402
EVQPNF04M
1
S1
Panasonic
Switch, Tactile, SPST-NO, 0.05A, 12V, SMD
CAS-120TA
1
S2
Copal Electronics
Switch, Slide, SPDT 100mA, SMT
881545-2
3
SH-J1, SH-J2, SH-J3
TE Connectivity
Shunt, 100mil, Gold plated, Black
5016
7
TP1, TP2, TP3, TP4, TP5,
TP7, TP8
Keystone
Test Point, Compact, SMT
5015
1
TP6
Keystone
Test Point, Miniature, SMT
REF5045AIDGKT
1
U1
Texas Instruments
Low Noise, Very Low Drift, Precision Voltage Reference, -40 to 125 degC, 8-pin MSOP (DGK), Green (RoHS & no
Sb/Br)
TPS7A4700RGW
1
U2
Texas Instruments
36-V, 1-A, 4.17-µVRMS, RF LDO Voltage Regulator, RGW0020A
OPA376AIDBVR
1
U3
Texas Instruments
Low-Noise, Low Quiescent Current, Precision Operational Amplifier e-trim Series, DBV0005A
SN74LVC1G08DCKR
2
U4, U8
Texas Instruments
Single 2-Input Positive-AND Gate, DCK0005A
OPA378AIDBVT
1
U5
Texas Instruments
Low-Noise, 900 kHz, RRIO, Precision Operational Amplifier, Zerø-Drift Series, 2.2 to 5.5 V, -40 to 125 degC, 5-pin
SOT23 (DBV0005A), Green (RoHS & no Sb/Br)
OPA625IDBVR
3
U6, U12, U13
Texas Instruments
High-Bandwidth, High-Precision, Low THD+N, 16-Bit and 18-Bit Analog-to-Digital Converter (ADC) Drivers,
DBV0006A
SN74LVC1G17DCKR
1
U7
Texas Instruments
SINGLE SCHMITT-TRIGGER BUFFER, DCK0005A
24
Qty
Reference Designators
ADS9110EVM-PDK
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Table 6. ADS9110EVM Bill of Materials (continued)
Manufacturer Part Number
Manufacturer
Description
TLV3012AIDCKR
Qty
2
U9, U10
Reference Designators
Texas Instruments
Nanopower, 1.8V, Comparator with Voltage Reference, DCK0006A
ADS9110IRGER
1
U11
Texas Instruments
18-Bit, 2-MSPS, 20-mW, SAR ADC with Enhanced Serial Interface, RGE0024H
BR24G32FVT-3AGE2
1
U14
Rohm
I2C BUS EEPROM (2-Wire), TSSOP-B8
C2012X7S1A226M125AC
0
C20
TDK
CAP, CERM, 22 µF, 10 V, +/- 20%, X7S, 0805
GRM21BR71A106KE51L
0
C23
Murata
CAP, CERM, 10 µF, 10 V, +/- 10%, X7R, 0805
ZRB18AD71A106KE01L
0
C24
Murata
CAP, CERM, 10 µF, 10 V, +/- 10%, X7T, 0603
GRM188R71E105KA12D
0
C36
Murata
CAP, CERM, 1 µF, 25 V, +/- 10%, X7R, 0603
N/A
0
FID1, FID2, FID3, FID4, FID5,
FID6
N/A
71430-0013
0
J8
Molex
ERJ-2GE0R00X
0
R3, R4, R7, R9, R13, R14,
R52
Panasonic
ERJ-2RKF1002X
0
R28
Panasonic
RES, 10.0 k, 1%, 0.1 W, 0402
RC0603FR-071RL
0
R33
Yageo America
RES, 1.00, 1%, 0.1 W, 0603
Fiducial mark. There is nothing to buy or mount.
Receptacle, SCSI, VHDCI, 68 pin, R/A, TH
RES, 0, 5%, 0.063 W, 0402
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Bill of Materials, PCB Layout, and Schematics
7.2
www.ti.com
PCB Layout
Figure 16 through Figure 19 illustrate the EVM PCB layout.
Figure 16. ADS9110EVM PCB Layer 1: Top Layer
26
ADS9110EVM-PDK
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Bill of Materials, PCB Layout, and Schematics
Figure 17. ADS9110EVM PCB Layer 2: GND Plane
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Bill of Materials, PCB Layout, and Schematics
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Figure 18. ADS9110EVM PCB Layer 3: Power Planes
28
ADS9110EVM-PDK
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Bill of Materials, PCB Layout, and Schematics
Figure 19. ADS9110EVM PCB Layer 4: Bottom Layer
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Bill of Materials, PCB Layout, and Schematics
7.3
www.ti.com
Schematic
Figure 20 through Figure 22 illustrate the EVM schematics.
1
2
3
4
5
6
J8
5V
5V
AGND
D2
C15
EVM_DVDD
10µF
3
4
HOST_A1_IO7
0.1µF
AGND
C19
1
V-
0.22µF
C17
RST
R31
AGND
C10
AGND
R29
R30
1.00k
499
AGND
HOST_A2_IO2
EVM_DVDD
EVM_DVDD
AGND
HOST_A2_IO3
C13
10pF
5
R27
HOST_A2_CLK1
HOST_A2_CLK2-4
C18
0.1µF
30.0k
R58
100k
0.1µF
AGND
Switch_RESET 4
AGND
6
3
V+
4
1
AGND
V-
0
1µF
EVM_DVDD
C40
AGND
R45
AGND
R41
1.00k
1.00k
C31
U11
13
14
1µF
2
1
AVDD
AVDD
DVDD
9
10
C34
2.21
REF_BUF
AINP
AINM
5
7
0.01µF
AGND
J6
AGND
3
2
1
1000pF
C35
0.01µF
REFP
REFP
3
C41
10µF
100
4
J7
142-0701-801
1
AGND
R59
AGND
U13
OPA625IDBVR
1
REFOUT
R28
DNP
10.0k
2.21
V-
AGND
R55
AGND
R54
1.00k
1.00k
C42
24
23
22
21
SDO-0
SDO-1
SDO-2
SDO-3
20
19
18
17
GND
GND
11
15
EP
5V
TP3
5016
TP2
5016
TP7
5016
0
R37
HOST_A1_CLK3
HOST_A1_IO7
HOST_A2_CLK1
0
R47
HOST_A1_IO7
0
R42
25
HOST_A2_CLK2-4
0
R43
HOST_A2_IO2
0
R46
HOST_A2_IO3
0
R49
HOST_A2_IO4
EVM_DVDD
0
R51
R57
0
EVM_ID_SDA
EVM_ID_SCL
EVM_PRSNT_N
HOST_A2_IO5
0
AGND
C44
10µF
AGND
DNPC36
1µF
MP1
MP2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
GND
GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
TP1
5016
AGND
AGND
1
AGND
TP5
5016
TP6
5015
R60
MP3
MP4
GND
GND
QTH-030-01-L-D-A
C
0
C48
10µF
AGND
J9
EVM_ID_PWR
R66
10.0k
0.1µF
AGND
WP
1
A0
VCC
8
2
A1
WP
7
3
A2
SCL
6
EVM_ID_SCL
4
VSS
SDA
5
EVM_ID_SDA
R67
10.0k
S2
1
2
3
C47
0.1µF
AGND
R65
10.0k
R64
10.0k
R61
10.0k
R63
10.0k
R62
10.0k
EVM_SD_DAT2
EVM_SD_DAT3
EVM_SD_CMD
EVM_SD_CLK
C50
0.1µF
EVM_SD_DAT0
EVM_SD_DAT1
DAT2
CD/DAT3
CMD
VDD
CLK
VSS
DAT0
DAT1
S1
S2
S3
S4
CD
SW
AGND
Orderable:
ADS9110EVM-PDK
TID #:
N/A
Number: PA006
Rev: A
Texas Instruments and/or its licensors do not warra
nt the accuracy or completeness of this specificati
on or any information contained therein. Texas ruments
Inst
and/or its licensors do not SVN Rev: Version control disabled
warrant that this design will meet the specificatio
ns, will be suitable for your application or rfitany
fo particular purpose, or will operate in anlementation.
imp
Texas Instruments and/or its Drawn By: Rafael Ordonez
Engineer: Rafael Ordonez
licensors do not warrant that the design is product
ion worthy. You should completely validate and test
your design implementation to confirm the system
unctionality
f
for your application.
5
9
12
13
14
D
502570-0893
AGND
CAS-120TA
4
1
2
3
4
5
6
7
8
10
11
AGND
3
EVM_SD_DAT2
EVM_SD_DAT3
EVM_SD_CMD
EVM_SD_CLK
EVM_SD_DAT0
EVM_SD_DAT1
EVM_ID_PWR
EVM_ID_PWR
C49
2
B
AGND
EVM_ID_PWR
AGND
A
71430-0013
AGND
BR24G32FVT-3AGE2
TP8
5016
AGND
AGND
COMPONENTS MARKED 'DNP' SHOULD NOT BE POPULATED.
AGND
EVM_DVDD EVM_ID_PWR
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
EVM_ID_PWR
1000pF
LDO_IN_5V5
HOST_A1_CLK2
R52
DNP
0
U14
D
HOST_A1_CLK1
0
R35
AGND
EVM_ID_PWR
AGND
NC
NC
NC
2 RST
CS
SCLK
SDI
RVS
AGND
5V
R50
2
3
4
5
0
V+
DNP
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
AGND
R34
0
R40
1
ADS9110IRGER
2
C43
1µF
DNPC23
10µF
10µF
5
AGND
OPA625_CM
3
6
12
AGND
C45
TSM-103-01-L-SV
4.5V
0.01µF
5V
AGND
R44
REFM
REFM
AGND
TEST_4.3V
REFOUT
4
8
C37
6
C
R38
100
CONVST
RST
16
AGND
R48
AGND
C26
10µF
AGND
EVM_DVDD
R53
2
C32
1µF
AGND
J4
TSM-103-01-L-SV
TEST_0.2V
3
AGND
EVM_SD_DAT3
2
3
4
5
OPA625_CM
AGND
C38
EVM_SD_DAT2
0
AGND
10µF
AGND
U12
OPA625IDBVR
EVM_REG_5V5
J5
AGND
C39
5
70
69
AGND
DNPC20
22µF
5V
AGND
S1
EVQPNF04M
C46
1µF
U7
SN74LVC1G17DCKR
C27 DNPC24
10µF
10µF
1
C29
10µF
B
R24
HOST_A2_IO5
10.0k
2
3
R33
DNP
1.00
C28
10µF
1
HOST_A2_IO4
R56
2
REF_BUF
J3
142-0701-801
HOST_A1_CLK3
HOST_A1_IO6
0
Switch_RESET
4.75
EVM_SD_DAT1
AGND
AGND
R32
4
2
HOST_A1_CLK2
3
0.1µF
U8
SN74LVC1G08DCKR
EVM_SD_CLK
5V
HOST_A1_CLK1
R23
10.0k
1
2
AGND
C9
0.1µF
HOST_A1_IO6
C14
EVM_SD_DAT0
R17
4.99k
V+
EVM_DVDD
EVM_SD_CMD
2.49k
CUS05S40,H3F
U6
OPA625IDBVR
5
4
5
C12
1µF
AGND
5
AGND
R22
1
1.00k
4.5V
U5
OPA378AIDBVT
3
6
R16
REFOUT
2
AGND
A
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Designed for:Public
Project Title:ADS9110EVM-PDK
Sheet Title: ADC and Drivers
Assembly Variant:001
File: PA006A_Schematic1.SchDoc
Contact: http://www.ti.com/support
AGND
Mod. Date: 9/2/2015
Sheet: 1 of 3
Size: B
http://www.ti.com
© Texas Instruments2015
6
Figure 20. Schematic Diagram (Page 1) of the ADS9110EVM PCB
30
ADS9110EVM-PDK
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1
2
3
4
LDO_IN_5V5
5
EVM_ID_PWR
C25
0.1µF
AGND
6
R6
10.0k
EVM_ID_PWR
1
1.25V_1
4
1
C11
D1
APT2012LZGCK
V+
V-
U9
TLV3012AIDCKR
1.3V
3
32.4k
3
5
2
0.1µF
AGND
C22
0.1µF
U4
SN74LVC1G08DCKR
A
LDO_IN_5V5
R26
1.25V_1
5
2
A
Green
6
5.5V
R25
10.0k
AGND
1
LDO_EN
1
EVM_ID_PWR
C30
4
R18
10.0k
3
AGND
0.1µF
AGND
AGND
4
AGND
AGND
6
2
2
Q1
NX3020NAKW,115
1
AGND
V+
V-
1.3V
3
5
2
U10
TLV3012AIDCKR
1.25V_2
EVM_DVDD
10.0k
C33
0.01µF
B
R36
1.25V_2
1.8V
R39
25.5k
B
AGND
AGND
5V
LDO_IN_5V5
EVM_REG_5V5
U2
1
20
OUT
OUT
3
R2
0.1
IN
IN
SENSE
EN
R19
15
16
13
0
LDO_EN
1µF
0603
14
NR
19
18
17
2
NC
NC
NC
NC
7
21
GND
PAD
AGND
6P4V2
6P4V1
3P2V
1P6V
0P8V
0P4V
0P2V
0P1V
R4
DNP
0
R9
DNP
0
R12
4
5
6
8
9
10
11
12
TPS7A4700RGW
AGND
20.0k
C8
J1
87898-0204
5V
R1
0.1µF
5
499
U3
OPA376AIDBVR
V+
V-
R15
3
20.0k
R5
10.0k
C6
1µF
AGND
AGND
TP4
5016
4
1
C
280k
AGND
2
R21
AGND
1
2
C7
AGND
C21
10µF
COMPONENTS MARKED 'DNP' SHOULD NOT BE POPULATED.
0
R7
DNP
0
R3
DNP
0
1µF
C16
1000pF
AGND
0
R13
DNP
0
R14
DNP
0
R11
R20
OPA625_CM
C1
47µF
C5
C3
AGND
47µF
C
AGND
J2
87898-0204
6
5
R8
0.22
4
VOUT
TRIM/NR
GND
VIN
TEMP
2
3
C2
1µF
REF5045AIDGKT
R10
20.0k
2
1
5V
U1A
REFOUT
AGND
AGND
C4
10µF
D
D
AGND
AGND
AGND
AGND
Orderable: ADS9110EVM-PDK
TID #:
N/A
Number: PA006
Rev: A
Texas Instruments and/or its licensors do not warra
nt the accuracy or completeness of this specificati
on or any information contained therein. Texas ruments
Inst
and/or its licensors do not SVN Rev: Version control disabled
warrant that this design will meet the specificatio
ns, will be suitable for your application or rfitany
fo particular purpose, or will operate in anlementation.
imp
Texas Instruments and/or its Drawn By: Rafael Ordonez
Engineer: Rafael Ordonez
licensors do not warrant that the design is product
ion worthy. You should completely validate and test
your design implementation to confirm the system
unctionality
f
for your application.
1
2
3
4
5
Designed for:Public
Project Title:ADS9110EVM-PDK
Sheet Title: LDO and Reference
Assembly Variant:001
File: PA006A_Schematic2.SchDoc
Contact: http://www.ti.com/support
Mod. Date: 9/18/2015
Sheet: 2 of 3
Size: B
http://www.ti.com
© Texas Instruments2015
6
Figure 21. Schematic Diagram (Page 2) of the ADS9110EVM PCB
SBAU249 – October 2015
Submit Documentation Feedback
ADS9110EVM-PDK
Copyright © 2015, Texas Instruments Incorporated
31
Bill of Materials, PCB Layout, and Schematics
1
www.ti.com
2
3
H1
H2
H3
H4
PMSSS 440 0025 PH
PMSSS 440 0025 PH
PMSSS 440 0025 PH
PMSSS 440 0025 PH
4
5
6
H12
MECH
102-1092-BL-00100
CABLE USB A MALE-B MICRO MALE 1M (Kit Item)
A
A
H5
H6
H7
H8
1891
1891
1891
1891
DNP
DNP
DNP
FID1
FID2
FID3
DNP
DNP
DNP
FID4
FID5
FID6
PCB Number: PA006
PCB Rev: A
H14
H15
RM3X4MM 2701
RM3X4MM 2701
H11
H9
H10
9774050360R
9774050360R
AP4GMCSH4-B
microSD Card, 4GB, Class 4
Logo1
Logo2
Logo3
PCB
LOGO
PCB
LOGO
PCB
LOGO
Pb-Free Symbol
Texas Instruments
FCC disclaimer
SH-J1
Printed Circuit Board for Evaluation of ADS9110
SH-J2
B
B
PCB: PHI-EVM-CONTROLLER (Edge# 6591636 rev. B)
USB Controller Board for ADC EVMs (Kit Item)
SH-J3
Label Table
Variant
001
LBL1
Label Text
ADS9110EVM-PDK
PCB Label
Size: 0.65" x 0.20 "
ZZ1
Label Assembly Note
This Assembly Note is for PCB labels only
C
ZZ2
Assembly Note
These assemblies are ESD sensitive, ESD precautions
shall be observed.
C
ZZ3
Assembly Note
These assemblies must be clean and free from flux
nd all
a contaminants. Use of no clean flux is not
ceptable.
ac
ZZ4
Assembly Note
These assemblies must comply with workmanship stand
ards IPC-A-610 Class 2, unless otherwise specified.
ZZ5
Assembly Note
Insert microSD card H11 into socket J9
ZZ6
Assembly Note
Place H14 and H15 screws in H9 and H10 standoffs
ZZ7
Assembly Note
Place H1, H2, H3, H4 screws in H5, H6, H8, H9offs
stand
D
ZZ8
Assembly Note
Mount Shuts at: J2, J4:1-2, and J6:2-3
D
Orderable: ADS9110EVM-PDK
TID #:
N/A
Number: PA006
Rev: A
Texas Instruments and/or its licensors do not warra
nt the accuracy or completeness of this specificati
on or any information contained therein. Texas ruments
Inst
and/or its licensors do not SVN Rev: Version control disabled
warrant that this design will meet the specificatio
ns, will be suitable for your application or rfitany
fo particular purpose, or will operate in anlementation.
imp
Texas Instruments and/or its Drawn By: Rafael Ordonez
Engineer: Rafael Ordonez
licensors do not warrant that the design is product
ion worthy. You should completely validate and test
your design implementation to confirm the system
unctionality
f
for your application.
1
2
3
4
5
Designed for:Public
Project Title:ADS9110EVM-PDK
Sheet Title:
Assembly Variant:001
File: PA006A_Hardware.SchDoc
Contact: http://www.ti.com/support
Mod. Date: 9/3/2015
Sheet: 3 of 3
Size: B
http://www.ti.com
© Texas Instruments2015
6
Figure 22. Schematic Diagram (Page 3) of the ADS9110EVM PCB
32
ADS9110EVM-PDK
SBAU249 – October 2015
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
STANDARD TERMS AND CONDITIONS FOR EVALUATION MODULES
1.
Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, or
documentation (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms and conditions set forth herein.
Acceptance of the EVM is expressly subject to the following terms and conditions.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms and conditions that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2
Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms and conditions do not apply to Software. The warranty, if any, for Software is covered in the applicable Software
License Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for any defects that are caused by neglect, misuse or mistreatment
by an entity other than TI, including improper installation or testing, or for any EVMs that have been altered or modified in any
way by an entity other than TI. Moreover, TI shall not be liable for any defects that result from User's design, specifications or
instructions for such EVMs. Testing and other quality control techniques are used to the extent TI deems necessary or as
mandated by government requirements. TI does not test all parameters of each EVM.
2.3 If any EVM fails to conform to the warranty set forth above, TI's sole liability shall be at its option to repair or replace such EVM,
or credit User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the
warranty period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to
repair or replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall
be warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
3
Regulatory Notices:
3.1 United States
3.1.1
Notice applicable to EVMs not FCC-Approved:
This kit is designed to allow product developers to evaluate electronic components, circuitry, or software associated with the kit
to determine whether to incorporate such items in a finished product and software developers to write software applications for
use with the end product. This kit is not a finished product and when assembled may not be resold or otherwise marketed unless
all required FCC equipment authorizations are first obtained. Operation is subject to the condition that this product not cause
harmful interference to licensed radio stations and that this product accept harmful interference. Unless the assembled kit is
designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must operate under the authority of
an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
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FCC Interference Statement for Class B EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance
with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•
•
•
•
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1
For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210
Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSS standard(s). Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of the device.
Concernant les EVMs avec appareils radio:
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation
est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et
d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage
radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope
rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le
présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le
manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne
non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de
l'émetteur
3.3 Japan
3.3.1
Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。
http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page
3.3.2
Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan are NOT certified by
TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, User is required by Radio Law of Japan to follow the instructions below with respect to EVMs:
1.
2.
3.
Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for
Enforcement of Radio Law of Japan,
Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to
EVMs, or
Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan
with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note
that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
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【無線電波を送信する製品の開発キットをお使いになる際の注意事項】
本開発キットは技術基準適合証明を受けておりません。
本製品のご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。
日本テキサス・インスツルメンツ株式会社
東京都新宿区西新宿６丁目２４番１号
西新宿三井ビル
3.3.3
Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧くださ
い。http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
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4
EVM Use Restrictions and Warnings:
4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT
LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.
4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling
or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information
related to, for example, temperatures and voltages.
4.3 Safety-Related Warnings and Restrictions:
4.3.1
User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user
guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and
customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input
and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or
property damage. If there are questions concerning performance ratings and specifications, User should contact a TI
field representative prior to connecting interface electronics including input power and intended loads. Any loads applied
outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible
permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any
load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit
components may have elevated case temperatures. These components include but are not limited to linear regulators,
switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the
information in the associated documentation. When working with the EVM, please be aware that the EVM may become
very warm.
4.3.2
EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the
dangers and application risks associated with handling electrical mechanical components, systems, and subsystems.
User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,
affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic
and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely
limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and
liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or
designees.
4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,
state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all
responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and
liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local
requirements.
5.
Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate
as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as
accurate, complete, reliable, current, or error-free.
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6.
Disclaimers:
6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY WRITTEN DESIGN MATERIALS PROVIDED WITH THE EVM (AND THE
DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL FAULTS." TI DISCLAIMS ALL OTHER
WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT NOT LIMITED TO ANY IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY
THIRD PARTY PATENTS, COPYRIGHTS, TRADE SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS AND
CONDITIONS SHALL BE CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY
OTHER INDUSTRIAL OR INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD
PARTY, TO USE THE EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY
INVENTION, DISCOVERY OR IMPROVEMENT MADE, CONCEIVED OR ACQUIRED PRIOR TO OR AFTER DELIVERY OF
THE EVM.
7.
USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS
LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,
EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY
HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS AND CONDITIONS. THIS OBLIGATION
SHALL APPLY WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY
OTHER LEGAL THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.
8.
Limitations on Damages and Liability:
8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,
INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE
TERMS ANDCONDITIONS OR THE USE OF THE EVMS PROVIDED HEREUNDER, REGARDLESS OF WHETHER TI HAS
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED
TO, COST OF REMOVAL OR REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS
OR SERVICES, RETESTING, OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS,
LOSS OF SAVINGS, LOSS OF USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL
BE BROUGHT AGAINST TI MORE THAN ONE YEAR AFTER THE RELATED CAUSE OF ACTION HAS OCCURRED.
8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY WARRANTY OR OTHER OBLIGATION
ARISING OUT OF OR IN CONNECTION WITH THESE TERMS AND CONDITIONS, OR ANY USE OF ANY TI EVM
PROVIDED HEREUNDER, EXCEED THE TOTAL AMOUNT PAID TO TI FOR THE PARTICULAR UNITS SOLD UNDER
THESE TERMS AND CONDITIONS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE CLAIMED. THE EXISTENCE
OF MORE THAN ONE CLAIM AGAINST THE PARTICULAR UNITS SOLD TO USER UNDER THESE TERMS AND
CONDITIONS SHALL NOT ENLARGE OR EXTEND THIS LIMIT.
9.
Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)
will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in
a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable
order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),
excluding any postage or packaging costs.
10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,
without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to
these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.
Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief
in any United States or foreign court.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2015, Texas Instruments Incorporated
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IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
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DLP® Products
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