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ADS9110
SBAS629B – OCTOBER 2015 – REVISED JUNE 2017
ADS9110 18-Bit, 2-MSPS, 15-mW, SAR ADC With Enhanced Performance Features
1 Features
3 Description
•
•
•
The ADS9110 is an 18-bit, 2-MSPS, successive
approximation
register
(SAR)
analog-to-digital
converter (ADC) with enhanced performance
features. The high throughput enables developers to
oversample the input signal to improve dynamic
range and accuracy of the measurement. The
ADS9120 is a pin-compatible, 16-bit, 2.5-MSPS
variant of the ADS9110.
1
•
•
•
•
•
•
Sample Rate: 2 MSPS
No Latency Output
Excellent DC and AC Performance:
– INL: ±0.5 LSB
– DNL: ±0.75 LSB
– SNR: 100 dB, THD: –118 dB
Wide Input Range:
– Unipolar Differential Input Range: ±VREF
– VREF Input Range: 2.5 V to 5 V,
Independent of AVDD
Low-Power Dissipation:
– 9 mW at 2 MSPS (AVDD Only)
– 15 mW at 2 MSPS (Total)
– Flexible Low-Power Modes Enable Power
Scaling with Throughput
Enhanced-SPI (multiSPI™) Digital Interface
JESD8-7A-Compliant Digital I/O at 1.8-V DVDD
Fully-Specified Over Extended Temperature
Range: –40°C to +125°C
Small Footprint: 4-mm × 4-mm VQFN
The ADS9110 boosts analog performance while
maintaining high-resolution data transfer by using TI’s
enhanced SPI feature. Enhanced SPI enables the
ADS9110 to achieve high throughput at lower clock
speeds, thereby simplifying board layout and lowering
system cost.
Enhanced SPI also simplifies the host clocking-in of
data, thereby making the device ideal for applications
involving FPGAs and DSPs. The ADS9110 is
compatible with a standard SPI Interface. The
ADS9110 has an internal data parity feature that can
be appended to the ADC data output. ADC data
validation by the host, using parity bits, improves
system reliability.
The device supports JESD8-7A compliant I/Os, the
extended industrial temperature range, and is offered
in a space-saving, 4-mm × 4-mm, VQFN package.
2 Applications
•
•
•
•
SPI Interface Clock at Full Throughput(1)
Test and Measurement
Motor Control
Medical Imaging
High-Precision, High-Speed Industrial
PART NUMBER
3-WIRE SPI
ADS9110
140 MHz
3-WIRE
ENHANCED-SPI
40 MHz
(1) For all features of the enhanced SPI, see the Interface
Module section.
Ease of System Design with ADS9110
Lowest Clock Speeds at 2-MSPS using 3-Wire EnhancedSPI
ADS9110 Block Diagram
ADS9110
AVDD
REFP
REFM
DVDD
Enhanced-SPI
AINP
MCU
CONVST
Data
AINP
Enhanced-SPI
18-Bit SAR ADC,
2-MSPS
Data Parity
AINM
AGND
RST
DGND
CONVST
CS
SCLK
SDI
SDO ± 0
SDO ± 1
SDO ± 2
SDO ± 3
RVS
CS
AINM
Parity
AINM
Multiple
Interface
Options
SCLK
Quiet time
ADC Conversion
CS
SDI
SDO
Data
Read
SPI
140-MHz
40-MHz
SCK
ISO
ADC Conversion
Enhanced SPI (Data + Parity)
40-MHz
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS9110
SBAS629B – OCTOBER 2015 – REVISED JUNE 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics........................................... 5
Timing Requirements: Conversion Cycle.................. 7
Timing Requirements: Asynchronous Reset, NAP,
and PD ....................................................................... 7
6.8 Timing Requirements: SPI-Compatible Serial
Interface ..................................................................... 7
6.9 Timing Requirements: Source-Synchronous Serial
Interface (External Clock) .......................................... 8
6.10 Timing Requirements: Source-Synchronous Serial
Interface (Internal Clock)............................................ 8
6.11 Typical Characteristics .......................................... 12
7
Detailed Description ............................................ 17
7.1 Overview ................................................................. 17
7.2
7.3
7.4
7.5
7.6
8
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
17
18
22
24
44
Application and Implementation ........................ 47
8.1 Application Information............................................ 47
8.2 Typical Application .................................................. 50
9
Power-Supply Recommendations...................... 55
9.1 Power-Supply Decoupling....................................... 55
9.2 Power Saving .......................................................... 55
10 Layout................................................................... 57
10.1 Layout Guidelines ................................................. 57
10.2 Layout Example .................................................... 58
11 Device and Documentation Support ................. 59
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
59
59
59
59
59
59
12 Mechanical, Packaging, and Orderable
Information ........................................................... 59
4 Revision History
Changes from Revision A (October 2015) to Revision B
Page
•
Changed Temperature Range Features bullet range from Industrial to Extended and from –40°C to +85°C to –40°C
to +125°C................................................................................................................................................................................ 1
•
Changed Description section ................................................................................................................................................. 1
•
Changed SPI Interface Clock at Full Throughput table.......................................................................................................... 1
•
Changed TA maximum specification from 85 to 125 in Absolute Maximum Ratings table..................................................... 4
•
Changed temperature range in conditions statement of Electrical Characteristics table from 85°C to 125°C ..................... 5
•
Changed temperature range from 85°C to 125°C in condition statements of all Timing Requirements tables .................... 7
•
Added DAQ Circuit With FDA Input Driver and Single-Ended or Differential Input section ................................................. 52
•
Changed Related Documentation section ........................................................................................................................... 59
Changes from Original (October 2015) to Revision A
•
2
Page
Released to production .......................................................................................................................................................... 1
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SBAS629B – OCTOBER 2015 – REVISED JUNE 2017
5 Pin Configuration and Functions
CS
SCLK
SDI
RVS
SDO-0
SDO-1
24
23
22
21
20
19
RGE Package
24-Pin VQFN
Top View
CONVST
1
18
SDO-2
RST
2
17
SDO-3
NC
3
16
DVDD
REFM
4
15
GND
REFP
5
14
AVDD
NC
6
13
AVDD
9
10
11
12
AINP
GND
NC
8
AINM
7
REFP
REFM
Thermal
Pad
Pin Functions
PIN
NAME
NO.
FUNCTION
AINM
10
Analog input
Negative analog input
AINP
9
Analog input
Positive analog input
AVDD
13, 14
Power supply
Analog power supply for the device
CONVST
1
Digital input
Conversion start input pin for the device.
A CONVST rising edge brings the device from ACQ state to CNV state.
CS
24
Digital input
Chip-select input pin for the device; active low.
The device takes control of the data bus when CS is low.
The SDO-x pins go to tri-state when CS is high.
DVDD
DESCRIPTION
16
Power supply
Interface supply
GND
11, 15
Power supply
Ground
NC
These pins must be left floating with no external connection
3, 6, 12
No connection
REFM
4, 8
Analog input
Reference ground potential
REFP
5, 7
Analog input
Reference voltage input
RST
2
Digital input
Asynchronous reset input pin for the device.
A low pulse on the RST pin resets the device and all register bits return to a default state.
RVS
21
Digital output
SCLK
23
Digital input
Clock input pin for the serial interface.
All system-synchronous data transfer protocols are timed with respect to the SCLK signal.
SDI
22
Digital input
Serial data input pin for the device.
This pin is used to feed the data or command into the device.
SDO-0
20
Digital output
Serial communication: data output 0
SDO-1
19
Digital output
Serial communication: data output 1
SDO-2
18
Digital output
Serial communication: data output 2
SDO-3
17
Digital output
Serial communication: data output 3
Thermal pad
Supply
Multi-function output pin for the device.
With CS held high, RVS reflects the status of the internal ADCST signal.
With CS low, the status of RVS depends on the output protocol selection.
Exposed thermal pad; connecting this pin to GND is recommended
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SBAS629B – OCTOBER 2015 – REVISED JUNE 2017
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
AVDD to GND
–0.3
2.1
V
DVDD to GND
–0.3
2.1
V
REFP to REFM
–0.3
5.5
V
REFM to GND
–0.1
0.1
V
Analog (AINP, AINM) to GND
–0.3
REFP + 0.3
V
Digital input (RST, CONVST, CS, SCLK, SDI) to GND
–0.3
DVDD + 0.3
V
Digital output (RVS, SDO-0, SDO-1, SDO-2, SDO-3) to GND
–0.3
DVDD + 0.3
V
Operating temperature, TA
–40
125
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
AVDD
Analog supply voltage
1.8
V
DVDD
Digital supply voltage
1.8
V
REFP
Positive reference
5
V
6.4 Thermal Information
ADS9110
THERMAL METRIC (1)
RGE (VQFN)
UNITS
24 PINS
RθJA
Junction-to-ambient thermal resistance
31.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
29.9
°C/W
RθJB
Junction-to-board thermal resistance
8.9
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
8.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.0
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBAS629B – OCTOBER 2015 – REVISED JUNE 2017
6.5 Electrical Characteristics
All specifications are for AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fDATA = 2 MSPS, unless otherwise noted.
All minimum and maximum specifications are for TA = –40°C to +125°C, unless otherwise noted.
All typical values are at TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
–VREF
VREF
V
–0.1
VREF + 0.1
V
ANALOG INPUT
FSR
Full-scale input range
(AINP – AINM) (1)
VIN
Absolute input voltage
(AINP and AINM to REFGND)
VCM
Common-mode voltage range
(AINP + AINM) / 2
CIN
Input capacitance
IIL
Input leakage current
TA = –40°C to +85°C
(VREF / 2) – 0.1
VREF / 2
(VREF / 2) + 0.1
(VREF / 2) –
0.075
VREF / 2
(VREF / 2) +
0.075
TA = –40°C to +125°C
In sample mode
V
60
In hold mode
pF
4
±1
µA
VOLTAGE REFERENCE INPUT
VREF
Reference input voltage range
IREF
Reference input current
2.5
Average current, VREF = 5 V,
2-kHz, full-scale input,
throughput = 2 MSPS
5
V
1.25
mA
18
Bits
DC ACCURACY
Resolution
NMC
No missing codes
18
TA = –40°C to +85°C
INL
Integral nonlinearity
TA = –40°C to +125°C
DNL
Differential nonlinearity
E(IO)
Input offset error
dVOS/dT
Input offset thermal drift
GE
Gain error
GE/dT
Gain error thermal drift
(1)
(2)
(3)
Common-mode rejection ratio
Bits
±0.5 (2)
1.5
LSB (3)
ppm
–5.7
±2
5.7
–1.85
±0.5
1.85
LSB
–7
±2
7
ppm
–0.75
±0.4 (2)
0.75
LSB
–1
±0.05 (2)
1
mV
1
–0.01 ±0.005 (2)
Transition noise
CMRR
–1.5
At dc to 20 kHz
μV/°C
0.01
%FS
0.25
ppm/°C
0.9
LSB
80
dB
Ideal input span, does not include gain or offset errors.
See Figure 9, Figure 10, Figure 25, and Figure 26 for statistical distribution data for INL, DNL, offset, and gain error parameters.
LSB = least-significant bit. 1 LSB at 18 bits is approximately 3.8 ppm.
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Electrical Characteristics (continued)
All specifications are for AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fDATA = 2 MSPS, unless otherwise noted.
All minimum and maximum specifications are for TA = –40°C to +125°C, unless otherwise noted.
All typical values are at TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
fIN = 2 kHz, TA = –40°C to +85°C
98
99.9
fIN = 2 kHz, TA = –40°C to +125°C
97
99.9
MAX
UNIT
AC ACCURACY (4)
SINAD
SNR
THD
SFDR
Signal-to-noise + distortion
Signal-to-noise ratio
Total harmonic distortion (5)
Spurious-free dynamic range
fIN = 100 kHz
95.4
fIN = 500 kHz
89
fIN = 2 kHz, TA = –40°C to +85°C
98.1
fIN = 2 kHz, TA = –40°C to +125°C
97.2
fIN = 100 kHz
dB
100
100
dB
95.5
fIN = 500 kHz
89.3
fIN = 2 kHz
–118
fIN = 100 kHz
–111
fIN = 500 kHz
–101
fIN = 2 kHz
123
fIN = 100 kHz
116
fIN = 500 kHz
106
dB
dB
DIGITAL INPUTS (6)
VIH
High-level input voltage
0.65 DVDD
DVDD + 0.3
V
VIL
Low-level input voltage
–0.3
0.35 DVDD
V
DIGITAL OUTPUTS
(6)
VOH
High-level output voltage
IOH = 2-mA source
VOL
Low-level output voltage
IOH = 2-mA sink
DVDD – 0.45
V
0.45
V
POWER SUPPLY
AVDD
Analog supply voltage
1.65
1.8
1.95
V
DVDD
Digital supply voltage
1.65
1.8
1.95
V
Active, 2-MSPS throughput,
TA = –40°C to +85°C
5
6.25
Active, 2-MSPS throughput,
TA = –40°C to +125°C
5
6.5
IDD
PD
AVDD supply current
(AVDD = 1.8 V)
AVDD power dissipation
(AVDD = 1.8 V)
mA
Static, ACQ state
3.7
Low-power, NAP mode
500
mA
µA
Power-down, PD state
1
Active, 2-MSPS throughput,
TA = –40°C to +85°C
9
11.25
Active, 2-MSPS throughput,
TA = –40°C to +125°C
9
11.7
mW
Static, ACQ state
6.6
Low-power, NAP mode
900
Power-down, PD state
1.8
mW
µW
TEMPERATURE RANGE
TA
(4)
(5)
(6)
6
Operating free-air temperature
–40
125
°C
All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.1 dB below full-scale,
unless otherwise specified.
Calculated on the first nine harmonics of the input frequency.
As per the JESD8-7A standard. Specified by design; not production tested.
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SBAS629B – OCTOBER 2015 – REVISED JUNE 2017
6.6 Timing Requirements: Conversion Cycle
All specifications are for AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fDATA = 2 MSPS, unless otherwise noted.
All minimum and maximum specifications are for TA = –40°C to +125°C. All typical values are at TA = 25°C. See Figure 1.
MIN
TYP
MAX
UNIT
2
MHz
TIMING REQUIREMENTS
fcycle
Sampling frequency
tcycle
ADC cycle time period
twh_CONVST
500
ns
Pulse duration: CONVST high
30
ns
twl_CONVST
Pulse duration: CONVST low
30
ns
tacq
Acquisition time
150
ns
tqt_acq
Quiet acquisition time (1)
25
ns
td_cnvcap
Quiet aperture time (1)
10
ns
TIMING SPECIFICATIONS
tconv
(1)
Conversion time
300
340
ns
See Figure 47.
6.7 Timing Requirements: Asynchronous Reset, NAP, and PD
All specifications are for AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fDATA = 2 MSPS, unless otherwise noted.
All minimum and maximum specifications are for TA = –40°C to +125°C. All typical values are at TA = 25°C. See Figure 2 and
Figure 3.
MIN
TYP
MAX
UNIT
TIMING REQUIREMENTS
twl_RST
Pulse duration: RST low
100
ns
TIMING SPECIFICATIONS
td_rst
Delay time: RST rising to RVS rising
1250
µs
tnap_wkup
tPWRUP
Wake-up time: NAP mode
300
ns
Power-up time: PD mode
250
µs
6.8 Timing Requirements: SPI-Compatible Serial Interface
All specifications are for AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fDATA = 2 MSPS, unless otherwise noted.
All minimum and maximum specifications are for TA = –40°C to +125°C. All typical values are at TA = 25°C. See Figure 4.
MIN
TYP
MAX
UNIT
75
MHz
TIMING REQUIREMENTS
fCLK
Serial clock frequency
tCLK
Serial clock time period
tph_CK
SCLK high time
0.45
0.55
tCLK
tpl_CK
SCLK low time
0.45
0.55
tCLK
tsu_CSCK
Setup time: CS falling to the first SCLK capture edge
tsu_CKDI
Setup time: SDI data valid to the SCLK capture edge
tht_CKDI
Hold time: SCLK capture edge to (previous) data valid on SDI
tht_CKCS
Delay time: last SCLK falling to CS rising
13.33
ns
5
ns
1.2
ns
0.65
ns
5
ns
TIMING SPECIFICATIONS
tden_CSDO
Delay time: CS falling to data enable
4.5
ns
tdz_CSDO
Delay time: CS rising to SDO going to 3-state
10
ns
td_CKDO
Delay time: SCLK launch edge to (next) data valid on SDO
6.5
ns
td_CSRDY_f
Delay time: CS falling to RVS falling
5
ns
td_CSRDY_r
Delay time:
CS rising to RVS rising
After NOP operation
10
After WR or RD operation
70
ns
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6.9 Timing Requirements: Source-Synchronous Serial Interface (External Clock)
All specifications are for AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fDATA = 2 MSPS, unless otherwise noted.
All minimum and maximum specifications are for TA = –40°C to +125°C. All typical values are at TA = 25°C. See Figure 5.
MIN
TYP
MAX
UNIT
100
MHz
TIMING REQUIREMENTS
fCLK
Serial clock frequency
tCLK
Serial clock time period
10
ns
TIMING SPECIFICATIONS (1)
td_CKSTR_r
Delay time: SCLK launch edge to RVS rising
td_CKSTR_f
Delay time: SCLK launch edge to RVS falling
toff_STRDO_f
Time offset: RVS rising to (next) data valid on SDO
–0.5
toff_STRDO_r
Time offset: RVS falling to (next) data valid on SDO
–0.5
(1)
8.5
ns
8.5
ns
0.5
ns
0.5
ns
Other parameters are the same as the Timing Requirements: SPI-Compatible Serial Interface table.
6.10 Timing Requirements: Source-Synchronous Serial Interface (Internal Clock)
All specifications are for AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fDATA = 2 MSPS, unless otherwise noted.
All minimum and maximum specifications are for TA = –40°C to +125°C. All typical values are at TA = 25°C. See Figure 6.
MIN
TYP
MAX
UNIT
TIMING SPECIFICATIONS (1)
td_CSSTR
Delay time: CS falling to RVS rising
12
40
ns
toff_STRDO_f
Time offset: RVS rising to (next) data valid on SDO
–0.5
0.5
ns
toff_STRDO_r
Time offset: RVS falling to (next) data valid on SDO
–0.5
0.5
ns
9.9
11.1
INTCLK / 2 option
19.8
22.2
INTCLK / 4 option
39.6
44.4
INTCLK option
tSTR
Strobe output time period
ns
tph_STR
Strobe output high time
0.45
0.55
tSTR
tpl_STR
Strobe output low time
0.45
0.55
tSTR
(1)
8
Other parameters are the same as the Timing Requirements: SPI-Compatible Serial Interface table.
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SBAS629B – OCTOBER 2015 – REVISED JUNE 2017
Sample
S
Sample
S+1
twh_CONVST
twl_CONVST
CONVST
tcycle
tconv_max
tconv
tacq
tconv_min
ADCST (Internal)
CNV (C)
ACQ (C+1)
CS
RVS
Figure 1. Conversion Cycle Timing Diagram
trst
twl_RST
RST
td_rst
CONVST
CS
SCLK
RVS
SDO-x
Figure 2. Asynchronous Reset Timing Diagram
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Sample
S
Sample
S+1
twh_CONVST
CONVST
tcycle
tconv
tnap
tnap_wkup
tacq
tconv_max
tconv_min
ADCST
(Internal)
CNV C
NAP + ACQ C+1
ACQ C+1
CS
RVS
t=0
Figure 3. NAP Mode Timing Diagram
tCLK
tph_CK
CS
SCLK
tpl_CK
(1)
tsu_CKDI
tsu_CSCK
tht_CKCS
SCLK(1)
tht_CKDI
SDI
tden_CSDO
SDO-x
tdz_CSDO
td_CKDO
SDO-x
(1)
The SCLK polarity, launch edge, and capture edge depend on the SPI protocol selected.
Figure 4. SPI-Compatible Serial Interface Timing Diagram
10
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tCLK
tph_CK
CS
tpl_CK
SCLK
td_CKSTR_f
tsu_CSCK
tht_CKCS
SCLK
td_CKSTR_r
RVS
tden_CSDO
tdz_CSDO
toff_STRDO_r
toff_STRDO_f
SDO-x
(DDR)
SDO-x
td_CSRDY_f
td_CSRDY_r
toff_STRDO_r
SDO-x
(SDR)
RVS
Figure 5. Source-Synchronous Serial Interface Timing Diagram (External Clock)
tSTR
CS
RVS
tph_STR
tden_CSDO
tdz_CSDO
toff_STRDO_r
tpl_STR
toff_STRDO_f
SDO-x
(DDR)
SDO-x
td_CSRDY_f
td_CSRDY_r
toff_STRDO_r
SDO-x
(SDR)
RVS
td_CSSTR
Figure 6. Source-Synchronous Serial Interface Timing Diagram (Internal Clock)
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6.11 Typical Characteristics
at TA = 25°C, AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fSAMPLE = 2 MSPS (unless otherwise noted)
0.75
Differential Nonlinearity (LSB)
Integral Nonlinearity (LSB)
1.5
1
0.5
0
-0.5
-1
-1.5
±131072
0.25
0
-0.25
-0.5
-0.75
-131072
131071
ADC Output Code
0.5
131071
Typical INL = ±0.5 LSB
Typical DNL = ±0.4 LSB
Figure 8. Typical DNL
600
600
480
480
Frequency
Frequency
Figure 7. Typical INL
360
240
Min
360
240
120
0
0
-1.5 -1.2 -0.9 -0.6 -0.3
0
0.3
0.6
0.9
1.2
1.5
-1
-0.8 -0.6 -0.4 -0.2
C009
Integral Nonlinearity (LSB)
0
0.2
0.4
0.6
0.8
1
C009
Differential Nonlinearity (LSB)
600 devices
600 devices
Figure 9. Typical INL Distribution
Figure 10. Typical DNL Distribution
0.75
Differential Nonlinearity (LSB)
1.5
Integral Nonlinearity (LSB)
Max
Min
Max
120
1
Maximum
0.5
0
-0.5
Minimum
-1
-1.5
0.5
Maximum
0.25
0
-0.25
Minimum
-0.5
-0.75
-40
-7
26
59
92
Free-Air Temperature (oC)
125
-40
C004
VREF = 5 V
-7
26
59
92
Free-Air Temperature (o C)
125
C003
VREF = 5 V
Figure 11. INL vs Temperature
12
C001
ADC Output Code
C002
Figure 12. DNL vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fSAMPLE = 2 MSPS (unless otherwise noted)
0.75
Differential Nonlinearity (LSB)
Integral Nonlinearity (LSB)
1.5
1
Maximum
0.5
0
-0.5
Minimum
-1
-1.5
Maximum
0.5
0.25
0
-0.25
-0.5
Minimum
-0.75
2.5
3
3.5
4
4.5
5
2.5
3
3.5
C006
Reference Voltage (V)
TA = 25°C
Figure 13. INL vs Reference Voltage
5
C005
Figure 14. DNL vs Reference Voltage
32768
24576
24576
Frequency
Frequency
4.5
TA = 25°C
32768
16384
16384
8192
8192
0
0
131069 131070 131071 131072 131073 131074 131075
131069
131070
C009
ADC Output Code
131071
131072
131073
131074
C010
ADC Output Code
Standard deviation = 0.9 LSB
Standard deviation = 0.9 LSB
Figure 15. DC Input Histogram, Code Center
Figure 16. DC Input Histogram, Code Transition
0
0
±40
±40
Power (dB)
Power (dB)
4
Reference Voltage (V)
±80
±120
±160
±80
±120
±160
±200
±200
0
200
400
600
800
fIN, Input Frequency ( kHz)
1000
0
fIN = 2 kHz, SNR = 100 dB, THD = –120 dB
200
400
600
800
fIN, Input Frequency ( kHz)
C011
1000
C012
fIN = 100 kHz, SNR = 97.5 dB, THD = –113 dB
Figure 17. Typical FFT
Figure 18. Typical FFT
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fSAMPLE = 2 MSPS (unless otherwise noted)
102
16.6
101
16.4
126
±114
125
100
16.2
SINAD
THD (dBFS)
ENOB
123
±118
122
121
±119
THD
±120
99
16
98
15.8
124
±117
120
119
±121
±40
26
±7
59
92
Free-Air Temperature (oC)
118
±122
-40
125
-7
59
Free-Air Temperature
92
125
(oC)
C014
fIN = 2 kHz, VREF = 5 V
Figure 20. Distortion Performance vs Temperature
Figure 19. Noise Performance vs Temperature
101
18
±113
124
100
17.5
±114
123
16.5
98
SNR
16
97
122
±115
THD (dBFS)
SINAD
THD
±116
121
±117
120
119
±118
ENOB
SFDR
15.5
2.5
3
3.5
4
4.5
118
±119
15
95
SFDR (dBFS)
17
99
ENOB (Bits)
SNR, SINAD (dBFS)
26
C013
fIN = 2 kHz, VREF = 5 V
96
SFDR (dBFS)
SNR
SFDR
±116
ENOB (Bits)
SNR, SINAD (dBFS)
±115
117
±120
5
2.5
3
3.5
4
4.5
5
C015
Reference Voltage (V)
Reference Voltage (V)
fIN = 2 kHz, TA = 25°C
fIN = 2 kHz, TA = 25°C
Figure 22. Distortion Performance vs Reference Voltage
Figure 21. Noise Performance vs Reference Voltage
100
17
16
SNR
15.5
ENOB
±96
124
±100
120
±104
116
112
±108
THD
15
±112
108
90
14.5
±116
104
14
±120
0
100
200
300
400
fIN, Input Frequency (kHz)
500
C017
100
0
100
200
300
400
500
C018
fIN, Input Frequency (kHz)
VREF = 5 V, TA = 25°C
VREF = 5 V, TA = 25°C
Figure 23. Noise Performance vs Input Frequency
14
SFDR
92
88
SFDR (dBFS)
96
THD (dBFS)
16.5
SINAD
ENOB (Bits)
SNR, SINAD (dBFS)
98
94
C016
Figure 24. Distortion Performance vs Input Frequency
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Typical Characteristics (continued)
600
500
480
400
Frequency
Frequency
at TA = 25°C, AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fSAMPLE = 2 MSPS (unless otherwise noted)
360
240
120
300
200
100
0
0
-1
-0.8 -0.6 -0.4 -0.2
0
0.2
0.4
0.6
0.8
1
-0.01
-0.006
C009
Offset (mV)
600 devices
0.006
0.01
C009
Figure 26. Gain Error Typical Distribution
1
0.01
0.5
0.005
Gain Error (%FS)
Offset (mV)
0.002
600 devices
Figure 25. Offset Typical Distribution
0
-0.5
0
-0.005
-1
-0.01
±40
±7
26
59
92
125
-40
-7
C019
Free-Air Temperature (oC)
26
59
92
125
C020
Free-Air Temperature (oC)
VREF = 5 V
VREF = 5 V
Figure 27. Offset vs Temperature
Figure 28. Gain Error vs Temperature
1
0.01
0.5
0.005
Gain Error (%FS)
Offset (mV)
-0.002
Gain Error (%FS)
0
-0.5
0
-0.005
-1
-0.01
2.5
3
3.5
4
4.5
5
2.5
3
C021
Reference Voltage (V)
3.5
4
4.5
Reference Voltage (V)
TA = 25°C
5
C022
TA = 25°C
Figure 29. Offset vs Reference Voltage
Figure 30. Gain Error vs Reference Voltage
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fSAMPLE = 2 MSPS (unless otherwise noted)
8
Analog Supply Current, Active (mA)
Analog Supply Current, Active (mA)
10
8
6
4
2
-7
26
59
92
Without
NAP
4
2
With
NAP
0
2000
0
-40
6
125
1600
C026
Free-Air Temperature (oC)
800
400
0
C027
TA = 25°C
2 MSPS
Figure 32. Supply Current vs Throughput
Figure 31. Supply Current vs Temperature
2
Reference Current (mA)
2
Reference Current (mA)
1200
fS, Throughput (kSPS)
1.5
1
0.5
-7
26
59
92
1
0.5
0
2000
0
-40
1.5
125
1600
1200
800
400
fS, Throughput (kSPS)
C028
Free-Air Temperature (oC)
0
C02
TA = 25°C
2 MSPS
Figure 34. Reference Current vs Throughput
Figure 33. Reference Current vs Temperature
Common-Mode Rejection Ratio (dB)
±86
±87
±88
±89
±90
±91
±92
±93
0
150
300
450
600
C025
fIN, Input Frequency (kHz)
Figure 35. CMRR vs Input Frequency
16
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7 Detailed Description
7.1 Overview
The ADS9110 is a high-speed, successive approximation register (SAR), analog-to-digital converter (ADC) based
on the charge redistribution architecture. This compact device features high performance at a high throughput
rate and at low power consumption.
The ADS9110 supports unipolar, fully-differential analog input signals and operates with a 2.5-V to 5-V external
reference, offering a wide selection of input ranges without additional input scaling.
When a conversion is initiated, the differential input between the AINP and AINM pins is sampled on the internal
capacitor array. The ADS9110 uses an internal clock to perform conversions. During the conversion process,
both analog inputs are disconnected from the internal circuit. At the end of conversion process, the device
reconnects the sampling capacitors to the AINP and AINM pins and enters acquisition phase.
The device consumes only 15 mW of power when operating at the full 2-MSPS throughput. Power consumption
at lower throughputs can be reduced by using the flexible low-power modes (NAP and PD).
The new multiSPI™ interface simplifies board layout, timing, and firmware, and achieves high throughput at
lower clock speeds, thus allowing easy interface to a variety of microprocessors, digital signal processors
(DSPs), and field-programmable gate arrays (FPGAs).
7.2 Functional Block Diagram
From a functional perspective, the device comprises of two modules: the converter module and the interface
module, as shown in this section.
The converter module samples and converts the analog input into an equivalent digital output code whereas the
interface module facilitates communication and data transfer with the host controller.
REFP AVDD
DVDD
RST
CONVST
CS
SCLK
AINP
Interface Module
Converter Module
SDI
SDO-0
SDO-1
AINM
SDO-2
SDO-3
RVS
REFM
GND
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7.3 Feature Description
7.3.1 Converter Module
As shown in Figure 36, the converter module samples the analog input signal (provided between the AINP and
AINM pins), compares this signal with the reference voltage (provided between the pair of REFP and REFM
pins), and generates an equivalent digital output code.
The converter module receives RST and CONVST inputs from the interface module and outputs the ADCST
signal and the conversion result back to the interface module.
REFP
DVDD
AVDD
RST
OSC
CONVST
CS
RST
AINP
AINM
SCLK
CONVST
Sampleand-Hold
Circuit
SDI
ADCST
Interface
Module
ADC
Conversion
Result
SDO-0
SDO-1
SDO-2
SDO-3
AGND
RVS
Converter Module
REFM
DGND
GND
Figure 36. Converter Module
7.3.1.1 Sample-and-Hold Circuit
The device supports unipolar, fully-differential analog input signals. Figure 37 shows a small-signal equivalent
circuit of the sample-and-hold circuit. Each sampling switch is represented by a resistance (Rs1 and Rs2, typically
30 Ω) in series with an ideal switch (sw1 and sw2). The sampling capacitors, Cs1 and Cs2, are typically 60 pF.
Device in Hold Mode
Rs1
sw1
AINP
4 pF
Cs1
REFP
4 pF
Cs2
GND
GND
AINN
Rs2
sw2
Figure 37. Input Sampling Stage Equivalent Circuit
During the acquisition process (in ACQ state), both positive and negative inputs are individually sampled on Cs1
and Cs2, respectively. During the conversion process (in CNV state), the device converts for the voltage
difference between the two sampled values: VAINP – VAINM.
Each analog input pin has electrostatic discharge (ESD) protection diodes to REFP and GND. Keep the analog
inputs within the specified range to avoid turning the diodes on.
18
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Feature Description (continued)
Equation 1 and Equation 2 show the full-scale voltage range (FSR) and common-mode voltage range (VCM)
supported at the analog inputs for any external reference voltage (VREF).
FSR r VREF
(1)
§ VREF ·
VCM ¨
¸ r 0.1 V
© 2 ¹
(2)
7.3.1.2 External Reference Source
The input range for the device is set by the external voltage applied at the two REFP pins. The REFM pins
function as the reference ground and must be connected to each reference capacitor.
The device takes very little static current from the reference pins in the RST and ACQ states. During the
conversion process (in CNV state), binary-weighted capacitors are switched onto the reference pins. The
switching frequency is proportional to the conversion clock frequency, but the dynamic charge requirements are
a function of the absolute values of the input voltage and the reference voltage. Reference capacitors decouple
the dynamic reference loads and a low-impedance reference driver is required to keep the voltage regulated to
within 1 LSB.
Most reference sources have very high broadband noise. The voltage reference source is recommended to be
filtered with a 160-Hz filter before being connected to the reference driver, as shown in Figure 38. See the ADC
Reference Driver section for the reference capacitor and driver selection. Also, the reference inputs are sensitive
to board layout; thus, the layout guidelines described in the Layout section must be followed.
5
REFP
TI Device
Buffer
CREF_FLT
1 µF
6
8 REFM
RREF_FLT
1 k:
9
REFM
7 REFP
Voltage
Reference
4
CREF
10 µF
CREF
10 µF
CREF
10 µF
Copyright © 2016, Texas Instruments Incorporated
Figure 38. Reference Driver Schematic
7.3.1.3 Internal Oscillator
The device features an internal oscillator (OSC) that provides the conversion clock; see Figure 36. Conversion
duration can vary but is bounded by the minimum and maximum value of tconv, as specified in the Timing
Requirements: Conversion Cycle table.
The interface module can use this internal clock (OSC) or an external clock (provided by the host controller on
the SCLK pin) or a combination of the internal and external clocks for executing the data transfer operations
between the device and host controller; see the Interface Module section for more details.
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Feature Description (continued)
7.3.1.4 ADC Transfer Function
The ADS9110 supports unipolar, fully-differential analog inputs. The device output is in twos compliment format.
Figure 39 and Table 1 show the ideal transfer characteristics for the device.
The LSB for the ADC is given by Equation 3:
1 LSB
FSR
18
2
2u
VREF
218
(3)
ADC Code (Hex)
1FFFF
00000
3FFFF
20001
20000
±VREF
+ 1 LSB
±1 LSB
0
VREF
± 1 LSB
VIN
Differential Analog Input
(AINP AINM)
Figure 39. Differential Transfer Characteristics
Table 1. Transfer Characteristics
20
DIFFERENTIAL ANALOG INPUT VOLTAGE
(AINP – AINM)
OUTPUT CODE
(Hex)
< –VREF
20000
–VREF + 1 LSB
20001
–1 LSB
3FFFF
0
00000
1 LSB
00001
> VREF – 1 LSB
1FFFF
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7.3.2 Interface Module
The interface module facilitates the communication and data transfer between the device and the host controller.
As shown in Figure 40, the module comprises of shift registers (both input data and output data), configuration
registers, and a protocol unit.
Interface Module
Shift Registers
RST
Output Data Register (ODR)
CONVST
D19
D18
D1
D0
CS
20 Bits
SCLK
Converter Module
B19
B18
B1
Protocol
20 Bits
B0
Input Data Register (IDR)
SDI
SDO-0
SDO-1
SDO-2
Command Processor
SCLK
Counter
SDO-3
RVS
Configuration Registers
Figure 40. Interface Module
The Pin Configuration and Functions section provides descriptions of the interface pins; the Data Transfer Frame
section details the functions of shift registers, the SCLK counter, and the command processor; the Data Transfer
Protocols section details supported protocols; and the Register Maps section explains the configuration registers
and bit settings.
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7.4 Device Functional Modes
As shown in Figure 41, the device supports three functional states: RST, ACQ, and CNV. The device state is
determined by the status of the CONVST and RST control signals provided by the host controller.
Power Up
ACQ
RST Rising Edge
CONVST Rising Edge
RST Falling Edge
End of Conversion
CNV
RST
RST Falling Edge
Figure 41. Device Functional States
7.4.1 RST State
In the ADS9110, the RST pin is an asynchronous digital input. To enter RST state, the host controller must pull
the RST pin low and keep it low for the twl_RST duration (as specified in the Timing Requirements: Asynchronous
Reset, NAP, and PD table).
In RST state, all configuration registers (see the Register Maps section) are reset to the default values, the RVS
pins remain low, and the SDO-x pins are tri-stated.
To exit RST state, the host controller must pull the RST pin high with CONVST and SCLK held low and CS held
high, as shown in Figure 42. After a delay of td_rst, the device enters ACQ state and the RVS pin goes high.
trst
twl_RST
RST
td_rst
CONVST
CS
SCLK
RVS
SDO-x
Figure 42. Asynchronous Reset
To operate the device in any of the other two states (ACQ or CNV), RST must be held high. With RST held high,
transitions on the CONVST pin determine the functional state of the device.
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Device Functional Modes (continued)
Figure 43 shows a typical conversion process. An internal signal, ADCST, goes low during conversion and goes
high at the end of conversion. With CS held high, RVS reflects the status of ADCST.
Sample
S
Sample
S+1
twh_CONVST
twl_CONVST
CONVST
tcycle
tconv_max
tconv
tacq
tconv_min
ADCST (Internal)
CNV (C)
ACQ (C+1)
CS
RVS
Figure 43. Typical Conversion Process
7.4.2 ACQ State
In ACQ state, the device acquires the analog input signal. The device enters ACQ state on power-up, after any
asynchronous reset, or after end of every conversion.
An RST falling edge takes the device from an ACQ state to a RST state. A CONVST rising edge takes the
device from an ACQ state to a CNV state.
The device offers a low-power NAP mode to reduce power consumption in the ACQ state; see the NAP Mode
section for more details on NAP mode.
7.4.3 CNV State
The device moves from ACQ state to CNV state on a rising edge of the CONVST pin. The conversion process
uses an internal clock and the device ignores any further transitions on the CONVST signal until the ongoing
conversion is complete (that is, during the time interval of tconv).
At the end of conversion, the device enters ACQ state. The cycle time for the device is given by Equation 4:
t cycle-min
tconv
t acq-min
(4)
NOTE
The conversion time, tconv, can vary within the specified limits of tconv_min and tconv_max (as
specified in the Timing Requirements: Conversion Cycle table). After initiating a
conversion, the host controller must monitor for a low-to-high transition on the RVS pin or
wait for the tconv_max duration to elapse before initiating a new operation (data transfer or
conversion). If RVS is not monitored, substitute tconv in Equation 4 with tconv_max.
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7.5 Programming
The device features four configuration registers (as described in the Register Maps section) and supports two
types of data transfer operations: data write (the host configures the device), and data read (the host reads data
from the device).
To access the internal configuration registers, the device supports the commands listed in Table 2.
Table 2. Supported Commands
OPCODE B[19:0]
COMMAND ACRONYM
0000_0000_0000_0000_0000
NOP
COMMAND DESCRIPTION
No operation
1001__0000_0000
RD_REG
Read contents from the
1010__
WR_REG
Write to the
1111_1111_1111_1111_1111
NOP
Remaining combinations
Reserved
No operation
These commands are reserved and treated by the
device as no operation
In the ADS9110, any data write to the device is always synchronous to the external clock provided on the SCLK
pin. The data read from the device can be synchronized to the same external clock or to an internal clock of the
device by programming the configuration registers (see the Data Transfer Protocols section for details).
In any data transfer frame, the contents of an internal, 20-bit, output data word are shifted out on the SDO pins.
The D[19:2] bits of the 20-bit output data word for any frame (F+1), are determined by the:
• Settings of the DATA_PATN[2:0] bits applicable to frame F+1 (see the DATA_CNTL register) and
• Command issued in frame F
If a valid RD_REG command is executed in frame F, then the D[19:12] bits in frame F+1 reflect the contents of
the selected register and the D[11:0] bits are 0s.
If the DATA_PATN[2:0] bits for frame F+1 are set to 1xxb, then the D[19:2] bits in frame F+1 are the fixed data
pattern shown in Figure 44.
For all other combinations, the D[19:2] bits for frame F+1 are the latest conversion result.
A valid RG_READ command is
received in the previous frame.
Output
Data Word
D[19:0]
D19
000
001
Conversion
Result
Register Data
_
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