ADS9226
SBAS842 –ADS9226
JULY 2020
SBAS842 – JULY 2020
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ADS9226 16-Bit, Dual, Low-Latency, Simultaneous-Sampling SAR ADC
1 Features
3 Description
•
The ADS9226 is a 16-bit, dual-channel, simultaneoussampling, analog-to-digital converter (ADC) with an
integrated reference buffer. The device can operate
on a single 5-V supply and supports unipolar, pseudodifferential analog input signals with excellent DC and
AC specifications.
•
•
•
•
•
•
•
•
•
High resolution, high throughput:
– 16 bits, 2.048 MSPS
Fast response time with low latency: 488 ns
Two simultaneously sampled channels
Unipolar, pseudo-differential inputs
Excellent DC and AC performance:
– 16-bits, no missing codes
– ±2.75-LSB max INL
– 90.8-dB SNR, –100-dB THD
Wide analog supply range from 4 V to 5.5 V
Integrated reference buffers
SPI-compatible serial interface
Extended temperature range: –40°C to +125°C
Small footprint: 5-mm × 5-mm VQFN
The device supports an SPI-compatible serial
(enhanced-SPI) interface, making the device easy to
pair with a diversity of microcontrollers, digital signal
processors (DSPs), and field-programmable gate
arrays (FPGAs).
The device comes in a space-saving, 5-mm × 5-mm,
VQFN package. The ADS9226 is specified for the
extended temperature range of –40°C to +125°C.
Device Information (1)
2 Applications
•
•
•
•
•
PART NUMBER
Servo drive position feedback
Servo drive power-stage modules
Telecom optical modules
Power quality analyzers
DC/AC power supplies, electronic loads
ADS9226
(1)
PACKAGE
VQFN (32)
BODY SIZE (NOM)
5.00 mm × 5.00 mm
For all available packages, see the orderable addendum at
the end of the datasheet.
Absolute/Incremental Encoder
SONAR
Reference
Position
I
ADC
sine
0°
ADC
Host
Encoder
Baseband
Signal
Host
Q
ADC
cosine
ADC
90°
Low Latency SAR
Low Latency SAR
Local Oscillator
Typical Application Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
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Copyright
© 2020 Texas
Instruments
Incorporated
intellectual
property
matters
and other important disclaimers. PRODUCTION DATA.
1
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................6
6.6 Timing Requirements.................................................. 8
6.7 Switching Characteristics............................................8
6.8 Timing Diagrams......................................................... 9
6.9 Typical Characteristics.............................................. 11
7 Detailed Description......................................................15
7.1 Overview................................................................... 15
7.2 Functional Block Diagram......................................... 15
7.3 Feature Description...................................................16
7.4 Device Functional Modes..........................................20
8 Application and Implementation.................................. 22
8.1 Application Information............................................. 22
8.2 Typical Application.................................................... 24
9 Power Supply Recommendations................................26
10 Layout...........................................................................27
10.1 Layout Guidelines................................................... 27
10.2 Layout Example...................................................... 28
11 Device and Documentation Support..........................29
11.1 Related Documentation...........................................29
11.2 Receiving Notification of Documentation Updates.. 29
11.3 Support Resources................................................. 29
11.4 Trademarks............................................................. 29
11.5 Electrostatic Discharge Caution.............................. 29
11.6 Glossary.................................................................. 29
12 Mechanical, Packaging, and Orderable
Information.................................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
July 2020
*
Initial release.
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REFM_A
REFP_A
GND
AVDD
DVDD
GND
DVDD
NC
32
31
30
29
28
27
26
25
5 Pin Configuration and Functions
AINP_A
1
24
SDO-0A
AINM_A
2
23
SDO-1A
NC
3
22
GND
4
REFIN
5
20
SDO-0B
NC
6
19
SDO-1B
AINM_B
7
18
AINP_B
8
17
21
16
15
14
13
12
11
10
9
Thermal Pad
Figure 5-1. RHB Package, 5-mm × 5-mm, 32-Pin VQFN, Top View
Pin Functions
PIN
NAME
NO.
FUNCTION
AINM_A
2
Analog input
Negative analog input for channel A.
AINM_B
7
Analog input
Negative analog input for channel B.
AINP_A
1
Analog input
Positive analog input for channel A.
AINP_B
8
Analog input
Positive analog input for channel B.
12, 29
Power supply
Analog power-supply pin. Short pins 12 and 29 together.
Place a 1-µF decoupling capacitor between pins 11 and 12.
Place a 1-µF decoupling capacitor between pins 29 and 30.
AVDD
DESCRIPTION
Chip-select input pin; active low.
The device takes control of the data bus when CS is low.
The SDO-xy pins go to Hi-Z when CS is high.
Connect these pins together externally with a short trace.
CS
13, 14
Digital input
DVDD
26, 28
Power supply
Interface power-supply pin.
Place a 1-µF decoupling capacitor between pins 27 and 26 and pins 27
and 28.
GND
4, 11, 15, 27,
30
Power supply
Device ground.
NC
3, 6, 17, 18,
21, 22, 25
No connection
No external connection.
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PIN
NAME
NO.
FUNCTION
REFIN
5
Analog input
Reference voltage for the ADC.
REFM_A
32
Analog input
ADC_A negative reference input.
Externally connect to the device GND.
REFM_B
9
Analog input
ADC_B negative reference input.
Externally connect to the device GND.
REFP_A
31
Analog output
Positive output of reference buffer A. ADC_A positive reference input.
Place a 10-µF decoupling capacitor between pins 31 and 32.
REFP_B
10
Analog output
Positive output of reference buffer B. ADC_B positive reference input.
Place a 10-µF decoupling capacitor between pins 9 and 10.
SCLK
16
Digital input
SDO-0A
24
Digital output
Data output 0 for channel A.
SDO-0B
20
Digital output
Data output 0 for channel B.
SDO-1A
23
Digital output
Data output 1 for channel A.
SDO-1B
19
Digital output
Data output 1 for channel B.
Thermal pad
4
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Supply
DESCRIPTION
Clock input pin for the serial interface.
Exposed thermal pad. TI recommends connecting this pin to the printed
circuit board (PCB) ground.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
AVDD to GND
DVDD to GND
MIN
MAX
–0.3
6
UNIT
V
–0.3
6
V
Digital input pins
GND – 0.3
DVDD + 0.3
V
Digital output pins
GND – 0.3
DVDD + 0.3
V
–0.3
AVDD + 0.3
V
AINP_A, AINP_B to GND, AINM_A, AINM_B to GND
REFM_A, REFM_B
GND – 0.1
GND + 0.1
V
REFP_A, REFP_B to GND
GND – 0.3
AVDD + 0.3
V
–0.3
AVDD + 0.3
V
Reference input voltage
REFIN to GND
Input or output current to any pin except power-supply pin
–10
Junction temperature, TJ
Storage temperature, Tstg
(1)
–65
10
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4
5
5.5
Operating
1.65
3
5.5
SCLK > 20 MHz
2.35
3
5.5
1.4
AVDD/2
AVDD/1.75 – 0.2
V
POWER SUPPLY
AVDD
DVDD
V
V
EXTERNAL REFERENCE INPUT
VREFIN
External reference
input voltage
ANALOG INPUTS
FSR
Full-scale input range
–VREFIN
VREFIN
V
VINP_x
Absolute input voltage
AINP_x(1)
–0.1
AVDD + 0.1
V
VINM_x
Absolute input voltage
AINM_x(2)
VREFIN – 0.1
VREFIN
VREFIN + 0.1
V
–40
25
125
°C
TEMPERATURE RANGE
TA
(1)
(2)
Ambient temperature
AINP_x refers to AINP_A and AINP_B positive input pins for ADC_A and ADC_B respectively.
AINM_x refers to AINM_A and AINM_B positive input pins for ADC_A and ADC_B respectively.
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6.4 Thermal Information
ADS9226
THERMAL METRIC(1)
UNIT
RHB (VQFN)
32 PINS
RθJA
Junction-to-ambient thermal resistance
29
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
17.1
°C/W
Junction-to-board thermal resistance
9.4
°C/W
ΨJT
Junction-to-top characterization parameter
0.2
°C/W
ΨJB
Junction-to-board characterization parameter
9.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
at AVDD = 4 V to 5.5 V, DVDD = 3.3 V, VREFIN = AVDD / 2 and maximum throughput (unless otherwise noted);
minimum and maximum values at TA = –40°C to +125°C; typical values at TA = 25°C and AVDD = 5 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
IIN
Analog input leakage current
Ci
Input capacitance
BW
Analog input bandwidth
±1
Sample mode
µA
16
Hold mode
pF
1
–3-dB input signal
52
–0.1-dB input signal
4.2
MHz
DC ACCURACY
Resolution
No missing codes
16
bit
DNL
Differential nonlinearity
–0.55
±0.25
0.55
LSB
INL
Integral nonlinearity
–2.75
±1
2.75
LSB
EO
Offset error
±2
9
LSB
–9
Offset error matching
ΔEO/ΔT
Offset error temperature drift
GE
Gain error
±0.5
1
–0.027
Gain error matching
ΔGE/ΔT
Gain drift
Transition noise
LSB
Mid code, PFS – 1000, NFS + 1000
±0.01
ppm/℃
0.027
%FSR
0.2
%FSR
5
ppm/°C
0.675
LSB
AC ACCURACY
6
SNR
Signal-to-noise ratio
SINAD
Signal-to-noise plus distortion
THD
Total harmonic distortion
SFDR
Spurious-free dynamic range
ISOXT
Channel to channel isolation
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fIN = 2 kHz
88
fIN = 100 kHz
fIN = 2 kHz
90.8
90
87
90.5
fIN = 100 kHz
89.6
fIN = 2 kHz
–100
fIN = 100 kHz
–95
fIN = 2 kHz
105
fIN = 100 kHz
100
fIN_ADCA = 15 kHz at 10% FSR
fIN_ADCB = 25 kHz at 100% FSR
–115
dB
dB
dB
dB
dB
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PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INTERNAL REFERENCE BUFFER
GREFBUF Reference buffer gain
1.75
Reference buffer output offset
(VREFP_x - VREFIN)(1)
–1
Reference buffer output offset
temperature drift
Reference buffer output capacitor
1
10
Reference buffer output mismatch
(VREFP_A - VREFP_B)
CREFP_x
0
V/V
For specified performance, between
each pair of REFP_x and REFM_x
mV
µV/C
–500
±50
500
µV
7
10
27
µF
0.7 × DVDD
DVDD +0.3
V
V
DIGITAL INPUTS
VIH
High-level input voltage
VIL
Low-level intput voltage
VIH
High-level input voltage
VIL
Low-level intput voltage
DVDD > 2.3 V
DVDD ≤ 2.3 V
–0.3
0.3 × DVDD
0.8 × DVDD
DVDD +0.3
V
–0.3
0.2 × DVDD
V
0.8 × DVDD
DVDD
V
0
0.2 × DVDD
V
DIGITAL OUTPUTS
VOH
High-level output voltage
IOH = 500-µA source
VOL
Low-level output voltage
IOH = 500-µA sink
POWER SUPPLY
IAVDD
Analog supply current
PSRR
Power supply rejection ratio
(1)
AVDD = 5 V, fDATA = 2.048 MSPS
16.5
AVDD = 5 V, no conversion
9
100-mVp-p ripple on AVDD,
frequency < 100 kHz
70
20
mA
dB
REFP_x refers to the REFP_A and REFP_B reference pins for the ADC_A and ADC_B respectively.
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6.6 Timing Requirements
at AVDD = 4 V to 5.5 V, DVDD = 2.35 V to 5.5 V and maximum throughput (unless otherwise noted); minimum
and maximum values at TA = –40°C to +125°C; typical values at TA = 25°C, AVDD = 5 V and DVDD = 3.3 V
MIN
NOM
MAX
UNIT
CONVERSION CONTROL
tCycle
Cycle time
488
ns
fSample
Sampling rate
tACQ
Acquisition time
2048
tWH_CS
Pulse duration: CS high
15
ns
tWL_CS
Pulse duration: CS low
15
ns
tCYCLE - 160
kSPS
ns
SPI MODES
fCLK
Serial clock frequency
tCLK
Serial clock time period
tPH_CLK
SCLK high time
tPL_CLK
SCLK low time
32.768
MHz
0.45
0.55
tCLK
0.45
0.55
tCLK
1/ fCLK
tSU_CSCK
Setup time: CS faling to first SCLK capture edge
14
ns
tHT_CKCS
Delay time: last SCLK launch edge to CS rising
8
ns
6.7 Switching Characteristics
at AVDD = 4 V to 5.5 V, DVDD = 2.35 V to 5.5 V and maximum throughput (unless otherwise noted); minimum
and maximum values at TA = –40°C to +125°C; typical values at TA = 25°C, AVDD = 5 V and DVDD = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
422
ns
CONVERSION
tCONV
Conversion time
SPI MODES
8
tDEN_CSDO
Delay time: CS falling to data valid on SDO-x
14
ns
tDZ_CSDO
Delay time: CS rising edge to SDO-x tristate
13
ns
tD_CKDO
Delay time: SCLK launch edge to next data valid on
SDO-x
16
ns
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6.8 Timing Diagrams
Sample
µN¶
Sample
µN+1¶
tcycle
> tCONV
CAVDD
CREF_A
CS
SDO-0x
CREF_B
SCLK
Output Data ADCx
Sample µN¶
CDVDD
Output Data ADCx
SDO-1x
Sample µN¶
Figure 6-1. Conversion Control Latency-0 Data Capture
Sample
µN¶
Sample
µN+1¶
Sample
µN+2¶
tcycle
tWH_CS
tWL_CS
CAVDD
CREF_A
CS
tCLK
SDO-0x
SDO-1x
CREF_B
SCLK
Output Data ADCx
Sample µN-1¶
Output Data ADCx
Sample µN-1¶
Output Data ADCx
Sample µN¶
CDVDD
Output Data ADCx
Sample µN¶
Figure 6-2. Conversion Control Latency-1 Data Capture
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tCLK
tPL_CK
CS
tPH_CK
SCLK
tD_CKDO
tSU_CSCK
tHT_CKCS
SDO-xy
SCLK
tDEN_CSDO
tDZ_CSDO
SDO-xy
Figure 6-3. SPI-Compatible Serial Interface Timing
10
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6.9 Typical Characteristics
0
0
-40
-40
Magnitude (dB)
Magnitude (dB)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREFIN = 2.5 V, and fSample = 2.048 MSPS (unless otherwise noted)
-80
-120
-160
-120
-160
-200
-200
0
250
500
Frequency (kHz)
750
1000
0
250
D001
fIN = 100 kHz, SNR = 90.1 dB, THD = –99.3 dB
750
1000
D002
Figure 6-4. Typical FFT at fIN = 100 kHz
Figure 6-5. Typical FFT at fIN = 500 kHz
95
95
93
91
89
87
85
-50
0
50
100
Free-Air Temperature (°C)
93
91
89
87
85
-50
150
0
D004
fIN = 2 kHz
150
D005
Figure 6-7. SINAD vs Free-Air Temperature
94
-100
92
Signal-to-Noise Ratio (dB)
-98
-102
-104
-106
-108
-50
50
100
Free-Air Temperature (°C)
fIN = 2 kHz
Figure 6-6. SNR vs Free-Air Temperature
Total Harmonic Distortion Ratio (dB)
500
Frequency (kHz)
fIN = 500 kHz, SNR = 90 dB, THD = –90.9 dB
Signal-to-Noise+Distortion Ratio (dB)
Signal-to-Noise Ratio (dB)
-80
90
88
86
84
0
50
100
Free-Air Temperature (°C)
150
D006
0
250
500
Frequency (KHz)
750
1000
D007
fIN = 2 kHz
Figure 6-8. THD vs Free-Air Temperature
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Figure 6-9. SNR vs Input Frequency
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-85
Total Harmonic Distortion Ratio (dB)
Signal-to-Noise+Distortion Ratio (dB)
93
91
89
87
85
83
-89
-93
-97
-101
-105
0
250
500
Frequency (KHz)
750
1000
0
250
500
Frequency (KHz)
D008
Figure 6-10. SINAD vs Input Frequency
750
1000
D009
Figure 6-11. THD vs Input Frequency
2
45000
40000
1.2
Offset Error (LSB)
Number of Hits
35000
30000
25000
20000
15000
10000
0.4
-0.4
-1.2
5000
-2
-40
0
-4
-3
-2
-1
0
ADC Code
1
2
3
D010
-7
26
59
Free-Air Temperature (°C)
92
125
D031
Standard deviation = 0.65 LSB
Figure 6-13. Offset Error vs Free-Air Temperature
Figure 6-12. DC Input Histogram
0.01
1
Differential Nonlinearity (LSB)
Gain Error (%FSR)
0.005
0
-0.005
-0.01
-0.015
-0.02
-40
-7
26
59
Free-Air Temperature (°C)
92
125
D032
Figure 6-14. Gain Error vs Free-Air Temperature
12
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0.6
0.2
-0.2
-0.6
-1
-32768
-16384
0
ADC A Code
16384
32768
D022
Figure 6-15. Typical DNL ADC A
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1
2
0.6
1.2
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
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0.2
-0.2
-0.6
-1
-32768
-16384
0
ADC B Code
16384
0.4
-0.4
-1.2
-2
-32768
32768
-16384
D023
Figure 6-16. Typical DNL ADC B
0
ADC A Code
16384
32768
D024
Figure 6-17. Typical INL ADC A
2
1
Differential Nonlinearity (LSB)
Integral Nonlinearity (LSB)
DNL Max
DNL Min
1.2
0.4
-0.4
-1.2
-2
-32768
-16384
0
ADC B Code
16384
0.6
0.2
-0.2
-0.6
-1
-50
32768
0
D025
Figure 6-18. Typical INL ADC B
50
100
Free-Air Temperature (°C)
150
D026
Figure 6-19. DNL vs Free-Air Temperature
2
20
1.2
16
AVDD Current (mA)
Integral Nonlinearity (LSB)
INL Max
INL Min
0.4
-0.4
-1.2
-2
-50
12
8
4
0
0
50
100
Free-Air Temperature (°C)
150
D027
Figure 6-20. INL vs Free-Air Temperature
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0
512
1024
fsample (kSPS)
1536
2048
D028
Figure 6-21. Dynamic AVDD Current vs Sampling
Rate
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20
10
19
9
Static AVDD Current (mA)
Dynamic AVDD Current (mA)
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18
17
16
15
-50
0
50
100
Free-Air Temperature (°C)
150
D029
Figure 6-22. Dynamic AVDD Current vs Free-Air
Temperature
14
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8
7
6
5
-50
0
50
100
Free-Air Temperature (°C)
150
D030
Figure 6-23. Static AVDD Current vs Free-Air
Temperature
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7 Detailed Description
7.1 Overview
The ADS9226 is a 16-bit, dual-channel, high-speed, simultaneous-sampling, analog-to-digital converter (ADC).
The device supports pseudo-differential input signals and a full-scale range equal to 2 × VREFIN .
When a conversion is initiated, the difference between the AINP_x and AINM_x pins is sampled on the internal
capacitor array. The device uses an internal clock to perform conversions. During the conversion process, both
analog inputs are disconnected from the internal circuit. At the end of the conversion process, the device
reconnects the sampling capacitors to the AINP_x and AINM_x pins and enters an acquisition phase. The device
includes reference buffers to provide the charge required by the ADCs during conversion.
The device includes a traditional serial programming interface (SPI)-compatible serial interface to interface with a
variety of microcontrollers, digital signal processors (DSPs), and field-programmable gate arrays (FPGAs).
7.2 Functional Block Diagram
REFM_A
REFP_A
AVDD
REFIN
DVDD
REFBUF_A
AINP_A
CS
ADC_A
AINM_A
SCLK
AVDD
Serial
Interface
SDO-0A
AINP_B
ADC_B
SDO-1B
AINM_B
AVDD
REFBUF_B
REFM_B
REFP_B
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REFIN
GND
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7.3 Feature Description
From a functional perspective, the device is comprised of five modules: two converters (ADC_A, ADC_B), two
reference buffers (REFBUF_A, REFBUF_B), and the serial interface, as illustrated in Section 7.2.
The converter module samples and converts the analog input into an equivalent digital output code. The
reference buffers provide the charge required by the converters for the conversion process. The serial interface
module facilitates communication and data transfer between the device and the host controller.
7.3.1 Converter Modules
As shown in Figure 7-1, both converter modules sample the analog input signal (provided between the AINP_x
and AINM_x pins), compare this signal with the reference voltage (between the pair of REFP_x and REFM_x
pins), and generate an equivalent digital output code. The converter modules receive the CS input from the
interface module, and output the ADCST signal and the conversion result back to the interface module.
REFP_x
DVDD
AVDD
OSC
CS
SCLK
AINP_x
CONVST
Sampleand-Hold
Circuit
AINM_x
ADCST
SDO-0A
Interface
Module
Conversion
Result
SDO-1B
AGND
ADC_A
ADC_B
REFM_x
GND
Figure 7-1. Converter Modules
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7.3.1.1 Analog Input With Sample-and-Hold
This device supports unipolar, pseudo-differential analog input signals. Figure 7-2 shows a small-signal
equivalent circuit of the sample-and-hold circuit. Each sampling switch is represented by a resistance (RS1 and
RS2, typically 120 Ω) in series with an ideal switch (SW1 and SW2). The sampling capacitors, CS1 and CS2, are
typically 16 pF.
RS1
SW1
AINP_x
1 pF
CS1
AVDD
1 pF
CS2
GND
RS2
GND
SW2
AINM_x
Device in Hold Mode
Figure 7-2. Analog Input Structure for Converter Module
During the acquisition process, both inputs are individually sampled on CS1 and CS2, respectively. During the
conversion process, both converters convert for the respective voltage difference between the sampled values:
VAINP_x – VINM_x.
Equation 1 and Equation 2 provide the full-scale input range (FSR) and bias voltage (VBIAS) at the negative
input), supported at the analog inputs for the reference voltage (VREFIN ) on the REFIN pin.
FSR = ±VREFIN = 2 × VREFIN
(1)
VBIAS = VREFIN ± 0.1 V
(2)
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7.3.1.2 ADC Transfer Function
This device supports unipolar, pseudo-differential input signals. The device output is in two's complement format.
Figure 7-3 and Table 7-1 show the ideal transfer characteristics for the device. Equation 3 gives the least
significant bit (LSB) for the ADC.
1 LSB = FSR / 2n
(3)
where
•
•
FSR is defined in Equation 1
n = Resolution of the device
ADC Code (Hex)
PFSC
MC
NFSC
A
B
C
VIN
Analog Input
(AINP_x ± AINM_x)
Figure 7-3. Ideal Transfer Characteristics
Table 7-1. Transfer Characteristics
STEP
18
INPUT VOLTAGE
(AINP_x-AINM_x)
CODE
DESCRIPTION
IDEAL OUTPUT CODE
(R = 16)
A
≤ –(VREF – 0.5 LSB)
NFSC
Negative full-scale code
8000
B
– 0.5 LSB to 0.5 LSB
MC
Mid code
0000
C
≥ (VREF – 1.5 LSB)
PFSC
Positive full-scale code
7FFF
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7.3.2 External Reference Voltage
The device requires an external reference voltage of the value VREFIN , as specified in Section 6. Figure 7-4
shows the connections for using the device with an external reference. A reference without an integrated buffer
can be used because of the high input impedance of the REFIN pin.
AVDD
±
REFP_x
REFBUF_x
External
Reference
Voltage
+
CFLT
REFIN
CREFBUF
GND
REFM_x
Figure 7-4. Connection Diagram for Reference and Reference Buffers
7.3.3 Reference Buffers
On the CS rising edge, both converters start converting the sampled value on the analog input, and the internal
capacitors are switched to the REFP_x pins. Most of the switching charge required during the conversion
process is provided by the external decoupling capacitor CREFP_x. If the charge lost from CREFP_x is not
replenished before the next CS rising edge, the subsequent conversion occurs with this different reference
voltage and causes a proportional error in the output code. To eliminate these errors, the internal reference
buffers of the device maintains the voltage on the REFP_x pins.
All performance characteristics of the device are specified with the internal reference buffer and a specified value
of CREFP_x. As shown in Figure 7-4, place a decoupling capacitor CREFP_x between the REFP_x pins and the
REFM_x pin as close to the device as possible.
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7.4 Device Functional Modes
This device supports two functional states: acquisition phase (ACQ) and conversion phase (CNV).
7.4.1 ACQ State
In ACQ state, the device acquires the analog input signal. The device enters ACQ state at power-up, when
coming out of power down and by the ADCST signal (internal). A CS rising edge takes the device from ACQ
state to CNV state.
7.4.2 CNV State
The device moves from ACQ state to CNV state and starts conversion on a rising edge of the CS pin. The
conversion process uses an internal clock. The host must provide a minimum time of tCYCLE between two
subsequent start of conversions.
7.4.3 Output Data Word
The output data word consists of a conversion result of N bits where N = 16 for the ADS9226. The output data
word D[N-1:0], as shown in Figure 7-5, is left-justified and split into two data lines (SDO-xy) for each ADC.
SCLK
1
2
8
9
SDO-1x
D15
D13
D1
0
SDO-0x
D14
D12
D0
0
For ADC_A, x = A. For ADC_B, x = B.
Figure 7-5. Output Data Word
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7.4.4 Conversion Control and Data Transfer Frame
A data transfer frame starts with a falling edge of the CS signal. In any frame, the clocks provided on the SCLK
pin are used to transfer the output data for the completed conversion. The device has two SDOs (SDO-0x and
SDO-1x) for each ADC. For ADC_A, the device provides data on SDO-0A and SDO-1A, whereas for ADC_B,
the device provides data on SDO-0B and SDO-1B. The most significant bit (Dn-1x) of the output data is launched
on the SDO-1x pins and the MSB-1 (Dn-2x) bit is launched on the SDO-0x pins on the falling edge of CS, any
subsequent output bits are launched on the rising edges provided on SCLK. When all output bits of the
conversion result are shifted out, the device launches 0's on the subsequent SCLK rising edges. The data
transfer frame ends with a rising edge of the CS signal. For detailed timing specifications, see Section 6 and
Figure 7-6.
The CS pulse high time determines if the data being read back is with a 0 sample latency or a 1 sample latency.
See Figure 6-1 and Figure 6-2 for the respective timing diagrams. The maximum-rated sampling rate of 2.048
MSPS is achieved with a latency-1 data capture.
CS
SCLK
SDO-1x
DN-1 x
D1 x
SDO-0x
DN-2 x
D0 x
For ADC_A, x = A. For ADC_B, x = B.
Figure 7-6. Data Transfer Frame for Reading Data
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The two primary circuits required to maximize the performance of a high-precision, successive approximation
register (SAR) analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This
section presents general principles for designing these circuits, followed by an application circuit designed using
the ADS9226.
8.1.1 ADC Input Driver
The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and a chargekickback filter. The amplifier is used for signal conditioning of the input signal and the low output impedance of
the amplifier provides a buffer between the signal source and the switched-capacitor inputs of the ADC. The
charge-kickback filter helps attenuate the sampling charge injection from the switched-capacitor input stage of
the ADC, and band-limits the wideband noise contributed by the front-end circuit. Careful design of the front-end
circuit is critical to meet the linearity and noise performance of the ADS9226.
8.1.1.1 Charge-Kickback Filter
The charge-kickback filter is an RC filter at the input pins of the ADC that filters the broadband noise from the
front-end drive circuitry and attenuates the sampling charge injection from the switched-capacitor input stage of
the ADC. A filter capacitor, CFLT (as shown in Figure 8-1), is connected from each input pin of the ADC to
ground. This capacitor helps reduce the sampling charge injection and provides a charge bucket to quickly
charge the internal sample-and-hold capacitors during the acquisition process. Generally, the value of this
capacitor must be at least 20 times the specified value of the ADC sampling capacitance. For the ADS9226, the
input sampling capacitance is equal to 16 pF; therefore, for optimal performance, keep CFLT greater than 320 pF.
This capacitor must be a COG- or NPO-type. The type of dielectric used in COG or NPO ceramic capacitors
provides the most stable electrical properties over voltage, frequency, and temperature changes.
RFLT
CFLT
Device
RFLT
CFLT
Figure 8-1. Charge-Kickback Filter
Driving capacitive loads can degrade the phase margin of the input amplifier, thus making the amplifier
marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of
the amplifiers. A higher value of RFLT helps with amplifier stability, but adds distortion as a result of interactions
with the nonlinear input impedance of the ADC. Distortion increases with source impedance, input signal
frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability of the
driver amplifier and distortion performance of the design. Always verify the stability and settling behavior of the
driving amplifier and charge-kickback filter by TINA-TI™ SPICE simulation. Keep the tolerance of the selected
resistors less than 1% to keep the inputs balanced.
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8.1.2 Input Amplifier Selection
Selection criteria for the input amplifiers is highly dependent on the input signal type, as well as the performance
goals, of the data acquisition system. Some key amplifier specifications to consider when selecting an
appropriate amplifier to drive the inputs of the ADC are:
•
Small-signal bandwidth. Select the small-signal bandwidth of the input amplifiers to be as high as possible
after meeting the power budget of the system. Higher bandwidth reduces the closed-loop output impedance
of the amplifier, thus allowing the amplifier to more easily drive the ADC sample-and-hold capacitor and the
RC filter (the charge-kickback filter) at the inputs of the ADC. Higher bandwidth amplifiers offer faster settling
times when driving the capacitive load of the charge-kickback filter, thus reducing harmonic distortion at
higher input frequencies. Equation 4 describes the unity-gain bandwidth (UGB) of the amplifier to be selected
in order to maintain the overall stability of the input driver circuit:
§
·
1
UGB t 4 u ¨
¸
S
2
u
R
u
C
FLT
FLT ¹
©
•
Distortion. Both the ADC and the input driver introduce distortion in a data acquisition block. Equation 5
shows that to make sure that the distortion performance of the data acquisition system is not limited by the
front-end circuit, the distortion of the input driver must be at least 10 dB less than the distortion of the ADC:
THD AMP d THD ADC
•
(4)
10 dB
(5)
Noise. Noise contribution of the front-end amplifiers must be as low as possible to prevent any degradation in
SNR performance of the system. Generally, to make sure that the noise performance of the data acquisition
system is not limited by the front-end circuit, the total noise contribution from the front-end circuit must be
kept below 20% of the input-referred noise of the ADC. Equation 6 explains that noise from the input driver
circuit is band-limited by designing a low cutoff frequency, charge-kickback filter:
§ V 1 _ AM P_ PP ·
¨
¸
NG u 2 u ¨ f
¸¸
6.6
¨
©
¹
2
en2 _ RM S u
S
uf
2
3 dB
d
1 VREF
u
u 10
5
2
§ SNR dB ·
¨
¸
20
©
¹
(6)
where
•
– V1 / f_AMP_PP is the peak-to-peak flicker noise in μV
– en_RMS is the amplifier broadband noise density in nV/√ Hz
– f–3dB is the 3-dB bandwidth of the charge-kickback filter
– NG is the noise gain of the front-end circuit that is equal to 1 in a buffer configuration
Settling Time. For DC signals with fast transients that are common in a multiplexed application, the input
signal must settle within an 16-bit accuracy at the device inputs during the acquisition time window. This
condition is critical to maintain the overall linearity performance of the ADC. Settling accuracy for DC
transients directly translates to the linear performance for AC input signals, especially those that may use the
ADC full-scale range. Typically, amplifier data sheets specify the output settling performance only up to 0.1%
to 0.001%, which may not be sufficient for the desired 16-bit accuracy. Therefore, always verify the settling
behavior of the input driver by TINA-TI SPICE simulations before selecting the amplifier.
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8.2 Typical Application
AVDD
AVDD
REFIN / 2
+
OPA836
15.8 Ÿ
±
AINP_x
330 pF
1 kŸ
ADS9226
ADC_x
VIN
330 pF
AINM_x
1 kŸ
15.8 Ÿ
REFIN
Input Driver
Figure 8-2. Typical Connection Diagram of the ADS9226 Application Circuit
8.2.1 Design Requirements
The design parameters are listed in Table 8-1 for this example.
Table 8-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
ADC sample rate
2 MSPS
Analog input signal
2 kHz, ±2.5 V, pseudo-differential
SNR
> 87 dB
THD
< –100 dB
Power supply
5-V analog, 3.3-V digital
8.2.2 Detailed Design Procedure
Figure 8-2 shows an application circuit for this example. The device incorporates two independently matched
reference buffers for each ADC. Decouple the reference buffer outputs (the REFP_A and REFP_B pins) with the
REFM_A and REFM_B pins, respectively, with 10-µF decoupling capacitors. The circuit in Figure 8-2 shows a
pseudo-differential data acquisition (DAQ) block optimized for low distortion and noise using the OPA836 and the
ADS9226. The single-ended inputs are level-shifted and driven using a high-bandwidth, low-distortion,
operational amplifier configured with a gain of –1 V/V and an optimal RC charge-kickback filter before going to
the ADC. Generally, the distortion from the input driver must be at least 10 dB less than the ADC distortion.
Therefore, these circuits use the OPA836 as an input driver that provides exceptional AC performance because
of its extremely low-distortion and high bandwidth specifications. In addition, the components of the chargekickback filter are selected to keep the noise from the front-end circuit low without adding distortion.
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8.2.3 Application Curve
Figure 8-3 provides the typical FFT for the circuit shown in Figure 8-2.
0
Magnitude (dB)
-50
-100
-150
-200
1
2
3 4 5 67 10
20 30 50 70100
Frequency (kHz)
200
500 1000
D031
SNR = 89.9 dB, THD = –102.9 dB
Figure 8-3. Typical FFT With a 2-kHz Signal
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9 Power Supply Recommendations
The device has two separate power supplies: AVDD and DVDD. The reference buffers and converter modules
(ADC_A and ADC_B) operate on AVDD. The serial interface operates on DVDD. AVDD and DVDD can be
independently set to any value within their permissible ranges.
As shown in Figure 9-1, connect pins 12 and 29 together and place 1-µF decoupling capacitors between pin 12
(AVDD) and pin 11 (GND), and between pin 29 (AVDD) and pin 30 (GND). To decouple the DVDD supply, place
a 1-µF decoupling capacitor between pin 28 (DVDD) and pin 27 (GND), and between pin 26 (DVDD) and pin 27
(GND).
1 µF
1 µF
11
GND
12
AVDD
29
AVDD
30
REFIN
GND
AVDD
DVDD
REFBUF_A
AVDD
28
DVDD
1 µF
AINP_A
GND
27
1 µF
ADC_A
DVDD
AINM_A
26
Serial
Interface
AINP_B
ADC_B
AINM_B
AVDD
REFBUF_B
REFIN
AVDD
Figure 9-1. Power-Supply Decoupling
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10 Layout
10.1 Layout Guidelines
This section provides some layout guidelines for achieving optimum performance with the ADS9226.
10.1.1 Signal Path
Route the analog input signals in opposite directions to the digital connections. The reference decoupling
components are kept away from the switching digital signals. This arrangement prevents noise generated by
digital switching activity from coupling to sensitive analog signals.
10.1.2 Grounding and PCB Stack-Up
Low inductance grounding is critical for achieving optimum performance. Grounding inductance is kept below 1
nH with 15-mil grounding vias and a printed circuit board (PCB) layout design that has at least four layers. Place
all critical components of the signal chain on the top layer with a solid analog ground from subsequent inner
layers to minimize via length to ground.
10.1.3 Decoupling of Power Supplies
Place the decoupling capacitors on AVDD and DVDD within 20 mil from the respective pins, and use a 15-mil via
to ground from each capacitor. Avoid placing vias between any supply pin and the respective decoupling
capacitor.
10.1.4 Reference Decoupling
Dynamic currents are present at the REFP_x and REFM_x pins during the conversion phase, and excellent
decoupling is required to achieve optimum performance. Place a 10-µF, X7R-grade, ceramic capacitor with at
least a 10-V rating. Select 0603- or 0805-size capacitors to keep equivalent series inductance (ESL) low.
Connect the REFM_x pins to the decoupling capacitor before a ground via. Also place decoupling capacitors on
the REFby2 pin.
10.1.5 Analog Input Decoupling
Dynamic currents are also present at the pseudo-differential analog inputs of the ADS9226. Use C0G- or NPOtype capacitors to decouple these inputs because with these types of capacitors, capacitance stays almost
constant over the full input voltage range. Lower-quality capacitors (such as X5R and X7R) have large
capacitance changes over the full input-voltage range that may cause degradation in the performance of the
device.
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10.2 Layout Example
CDVDD
CAVDD
CREFP_A
RFILT
CDVDD
CFILT
RFILT
32
CFILT
25
1
24
ADS9226
CREFIN
8
17
9
16
CREFP_B
RFILT
CAVDD
CFILT
RFILT
CFILT
Figure 10-1. Example Layout for the ADS9226
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11 Device and Documentation Support
11.1 Related Documentation
For related documentation see the following:
• Texas Instruments, REF50xx Low-Noise, Very Low Drift, Precision Voltage Reference data sheet
• Texas Instruments, OPAx836 Very Low Power, Rail-ro-Rail Out Operational Amplifiers data sheet
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TINA-TI™ and TI E2E™ are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ADS9226IRHBR
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
ADS9226
ADS9226IRHBT
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
ADS9226
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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