ADS931

® ADS 931 E ADS931 8-Bit, 30MHz Sampling ANALOG-TO-DIGITAL CONVERTER TM FEATURES q +2.7V TO +5.5V SUPPLY OPERATION q LOW POWER: 69mW at +3V q ADJUSTABLE FULL SCALE RANGE WITH EXTERNAL REFERENCE q NO MISSING CODES q POWER DOWN q 28-LEAD SSOP PACKAGE DESCRIPTION The ADS931 is a high speed pipelined analog-todigital converter that is specified to operate from standard +5V or +3V power supplies. This converter includes a high bandwidth track/hold and an 8-bit quantizer. The performance is specified with a singleended input range of 1V to 2V when operating off of a +3V supply. This device also allows for standard input ranges such as 2V to 4V or 2V to 3V, when operating on +5V supplies. The full scale input range is set by an external reference. The ADS931 employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications. Its low distortion and high SNR give the extra margin needed for telecommunications, video and test instrumentation applications. This high performance A/D converter is specified for performance at a 30MHz sampling rate. The ADS931 is available in a 28-Lead SSOP package. CLK ADS931 Timing Circuitry LVDD APPLICATIONS q BATTERY POWERED EQUIPMENT q CAMCORDERS q PORTABLE TEST EQUIPMENT q DIGITAL CAMERAS q COMMUNICATIONS IN T/H Pipeline A/D Error Correction Logic 3-State Outputs 8-Bit Digital Data Reference Ladder REFT CM REFB Pwrdn OE International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1996 Burr-Brown Corporation PDS-1349C 1 Printed in U.S.A. March, 1998 ADS931 SPECIFICATIONS At TA = full specified temperature range unless otherwise noted. +VS = LVDD = +3V, specified single-ended input (1V to 2V) and sampling rate = 30MHz, unless otherwise specified. The input range is 2.25V to 3.25V when specified for +5V operation. ADS931E PARAMETER RESOLUTION SPECIFIED TEMPERATURE RANGE ANALOG INPUT Specified Full Scale Input Range(1) Common-mode Voltage Analog Input Bias Current Input Impedance DIGITAL INPUTS Logic Family High Input Voltage, VIH Low Input Voltage, VIL High Input Current, IIH Low Input Current, IIL Input Capacitance CONVERSION CHARACTERISTICS Start Conversion Sample Rate Data Latency DYNAMIC CHARACTERISTICS Differential Linearity Error f = 500MHz f = 12.5MHz No Missing Codes Integral Nonlinearity Error, f = 500kHz Spurious Free Dynamic Range(2) f = 500kHz (–1dBFS input) f = 12.5MHz (–1dBFS input) Two-Tone Intermodulation Distortion(4) f = 3.6MHz and 3.5MHz (–7dBFS each tone) Signal-to-Noise Ratio (SNR) f = 500kHz (–1dBFS input) f = 12.5MHz (–1dBFS input) Signal-to-(Noise + Distortion) (SINAD) f = 500kHz (–1dBFS input) f = 12.5MHz (–1dBFS input) Effective Number of Bits Differential Gain Error Differential Phase Error Output Noise Aperture Delay Time Aperture Jitter Analog Input Bandwidth Small Signal Full Power Overvoltage Recovery Time(6) DIGITAL OUTPUTS Logic Family Logic Coding High Output Voltage, VOH Low Output Voltage, VOL 3-State Enable Time 3-State Disable Time Internal Pull-Down Power-Down Enable Time Power-Down Disable Time Internal Pull-Down ACCURACY Gain Error Input Offset(7) Power Supply Rejection (Gain) External REFT Voltage Range External REFB Voltage Range Reference Input Resistance VS = +3V and +5V Ambient Air 1Vp-p +1.0 +1.5 1 1.25 || 5 TTL/HCT Compatible CMOS +2.0 ±10 ±10 5 Rising Edge of Convert Clock 10k 5 30M Samples/s Clk Cycles LVDD +0.8 V V µA µA pF CONDITIONS MIN TYP 8 –40 to +85 +2.0 MAX UNITS Bits °C V V µA MΩ || pF VS = +3V and +5V VS = +3V and +5V VS = +3V and +5V 43 ±0.7 ±0.7 Guaranteed ±1.0 49 49 54 ±1.0 LSB LSB LSB dBFS(3) dBFS dBFS dB dB dB dB Bits % degrees LSBs rms ns ps rms MHz MHz ns ±2.5 VS = +3V and +5V 44 VS = +3V and +5V 40 f = 12MHz(5) NTSC, PAL NTSC, PAL Input AC-Grounded 45 45 7.2 2.3 1 0.2 2 7 350 100 2 TTL/HCT Compatible CMOS Straight Offset Binary 2.4 OE = L OE = H Pwrdn = L Pwrdn = H VS = +3V and +5V Referred to Ideal Midscale ∆ VS = +10% 2.4 ±6.5 75 2 1 3.5 ±25 VS–0.8 REFT –0.5 4 %FS mV dB V V kΩ 20 2 50 133 18 50 VDD 0.4 40 10 V V ns ns kΩ ns ns kΩ 48 48 –20dBFS Input 0dBFS Input CL = 15pF 42 REFB +0.5 0.8 ® ADS931 2 SPECIFICATIONS (CONT) At TA = full specified temperature range unless otherwise noted. +VS = LVDD = +3V, specified single-ended input (1V to 2V) and sampling rate = 30MHz, unless otherwise specified. The input range is 2.25V to 3.25V when specified for +5V operation. ADS931E PARAMETER POWER SUPPLY REQUIREMENTS Supply Voltage: +VS Supply Current: +IS Power Dissipation Power Dissipation (Power Down) Thermal Resistance, θJA 28-Lead SSOP CONDITIONS MIN TYP MAX UNITS Operating VS = +3V VS = +3V VS = +5V VS = +3V VS = +5V +2.7 +3.0 23 69 154 10 15 50 +5.5 29 87 V mA mW mW mW mW ° C/W NOTES: (1) The single-ended input range is set by REFB and REFT values. (2) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (3) dBFS is dB relative to full scale. (4) Two-tone intermodulation distortion is referred to as the largest fundamental tone. (5) Based on (SINAD –1.76)/6.02. (6) No “Rollover” of bits. (7) Offset deviation from ideal negative full scale. ABSOLUTE MAXIMUM RATINGS +VS ....................................................................................................... +6V Analog Input ........................................................... (–0.3V) to (+VS +0.3V) Logic Input ............................................................. (–0.3V) to (+VS +0.3V) Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature ..................................................................... +150°C ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT ADS931E PACKAGE 28-Lead SSOP PACKAGE DRAWING NUMBER(1) 324 TEMPERATURE RANGE –40 °C to +85°C NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 ADS931 PIN CONFIGURATION Top View SSOP PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 DESIGNATOR +VS LVDD NC NC Bit 8 (LSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (MSB) GND GND CLK OE Pwrdn +VS GND GND LpBy REFT NC REFB LnBy CM IN +VS DESCRIPTION Analog Supply Output Logic Driver Supply Voltage No Connection No Connection Data Bit 8 (D7) LSB Data Bit 7 (D6) Data Bit 6 (D5) Data Bit 5 (D4) Data Bit 4 (D3) Data Bit 3 (D2) Data Bit 2 (D1) Data Bit 1 (D0) MSB Analog Ground Analog Ground Convert Clock Input Output Enable, Active Low Power Down Pin Analog Supply Analog Ground Analog Ground Positive Ladder Bypass Reference Voltage Top No Connection Reference Voltage Bottom Negative Ladder Bypass Common-Mode Pin Analog Input Analog Supply +VS LVDD NC NC Bit 8 (LSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (MSB) GND GND 1 2 3 4 5 6 7 ADS931 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 +VS IN CM LnBy REFB NC REFT LpBy GND GND +VS Pwrdn OE CLK TIMING DIAGRAM N+1 Analog In N tD Clock tCONV N+2 N+3 N+4 N+5 tL tH N+6 N+7 5 Clock Cycles t2 Data Out N–5 N–4 N–3 N–2 N–1 N t1 N+1 N+2 Data Invalid SYMBOL tCONV tL tH tD t1 t2 DESCRIPTION Convert Clock Period Clock Pulse Low Clock Pulse High Aperture Delay Data Hold Time, CL = 0pF New Data Delay Time, CL = 15pF max MIN 33 15.5 15.5 3.9 TYP MAX 100µs UNITS ns ns ns ns ns ns 16.5 16.5 2 12 ® ADS931 4 TYPICAL PERFORMANCE CURVES At TA = +25°C, VS = +3V, specified single-ended input (–1dBFS) and sampling rate = 30MHz, unless otherwise specified. SPECTRAL PERFORMANCE 0 fIN = 500kHz –20 Amplitude (dB) Amplitude (dB) SPECTRAL PERFORMANCE 0 fIN = 3.58MHz –20 –40 –40 –60 –60 –80 –80 –100 0 5 10 Frequency (MHz) 15 –100 0 5 10 Frequency (MHz) 15 SPECTRAL PERFORMANCE 0 fIN = 12.5MHz –20 Amplitude (dB) Amplitude (dB) SPECTRAL PERFORMANCE 0 –20 –40 –60 –80 –100 –120 fIN = 12.5MHz VS = +5V REFT = +3.25V REFB = +2.25V –40 –60 –80 –100 0 5 10 Frequency (MHz) 15 0 3 6 9 12 15 Frequency (MHz) UNDERSAMPLING PERFORMANCE 0 –20 Amplitude (dB) TWO-TONE INTERMODULATION 0 f1 = 3.6MHz at –7dB f2 = 3.5MHz at –7dB 2f1 – f2 55.7dBFS 2f2 – f1 54.6dBFS fIN = 20MHz fS = 16MHz Magnitude (dBFS) –20 –40 –60 –80 –100 –120 0 1.6 3.2 4.8 6.4 8.0 Frequency (MHz) –40 –60 –80 –100 0 2 4 6 8 10 Frequency (MHz) ® 5 ADS931 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = +3V, specified single-ended input (–1dBFS) and sampling rate = 30MHz, unless otherwise specified. DIFFERENTIAL LINEARITY ERROR 2.0 fIN = 500kHz 1.0 DLE (LSB) DLE (LSB) DIFFERENTIAL LINEARITY ERROR 2.0 fIN = 12.5MHz 1.0 0 0 –1.0 –1.0 –2.0 0 64 128 Output Code 192 256 –2.0 0 64 128 Output Code 192 256 INTEGRAL LINEARITY ERROR 4.0 fIN = 500kHz SWEPT POWER SFDR 100 dBFS SFDR (dBFS, dBc) 2.0 80 ILE (LSB) 60 0 40 –2.0 20 dBc –4.0 0 64 128 Output Code 192 256 0 –50 –40 –30 –20 –10 0 Input Amplitude (dBFS) DYNAMIC PERFORMANCE vs INPUT FREQUENCY 50 SFDR 0.7 0.9 DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE SFDR, SNR (dB) DLE (LSB) 48 0.5 SNR 46 0.3 fIN = 500kHz fIN = 12.5MHz 44 0.1 1 10 Frequency (MHz) 100 0.1 –50 –25 0 25 50 75 100 Temperature (°C) ® ADS931 6 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = +3V, specified single-ended input (–1dBFS) and sampling rate = 30MHz, unless otherwise specified. SPURIOUS FREE DYNAMIC RANGE (SFDR) vs TEMPERATURE 54 50 SIGNAL-TO-NOISE RATIO vs TEMPERATURE 52 fIN = 12.5MHz fIN = 12.5MHz 48 SFDR (dBFS) SNR (dB) 50 fIN = 500kHz 48 fIN = 500kHz 46 46 44 –50 –25 0 25 50 75 100 Temperature (°C) 44 –50 –25 0 25 50 75 100 Temperature (°C) POWER DISSIPATION vs TEMPERATURE 66 2.6 GAIN ERROR vs TEMPERATURE Gain Error (%FS) 64 Power (mW) 2.5 62 2.4 60 2.3 58 –50 –25 0 25 50 75 100 Temperature (°C) 2.2 –50 –25 0 25 50 75 100 Temperature (°C) OFFSET ERROR vs TEMPERATURE 9 12 10 8 Offset Error (mV) Counts (x 105) OUTPUT NOISE HISTOGRAM (DC Input) 8 6 4 2 7 6 5 –50 –25 0 25 50 75 100 Temperature (°C) 0 N–2 N–1 N Output Code N+1 N+2 ® 7 ADS931 THEORY OF OPERATION The ADS931 is a high speed sampling analog-to-digital converter that utilizes a pipeline architecture. The fully differential topology and digital error correction guarantee 8-bit resolution. The track/hold circuit is shown in Figure 1. The switches are controlled by an internal clock which has a non-overlapping two phase signal, φ1 and φ2. At the sampling time the input signal is sampled on the bottom plates of the input capacitors. In the next clock phase, φ2, the bottom plates of the input capacitors are connected together and the feedback capacitors are switched to the op amp output. At this time the charge redistributes between CI and CH, completing one track/hold cycle. The differential output is a held DC representation of the analog input at the sample time. In the normal mode of operation, the complementary input is tied to the common-mode voltage. In this case, the track/hold circuit converts a single-ended input signal into a fully differential signal for the quantizer. Consequently, the input signal gets amplified by a gain or two, which improves the signal-to-noise performance. Other parameters such as small-signal and full-power bandwidth, and wideband noise are also defined in this stage. Op Amp Bias φ1 VCM φ1 CH φ2 CI IN IN (Opt.) φ1 φ1 φ2 CI CH φ1 Input Clock (50%) Op Amp Bias Internal Non-overlapping Clock φ1 φ2 φ1 VCM φ1 φ1 OUT OUT φ2 FIGURE 1. Input Track/Hold Configuration with Timing Signals. IN Input T/H 2-Bit Flash STAGE 1 2-Bit DAC Digital Delay Σ x2 + – Digital Delay 2-Bit Flash STAGE 2 2-Bit DAC B1 (MSB) Digital Error Correction Σ x2 + – B2 B3 B4 B5 B6 B7 B8 (LSB) Digital Delay 2-Bit Flash STAGE 6 2-Bit DAC Σ x2 + – STAGE 7 2-Bit Flash Digital Delay FIGURE 2. Pipeline A/D Architecture. ® ADS931 8 The pipelined quantizer architecture has 7 stages with each stage containing a two-bit quantizer and a two bit digitalto-analog converter, as shown in Figure 2. Each two-bit quantizer stage converts on the edge of the sub-clock, which is the same frequency of the externally applied clock. The output of each quantizer is fed into its own delay line to time-align it with the data created from the subsequent quantizer stages. This aligned data is fed into a digital error correction circuit which can adjust the output data based on the information found on the redundant bits. This technique provides the ADS931 with excellent differential linearity and guarantees no missing codes at the 8-bit level. To accommodate a bipolar signal swing, the ADS931 operates with a common-mode voltage (VCM) which is derived from the external references. Due to the symmetric resistor ladder inside the ADS931, VCM is situated between the top and bottom reference voltage. Equation (1) can be used for calculating the common-mode voltage level. VCM = (REFT +REFB)/2 (1) of the converter will start to degrade due to large variations of the input’s switch ON resistance over the input voltage. Therefore, the signal swing should remain approximately 0.5V away from each rail during normal operation. DRIVING THE ANALOG INPUTS AC-COUPLED DRIVER Figure 3 shows an example of an ac-coupled, single-ended interface circuit using a high speed op amp which operates on dual supplies (OPA650, OPA658). The mid-point reference voltage, (VCM), biases the bipolar, ground-referenced input signal. The capacitor C1 and resistor R1 form a highpass filter with the –3dB frequency set at f–3dB = 1/(2 π R1 C1) (2) The values for C1 and R1 are not critical in most applications and can be set freely. The values shown in Figure 3 correspond to a corner frequency of 1.6kHz. +VS +5V VIN OPA65x R1 1kΩ VCM 402Ω C1 RS 50Ω 0.1µF IN ADS931 CM At the same time, the two external reference voltage levels define the full-scale input range for the ADS931. This makes it possible for the input range to be adapted to the signal swing of the front end. APPLICATIONS SIGNAL SWING AND COMMON-MODE CONSIDERATIONS The ADS931 is primarily designed and specified for a +3V single supply voltage. However, due to its supply range of +2.7V to +5.25V, it is well suited for +5V applications. The nominal input signal swing is 1Vp-p, situated between +1V and +2V. This means that the signal swings ±0.5V around a common-mode voltage of +1.5V when using a 3V rail, or typically +2.75V on a 5V supply. In some applications, it might be advantageous to increase the input signal swing. For example, increasing it to 2Vp-p may improve the achievable signal-to-noise performance. However, consideration should be given to keeping the signal swing within the linear range of operation of the driving circuitry to avoid any excessive distortion. In extreme situations, the performance +5V C1 0.1µF VIN OPA680 R1 1kΩ RS 50Ω –5V 402Ω 0.1µF FIGURE 3. AC-Coupled, Single-Ended Interface Circuit. Figure 4 depicts a circuit that can be used in single-supply applications. The mid-reference voltage biases the op amp up to the appropriate common-mode voltage, for example VCM = +1.5V. With the use of capacitor CG, the DC gain for the non-inverting op amp input is set to +1V/V. As a result, the transfer function is modified to VOUT = VIN {(1 + RF/RG) + VCM} +5V (3) IN 22pF VCM ADS931 CM RF 402Ω RG 402Ω CG 0.1µF NOTE: (1) See text for discussion. RP(1) 402Ω 0.1µF FIGURE 4. +5V Single-Supply Interface Circuit Example Using the Voltage Feedback Amplifier OPA680. ® 9 ADS931 Again, the input coupling capacitor C1 and resistor R1 form a high-pass filter. At the same time, the input impedance is defined by R1. Although many high-speed op amps operate on single supply voltages down to +3V, their ac-performance is often lower when compared to their +5V acperformance. This is especially true at signal frequencies of 5MHz or higher, where noticeable degradation is exhibited that will limit the performance of the system. If possible, the op amp and A/D converter pair should be supplied with +5V and the common-mode voltage set to +2.5V, which is usually the preferred dc bias level for single-supply op amps. Keeping the signal swing within 1Vp-p prevents the op amp from exhibiting excessive distortion caused by its slew-rate limitations. Depending on the selected amplifier, the use of a pull-up or pull-down resistor (RP) located directly at its output may considerably improve the distortion performance. Resistor RS isolates the op amp’s output from the capacitive load to avoid gain peaking or even oscillation. It can also be used to establish a defined bandwidth in order to roll off the high frequency noise. The value of RS is usually set between 10Ω and 100Ω. DC-COUPLED INTERFACE CIRCUIT Shown in Figure 5 is a single-supply, DC-coupled circuit which can be set in a gain of –1V/V or higher. Depending on the gain, the divider ratio set by resistors R1 and R2 must be adjusted to yield the correct common-mode voltage for the ADS931. With a +3V supply, the input signal of the ADS931 is 1Vp-p, typically centered around the common-mode voltage of +1.5V, which can be derived from the external references. EXTERNAL REFERENCE The ADS931 requires external references on pin 22 (REFT) and pin 24 (REFB). Internally those pins are connected by the resistor ladder, which has a nominal resistance of 4kΩ (±15%). In order to establish a correct voltage drop across the ladder, the external reference circuit must be able to supply typically 250µA of current. With this current the fullscale input range of the ADS931 is set between +1V and +2V, or 1Vp-p. In general, the voltage drop across REFT and REFB determines the input full-scale range (FSR) of the ADS931. Equation (4) can be used to calculate the span. FSR = REFT – REFB (4) Depending on the application, several options are possible to supply the external reference voltages to the ADS931 without degrading the typical performance. LOW-COST SOLUTION The easiest way to achieve the required reference voltages is to place the reference ladder of the ADS931 between the supply rails, as shown in Figure 6. Two additional resistors (RT, RB) are necessary to set the correct current through the ladder. The table in Figure 6 lists the value for several possible configurations, however depending on the desired full-scale swing and supply voltage, different resistor values might be selected. The trade-offs, when selecting this reference circuit, are the variations in the reference voltages due to component tolerances, temperature drift and power supply variations. In any case, it is recommended to bypass the reference ladder with at least 0.1µF ceramic capacitors, as shown in Figure 6. The purpose of the capacitors is twofold. They will bypass most of the high frequency noise which results from feedthrough of the clock and switching noise from the sample and hold stages. Secondly, they serve as a charge reservoir to supply instantaneous current to internal nodes. HIGH ACCURACY SOLUTION For those application demanding a higher level of dc accuracy and drift a reference circuit with a precision reference element might be used (see Figure 7). A stable +1.2V +5V RF RIN VIN A1 RS IN 22pF CM R1 0.1µF C2 R2 REFB REFT ADS931 External Top Reference 2kΩ RCM1 2kΩ RCM2 External Bottom Reference FIGURE 5. Single-Ended, DC-Coupled Interface Circuit. ® ADS931 10 +3V 10µF 0.1µF RT 4kΩ +VS 0.1µF VIN 2kΩ +1.5V 0.1µF CM 1kΩ LnBy +VS 3V 5V 5V 5V RT 4kΩ 12kΩ 8kΩ 3kΩ RB 4kΩ 12kΩ 8kΩ 3kΩ REFT REFB 2V 2V 3V 3.5V 1V 1V 2V 1.5V 1kΩ REFB 0.1µF RB 4kΩ 0.1µF IN 1kΩ ADS931 1kΩ LpBy 0.1µF REFT 0.1µF FIGURE 6. Low-cost Solution to Supply External Reference Voltages. +VS 10Ω +VS 1/2 A1 RF1 10kΩ RG1 REF1004 +1.2V 5kΩ Top Reference 3kΩ 1/2 A1 10Ω Bottom Reference RF2 RG2 FIGURE 7. High Accuracy Solution to Supply External Reference Voltages. reference voltage is established by a two terminal bandgap reference diode, the REF1004-1.2. Using a general-purpose single-supply dual operational amplifier (A1), like an OPA2237, OPA2234 or MC34072, the two required reference voltages for the ADS931 can be generated by setting each op amp to the appropriate gain; for example: set REFT to +2V and REFB to +1V. CLOCK INPUT The clock input of the ADS931 is designed to accommodate either +3V or +5V CMOS logic levels. To drive the clock input with a minimum amount of duty cycle variation and support the maximum sampling rate (30MSPS), high speed or advanced CMOS logic should be used (HC/HCT, AC/ACT). When digitizing at high sampling rates, a 50% ® 11 ADS931 duty cycle, along with fast rise and fall times (2ns or less), are recommended to meet the rated performance specifications. However, the ADS931 performance is tolerant to duty cycle variations of as much as ±10%, which should not affect the performance. For applications operating with input frequencies up to Nyquist (fCLK/2) or undersampling applications, special consideration must be made to provide a clock with very low jitter. Clock jitter leads to aperture jitter (tA) which can be the ultimate limitation to achieving good SNR performance. Equation (5) shows the relationship between aperture jitter, input frequency and the signal-tonoise ratio: SNR = 20log10 [1/(2 π fIN tA)] DIGITAL OUTPUTS The digital outputs of the ADS931 are standard CMOS stages and designed to be compatible to both high speed TTL and CMOS logic families. The logic thresholds are for low-voltage CMOS: VOL = 0.4V, VOH = 2.4V, which allows the ADS931 to directly interface to 3V logic. The digital output driver of the ADS931 uses a dedicated digital supply pin (pin 2, LVDD), see Figure 8. By adjusting the voltage on LVDD, the digital output levels will vary respectively. It is recommended to limit the fan-out to one in order to keep the capacitive loading on the data lines below the specified 15pF. If necessary, external buffers or latches may be used to provide the added benefit of isolating the A/D converter from any digital activities on the bus coupling back high frequency noise, which degrades the performance. STRAIGHT OFFSET BINARY (SOB) PIN 12 FLOATING or LO 11111111 11111111 11111110 11100000 11000000 10100000 10000001 10000000 01111111 01100000 01000000 00100000 00000001 00000000 +VS +LVDD ADS931 Digital Output Stage FIGURE 8. Independent Supply Connection for Output Stage. During power-down, the digital outputs are set in 3-state. With the clock applied, the converter does not accurately process the sampled signal. After removing the power-down condition, the output data from the following 5 clock cycles is invalid (data latency). DECOUPLING AND GROUNDING CONSIDERATIONS The ADS931 has several supply pins, one of which is dedicated to supply only the output driver (LVDD). The remaining supply pins are not divided into analog and digital supply pins (+VS) since they are internally connected on the chip. For this reason, it is recommended that the converter be treated as an analog component and to power it only from the analog supply. Digital supply lines often carry high levels of noise which can couple back into the converter and limit performance. Because of the pipeline architecture, the converter also generates high frequency transients and noise that are fed back into the supply and reference lines. This requires that the supply and reference pins be sufficiently bypassed. Figure 9 shows the recommended decoupling scheme for the analog supplies. In most cases, 0.1µF ceramic chip capacitors are adequate to keep the impedance low over a wide frequency range. Their effectiveness largely depends on the proximity to the individual supply pin. Therefore, they should be located as close as possible to the supply pins. In addition, one larger bipolar capacitor (1µF to 22µF) should be placed on the PC board in proximity of the converter circuit. (5) SINGLE-ENDED INPUT +FS (IN = REFT Voltage) +FS –1LSB +FS –2LSB +3/4 Full Scale +1/2 Full Scale +1/4 Full Scale +1LSB Bipolar Zero (IN +1.5V) –1LSB –1/4 Full Scale –1/2 Full Scale –3/4 Full Scale –FS +1LSB –FS (IN = REFB Voltage) TABLE I. Coding Table for the ADS931. +VS 1 GND 13 14 ADS931 +VS 18 GND 19 20 +VS 28 POWER-DOWN MODE The ADS931’s low power consumption can be reduced even further by initiating a power-down mode. For this, the Power Down pin (pin 17) must be tied to a logic “High” reducing the current drawn from the supply by approximately 84%. In normal operation, the power-down mode is disabled by an internal pull-down resistor (50kΩ). 0.1µF 0.1µF 0.1µF FIGURE 9. Recommended Bypassing for Analog Supply Pins. ® ADS931 12