AFE1115E

® AFE 111 5 ® AFE1115 HDSL/MDSL ANALOG FRONT END WITH VCXO FEATURES q COMPLETE HDSL ANALOG INTERFACE q E1, T1 AND MDSL OPERATION q VCXO AND VCXO CONTROL CIRCUITRY q +5V ONLY (5V or 3.3V Digital) q SCALEABLE DATA RATE q 300mW POWER DISSIPATION q 56-PIN SSOP DESCRIPTION Burr-Brown’s Analog Front End greatly reduces the size and cost of an HDSL (High bit rate Digital Subscriber Line) system by providing all of the active analog circuitry needed to connect an HDSL digital signal processor to an external compromise hybrid and a HDSL line transformer. The transmit and receive filter responses automatically change with clock frequency—allowing the AFE1115 to operate over a range of data rates from 196kbps to 1.168Mbps. Functionally, this unit consists of a transmit and a receive section with a VCXO (Voltage Controlled vcDATA vcSCLK vcLE VCXO DAC Oscillator Crystal Oscillator) control DAC and VCXO circuitry. The transmit section generates, filters, and buffers outgoing 2B1Q data. The receive section filters and digitizes the symbol data received on the telephone line. Data to the VCXO and symbol data are sent to the AFE1115 via two serial interfaces; the receive data is available as a 14-bit parallel word. This IC operates on a single 5V supply. The digital circuitry in the unit can be connected to a supply from 3.3V to 5V. It is housed in a small 56-pin SSOP package. vcDAC VCXO Output VCXO Input VCXO Output Clock Pulse Former Filter Output Buffer txLINE+ txLINE– PLLOUT PLLIN txDATA+ txSCLK txCLK rxSYNC rxLOOP 2 rxGAIN Delta-Sigma Modulator 14 rxDATA Decimation Filter Receive Control Transmit Control Voltage Reference REFP VCM REFN rxLINE+ rxLINE– rxHYB+ rxHYB– International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1997 Burr-Brown Corporation PDS-1384 1 AFE1115 Printed in U.S.A. July, 1997 SPECIFICATIONS Typical at 25°C, AVDD = +5V, DVDD = +3.3V, ftx = 584kHz (E1 rate), unless otherwise specified. AFE1115E PARAMETER RECEIVE CHANNEL Number of Inputs Input Voltage Range Common-Mode Voltage Input Impedance All Inputs Input Capacitance Input Gain Matching Resolution Programmable Gain Settling Time for Gain Change Gain + Offset Error Output Data Coding Output Data Rate, rxSYNC(3) TRANSMIT CHANNEL Transmit Clock Rate, ftx T1 Transmit –3dB Point T1 Rate Power(4, 5) E1 Transmit –3dB Point E1 Transmit Power(4, 5) Pulse Output Common-Mode Voltage, VCM Output Resistance(6) TRANSCEIVER PERFORMANCE Uncancelled Echo(7) COMMENTS Differential Balanced Differential(1) MIN 2 ±3.0 +2.5 See Typical Performance Curves 10 ±2 14 –3 +9 6 5 98 Symbol Rate Bellcore TA-NWT-3017 Compliant See Test Method Section ETSI RTR/TM-03036 Compliant See Test Method Section 98 196 13 292 13 14 See Typical Performance Curves AVDD/2 1 –67 –67 –71 –73 8 Positive Full Scale Output Negative Full Scale Output See VCXO Circuit and Layout Section 4.5 0.5 14 584 584 V V pF % Bits dB Symbol Periods %FSR(2) kHz kHz kHz dBm kHz dBm V Ω dB dB dB dB Bits V V TYP MAX UNITS Line Input vs Hybrid Input Three Gains: –3dB, 3dB, and 9dB Tested at Each Gain Range Two’s Complement DC to 1MHz rxGAIN = –3dB, Loopback Enabled rxGAIN = –3dB, Loopback Disabled rxGAIN = 3dB, Loopback Disabled rxGAIN = 9dB, Loopback Disabled VCXO VCXO VCXO VCXO VCXO PERFORMANCE Control DAC Resolution Control DAC Output Control DAC Output Performance DIGITAL INTERFACE(6) Logic Levels VIH VIL VOH VOL POWER Analog Power Supply Voltage Analog Power Supply Voltage Digital Power Supply Voltage Digital Power Supply Voltage Power Dissipation(4, 5, 8) Power Dissipation(4, 5, 8) PSRR TEMPERATURE RANGE Operating(6) |IIH| < 10µA |IIL| < 10µA IOH = –20µA IOL = 20µA Specification Operating Range Specification Operating Range AVDD = 5V, DVDD = 3.3V, AVDD = DVDD = 5V DVDD –1 –0.3 DVDD –0.5 DVDD +0.3 +0.8 +0.4 5 V V V V V V V V mW mW dB °C 4.75 3.3 3.15 300 350 60 –40 5.25 5.25 +85 NOTES: (1) With a balanced differential signal, the positive input is 180° out of phase with the negative input, therefore the actual voltage swing about the commonmode voltage on each pin is ±1.5V to achieve a total input range of ±3.0V or 6Vp-p. (2) FSR is Full-Scale Range. (3) The output data is available at twice the symbol rate with interpolated values. (4) With a pseudo-random equiprobable sequence of HDSL pulses; 13.5dBm applied to the transformer (16.5dBm output from txLINEP and txLINEN). (5) See the Test Method section of this data sheet for more information. (6) Guaranteed by design and characterization. (7) Uncancelled Echo is a measure of the total analog errors in the transmitter and receiver sections including the effect of non-linearity and noise. See the Discussion of Specifications sections of this data sheet for more information. (8) Power dissipation includes only the power dissipated with in the component and does not include power dissipated in the external loads. See the Discussion of Specifications section for more information. ® AFE1115 2 PIN CONFIGURATION PACKAGE/ORDERING INFORMATION PACKAGE DRAWING NUMBER(1) 346 TEMPERATURE RANGE –40° C to +85°C PRODUCT PACKAGE 56-Pin Plastic SSOP vcOUT vcINP vcCLK DVDD Unused Pin Unused Pin txCLK txSCLK txDATA rxDATA0 rxDATA1 rxDATA2 rxDATA3 rxDATA4 rxDATA5 GNDD DVDD rxDATA6 rxDATA7 rxDATA8 rxDATA9 rxDATA10 rxDATA11 rxDATA12 rxDATA13 Unused Pin rxSYNC rxGAIN0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 AFE1115E 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 DGND AFE1115E vcSCLK vcDATA vcLATCH PLLIN PLLOUT AVDD AGND AGND vcDAC AGND txLINE+ AVDD txLINE– AGND AVDD vrREF VCM vrREF AGND AGND rxLINE+ rxLINE– rxHYB+ rxHYB– AVDD rxLOOP rxGAIN1 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ® 3 AFE1115 PIN DESCRIPTIONS PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 TYPE Output Input Output Power NC NC Input Input Input Output Output Output Output Output Output Ground Power Output Output Output Output Output Output Output Output NC Input Input Input Input Power Input Input Input Input Ground Ground Output Output Output Power Ground Output Power Output Ground Output Ground Ground Power Output Input Input Input Input Ground NAME vcOUT vcINP vcCLK DVDD Unused Pin Unused Pin txCLK txSCLK txDATA rxDATA0 rxDATA1 rxDATA2 rxDATA3 rxDATA4 rxDATA5 GNDD DVDD rxDATA6 rxDATA7 rxDATA8 rxDATA9 rxDATA10 rxDATA11 rxDATA12 rxDATA13 Unused Pin rxSYNC rxGAIN0 rxGAIN1 rxLOOP AVDD rxHYB– rxHYB+ rxLINE– rxLINE+ AGND AGND vrREFP VCM vrREFN AVDD AGND txLINE– AVDD txLINE+ AGND vcDAC AGND AGND AVDD PLLOUT PLLIN vcLATCH vcDATA vcSCLK DGND DESCRIPTION VCXO Output VCXO Input VCXO Output Clock Digital Supply (+3.3 to +5V) Transmit Baud Clock (XMTLE signal) (1168kHz for E1) Transmit Serial Clock Transmit Data Input ADC Output Bit-0 ADC Output Bit-1 ADC Output Bit-2 ADC Output Bit-3 ADC Output Bit-4 ADC Output Bit-5 Digital Ground Digital Supply (+3.3 to +5V) ADC Output Bit-6 ADC Output Bit-7 ADC Output Bit-8 ADC Output Bit-9 ADC Output Bit-10 ADC Output Bit-11 ADC Output Bit-12 ADC Output Bit-13 (DVDD may be connected for pinout compatibility with AFE1105) ADC Sync Signal (392kHz for T1, 584kHz for E1) Receive Gain Control Bit-0 Receive Gain Control Bit-1 Loopback Control Signal (loopback is enabled by positive signal) Analog Supply (+5V) Negative Input from Hybrid Network Positive Input from Hybrid Network Negative Line Input Positive Line Input Analog Ground Analog Ground Positive Reference Output Common-mode Voltage (buffered) Negative Reference Output Analog Supply (+5V) Analog Ground Negative Line Output Analog Supply (+5V) Positive Line Output Analog Ground VCXO Control Analog Ground PLL Ground PLL Supply PLL Filter Output PLL Filter Input VCXO Control Latch Enable VCXO Control Data VCXO Control Serial Clock Digital Ground The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® AFE1115 4 TYPICAL PERFORMANCE CURVES At Output of Pulse Transformer The curves shown below are measured at the line output of the HDSL transformer. Typical at 25°C, AVDD = +5V, DVDD = +3.3V, unless otherwise specified. POWER SPECTRAL DENSITY LIMIT –20 Power Spectral Density (dBm/Hz) –38dBm/Hz for T1 –40 –40dBm/Hz for E1 –60 –80dB/decade T1 E1 –118dBm/Hz for T1 –120dBm/Hz for E1 –80 196kHz –100 292kHz –120 1K 10K 100K Frequency (Hz) 1M 10M CURVE 1. Upper Bound of Power Spectral Density Measured at Output of HDSL Transformer. 0.4T 0.4T B = 1.07 C = 1.00 D = 0.93 NORMALIZED LEVEL A B C D E F G H 0.01 1.07 1.00 0.93 0.03 –0.01 –0.16 –0.05 QUATERNARY SYMBOLS +3 0.0264 2.8248 2.6400 2.4552 0.0792 –0.0264 –0.4224 –0.1320 +1 0.0088 0.9416 0.8800 0.8184 0.0264 –0.0088 –0.1408 –0.0440 –1 –0.0088 –0.9416 –0.8800 –0.8184 –0.0264 0.0088 0.1408 0.0440 –3 –0.0264 –2.8248 –2.6400 –2.4552 –0.0792 0.0264 0.4224 0.1320 DON'T DELETE TABLE UNTIL KNOWN IF TEEPLE IS LEAVING IT IN? 1.25T A = 0.01 F = –0.01 –1.2T –0.6T 0.5T E = 0.03 H = –0.05 14T A = 0.01 F = –0.01 50T G = –0.16 CURVE 2. Transmitted Pulse Template and Actual Performance as Measured at Transformer Output. INPUT IMPEDANCE vs BIT RATE 200 Input Impedance (kΩ) 150 100 T1 = 784kbps, 45kΩ 50 E1 = 1168kbps, 30kΩ 0 100 300 500 700 Bit Rate (kbps) 900 1100 1300 CURVE 3. Input Impedance of rxLINE and rxHYB. ® 5 AFE1115 THEORY OF OPERATION The transmit channel consists of a switched-capacitor pulse forming network followed by a differential line driver. The pulse forming network receives symbol data through a serial interface and generates a standard 2B1Q output waveform. The output meets the pulse mask and power spectral density requirements defined in European Telecommunications Standards Institute document RTR/TM-03036 for E1 mode and in sections 6.2.1 and 6.2.2.1 of Bellcore technical advisory TA-NWT-001210 for T1 mode. The differential line driver uses a composite output stage combining class B operation (for high efficiency driving large signals) with class AB operation (to minimize crossover distortion). The receive channel is designed around a fourth-order delta sigma A/D converter. It includes a difference amplifier designed to be used with an external compromise hybrid for first order analog echo cancellation. A programmable gain amplifier with gains of –3dB to +9dB is also included. The delta sigma modulator operating at a 24X oversampling ratio produces a parallel 14-bit output at symbol rates up to 584kHz. The basic functionality of the AFE1115 is illustrated in Figure 1 shown below. The receive channel operates by summing the two differential inputs, one from the line (rxLINE) and the other from the compromise hybrid (rxHYB). These two inputs are connected so that the hybrid signal is subtracted from the line signal. This connection is described in the paragraph titled “Echo Cancellation in the AFE”. The equivalent gain for each input in the difference amp is one. The resulting signal then passes to a programmable gain amplifier which can be set for gains of –3dB through +9dB. The ADC converts the signal to a 14-bit digital word, rxD13-rxD0. An independent VCXO control DAC and VCXO circuitry is also included on the chip. This VCXO is designed to be used in remote units for clock recovery. The VCXO is formed with the on-board circuitry plus external crystal and varactor diodes. The VCXO control DAC receives control data through a serial interface which sets a voltage level at the output of the DAC. The DAC output controls the frequency of the VCXO. To achieve specified analog performance when using the VCXO, the crystal frequency of the VCXO must be 48x the baud rate. rxLOOP INPUT rxLOOP is the loopback control signal. When enabled, the rxLINE+ and rxLINE– inputs are disconnected from the AFE. The rxHYB+ and rxHYB– inputs remain connected. Loopback is enabled by applying a positive signal (Logic 1) to rxLOOP. ECHO CANCELLATION IN THE AFE The rxHYB input is designed to be subtracted from the rxLINE input for first order echo cancellation. To accomplish this, note that the rxLINE input is connected to the same polarity signal at the transformer (positive to positive and negative to negative) while the rxHYB input is connected to opposite polarity through the compromise hybrid (negative to positive and positive to negative) as shown in Figure 2. RECEIVE DATA CODING The data from the receive channel A/D converter is coded in two’s complement. ANALOG INPUT Positive Full Scale Mid Scale Negative Full Scale OUTPUT CODE (rxDATA) 01111111111111 00000000000000 10000000000000 vcDATA vcSCLK vcLE VCXO DAC VCXO vcDAC VCXO Output VCXO Input VCXO Output Clock Transformer Switched Capacitor Pulse Former Line Driver Telephone Wire Pair DSP PLL Hybrid ∆Σ ADC Digital Filter AFE1115 Programmable Gain Amp Difference Amplifier FIGURE 1. Functional Block Diagram of AFE1115 Circuit. ® AFE1115 6 0.1µF txPLLOUT 1kΩ txPLLIN Parasitic Capacitance Must be Minimized at These Points. DVDD 68.1kΩ BB809 68.1kΩ 150pF 68.1kΩ vcDAC, 47 0.1µF VCXO Input, 2 150pF VCXO Output, 1 1kΩ 200Ω 0.1µF REFP VCM REFN 0.1µF 0.1µF VCXO Output Clock, 3 vcDATA vcSCLK vcLE txLINEP 0.01µF txLINEN Input Antialias Filter fc ≅ 2xSymbol Rate 750Ω 1:2.3 Transformer Tip Ring – Compromise Hybrid – + + 0.01µF txDAT txCLK rxSYNC rxGAIN rxLOOP rxG1 rxD13 AFE1115 rxHYB+ 100pF 750Ω rxHYB– 750Ω PGND DGND AGND AGND AGND AGND DVDD 5V to 3.3V Digital 0.1µF 0.1µF 0.1µF AVDD AVDD AVDD rxLINE– 100pF 750Ω rxLINE+ AVDD 5V Analog 0.1µF 0.1µF 1 - 10µF 5 - 10Ω resistor may be needed for isolation FIGURE 2. Basic Connection Diagram. RECEIVE CHANNEL PROGRAMMABLE GAIN AMPLIFIER The gain of the amplifier at the input of the Receive Channel is set by two gain control pins, rxGAIN1 and rxGAIN0. The resulting gain between –3dB and +9dB is shown below. rxGAIN1 0 0 1 rxGAIN0 0 1 0 GAIN –3dB +3dB +9dB SCALEABLE DATA RATE The AFE1115 scales operation with the clock frequency. All internal filters and the pulse former change frequency with the clock speed so that the unit can be used at different frequencies just by changing the clock speed. rxHYB AND rxLINE INPUT ANTI-ALIASING FILTERS An external input anti-aliasing filter is needed on the hybrid and line inputs as shown in the Basic Connection Diagram above. The –3dB frequency of the input anti-aliasing filter for the rxLINE and rxHYB differential inputs should be approximately 1MHz for E1 and T1 symbol rates. Suggested values for the filter are 750Ω for each of the two input resistors and 100pF for the capacitor. Together the two 750Ω resistors and the 100pF capacitor result in a 3dB frequency of just over 1MHz. The 750Ω input resistors will result in a minimal voltage divider loss with the input impedance of the AFE1115. For speed less than E1, the anti-aliasing filters will give best performance with 3dB frequency approximately equal to two times the symbol rate. For instance, a 3dB frequency of 400kHz may be used for a single line symbol rate of 196k symbols per second. ® 7 AFE1115 rxHYB AND rxLINE INPUT COMMON-MODE OPTIONAL VOLTAGE The AFE1115 will meet specifications with the application circuit shown in the Basic Connection Diagram (Figure 2) above. However, slightly improved performance may be obtained with the Hybrid input (rxHYB) and the Line input (rxLINE) set to a common mode voltage of 1.5V. The negative reference output pin (vrREFN, pin 40) provides a good 1.5V level to use to set the common-mode voltage. The circuit shown in Figure 3 can be used to set the common-mode voltage of the Line input to 1.5V. A similar circuit can be used to set the Hybrid input to 1.5V. Another option for the Hybrid input is to design the external compromise hybrid so that the signal into the rsHYB inputs is centered at 1.5V. If the compromise hybrid circuit is AC coupled to the rxHYB inputs, an external pull-up resistor to vrREFN may be needed to center the input at 1.5V. 375Ω rxLINE– 2kΩ to vrREFN (1.5V) 2kΩ 375Ω rxLINE+ 0.1µF to Line 0.1µF AFE 100pF FIGURE 3. Optional rxLINE Input Common-mode Voltage Control. TRANSMIT DATA TIMING t1 txSCLK (tx serial clock) t2 txCLK (baud clock) t6 txDATA (tx data input) MSB Bit 1 t8 t9 Bit 2 Bit 3 LSB Bit 16 t7 t3 t4 t5 VCXO CONTROL TIMING t1 vcSCLK (serial clock) t2 vcLE (latch enable) t6 vcDATA (data) MSB Bit 1 t8 t9 Bit 2 Bit 3 LSB Bit 16 t7 t3 t4 t5 SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t9 DESCRIPTION Serial Clock Period Serial Clock LOW Serial Clock HIGH Delay of 16th clock rising edge to falling edge of txCLK or vcLE Dealy of txCLK or vcLE to the next rising edge of Serial Clock txCLK or vcLE HIGH txCLK or vcLE LOW DATA setup time DATA hold time MIN 35 15 15 10 10 15 15 10 10 TYP MAX UNITS ns ns ns ns ns ns ns ns ns FIGURE 4. Timing Diagram. ® AFE1115 8 TRANSMIT SYMBOL DATA During each symbol period transmit symbol data are sent to the AFE1115 in serial format through the txDATA input pin. A 16 bit word is sent to the AFE1115 to determine the symbol that is transmitted by the AFE1115. The symbol data is contained in the first three bits of the data, the remaining 13 bits of the 16 bit word are ignored. The most significant bit (MSB) is the transmit enable bit. When the MSB is a logic 0, a zero symbol only is transmitted regardless of the state of the other two bits. When the MSB is a logic 1, bits 2 and 3 determine the symbol transmitted as shown in the table below. MSB - BIT 1 0 1 1 1 1 BIT 2 X 1 1 0 0 BIT 3 X 1 0 1 0 2B1Q SYMBOL O +3 +1 –1 –3 VCXO CONTROL D/A CONVERTER DATA During each symbol period VCXO control D/A converter data is sent to the AFE1115 in serial format through the vcDATA input pin. A 16 bit word is sent to the AFE1115 to determine the output of the VCXO control D/A converter. The VCXO control D/A converter is connected to the VCXO circuit to control the VCXO frequency. The D/A converter input is contained in the first eight bits of the data, the remaining eight bits of the 16 bit word are ignored. INPUT CODE (vcDATA) MSB 01111111XXXXXXXX 00000000XXXXXXXX 10000000XXXXXXXX ANALOG OUTPUT Negative Full Scale (+0.5V) Mid Scale (+2.5V) Positive Full Scale (+4.5V) TABLE II. VCXO Control DAC Output. X = Don’t Care. TABLE I. Transmit Symbol Data (txDATA). X = Don’t Care. RECEIVE TIMING t16 T = one symbol period txCLK t15 t10 rxSYNC t11 t12 rxDATA Data 1 t14 t14 t13 Data 1a t14 t14 Data 2 NOTES: (1) rxSYNC can shift to one of 48 discrete delay times from the leading edge of txCLK. (2) Timing is valid for load capacitance of 10pF or less. (3) It is recommended that rxDATA is read on the rising edge of rxSYNC. (4) Data 1a is an interpolated value between Data 1 and Data 2. FIGURE 5. Receive Timing Diagram. PARAMETER t10 t11 t12 t13 t14 t15 t16 DESCRIPTION rxSYNC Pulse Width Delay of rxSYNC from rising edge of txCLK, n = 0 to 47 Nominal Time at Which rxDATA Changes from Data 1 to Data 1a Nominal Time at Which rxDATA Changes from Data 1a to Data 2 Uncertainty of t12 and t13 txCLK Pulse Width Symbol Period, T T/16 1.7 MIN T/24 nT/48 – T/96 (n + 1.5) T/48 (n + 25.5) T/48 20 15T/16 10.2 µs ns nT/48 + T/96 TYP MAX VALUE TABLE III. Receive Timing (n = Delay Increments from txCLK). ® 9 AFE1115 RECEIVE TIMING The rxSYNC signal controls portions of the A/D converter’s decimation filter and the data output timing of the A/D converter. It is generated at the symbol rate by the user and must be synchronized with txCLK. The leading edge of rxSYNC can occur at the leading edge of txCLK or it can be shifted by the user in increments of 1/48 of a symbol period to one of 47 discrete delay times after the leading edge of txCLK. The bandwidth of the A/D converter decimation filter is equal to one half of the symbol rate. The A/D converter data output rate is 2X the symbol rate. The specifications of the AFE1115 assume that one A/D converter output is used per symbol period and the other output is ignored. The Receive Timing Diagram above suggests using the rxSYNC pulse to read the first data output in a symbol period. Either data output may be used. Both data outputs may be used for more flexible post-processing. Symbol sequences are generated by the tester and applied both to the AFE and to the input of an adaptive filter. The output of the adaptive filter is subtracted from the AFE output to form the uncancelled echo signal. Once the filter taps have converged, the RMS value of the uncancelled echo is calculated. Since there is no far-end signal source or additive line noise, the uncancelled echo contains only noise and linearity errors generated in the transmitter and receiver. The data sheet value for uncancelled echo is the ratio of the RMS uncancelled echo (referred to the receiver input through the receiver gain) to the nominal transmitted signal (13.5dBm into 135Ω, or 1.74Vrms). This echo value is measured under a variety of conditions: with loopback enabled (line input disabled); with loopback disabled under all receiver gain ranges; and with the line shorted (S1 closed in Figure 6). POWER DISSIPATION Approximately 75% of the power dissipation in the AFE1115 is in the analog circuitry, and this component does not change with clock frequency. However, the power dissipation in the digital circuitry does decrease with lower clock frequency. In addition, the power dissipation in the digital section is decreased with operation from a smaller supply voltage, such as 3.3V. (The analog supply, must remain in the range 4.75V to 5.25V.) The power dissipation listed in the specifications section applies under these normal operating conditions: 5V Analog Power Supply; 3.3V Digital Power Supply; E1 baud rate; DISCUSSION OF SPECIFICATIONS UNCANCELLED ECHO The key measure of transceiver performance is uncancelled echo. This measurement is made as shown in the diagram of Figure 6 and the measurement is made as follows. The AFE is connected to an output circuit including a typical 1:2.3 line transformer. The line is simulated by a 135Ω resistor. Transmit Data 11.6Ω txDATP txLINEP 11.6Ω txLINEN 1.5kΩ rxHYBP 3kΩ 1:2 5.6Ω 135Ω S1 5.6Ω 100pF AFE1115 Adaptive Filter rxHYBN 1.5Ω 750Ω rxLINEP 100pF rxLINEN 750Ω Uncancelled Echo rxD13 - rxD0 FIGURE 6. Uncancelled Echo Test Diagram. ® AFE1115 10 13.5dBm delivered to the line; and a pseudo-random equiprobable sequence of HDSL pulses. The power dissipation specifications includes all power dissipated in the AFE1115, it does not include power dissipated in the external load. The external power is 16.5dBm, 13.5dBm to the line and 13.5dBm to the impedance matching resistors. The external load power of 16.5dBm is 45mW. The typical power dissipation in the AFE1115 under various conditions is shown in TYPICAL POWER DISSIPATION IN THE AFE1115 (mW) 300 350 290 330 280 300 sible. The placement of the Tantalum capacitor is not as critical, but should be close to the pin. In each case, the capacitor should be connected between AVDD and AGND (pins 49 and 50). The capacitors should be placed in quiet analog areas rather than noisy digital areas. In most systems, it will be natural to derive AVDD for the phase-locked loop (PLL) from the AVDD supply. A 5Ω to 10Ω resistor should be used to connect PLL AVDD (pin 49) to the analog supply. This resistor in combination with the 10µF capacitor form a lowpass filter—keeping glitches on the analog supply from affecting the phase locked loop. Ideally, the phase-locked loop power supply would originate from the analog supply (via the 5Ω to 10Ω resistor) near the power connector for the printed circuit board. Likewise, the PLL ground should connect to a large PCB trace or small ground plane which returns to the power supply connector underneath the PLL AVDD supply path. The PLL “ground plane” should also extend underneath PLLIN and PLLOUT (pins 51 and 52). The remaining portion of the AFE1115 should be considered analog. The four non-PLL AGND pins (pins 36, 37, 42, and 46) should be connected directly to a common analog ground plane and all non-PLL AVDD pins should be connected to an analog 5V power plane. Both of these planes should have a low impedance path to the power supply. Ideally, all ground planes and traces and all power planes and traces should return to the power supply connector before being connected together (if necessary). Each ground and power pair should be routed over each other, should not overlap any portion of another pair, and the pairs should be separated by a distance of at least 0.25 inch (6mm). One exception is that the digital and analog ground planes should be connected together underneath the AFE1115 by a small trace. BIT RATE PER AFE1115 (Symbols/sec) 1168 (E1) 1168 (E1) 784 (T1) 784 (T1) 292 (1/4 E1) 292 (1/4 E1) DVDD (V) 3.3 5 3.3 5 3.3 5 TABLE IV. Typical Power Dissipation. Table IV. LAYOUT The analog front end of an HDSL system has a number of conflicting requirements. It must accept and deliver digital outputs at fairly high rates of speed, generate a VCXO clock, phase-lock to a high-speed digital clock, and convert the line input to a high-precision (14-bit) digital output. Thus, there are really four sections of the AFE1115: the digital section, the phase-locked loop, the VCXO and the analog section. DIGITAL LAYOUT The power supply for the digital section of the AFE1115 can range from 3.3V to 5V. This supply should be decoupled to digital ground with a ceramic 0.1µF capacitor placed as close as possible to digital ground (DGND, pin 16) and digital power (DVDD, pin 17). Ideally, both a digital power supply plane and a digital ground plane should run to and underneath the digital pins of the AFE1115 (pins 7 through 30). However, DVDD may be supplied by a wide printed circuit board trance. A digital ground plane underneath all digital pins is strongly recommended. The VCXO circuit needs special attention for layout. There is a portion of the external VCXO circuitry which needs to be as far away as possible from a ground or power plane or other traces. See the discussion below in the section titled VCXO Circuit and Layout. ANALOG LAYOUT The phase-locked loop is powered from AVDD (pin 50) and its ground is referenced to AGND (pin 49). Note that AVDD must be in the 4.75V to 5.25V range. This portion of the AFE1115 should be decoupled with both 10µF Tantalum capacitor and a 0.1µF ceramic capacitor. The ceramic capacitor should be placed as close to the AFE1115 as pos- VCXO CIRCUIT AND LAYOUT The VCXO circuitry is shown in Figure 7. The basic VCXO circuit consists of on-chip control DAC, amplifiers, Schmidt triggers, and clock buffer along with an external crystal and varactor diodes. The control DAC output (vcDAC) varies the capacitance of the varactor diodes (D1 and D2), which controls the frequency at which the crystal circuit oscillates. The buffered clock output is available at pin 3, VCXO Clock Output. Important Note: To achieve specified analog performance when using VCXO, the crystal frequency of the VCXO must be 48x the baud rate. In addition, the txCLK and the rxSYNC control signals must be derived from the VCXO clock so that the edges of the control signal are synchronized with the 48x crystal frequency. If these recommendations are followed, the key internal analog decisions are made at the time of minimum noise. As an example, for an E1 rate of 1168kbps, the symbol rate is 584k symbols per second. In this case the VCXO crystal frequency should be 48 x 584k = 28.032MHz. Likewise, for T1, the crystal frequency should be 18.816MHz. ® 11 AFE1115 The performance of the VCXO is critically dependent on the external components and printed circuit board layout that is used. The varactor diodes and the crystal are particularly important components. The printed circuit board layout containing the two varactor diodes, D1 and D2, in the VCXO external circuitry is critical to the performance of the VCXO. In particular, the two connection points of the varactor diodes shown in the Figure 7 must have very low parasitic capacitance to ground to achieve the best tuning range possible. To achieve lowest parasitic capacitance to ground, there must be no ground plane or other PCB traces near these two points. Ground planes and other traces should be kept 1 cm away from these two points where possible. Figure 8 shows an example of a printed circuit board layout of the sensitive VCXO circuitry for the circuit shown in Figure 7. There should be no ground planes, power planes or other traces in the white area indicated around the two sensitive points. The balance of the circuit board should be covered by ground planes where possible. With the circuit shown in Figure 7, these typical specifications were achieved. Pull Range at 20MHz Frequency Range of Crystal that can be used Crystal Frequency ±125ppm 10MHz to 28MHz 48x baud rate Parasitic capacitance must be minimized at these points. No other traces or ground plane should be inside the dotted box. DVDD D2 D1 68.1kΩ R4 68.1kΩ 150pF R5 68.1kΩ R2 AFE1115 VCXO Input, 2 150pF VCXO Output, 1 RL vcDAC, 47 0.1µF Buffered VCXO Clock Output RL = 1kΩ for 5V Operation RL = 600Ω for 3.3V Operation D1 = D2 = Philips Semiconductor BB809 VCXO Clock Output, 3 FIGURE 7. VCXO Circuitry. No ground/power planes or other traces in this area Sensitive Points 68.1k Ground Plane To AFE1115 Pin #47 68.1k To AFE1115 Pin #2 FIGURE 8. VCXO Circuit Layout, Approximately Two Times Actual Size. ® AFE1115 12 XTAL