®
AFE
AFE1124
112
E
4
FEATURES
● SERIAL DIGITAL INTERFACE
● 28-PIN SSOP
● E1, T1 AND MDSL OPERATION
DESCRIPTION
ET
HDSL/MDSL ANALOG FRONT END
● 64kbps TO 1168kbps OPERATION
● SCALEABLE DATA RATE
● 250mW POWER DISSIPATION
● COMPLETE HDSL ANALOG INTERFACE
● +5V POWER (5V or 3.3V Digital)
Functionally, this unit consists of a transmit and a
receive section. The transmit section generates analog
signals from 2-bit digital symbol data and filters the
analog signals to create 2B1Q symbols. The on board
differential line driver provides a 13.5dBm signal to
the telephone line. The receive section filters and
digitizes the symbol data received on the telephone
line. This IC operates on a single 5V supply. The
digital circuitry in the unit can be connected to a
supply from 3.3V to 5V. It is housed in a 28-pin SSOP
package.
SO
L
Burr-Brown’s Analog Front End chip greatly reduces
the size and cost of an xDSL (Digital Subscriber Line)
system by providing all of the active analog circuitry
needed to connect a digital signal processor to an
external compromise hybrid and line transformer. The
AFE1124 is optimized for HDSL (High bit rate DSL)
and for lower speed MDSL (Medium speed DSL) and
RADSL (Rate Adaptive DSL) applications. Because
the transmit and receive filter responses automatically
change with clock frequency, the AFE1124 is particularly suitable for RADSL and multiple rate DSL systems. The device operates over a wide range of data
rates from 64kbps to 1168kbps.
txLINE
OB
Pulse Former
tx and rx
Interface
Lines
txLINE
Line Driver
tx and rx
Control
Registers
Difference
Amplifier
Decimation
Filter
rxHYB
∆Σ
Modulator
rxLINE
Programmable
Gain Amp
AFE1124
rxHYB
rxLINE
Patents Pending
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
®
©
SBWS006
1997 Burr-Brown Corporation
PDS-1425A
1
AFE1124
Printed in U.S.A. October, 1997
SPECIFICATIONS
Typical at 25°C, AVDD = +5V, DVDD = +3.3V, ftx = 584kHz (E1 rate), unless otherwise noted.
AFE1124E
TRANSMIT CHANNEL
Transmit Clock Rate, ftx
T1 Transmit –3dB Point
T1 Rate Power(4, 5)
E1 Transmit –3dB Point
E1 Transmit Power(4, 5)
Pulse Output
Common-Mode Voltage, VCM
Output Resistance(6)
Differential
Balanced Differential(1)
2
Line Input vs Hybrid Input
0dB, 3dB, 6dB, 9dB and 12dB
Tested at Each Gain Range
Two’s Complement
32
64
Symbol Rate
ETSI RTR/TM – Compliant
See Test Method Section, txBoost = 0
ETSI RTR/TM – Compliant
See Test Method Section, txBoost = 0
DC to 1MHz
32
MAX
UNITS
V
V
pF
%
Bits
dB
Symbol Periods
%FSR(2)
|IIH| < 10µA
|IIL| < 10µA
IOH = –20µA
IOL = 20µA
13
584
kHz
kHz
dBm
kHz
dBm
14
13
14
See Typical Performance Curves
AVDD /2
1
–71
–71
–74
–76
–78
–80
DVDD +0.3
+0.8
V
V
V
V
ns
5.25
V
V
V
V
mW
mW
dB
+85
°C
5.25
3.3
3.15
–40
dB
dB
dB
dB
dB
dB
5
4.75
V
Ω
–68.5
–68.5
–71
–73.5
–75.5
–77.5
+0.4
14
9
TEMPERATURE RANGE
Operating(6)
kHz
kbits/sec
292
DVDD –1
–0.3
DVDD –0.5
Specification
Operating Range
Specification
Operating Range
AVDD = 5V, DVDD = 3.3V,
AVDD = DVDD = 5V
584
1168
196
rxGAIN = 0dB, Loopback Enabled
rxGAIN = 0dB, Loopback Disabled
rxGAIN = 3dB, Loopback Disabled
rxGAIN = 6dB, Loopback Disabled
rxGAIN = 9dB, Loopback Disabled
rxGAIN = 12dB, Loopback Disabled
DIGITAL INTERFACE(6)
Logic Levels
VIH
VIL
VOH
VOL
trx1 Interface
POWER
Analog Power Supply Voltage
Analog Power Supply Voltage
Digital Power Supply Voltage
Digital Power Supply Voltage
Power Dissipation(4, 5)
Power Dissipation(4, 5)
PSRR
TYP
±3.0
AVDD/2
See Typical Performance Curves
10
±2
14
0
+12
6
5
SO
L
TRANSCEIVER PERFORMANCE
Uncancelled Echo(5)
MIN
ET
RECEIVE CHANNEL
Number of Inputs
Input Voltage Range
Common-Mode Voltage
Input Impedance All Inputs
Input Capacitance
Input Gain Matching
Resolution
Programmable Gain
Settling Time for Gain Change
Gain + Offset Error
Output Data Coding
Output Symbol Rate, rxSYNC(3)
Output Bit Rate, rxSYNC(3)
COMMENTS
E
PARAMETER
250
300
55
OB
NOTES: (1) With a balanced differential signal, the positive input is 180° out of phase with the negative input, therefore the actual voltage swing about the commonmode voltage on each pin is ±1.5V to achieve a total input range of ±3.0V or 6Vp-p. (2) FSR is Full-Scale Range. (3) The output data is available at twice the symbol
rate with interpolated values. (4) With a pseudo-random equiprobable sequence of HDSL pulses; 13.5dBm applied to the transformer (16.5dBm output from txLINEP
and txLINEN). (5) See the Discussion of Specifications section of this data sheet for more information. (6) Guaranteed by design and characterization.
®
AFE1124
2
PIN CONFIGURATION
PACKAGE/ORDERING INFORMATION
1
28
NC
NC
2
27
AGND
DVDD
3
26
txLINE+
DGND
4
25
AVDD
txbaudCLK
5
24
txLIKNE–
tx48xCLK
6
23
AGND
Data In
7
22
AVDD
AFE1124
PACKAGE
AFE1124E
28-Pin SSOP
324
TEMPERATURE
RANGE
–40 to +85
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
E
NC
PRODUCT
PACKAGE
DRAWING
NUMBER(1)
ABSOLUTE MAXIMUM RATINGS
8
21
vrREFN
rx48xCLK
9
20
VCM
Data Out
10
19
vrREFP
DVDD
11
18
AGND
DGND
12
17
rxLINE+
AVDD
13
16
rxLINE–
rxHYB–
14
15
rxHYB+
ET
rxbaudCLK
Analog Inputs: Current .............................................. ±100mA, Momentary
±10mA, Continuous
Voltage .................................. AGND –0.3V to AVDD +0.3V
Analog Outputs Short Circuit to Ground (+25°C) ..................... Continuous
AVDD to AGND ........................................................................ –0.3V to 6V
DVDD to DGND ........................................................................ –0.3V to 6V
Digital Input Voltage to DGND .................................. –0.3V to DVDD +0.3V
Digital Output Voltage to DGND ............................... –0.3V to DVDD +0.3V
AGND, DGND, Differential Voltage ..................................................... 0.3V
Junction Temperature (TJ) ............................................................. +150°C
Storage Temperature Range .......................................... –40°C to +125°C
Lead Temperature (soldering, 3s) .................................................. +260°C
Power Dissipation .......................................................................... 700mW
ELECTROSTATIC
DISCHARGE SENSITIVITY
SO
L
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
OB
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
3
AFE1124
PIN DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
No Connection
No Connection
Power
Ground
Input
Input
Input
Input
Input
Output
Power
Ground
Power
Input
Input
Input
Input
Ground
Output
Output
Output
Power
Ground
Output
Power
Output
Ground
No Connection
NC
NC
DVDD
DGND
txbaudCLK
tx48xCLK
Data In
rxbaudCLK
rx48xCLK
Data Out
DVDD
DGND
AVDD
rxHYB–
rxHYB+
rxLINE–
rxLINE+
AGND
vrREFP
VCM
vrREFN
AVDD
AGND
txLINE–
AVDD
txLINE+
AGND
NC
DESCRIPTION
Digital Supply (+3.3 to +5V)
Digital Ground
Transmit Baud Clock (584kHz for E1)
Transmit Clock at 48x baud clock (28.032MHz for E1)
Input Data Word
Receive baud clock (584kHz for E1)
Receive clock at 48x baud clock (28.032MHz for E1)
Output Data Word
Digital Supply (+3.3 to +5V)
Digital Ground
Analog Supply (+5V)
Negative input from hybrid network
Positive input from hybrid network
Negative line input
Positive line input
Analog Ground
Positive reference output
Common-mode voltage (buffered)
Negative reference output
Analog Supply (+5V)
Analog Ground
Negative line output
Output buffer supply (+5V)
Positive line output
Output buffer ground
E
NAME
ET
TYPE
SO
L
PIN #
BLOCK DIAGRAM
Pulse
Former
Filter
Output
Buffer
txbaudCLK
tx48xCLK
Voltage
Reference
Transmit
Control
txLINE+
txLINE–
REFP
VCM
REFN
OB
Data In
rxbaudCLK
rx48xCLK
Receive
Control
rxLINE+
Data Out
∆Σ
Modulator
rxHYB+
rxHYB–
Decimation
Filter
®
AFE1124
rxLINE–
4
TYPICAL PERFORMANCE CURVES
At Output of HDSL Pulse Transformer
The curves shown below are measured at the line output of the HDSL transformer. Typical at 25°C, AVDD+ = +5V, DVDD+ = +3.3V, fTX = 1168kHz, unless otherwise specified.
POWER SPECTRAL DENSITY LIMIT
–40
E
–38dBm/Hz for T1
–80dB/decade
T1
–40dBm/Hz for E1
E1
–60
–80
196kHz
292kHz
–118dBm/Hz
for T1
ET
Power Spectral Density (dBm/Hz)
–20
–120dBm/Hz
for E1
–100
–120
1K
10K
1M
100K
10M
Frequency (Hz)
CURVE 1. Upper Bound of Power Spectral Density Measured at Output of HDSL Transformer.
0.4T 0.4T
SO
L
B = 1.07
C = 1.00
D = 0.93
1.25T
A = 0.01
E = 0.03
F = –0.01
–1.2T
–0.6T
A = 0.01
H = –0.05
14T
G = –0.16
0.5T
F = –0.01
50T
Input Impedance (kΩ)
OB
CURVE 2. Transmitted Pulse Template Measured at HDSL Transformer Output.
INPUT IMPEDANCE vs BIT RATE
200
150
100
T1 = 784kbps,
32kΩ
50
E1 = 1168kbps,
21kΩ
0
100
300
700
500
900
1100
1300
Bit Rate (kbps)
CURVE 3. Input Impedance of rxLINE and rxHYB.
®
5
AFE1124
THEORY OF OPERATION
compromise hybrid (rxHYB). The connection of these two
inputs so that the hybrid signal is subtracted from the line
signal is described in the paragraph titled “Echo Cancellation in the AFE”. The equivalent gain for each input in the
difference amp is one. The resulting signal then passes to a
programmable gain amplifier which can be set for gains of
0dB through +12dB. Following the PGA, the ADC converts
the signal to a 14-bit digital word.
E
The AFE1124 consists of a transmit and a receive channel.
It interfaces to the HDSL DSP through a six wire serial
interface, three wires for the transmit channel and three
wires for the receive channel. It interfaces to the HDSL
telephone line transformer and external compromise hybrid
through transmit and receive analog connections.
The serial interface consists of three wires for transmit and
three wires for receive. The three wire transmit interface is
transmit baud rate clock, transmit 48x oversampling clock
and Data Out. The three wire receive interface is receive
baud rate clock, receive 48x oversampling clock and Data
In. The transmit and receive clocks are supplied to the
AFE1124 from the DSP and are completely independent.
The receive channel is designed around a fourth-order delta
sigma A/D converter. It includes a difference amplifier
designed to be used with an external compromise hybrid for
first order analog echo cancellation. A programmable gain
amplifier with gains of 0dB to +12dB is also included. The
delta sigma modulator operating at a 24X oversampling ratio
produces a 14-bit output at rates up to 584kHz (1.168Mbps).
The receive channel operates by summing the two differential inputs, one from the line (rxLINE) and the other from the
DIGITAL DATA INTERFACE
ET
The transmit channel consists of a switched-capacitor pulse
forming network followed by a differential line driver. The
pulse forming network receives 2-bit digital symbol data and
generates a filtered 2B1Q analog output waveform. The
differential line driver uses a composite output stage combining class B operation (for high efficiency driving large
signals) with class AB operation (to minimize crossover
distortion).
Data is received by the AFE1124 from the DSP on the Data
In line. Data is transmitted from the AFE1124 to the DSP on
the Data Out line. The paragraphs below describe the timing
of these signals and data structure.
SO
L
Data is transmitted and received in synchronization with the
48x transmit and receive clocks (tx48xCLK and rx48xCLK).
There are 48-bit times in each baud period. Data In is
rxbaudCLK
rx48xCLK
Data Out
HDSL
DSP
AFE1124
txbaudCLK
tx48xCLK
Data In
FIGURE 1. DSP Interface.
4ns
4ns
txbaudCLK
from DSP
OB
A
4ns
tx48xCLK
from DSP
B
4ns
48
Data In
from DSP
1
2
3
4
MSB
Bit 15
15
16
LSB
Bit 0
47
48
1
MSB
Bit 15
Transmit Timing Notes: (1) A baud period consists of 48 periods of the tx48xCLK. (2) The falling edge of the txbaudCLK
can occur anywhere in area A. The rising edge can occur anywhere in area B. However, neither edge of the txbaudCLK
can occur within 4ns (on either side) of any rising edge of tx48xCLK. (3) The AFE1124 reads Data In on the rising edge
of the tx48xCLK. Data In must be stable at least 4ns before the rising edge of tx48xCLK and it must remain stable at
least 4ns after the rising edge of tx48CLK. (4) Symbol data is transferred to the transmit pulse former after the LSB is
read. The output analog symbol data reaches the peak of the symbol approximately 24 tx48xCLK periods later.
FIGURE 2. Transmit Timing Diagram.
®
AFE1124
6
received in the first 16 bits of each baud period. The
remaining 32-bit periods are not used for Data In. Data Out
is transmitted during the first 16 bits of the baud period. A
second interpolated value is transmitted in subsequent bits of
the baud period.
be valid on the rising edge of the tx48xCLK. The AFE1124
reads Data In on the rising edge of the tx48xCLK. The bits
are defined in Table I. Data In is read by the AFE1124
during the first 16 bits periods of each baud period. Only the
first 8 bits are used in the AFE1124. The second 8 bits are
reserved for use in the future products. The remaining 32
bits periods of the baud period are not used for Data In.
txbaudCLK: The transmit data baud rate, generated by the
DSP. It is 392kHz for T1 or 584kHz for E1. It may vary from
32kHz (64kbps) to 584kHz (1.168Mbps).
E
Data In Bits:
tx enable signal—This bit controls the tx Symbol definition
bits. If this bit is 0, only a 0 symbol is transmitted regardless
of the state of the tx Symbol definition bits. If this bit is 1,
the tx Symbol definition bits determine the output symbol.
Data In: This is a 16-bit output data word sent from the DSP
to the AFE. The sixteen bits include tx symbol information
and other control bits, as described below. The data should
be clocked out of the DSP on the falling edge and it should
tx Symbol Definition—These two bits determine the output
2B1Q symbol transmitted.
MSB
1
ET
tx48xCLK: The transmit pulse former oversampling sampling clock, generated by the DSP. It is 48x the transmit
symbol rate or 28.032MHz for 584kHz symbol rate. This
clock should run continuously.
Rx Gain Settings—These bits set the gain of the receive
channel programmable gain amplifier.
LSB
2
3
1
1
8
SO
L
Reserved
tx Boost
Loopback
rx Gain
tx Symbol
tx Enable
FIGURE 3. Data In Word.
4ns
rxbaudCLK
from DSP
4ns
A
B
4ns
rx48xCLK
from DSP
1
MSB
Bit 15
OB
Data Out
from AFE1124
48
4ns
14
15
16
17
23
24
LSB
Bit 0
25
26
MSB
Bit 15
39
40
47
48
1
MSB
Bit 15
LSB
Bit 0
trx1
Data 1
Data 1a
Interdata 8 Bits
Interdata 8 Bits
Data 2
Receive Timing Notes: (1) A baud period consists of 48 periods of the tx48xCLK. (2) The falling edge of the rxbaudCLK
can occur anywhere in area A. The rising edge can occur anywhere in area B. However, neither edge of the
rxbaudCLK can occur within 4ns (on either side) of any rising edge of rx48xCLK. (3) For all data bits after the MSB of
Data 1, the AFE1124 transfers Data Out on the falling edge of the rx48xCLK. The time from the falling edge of
rx48xCLK until Data Out is stable is trx1.
MIN
MAX
9ns
14ns
trx1
(4) The AFE1124 transfers the MSB of Data 1 on the falling edge of rxbaudCLK. If the falling edge of rxbaudCLK is
synchronized with the falling edge of rx48xCLK, all of the Data Out bits will be the same width. In any case, the time
from the falling edge of rxbaud CLK until the MSB of Data 1 is stable is trx1.
FIGURE 4. Receive Timing Diagram.
®
7
AFE1124
DATA OUT PER SYMBOL PERIOD
txBoost—This bit controls the addition of 0.5dB additional
power to the output line driver.
BIT
DESCRIPTION
BIT STATE
OUTPUT STATE
15 (MSB)
tx Enable Signal
0
1
AFE Transmits a 0 Symbol
AFE Transmits HDSL Symbol
as defined by bits 14 and 13
14 and 13
tx Symbol
Definition
00
–3 Transmit Symbol
01
11
10
–1 Transmit Symbol
+1 Transmit Symbol
+3 Transmit Symbol
000
001
010
011
100
101
110
111
rx gain in AFE 0dB
rx gain in AFE 3dB
rx gain in AFE 6dB
rx gain in AFE 9dB
rx gain in AFE 12dB
rx gain in AFE Reserved
rx gain in AFE Reserved
rx gain in AFE Reserved
rx Gain Settings
16
Interdata Bits
8
Data 1a
16
Interdata bits
8
Total Bits/Symbol Period
48
MSB
LSB
14
Loopback Control
1
0
Loopback Mode
Normal Operation
8
tx Boost
0
1
Normal Transmit Power
+0.5dB Transmit Power Boost
SPARE
A/D Converter Data
FIGURE 5. Data Out Word.
ANALOG-TO-DIGITAL CONVERTER DATA
The A/D converter data from the receive channel is coded in
twos complement.
ANALOG INPUT
NA
TABLE I. Data In.
rxbaudCLK: This is the receive data baud rate (symbol
clock), generated by the DSP. It is 392kHz for T1 or 584kHz
for E1. It can vary from 32kHz (64kbps) to 584kHz
(1.168Mbps).
A/D CONVERTER DATA
MSB
LSB
Positive Full Scale
01111111111111
Mid Scale
00000000000000
Negative Full Scale
10000000000000
ECHO CANCELLATION IN THE AFE
The rxHYB input is subtracted from the rxLINE input for
first order echo cancellation. For correct operation, be certain that the rxLINE input is connected to the same polarity
signal at the transformer (+ to + and – to –) while the rxHYB
input is connected to opposite polarity through the compromise hybrid (– to + and + to –) as shown in the Basic
Connection Diagram.
rx48xCLK: This is the A/D converter over-sampling clock,
generated by the DSP. It is 48x the receive symbol rate or
28.032MHz for 584kHz symbol rate. This clock should run
continuously.
Data Out: This is the 14-bit A/D converter output data (+2
spare bits) sent from the AFE to the DSP. The 14 bits from
the A/D Converter will be the upper bits of the 16-bit word
(bits 15-2). The spare bits (1 and 0) will be always be low.
Eight additional (interdata) bits follow which are always
high. The data is clocked out on the falling edge of rx48xCLK.
The bandwidth of the A/D converter decimation filter is
equal to one half of the symbol rate. The nominal output rate
of the A/D converter is one conversion per symbol period.
For more flexible post processing, there is a second interpolated A/D conversion available in each symbol period. In
Figure 4, the first conversion is shown as Data 1 and the
second conversion is shown as Data 1a. It is suggested that
rxbaudCLK is used with the rx48xCLK to read Data 1 while
Data 1a is ignored. However, either or both outputs may be
used for more flexible post-processing.
OB
SCALEABLE TIMING
The AFE1124 scales operation with the clock frequency. All
internal filters and the pulse former change frequency with
the clock speed so that the unit can be used at different
frequencies just by changing the clock speed.
For the receive channel, the digital filtering of the delta
sigma converter scales directly with the clock speed. The
bandwidth of the converter’s decimation filter is always onehalf of the symbol rate. The only receive channel issue in
changing baud rate is the passive single pole anti-alias filter
(see the following section). For systems implementing a
broad range of speeds, selectable cutoff frequencies for the
passive anti-alias filter should be used.
®
AFE1124
2
Reserved
SO
L
9
7-0
BITS
ET
12 - 10
DATA
Data 1
E
Loopback Control—This bit controls the operation of
loopback. When enabled (logic 1), the rxLINE+ and rxline–
inputs are disconnected from the AFE. The rxHYB+ and
rxHYB– inputs remain connected. When disabled, the
rxLINE+ and rxLINE– inputs are connected.
8
VCM
0.1µF
0.1µF
E
0.1µF
REFP
REFN
1:2 Transformer
13Ω
txLINE+
Tip
0.01µF
13Ω
txLINE–
Input Antialias Filter
fc ≅ 2 x Symbol Rate
–
+
rxHYB+
rx48xCLK
Data Out
Ring
0.01µF
Compromise
Hybrid
750Ω
rxbaudCLK
HDSL DSP
+
ET
–
AFE1124
100pF
txbaudCLK
tx48xCLK
750Ω
Data In
rxHYB–
750Ω
SO
L
rxLINE–
100pF
GNDA
750Ω
GNDA
rxLINE+
GNDA
DVDD DVDD
AVDD
AVDD
AVDD
5V to 3.3V Digital
5V Analog
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
1 - 10µF
OB
FIGURE 6. Basic Connection Diagram.
For the transmit channel, the pulse shape and the power
spectral density scale directly with the clock rate. The power
spectral density shown in Curve 1 and the pulse template
shown in Curve 2 are measured at the output of the transformer. The transformer and the RC circuit on the output
provide some smoothing for the output transmission. At
lower bit rates, the amount of smoothing will be less.
for the rxLINE and rxHYB differential inputs should be
approximately 1MHz for T1 and E1 symbol rates. Suggested
values for the filter are 750Ω for each of the two input
resistors and 100pF for the capacitor. Together the two
750Ω resistors and the 100pF capacitor result in a 3dB
frequency of just over 1MHz. The 750Ω input resistors will
result in minimal voltage divider loss with the input impedance of the AFE1124.
RXHYB AND RXLINE INPUT
ANTI-ALIASING FILTERS
An external input antialiasing filter is needed on the hybrid
and line inputs as shown in the Basic Connection Diagram
above. The –3dB frequency of the input anti-aliasing filter
The antialiasing filters will give best performance with 3dB
frequency approximately equal to the bit rate. For instance,
a 3dB frequency of 320kHz may be used for a single line bit
rate of 320k bits per second.
®
9
AFE1124
UNCANCELED ECHO
A key measure of transceiver performance is uncancelled
echo. Uncancelled echo is the summation of all of the errors
in the transmit and receive paths of the AFE1124. It includes
effects of linearity, distortion and noise. Uncancelled echo is
tested in production by Burr-Brown with a circuit that is
similar to the one shown in Figure 7, Uncancelled Echo Test
Diagram.
BIT RATE
PER AFE1124
(Symbols/sec)
DVDD
(V)
TYPICAL POWER
DISSIPATION
IN THE AFE1124
(mW)
584 (E1)
584 (E1)
392 (T1)
392 (T1)
146 (E1/4)
146 (E1/4)
3.3
5
3.3
5
3.3
5
250
300
240
270
230
245
E
DISCUSSION OF
SPECIFICATIONS
TABLE II. Typical Power Dissipation.
circuit uses a 1:2 transformer. The power measurements
shown in Table II use an equivalent resistive load instead of
the transformer to eliminate frequency dependent impedances of the transformer.
The measurement of uncancelled echo is made as follows.
ET
The AFE is connected to an output circuit including a typical
1:2 line transformer. The line is simulated by a 135Ω
resistor. Symbol sequences are generated by the tester and
applied both to the AFE and to the input of an adaptive filter.
The output of the adaptive filter is subtracted from the AFE
output to form the uncanceled echo signal. Once the filter
taps have converged, the RMS value of the uncancelled echo
is calculated. Since there is no far-end signal source or
additive line noise, the uncanceled echo contains only noise
and linearity errors generated in the transmit and receive
sections of the AFE1124.
LAYOUT
The analog front end of an HDSL system has two conflicting
requirements. It must accept and deliver moderately high
rate digital signals and it must generate, drive, and convert
precision analog signals. To achieve optimal system performance with the AFE1124, both the digital and the analog
sections must be treated carefully in board layout design.
The data sheet value for uncancelled echo is the ratio of
the RMS uncanceled echo (referred to the receiver input
through the receiver gain) to the nominal transmitted signal
(13.5dBm into 135Ω, or 1.74Vrms). This echo value is
measured under a variety of conditions: with loopback
enabled (line input disconnected); with loopback disabled
under all receiver gain ranges; and with the line shorted (S1
closed in Figure 7).
SO
L
The power supply for the digital section of the AFE1124 can
range from 3.3V to 5V. This supply should be decoupled to
digital ground with ceramic 0.1µF capacitors placed as close
to DGND and DVDD as possible. One capacitor should be
placed between pins 3 and 4 and the second capacitor
between pins 11 and 12. Ideally, both a digital power supply
plane and a digital ground plane should run up to and
underneath the digital pins of the AFE1124 (pins 5 through
10). However, DVDD may be supplied by a wide printed
circuit board (PCB) trace. A digital ground plane underneath
all digital pins is strongly recommended.
POWER DISSIPATION
Approximately 80% of the power dissipation in the AFE1124
is in the analog circuitry, and this component does not
change with clock frequency. However, the power dissipation in the digital circuitry does decrease with lower clock
frequency. In addition, the power dissipation in the digital
section is decreased when operating from a smaller supply
voltage, such as 3.3V. (The analog supply, AVDD, must
remain in the range 4.75V to 5.25V).
OB
The remaining portion of the AFE1124 should be considered
analog. All AGND pins should be connected directly to a
common analog ground plane and all AVDD pins should be
connected to an analog 5V power plane. Both of these planes
should have a low impedance path to the power supply. The
analog power supply pins should be decoupled to analog
ground with ceramic 0.1µF capacitors placed as close to the
AFE1124 as possible. One 10µF tantalum capacitor should
also be used with each AFE1124 between the analog supply
and analog ground.
The power dissipation listed in the specifications section
applies under these normal operating conditions: 5V Analog
Power Supply; 3.3V Digital Power Supply; standard 13.5dBm
delivered to the line; and a pseudo-random equiprobable
sequence of HDSL output pulses. The power dissipation
specifications includes all power dissipated in the AFE1124,
it does not include power dissipated in the external load.
The external power is 16.5dBm: 13.5dBm to the line and
13.5dBm to the impedance matching resistors. The external
load power of 16.5dBm is 45mW. The typical power dissipation in the AFE1124 under various conditions is shown in
Table II.
Ideally, all ground planes and traces and all power planes
and traces should return to the power supply connector
before being connected together (if necessary). Each ground
and power pair should be routed over each other, should not
overlap any portion of another pair, and the pairs should be
separated by a distance of at least 0.25 inch (6mm). One
exception is that the digital and analog ground planes should
be connected together underneath the AFE1104 by a small
trace.
The T1 and E1 power measurements in the Specifications
are made with the output circuit shown in Figure 7. This
®
AFE1124
10
13Ω
Transmit
Data
txDATP
1:2
5.6Ω
txLINEP
13Ω
5.6Ω
135Ω
S1
1.5kΩ
rxHYBP
3kΩ
100pF
rxHYBN
ET
Adaptive
Filter
AFE1124
E
txLINEN
1.5Ω
750Ω
rxLINEP
100pF
rxLINEN
750Ω
rxD13 - rxD0
SO
L
Uncancelled
Echo
OB
FIGURE 7. Uncancelled Echo Test Diagram.
®
11
AFE1124
IMPORTANT NOTICE
E
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
ET
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
SO
L
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
OB
Copyright 2000, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
2-Oct-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
AFE1124E/1K
NRND
Package Type Package Pins Package
Drawing
Qty
SSOP
DB
28
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
TBD
Call TI
Call TI
Op Temp (°C)
Device Marking
(4/5)
AFE1124E
G
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
2-Oct-2016
Addendum-Page 2
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