AFE2126E

® AFE 212 6 AFE2126 For most current data sheet and other product information, visit www.burr-brown.com Dual HDSL /SDSL ANALOG FRONT END FEATURES q q q q q q SERIAL DIGITAL INTERFACE 48-LEAD SSOP PACKAGE E1, T1 AND SDSL OPERATION 64kbps TO 1168kbps OPERATION SCALEABLE DATA RATE 280mW POWER DISSIPATION PER CHANNEL q TWO COMPLETE HDSL ANALOG INTERFACES q +5V POWER (5V or 3.3V Digital) q WIDE Rx GAIN RANGE: 0dB TO 18dB DESCRIPTION Burr-Brown’s dual Analog Front End chip greatly reduces the size and cost of a DSL (Digital Subscriber Line) system by providing all of the active analog circuitry needed to connect two digital signal processors to external compromise hybrids and line transformers. The AFE2126 is optimized for HDSL (High bit rate DSL) and for SDSL (symmetrical DSL) applications. The AFE2126 is particularly suitable for multiple rate DSL systems because the transmit and receive filter responses automatically change with clock frequency. The device operates over a wide range of data rates from 64kbps to 1168kbps. Functionally, each half of this unit consists of a transmit and a receive section. The transmit section generates analog signals from 2-bit digital symbol data, and filters the analog signals to create 2B1Q symbols. The onboard differential line driver provides a 13.5dBm signal to the telephone line. The receive section filters and digitizes the symbol data received on the telephone line. This IC operates on a single 5V supply. The digital circuitry in the unit can be connected to a supply from 3.3V to 5V. It is housed in a 48-lead SSOP package. txLINE+ Pulse Former txLINE– Line Driver tx and rx Interface Lines tx and rx Control Registers Difference Amplifier Decimation Filter ∆Σ Modulator Programmable Gain Amp 1/2 of AFE2126 rxHYB+ rxHYB– rxLINE+ rxLINE– Patents Pending International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1999 Burr-Brown Corporation PDS-1561A 1 Printed in U.S.A. December, 1999 AFE2126 SPECIFICATIONS Specifications at 25°C, AVDD = +5V, DVDD = +3.3V, and txBaudCLK = 584kHz (E1 rate), unless otherwise noted. Specifications apply to each channel of the AFE2126. AFE2126E PARAMETER RESOLUTION RECEIVE CHANNEL Number of Inputs Input Voltage Range Common-Mode Voltage Input Impedance All Inputs Input Capacitance Input Gain Matching Programmable Gain Settling Time Gain + Offset Error Output Data Coding Output Word Rate(3) Output Bit Rate(3) TRANSMIT CHANNEL Transmit Clock Rate, txBaudCLK T1 Transmit –3dB Point T1 Rate Power(4, 5) E1 Transmit –3dB Point E1 Transmit Power(4, 5) Common-Mode Voltage, VCM Output Resistance(6) TRANSCEIVER PERFORMANCE Uncancelled Echo(5) Differential Balanced Differential(1) COMMENTS MIN 14 2 ±3.0 AVDD/2 See Typical Performance Curves 10 ±2 0 +18 6 5 32 64 Symbol Rate T1/E1 4/99-002R4 Draft Compliant ETSI Compliant 13 DC to 1MHz rxGAIN = 0dB, Loopback Enabled rxGAIN = 0dB, Loopback Disabled rxGAIN = 3dB, Loopback Disabled rxGAIN = 6dB, Loopback Disabled rxGAIN = 9dB, Loopback Disabled rxGAIN = 12dB, Loopback Disabled rxGAIN = 15dB, Loopback Disabled rxGAIN = 18dB, Loopback Disabled AVDD /2 1 –71 –71 –74 –76 –78 –80 –82 –84 –68.5 –68.5 –71 –73.5 –75.5 –77.5 –79.5 –81.5 32 196 13 292 14 14 584 1168 584 V V pF % dB Symbol Periods %FSR(2) kHz kbits/sec kHz kHz dBm kHz dBm V Ω dB dB dB dB dB dB dB dB TYP MAX UNITS Bits Line Input vs Hybrid Input 0dB, 3dB, 6dB, 9dB, 12dB, 15dB, and 18dB For Any Change in Gain or txBaud CLK Tested at Each Gain Range Two’s Complement DIGITAL INTERFACE(6) Logic Levels VIH VIL VOH VOL trx1 Interface POWER Analog Power Supply Voltage Analog Power Supply Voltage Digital Power Supply Voltage Digital Power Supply Voltage Power Dissipation(4, 5) Power Dissipation(4, 5) Power Supply Rejection Ratio (PSRR) TEMPERATURE RANGE Operating(6) |IIH| < 10µA |IIL| < 10µA IOH = –20µA IOL = 20µA DVDD – 1 –0.3 DVDD – 0.5 9 DVDD + 0.3 +0.8 +0.4 14 5 V V V V ns V V V V mW mW dB °C Specification Operating Range Specification Operating Range AVDD = 5V, DVDD = 3.3V, AVDD = DVDD = 5V 4.75 3.3 3.15 275 325 55 –40 5.25 5.25 +85 NOTES: (1) With a balanced differential signal, the positive input is 180° out of phase with the negative input, therefore, the actual voltage swing about the commonmode voltage on each pin is ±1.5V to achieve a total input range of ±3.0V or 6Vp-p. (2) FSR is Full-Scale Range. (3) The output data is available at twice the symbol rate. (4) With a pseudo-random equiprobable sequence of HDSL pulses; 13.5dBm applied to the transformer (16.5dBm output from txLINEP and txLINEN). (5) See the Discussion of Specifications section of this data sheet for more information. (6) Functionality only is guaranteed over temperature range. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® AFE2126 2 ABSOLUTE MAXIMUM RATINGS Analog Inputs: Current .............................................. ±100mA, Momentary ±10mA, Continuous Voltage .................................. AGND –0.3V to AVDD +0.3V Analog Outputs Short Circuit to Ground (+25°C) ..................... Continuous AVDD to AGND ......................................................................... –0.3V to 6V DVDD to DGND ......................................................................... –0.3V to 6V Digital Input Voltage to DGND .................................. –0.3V to DVDD +0.3V Digital Output Voltage to DGND ............................... –0.3V to DVDD +0.3V AGND, DGND, Differential Voltage .................................................... 0.3V Junction Temperature (TJ) ............................................................. +150°C Storage Temperature Range .......................................... –40°C to +125°C Lead Temperature (soldering, 3s) .................................................. +260°C Power Dissipation .......................................................................... 700mW ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PACKAGE DRAWING NUMBER 333 SPECIFIED TEMPERATURE RANGE –40°C to +85°C PACKAGE MARKING AFE2126E ORDERING NUMBER(1) AFE2126E/500 AFE2126E/1K TRANSPORT MEDIA Tape and Reel Tape and Reel PRODUCT AFE2126E PACKAGE SSOP-48 " " " " " NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “AFE2126E/1K” will get a single 1000-piece Tape and Reel. BLOCK DIAGRAM 1/2 AFE2126 Pulse Former Filter txLINE+ Output Buffer txLINE– txbaudCLK tx48xCLK Data In Transmit Control REFP Voltage Reference VCM REFN rxbaudCLK Receive Control rxLINE+ Data Out ∆Σ Modulator rxLINE– rxHYB+ rxHYB– rx48xCLK Decimation Filter ® 3 AFE2126 PIN CONFIGURATION Top View SSOP PIN DESCRIPTIONS PIN # TYPE NAME DESCRIPTION CHANNEL A 1 2 Data OutA rx48xCLKA rxbaudCLKA Data InA tx48xCLKA txbaudCLKA DVDD DGND AGND txLINE+A AVDD txLINE–A AGND AVDD REFNA VCMA REFPA AGND AGND rxLINE+A rxLINE–A rxHYB+A rxHYB–A AVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 Data OutB rx48xCLKB rxbaudCLKB Data InB tx48xCLKB txbaudCLKB DVDD DGND AGND txLINE+B AVDD txLINE–B AGND AVDD REFNB VCMB REFPB AGND AGND rxLINE+B rxLINE–B rxHYB+B rxHYB–B AVDD Output Input Input Input Input Input Power Ground Ground Output Power Output Ground Power Output Output Output Ground Ground Input Input Input Input Power Power Data OutA rx48xCLKA rxbaudCLKA Data InA tx48xCLKA txbaudCLKA DVDD DGND AGND txLINE+A AVDD txLINE–A AGND AVDD REFNA VCMA REFPA AGND AGND rxLINE+A rxLINE–A rxHYB+A rxHYB–A AVDD AVDD Output Data Word Receive Clock at 48x Baud Clock (23.032MHz for E1) Receive Baud Clock (584kHz for E1) Input Data Word Transmit Clock (584kHz for E1) Transmit Baud Clock at 48x Baud Clock (584kHz for E1) Digital Supply (+3.3V to +5V) Digital Ground Analog Ground Transmit Line Driver Output, Positive Analog Supply (+5V) Transmit Line Driver Output, Negative Analog Ground Analog Supply (+5V) Negative Reference Output Common-Mode Voltage (buffered) Positive Reference Output Analog Ground Analog Ground Positive Line Input Negative Line Input Positive Input from Hybrid Network Negative Input from Hybrid Network Analog Supply (+5V) Analog Supply (+5V) 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AFE2126 Channel A Channel B 37 36 35 34 33 32 31 30 29 28 27 26 25 17 18 19 20 21 22 23 24 25 CHANNEL B 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Input Input Input Input Ground Ground Output Output Output Power Ground Output Power Output Ground Ground Power Input Input Input Input Input Output rxHYB–B rxHYB+B rxLINE–B rxLINE+B AGND AGND REFPB VCMB REFNB AVDD AGND txLINE–B AVDD txLINE+B AGND DGND DVDD txbaudCLKB tx48xCLKB Data InB rxbaudCLKB rx48xCLKB Data OutB Negative Input from Hybrid Network Positive Input from Hybrid Network Negative Line Input Postiive Line Input Analog Ground Analog Ground Positive Reference Output Common-Mode Voltage (buffered) Negative Reference Output Analog Supply (+5V) Analog Ground Transmit LIne Driver Output, Negative Analog Supply (+5V) Transmit Line Driver Output, Positive Analog Ground Digital Ground Digital Supply (+3.3V to +5V) Transmit Baud Clock (584kHz for E1) Transmit Clock at 48x Baud Clock (28.032MHz for E1) Input Data Word Receive Baud Clock (584kHz for E1) Receive Clock at 48x Baud Clock (28.032MHz for E1) Output Data Word ® AFE2126 4 TYPICAL PERFORMANCE CURVES At Output of HDSL Pulse Transformer The curves shown below are measured at the line output of the HDSL transformer. Typical at 25°C, AVDD+ = +5V, DVDD+ = +3.3V, txBaudCLK = 392kHz (T1), unless otherwise specified. POWER SPECTRAL DENSITY LIMIT - T1 RATE 0 Power Spectral Density (dBm/Hz) –20 –40 –60 –80 –100 –120 0 500 1000 1500 2000 2500 Frequency (kHz) CURVE 1. Upper Bound of Power Spectral Density Measured at Output of HDSL Transformer. INPUT IMPEDANCE vs BIT RATE 120 Input Impedance (kΩ) 90 60 T1 = 784kbps, 16kΩ 30 E1 = 1168kbps, 10.5kΩ 0 100 300 500 700 Bit Rate (kbps) 900 1100 1300 CURVE 2. Input Impedance of rxLINE and rxHYB. ® 5 AFE2126 THEORY OF OPERATION The AFE2126 has two HDSL Analog Front End (AFE) circuits on chip (channel A and channel B). Each AFE consists of a transmit and a receive channel which interfaces to a HDSL DSP through a six-wire serial interface—three wires for the transmit channel and three wires for the receive channel. It interfaces to the HDSL telephone line transformer and external compromise hybrid through transmit and receive analog connections. The transmit channel consists of a switched-capacitor pulse forming network followed by a differential line driver. The pulse-forming network receives 2-bit digital symbol data and generates a filtered 2B1Q analog output waveform. The differential line driver uses a composite output stage combining class B operation (for high efficiency driving large signals) with class AB operation (to minimize crossover distortion). The receive channel is designed around a fourth-order deltasigma analog-to-digital converter. It includes a difference amplifier designed to be used with an external compromise hybrid for first-order analog echo cancellation. A programmable gain amplifier with gains of 0dB to +18dB is also included. The delta-sigma modulator, operating at a 24x oversampling ratio, produces a 14-bit output at rates up to 584kHz (1.168Mbps). The receive channel operates by summing the two differential inputs, one from the line (rxLINE) and the other from the compromise hybrid (rxHYB). The connection of these two inputs, so that the hybrid signal is subtracted from the line signal, is described in the paragraph titled “Echo Cancellation in the AFE.” The equivalent gain for each input in the difference amp is one. The resulting signal then passes to a programmable gain amplifier which can be set for gains of 0dB through +18dB. Following the PGA, the ADC converts the signal to a 14-bit digital word. The serial interface consists of three wires for transmit and three wires for receive. The three-wire transmit interface is transmit baud rate clock, transmit 48x oversampling clock and Data Out. The three-wire receive interface is receive baud rate clock, receive 48x oversampling clock and Data In. The transmit and receive clocks are supplied to the AFE2126 from the DSP and are completely independent. DIGITAL DATA INTERFACE Data is received by the AFE2126 from the DSP on the Data In line. Data is transmitted from the AFE2126 to the DSP on the Data Out line. The following paragraphs describe the timing of these signals and data structure. rxbaudCLK rx48xCLK Data Out HDSL DSP txbaudCLK tx48xCLK Data In 1/2 AFE2126 FIGURE 1. DSP Interface. 4ns txbaudCLK from DSP 4ns tx48xCLK from DSP 48 1 4ns A 4ns 2 3 4 B 15 16 47 48 1 Data In from DSP MSB Bit 15 LSB Bit 0 MSB Bit 15 Transmit Timing Notes: (1) A baud period consists of 48 periods of the tx48xCLK. (2) The falling edge of the txbaudCLK can occur anywhere in area A. The rising edge can occur anywhere in area B. However, neither edge of the txbaudCLK can occur within 4ns (on either side) of any rising edge of tx48xCLK. (3) The AFE2126 reads Data In on the rising edge of the tx48xCLK. Data In must be stable at least 4ns before the rising edge of tx48xCLK and it must remain stable at least 4ns after the rising edge of tx48xCLK. (4) Symbol data is transferred to the transmit pulse former after the LSB is read. The output analog symbol data reaches the peak of the symbol approximately 24 tx48xCLK periods later. FIGURE 2. Transmit Timing Diagram. ® AFE2126 6 Data is transmitted and received in synchronization with the 48x transmit and receive clocks (tx48xCLK and rx48xCLK). There are 48-bit times in each baud period. Data In is received in the first 16 bits of each baud period. The remaining 32-bit periods are not used for Data In. Data Out is transmitted during the first 16 bits of the baud period. A second interpolated value is transmitted in subsequent bits of the baud period. txbaudCLK: The transmit data baud rate generated by the DSP. It is 392kHz for T1 or 584kHz for E1. It may vary from 32kHz (64kbps) to 584kHz (1.168Mbps). tx48xCLK: The transmit pulse former oversampling sampling clock generated by the DSP. It is 48x the transmit symbol rate or 28.032MHz for 584kHz symbol rate. This clock should run continuously. Data In: This is a 16-bit output data word sent from the DSP to the AFE. The sixteen bits include tx symbol information and other control bits, as described below. The data should be clocked out of the DSP on the falling edge and should be valid on the rising edge of the tx48xCLK. The AFE2126 reads Data In on the rising edge of the tx48xCLK. The bits are defined in Table I. Data In is read by the AFE2126 during the first 16 bits periods of each baud period. Only the first 8 bits are used in the AFE2126. The second 8 bits are reserved for use in the future products. The remaining 32 bits periods of the baud period are not used for Data In. Data In Bits tx Enable Signal—This bit controls the tx Symbol definition bits. If this bit is 0, only a 0 symbol is transmitted regardless of the state of the tx Symbol definition bits. If this bit is 1, the tx Symbol definition bits determine the output symbol. tx Symbol Definition—These two bits determine the output 2B1Q symbol transmitted. MSB 1 2 3 1 9 LSB Reserved Loopback rx Gain tx Symbol tx Enable FIGURE 3. Data In Word. 4ns rxbaudCLK from DSP 4ns rx48xCLK from DSP Data Out from AFE2126 48 1 4ns A 4ns 14 15 16 17 23 B 24 25 26 39 40 47 48 1 MSB Bit 15 LSB Bit 0 MSB Bit 15 LSB Bit 0 MSB Bit 15 trx1 Data 1 Interdata 8 Bits Data 1a Interdata 8 Bits Data 2 Receive Timing Notes: (1) A baud period consists of 48 periods of the tx48xCLK. (2) The falling edge of the rxbaudCLK can occur anywhere in area A. The rising edge can occur anywhere in area B. However, neither edge of the rxbaudCLK can occur within 4ns (on either side) of any rising edge of rx48xCLK. (3) For all data bits after the MSB of Data 1, the AFE2126 transfers Data Out on the falling edge of the rx48xCLK. The time from the falling edge of rx48xCLK until Data Out is stable is trx1. min trx1 9ns max 14ns (4) The AFE2126 transfers the MSB of Data 1 on the falling edge of rxbaudCLK. If the falling edge of rxbaudCLK is synchronized with the falling edge of rx48xCLK, all of the Data Out bits will be the same width. In any case, the time from the falling edge of rxbaudCLK until the MSB of Data 1 is stable is trx1. FIGURE 4. Receive Timing Diagram. ® 7 AFE2126 BIT 15 (MSB) DESCRIPTION tx Enable Signal BIT STATE 0 1 00 01 11 10 OUTPUT STATE AFE Transmits a 0 Symbol AFE Transmits HDSL Symbol as defined by bits 14 and 13 –3 Transmit Symbol –1 Transmit Symbol +1 Transmit Symbol +3 Transmit Symbol rx gain in AFE 0dB rx gain in AFE 3dB rx gain in AFE 6dB rx gain in AFE 9dB rx gain in AFE 12dB rx gain in AFE 15dB rx gain in AFE 18dB rx gain in AFE Reserved Loopback Mode Normal Operation NA DATA OUT PER SYMBOL PERIOD DATA Data 1 Interdata Bits Data 1a Interdata bits Total Bits/Symbol Period BITS 16 8 16 8 48 14 and 13 tx Symbol Definition 12 - 10 rx Gain Settings 000 001 010 011 100 101 110 111 1 0 MSB 14 LSB 2 9 8-0 Loopback Control SPARE Reserved A/D Converter Data TABLE I. Data In. Rx Gain Settings—These bits set the gain of the receive channel programmable gain amplifier. Loopback Control—This bit controls the operation of loopback. When enabled (logic 1), the rxLINE+ and rxLINE– inputs are disconnected from the AFE. The rxHYB+ and rxHYB– inputs remain connected. When disabled, the rxLINE+ and rxLINE– inputs are connected. rxbaudCLK: This is the receive data baud rate (symbol clock) generated by the DSP. It is 392kHz for T1 or 584kHz for E1. It can vary from 32kHz (64kbps) to 584kHz (1.168Mbps). rx48xCLK: This is the A/D converter oversampling clock generated by the DSP. It is 48x the receive symbol rate or 28.032MHz for 584kHz symbol rate. This clock should run continuously. Data Out: This is the 14-bit A/D converter output data (+2 spare bits) sent from the AFE to the DSP. The 14 bits from the A/D Converter will be the upper bits of the 16-bit word (bits 15-2). The spare bits (1 and 0) will be always be low. Eight additional (interdata) bits follow and are always high. The data is clocked out on the falling edge of rx48xCLK. The bandwidth of the A/D converter decimation filter is equal to one-half of the symbol rate. The nominal output rate of the A/D converter is one conversion per symbol period. For more flexible post processing, there is a second true A/D conversion available in each symbol period. In Figure 4, the first conversion is shown as Data 1 and the second conversion is shown as Data 1a. It is suggested that rxbaudCLK is used with the rx48xCLK to read Data 1 while Data 1a is ignored. However, either or both outputs may be used for more flexible post-processing. FIGURE 5. Data Out Word. ANALOG-TO-DIGITAL CONVERTER DATA The A/D converter data from the receive channel is coded in Binary Two’s Complement. ANALOG INPUT A/D CONVERTER DATA MSB Positive Full Scale Mid Scale Negative Full Scale LSB 01111111111111 00000000000000 10000000000000 TABLE II. rx Data Format. ECHO CANCELLATION IN THE AFE The rxHYB input is subtracted from the rxLINE input for first order echo cancellation. For correct operation, be certain that the rxLINE input is connected to the same polarity signal at the transformer (+ to + and – to –) while the rxHYB input is connected to opposite polarity through the compromise hybrid (– to + and + to –) as shown in Figure 6. SCALEABLE TIMING The AFE2126 scales operation with the clock frequency. All internal filters and the pulse former change frequency with the clock speed so that the unit can be used at different frequencies just by changing the clock speed. For the receive channel, the digital filtering of the deltasigma converter scales directly with the clock speed. The bandwidth of the converter’s decimation filter is always onehalf of the symbol rate. The only receive channel issue in changing baud rate is the passive single pole anti-alias filter (see the “rxHYB and rxLINE Input Anti-Aliasing Filters” section). For systems implementing a broad range of speeds, selectable cutoff frequencies for the passive anti-alias filter should be used. ® AFE2126 8 0.1µF REFP VCM REFN 0.1µF 0.1µF 13Ω txLINE+ 13Ω txLINE– – Input Antialias Filter fc ≅ 2 x Symbol Rate 750Ω rxbaudCLK rx48xCLK HDSL DSP Data Out txbaudCLK tx48xCLK Data In rxHYB– 750Ω rxLINE– rxHYB+ Compromise Hybrid – + + 0.01µF 0.01µF 1:2 Transformer Tip Ring 1/2 AFE2126 100pF 750Ω 100pF GNDA GNDA GNDA DVDD DVDD 5V to 3.3V Digital 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF AVDD AVDD rxLINE+ 750Ω AVDD 5V Analog 1 - 10µF FIGURE 6. Basic Connection Diagram for Each Channel of the AFE2126. For the transmit channel, the pulse shape and the power spectral density scale directly with the clock rate. The power spectral density shown in Curve 1 is measured at the output of the transformer. The transformer and the RC circuit on the output provide some smoothing for the output transmission. At lower bit rates, the amount of smoothing will be less. rxHYB AND rxLINE INPUT ANTI-ALIASING FILTERS An external input antialiasing filter is needed on the hybrid and line inputs as shown in Figure 6. The –3dB frequency of the input anti-aliasing filter for the rxLINE and rxHYB differential inputs should be approximately 1MHz for T1 and E1 symbol rates. Suggested values for the filter are 750Ω for each of the two input resistors and 100pF for the capacitor. Together, the two 750Ω resistors and the 100pF capacitor result in a 3dB frequency of just over 1MHz. The 750Ω input resistors will result in minimal voltage divider loss with the input impedance of the AFE2126. The anti-aliasing filters will give best performance with 3dB frequency approximately equal to the bit rate. For example, a 3dB frequency of 320kHz may be used for a single line bit rate of 320k bits per second. ® 9 AFE2126 DISCUSSION OF SPECIFICATIONS UNCANCELED ECHO A key measure of transceiver performance is uncancelled echo. Uncancelled echo is the summation of all of the errors in the transmit and receive paths of the AFE2126. It includes effects of linearity, distortion, and noise. Uncancelled echo is tested in production by Burr-Brown with a circuit that is similar to the one shown in Figure 7. The measurement of uncancelled echo is made as follows: The AFE is connected to an output circuit including a typical 1:2 line transformer. The line is simulated by a 135Ω resistor. Symbol sequences are generated by the tester and applied both to the AFE and to the input of an adaptive filter. The output of the adaptive filter is subtracted from the AFE output to form the uncanceled echo signal. Once the filter taps have converged, the rms value of the uncancelled echo is calculated. Since there is no far-end signal source or additive line noise, the uncanceled echo contains only noise and linearity errors generated in the transmit and receive sections of the AFE2126. The data sheet value for uncancelled echo is the ratio of the rms uncanceled echo (referred to the receiver input through the receiver gain) to the nominal transmitted signal (13.5dBm into 135Ω, or 1.74Vrms). This echo value is measured under a variety of conditions: with loopback enabled (line input disconnected); with loopback disabled under all receiver gain ranges; and with the line shorted (S1 closed in Figure 7). POWER DISSIPATION Approximately 80% of the power dissipation in the AFE2126 is in the analog circuitry, and this component does not change with clock frequency. However, the power dissipation in the digital circuitry does decrease with lower clock frequency. In addition, the power dissipation in the digital section is decreased when operating from a smaller supply voltage, such as 3.3V. (The analog supply, AVDD, must remain in the range 4.75V to 5.25V). The power dissipation listed in the Specifications Table applies under these normal operating conditions: 5V analog power supply, 3.3V digital power supply, standard 13.5dBm delivered to the line, and a pseudo-random equiprobable sequence of HDSL output pulses. The power dissipation specifications includes all power dissipated in the AFE2126. However, it does not include power dissipated in the external load. The external power is 16.5dBm, 13.5dBm to the line, and 13.5dBm to the impedance matching resistors. The external load power of 16.5dBm is 45mW. The typical power dissipation for each half of the AFE2126 under various conditions is shown in Table III. The T1 and E1 power measurements in the Specifications are made with the output circuit shown in Figure 7. This circuit uses a 1:2 transformer. The power measurements shown in Table III use an equivalent resistive load instead of the transformer to eliminate frequency dependent impedances of the transformer. TYPICAL POWER DISSIPATION IN THE AFE2126 (per channel) (mW) 275 325 265 295 255 270 BIT RATE (symbols/sec) 584 (E1) 584 (E1) 392 (T1) 392 (T1) 146 (E1/4) 146 (E1/4) DVDD (V) +3.3 +5 +3.3 +5 +3.3 +5 TABLE III. Typical Power Dissipation (per channel). Transmit Data 13Ω txDATP txLINEP 13Ω txLINEN 1.5kΩ rxHYBP 1:2 5.6Ω 135Ω S1 5.6Ω 1/2 AFE2126 Adaptive Filter 100pF 3kΩ rxHYBN 1.5Ω 750Ω rxLINEP 100pF rxLINEN 750Ω Uncancelled Echo rxD13 - rxD0 FIGURE 7. Uncancelled Echo Test Diagram. ® AFE2126 10 LAYOUT The analog front end of an HDSL system has two conflicting requirements. It must accept and deliver moderately high rate digital signals and it must generate, drive, and convert precision analog signals. To achieve optimal system performance with the AFE2126, both the digital and the analog sections must be treated carefully in board layout design. The power supply for the digital section of the AFE2126 can range from 3.3V to 5V. This supply should be decoupled to digital ground with ceramic 0.1µF capacitors placed as close to DGND and DVDD as possible. One capacitor should be placed between pins 7 and 8, and the second capacitor, between pins 41 and 42. Ideally, both a digital power supply plane and a digital ground plane should run up to, and underneath the digital pins of the AFE2126 (pins 1 through 6, and pins 43 through 48). However, DVDD may be supplied by a wide printed circuit board (PCB) trace. A digital ground plane underneath all digital pins is strongly recommended. The remaining portion of the AFE2126 should be considered analog. All AGND pins should be connected directly to a common analog ground plane and all AVDD pins should be connected to an analog 5V power plane. Both of these planes should have a low impedance path to the power supply. The analog power supply pins should be decoupled to analog ground with ceramic 0.1µF capacitors placed as close to the AFE2126 as possible. One 10µF tantalum capacitor should also be used with each AFE2126 between the analog supply and analog ground. Ideally, all ground planes and traces, and all power planes and traces should return to the power supply connector before being connected together (if necessary). Each ground and power pair should be routed over each other, should not overlap any portion of another pair, and the pairs should be separated by a distance of at least 0.25 inch (6mm). One exception is that the digital and analog ground planes should be connected together underneath the AFE2126 by a small trace. ® 11 AFE2126