AFE5808
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SLOS688D – SEPTEMBER 2010 – REVISED JANUARY 2014
Fully Integrated, 8-Channel Ultrasound Analog Front End With Passive CW Mixer, 0.75
nV/rtHz, 14/12-Bit, 65 MSPS, 153 mW/CH
Check for Samples: AFE5808
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
8-Channel Complete Analog Front-End
– LNA, VCAT, PGA, LPF, ADC, and CW Mixer
Programmable Gain Low-Noise Amplifier
(LNA)
– 24/18/12 dB Gain
– 0.25/0.5/1 VPP Linear Input Range
– 0.63/0.7/0.9 nV/rtHz Input Referred Noise
– Programmable Active Termination
40 dB Low Noise Voltage Controlled
Attenuator (VCAT)
24/30 dB Programmable Gain Amplifier (PGA)
3rd Order Linear Phase Low-Pass Filter (LPF)
– 10, 15, 20, 30 MHz
14-bit Analog to Digital Converter (ADC)
– 77 dBFS SNR at 65 MSPS
– LVDS Outputs
Noise/Power Optimizations (Full Chain)
– 153 mW/CH at 0.75 nV/rtHz, 65 MSPS
– 98 mW/CH at 1.1 nV/rtHz, 40 MSPS
– 80 mW/CH at CW Mode
Excellent Device-to-Device Gain Matching
– ±0.5 dB (typical) and ±0.9 dB (max)
Low Harmonic Distortion
Fast and Consistent Overload Recovery
Passive Mixer for Continuous Wave Doppler
(CWD)
– Low Close-in Phase Noise –156 dBc/Hz at 1
KHz off 2.5 MHz Carrier
– Phase Resolution of 1/16λ
– Support 16X, 8X, 4X and 1X CW Clocks
– 12-dB Suppression on 3rd and 5th
Harmonics
•
– Flexible Input Clocks
Small Package: 15 mm × 9 mm, 135-BGA
APPLICATIONS
•
•
Medical Ultrasound Imaging
Nondestructive Evaluation Equipments
DESCRIPTION
The AFE5808 is a highly integrated analog front-end
(AFE) solution specifically designed for ultrasound
systems in which high performance and small size
are required. The AFE5808 integrates a complete
time-gain-control (TGC) imaging path and a
continuous wave Doppler (CWD) path. It also enables
users to select one of various power/noise
combinations to optimize system performance.
Therefore, the AFE5808 is a suitable ultrasound
analog front end solution not only for high-end
systems, but also for portable ones.
The AFE5808 contains eight channels of voltage
controlled amplifier (VCA), 14/12-bit Analog-to-Digital
Converter (ADC), and CW mixer. The VCA includes
Low noise Amplifier(LNA), Voltage controlled
Attenuator(VCAT),
Programmable
Gain
Amplifier(PGA), and Low-Pass Filter (LPF). The LNA
gain is programmable to support 250 mVPP to 1 VPP
input signals. Programmable active termination is
also supported by the LNA. The ultra-low noise VCAT
provides an attenuation control range of 40 dB and
improves overall low gain SNR which benefits
harmonic imaging and near field imaging. The PGA
provides gain options of 24 dB and 30 dB. Before the
ADC, a LPF can be configured as 10, 15, 20, or 30
MHz to support ultrasound applications with different
frequencies. The high-performance 14 bit/65 MSPS
ADC in the AFE5808 achieves 77 dBFS SNR. It
ensures excellent SNR at low chain gain. The ADC’s
LVDS outputs enable flexible system integration
desired for miniaturized systems.
NOTE
AFE5808A is an enhanced version of AFE5808 and it is recommended for new designs.
Compared to AFE5808, it expands the cut-off frequency range of the digital high pass
filter; increases the handling capability of extreme overload signals; lowers the correlated
noise significantly when high impedance source appears.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2014, Texas Instruments Incorporated
AFE5808
SLOS688D – SEPTEMBER 2010 – REVISED JANUARY 2014
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION CONTINUED
The AFE5808 also integrates a low power passive mixer and a low noise summing amplifier to accomplish onchip CWD beamformer. 16 selectable phase-delays can be applied to each analog input signal. Meanwhile a
unique 3rd and 5th order harmonic suppression filter is implemented to enhance CW sensitivity.
The AFE5808 is available in a 15-mm × 9-mm, 135-pin BGA package and it is specified for operation from 0°C to
85°C. It is also pin-to-pin compatible to the AFE5807, AFE5803, and AFE5808A.
AFE5808 (1 of 8 Channels)
SPI IN
SPI Logic
VCAT
0 to -40dB
LNA
3rd LP Filter
10, 15, 20,
30 MHz
PGA
24, 30dB
LNA IN
16X CLK
1X CLK
16 Phases
Generator
CW Mixer
16X8
Crosspoint SW
SPI OUT
14Bit
ADC
LVDS
Summing
Amplifier
Reference
Reference
CW I/Q Vout
Differential
TGC Vcntl
EXT/INT
REFs
1X CLK
Figure 1. Block Diagram
Table 1. PACKAGING/ORDERING INFORMATION (1)
(1)
2
PRODUCT
PACKAGE TYPE
OPERATING
ORDERING NUMBER
TRANSPORT MEDIA,
QUANTITY
AFE5808
ZCF
0°C to 85°C
AFE5808ZCF
Tray, 160
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
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SLOS688D – SEPTEMBER 2010 – REVISED JANUARY 2014
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
AVDD
–0.3
3.9
V
AVDD_ADC
–0.3
2.2
V
AVDD_5V
–0.3
6
V
DVDD
–0.3
2.2
V
Voltage between AVSS and LVSS
–0.3
0.3
V
Voltage at analog inputs and digital inputs
–0.3
min [3.6, AVDD + 0.3]
V
260
°C
Supply voltage range
Peak solder temperature (2)
Maximum junction temperature (TJ), any condition
105
°C
–55
150
°C
0
85
°C
HBM
2000
V
CDM
500
V
Storage temperature range
Operating temperature range
ESD Ratings
(1)
(2)
UNIT
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied Exposure to absolute maximum rated conditions for extended periods may degrade device reliability.
Device complies with JSTD-020D.
THERMAL INFORMATION
AFE5808
THERMAL METRIC (1)
BGA
UNIT
135 PINS
θJA
Junction-to-ambient thermal resistance
θJCtop
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance
11.5
ψJT
Junction-to-top characterization parameter
0.2
ψJB
Junction-to-board characterization parameter
10.8
θJCbot
Junction-to-case (bottom) thermal resistance
n/a
(1)
34.1
5
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MIN
MAX
AVDD
UNIT
3.15
3.6
V
AVDD_ADC
1.7
1.9
V
DVDD
1.7
1.9
V
4.75
5.5
V
0
85
°C
AVDD_5V
Ambient Temperature, TA
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AFE5808
SLOS688D – SEPTEMBER 2010 – REVISED JANUARY 2014
www.ti.com
PINOUT INFORMATION
Table 2. Top View
ZCF (BGA-135)
1
2
3
4
5
6
7
8
9
A
AVDD
INP8
INP7
INP6
INP5
INP4
INP3
INP2
INP1
B
CM_BYP
ACT8
ACT7
ACT6
ACT5
ACT4
ACT3
ACT2
ACT1
C
AVSS
INM8
INM7
INM6
INM5
INM4
INM3
INM2
INM1
D
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVDD
AVDD
E
CW_IP_AMPINP
CW_IP_AMPINM
AVSS
AVSS
AVSS
AVSS
AVSS
AVDD
AVDD
F
CW_IP_OUTM
CW_IP_OUTP
AVSS
AVSS
AVSS
AVSS
AVSS
CLKP_16X
CLKM_16X
G
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
CLKP_1X
CLKM_1X
H
CW_QP_OUTM
CW_QP_OUTP
AVSS
AVSS
AVSS
AVSS
AVSS
PDN_GLOBAL
RESET
J
CW_QP_AMPINP
CW_QP_AMPINM
AVSS
AVSS
AVSS
AVDD_ADC
AVDD_ADC
PDN_VCA
SCLK
K
AVDD
AVDD_5V
VCNTLP
VCNTLM
VHIGH
AVSS
DNC
AVDD_ADC
SDATA
L
CLKP_ADC
CLKM_ADC
AVDD_ADC
REFM
DNC
DNC
DNC
PDN_ADC
SEN
M
AVDD_ADC
AVDD_ADC
VREF_IN
REFP
DNC
DNC
DNC
DNC
SDOUT
N
D8P
D8M
DVDD
DNC
DVSS
DNC
DVDD
D1M
D1P
P
D7M
D6M
D5M
FCLKM
DVSS
DCLKM
D4M
D3M
D2M
R
D7P
D6P
D5P
FCLKP
DVSS
DCLKP
D4P
D3P
D2P
Table 3. PIN FUNCTIONS
PIN
DESCRIPTION
NO.
NAME
B9~ B2
ACT1...ACT8
Active termination input pins for CH1~8. 1-µF capacitors are recommended. See the Applicaiton
Information section.
A1, D8, D9,
E8, E9, K1
AVDD
3.3-V Analog supply for LNA, VCAT, PGA, LPF and CWD blocks
K2
AVDD_5V
5.0-V Analog supply for LNA, VCAT, PGA, LPF and CWD blocks
J6, J7, K8, L3,
M1, M2
AVDD_ADC
1.8-V Analog power supply for ADC
C1, D1~D7,
E3~E7, F3~F7,
G1~G7,
AVSS
H3~H7,J3~J5,
K6
Analog ground
L2
CLKM_ADC
Negative input of differential ADC clock. In the single-end clock mode, it can be tied to GND directly or
through a 0.1-µF capacitor.
L1
CLKP_ADC
Positive input of differential ADC clock. In the single-end clock mode, it can be tied to clock signal
directly or through a 0.1-µF capacitor.
F9
CLKM_16X
Negative input of differential CW 16X clock. Tie to GND when the CMOS clock mode is enabled. In the
4X and 8X CW clock modes, this pin becomes the 4X or 8X CLKM input. In the 1X CW clock mode,
this pin becomes the in-phase 1X CLKM for the CW mixer. Can be floated if CW mode is not used.
F8
CLKP_16X
Positive input of differential CW 16X clock. In 4X and 8X clock modes, this pin becomes the 4X or 8X
CLKP input. In the 1X CW clock mode, this pin becomes the in-phase 1X CLKP for the CW mixer. Can
be floated if CW mode is not used.
G9
CLKM_1X
Negative input of differential CW 1X clock. Tie to GND when the CMOS clock mode is enabled (Refer
to Figure 88 for details). In the 1X clock mode, this pin is the quadrature-phase 1X CLKM for the CW
mixer. Can be floated if CW mode is not used.
G8
CLKP_1X
Positive input of differential CW 1X clock. In the 1X clock mode, this pin is the quadrature-phase 1X
CLKP for the CW mixer. Can be floated if CW mode is not used.
B1
CM_BYP
Bias voltage and bypass to ground. ≥ 1 µF is recommended. To suppress the ultra low frequency
noise, 10 µF can be used.
E2
CW_IP_AMPINM
Negative differential input of the In-phase summing amplifier. External LPF capacitor has to be
connected between CW_IP_AMPINM and CW_IP_OUTP. This pin becomes the CH7 PGA negative
output when PGA test mode is enabled. Can be floated if not used.
E1
CW_IP_AMPINP
Positive differential input of the In-phase summing amplifier. External LPF capacitor has to be
connected between CW_IP_AMPINP and CW_IP_OUTM. This pin becomes the CH7 PGA positive
output when PGA test mode is enabled. Can be floated if not used.
4
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SLOS688D – SEPTEMBER 2010 – REVISED JANUARY 2014
Table 3. PIN FUNCTIONS (continued)
PIN
DESCRIPTION
NO.
NAME
F1
CW_IP_OUTM
Negative differential output for the In-phase summing amplifier. External LPF capacitor has to be
connected between CW_IP_AMPINP and CW_IP_OUTPM. Can be floated if not used.
F2
CW_IP_OUTP
Positive differential output for the In-phase summing amplifier. External LPF capacitor has to be
connected between CW_IP_AMPINM and CW_IP_OUTP. Can be floated if not used.
J2
CW_QP_AMPIN
M
Negative differential input of the quadrature-phase summing amplifier. External LPF capacitor has to
be connected between CW_QP_AMPINM and CW_QP_OUTP. This pin becomes CH8 PGA negative
output when PGA test mode is enabled. Can be floated if not used.
J1
Positive differential input of the quadrature-phase summing amplifier. External LPF capacitor has to be
CW_QP_AMPINP connected between CW_QP_AMPINP and CW_QP_OUTM. This pin becomes CH8 PGA positive
output when PGA test mode is enabled. Can be floated if not used.
H1
CW_QP_OUTM
Negative differential output for the quadrature-phase summing amplifier. External LPF capacitor has to
be connected between CW_QP_AMPINP and CW_QP_OUTM. Can be floated if not used.
H2
CW_QP_OUTP
Positive differential output for the quadrature-phase summing amplifier. External LPF capacitor has to
be connected between CW_QP_AMPINM and CW_QP_OUTP. Can be floated if not used.
N8, P9~P7,
P3~P1, N2
D1M~D8M
ADC CH1~8 LVDS negative outputs
N9, R9~R7,
R3~R1, N1
D1P~D8P
ADC CH1~8 LVDS positive outputs
P6
DCLKM
LVDS bit clock (7x) negative output
R6
DCLKP
LVDS bit clock (7x) positive output
K7,
L5~L7,M5~M8, DNC
N4, N6
Do not connect. Must leave floated
N3, N7
DVDD
ADC digital and I/O power supply, 1.8 V
N5, P5, R5
DVSS
ADC digital ground
P4
FCLKM
LVDS frame clock (1X) negative output
R4
FCLKP
LVDS frame clock (1X) positive output
C9~C2
INM1…INM8
CH1~8 complimentary analog inputs. Bypass to ground with ≥ 0.015-µF capacitors. The HPF response
of the LNA depends on the capacitors.
A9~A2
INP1...INP8
CH1~8 analog inputs. AC couple to inputs with ≥ 0.1-µF capacitors.
L8
PDN_ADC
ADC partial (fast) power down control pin with an internal pull down resistor of 100 kΩ. Active High.
J8
PDN_VCA
VCA partial (fast) power down control pin with an internal pull down resistor of 20 kΩ. Active High.
H8
PDN_GLOBAL
Global (complete) power-down control pin for the entire chip with an internal pull down resistor of 20
kΩ. Active High.
L4
REFM
0.5V reference output in the internal reference mode. Must leave floated in the internal reference
mode. Adding a test point on the PCB is recommended for monitoring the reference output.
M4
REFP
1.5V reference output in the internal reference mode. Must leave floated in the internal reference
mode. Adding a test point on the PCB is recommended for monitoring the reference output.
H9
RESET
Hardware reset pin with an internal pull-down resistor of 20 kΩ. Active high.
J9
SCLK
Serial interface clock input with an internal pull-down resistor of 20 kΩ
K9
SDATA
Serial interface data input with an internal pull-down resistor of 20 kΩ
M9
SDOUT
Serial interface data readout. High impedance when readout is disabled.
L9
SEN
Serial interface enable with an internal pull up resistor of 20 kΩ. Active low.
K4
VCNTLM
Negative differential attenuation control pin.
K3
VCNTLP
Positive differential attenuation control pin
K5
VHIGH
Bias voltage; bypass to ground with ≥ 1 µF.
M3
VREF_IN
ADC 1.4V reference input in the external reference mode; bypass to ground with 0.1 µF.
K7, L5~L7,
M5~M8, N4,
N6
DNC
Do not connect. Must leave floated
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AFE5808
SLOS688D – SEPTEMBER 2010 – REVISED JANUARY 2014
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ELECTRICAL CHARACTERISTICS
AVDD_5V = 5V, AVDD = 3.3V, AVDD_ADC = 1.8V, DVDD = 1.8V, AC-coupled with 0.1 µF at INP and bypassed to ground
with 15nF at INM, No active termination, VCNTL= 0 V, fIN= 5 MHz, LNA = 18 dB, PGA = 24 dB, 14 Bit, sample rate = 65 MSPS,
LPF Filter = 15 MHz, low noise mode, VOUT = –1 dBFS, internal 500-Ω CW feedback resistor, CMOS CW clocks, ADC
configured in internal reference mode, Single-ended VCNTL mode, VCNTLM = GND, at ambient temperature TA = 25°C,
unless otherwise noted. Min and max values are specified across full-temperature range with AVDD_5V = 5 V, AVDD = 3.3
V, AVDD_ADC = 1.8 V, DVDD = 1.8 V
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
TGC FULL SIGNAL CHANNEL (LNA+VCAT+LPF+ADC)
en (RTI)
Input voltage noise over LNA Gain(low
noise mode)
Rs = 0 Ω, f = 2 MHz, LNA = 24/18/12 dB, PGA = 24 dB
0.76/0.83/1.16
Rs = 0 Ω, f = 2 MHz,LNA = 24/18/12 dB, PGA = 30 dB
0.75/0.86/1.12
Input voltage noise over LNA Gain(low
power mode)
Rs = 0 Ω, f = 2 MHz,LNA = 24/18/12 dB, PGA = 24 dB
1.1/1.2/1.45
Rs = 0 Ω, f = 2 MHz, LNA = 24/18/12 dB, PGA = 30 dB
1.1/1.2/1.45
Input Voltage Noise over LNA
Gain(Medium Power Mode)
Rs = 0 Ω, f = 2 MHz,LNA = 24/18/12 dB, PGA = 24 dB
1/1.05/1.25
Rs = 0 Ω, f = 2 MHz, LNA = 24/18/12 dB, PGA = 30 dB
0.95/1.0/1.2
Rs = 200 Ω, 200-Ω active termination, PGA = 24 dB, LNA = 12/18/24 dB
3.85/2.4/1.8
dB
Rs = 100 Ω, 100-Ω active termination, PGA = 24 dB, LNA = 12/18/24 dB
5.3/3.1/2.3
dB
nV/rtHz
nV/rtHz
nV/rtHz
Input referred current noise
NF
2.7
Noise figure
VMAX
Maximum Linear Input Voltage
LNA gain = 24/18/12 dB
250/500/1000
VCLAMP
Clamp Voltage
Reg52[10:9] = 0, LNA = 24/18/12 dB
350/600/1150
pA/rtHz
mVpp
Low noise mode
24/30
PGA Gain
dB
Medium/Low power mode
24/28.5
LNA = 24 dB, PGA = 30 dB, Low noise mode
Total gain
Ch-CH Noise Correlation Factor without
Signal (1)
Ch-CH Noise Correlation Factor with
Signal (1)
54
LNA = 24 dB, PGA = 30 dB, Med power mode
52.5
LNA = 24 dB, PGA = 30 dB, Low power mode
52.5
Summing of 8 channels
0
Full band (VCNTL = 0/0.8)
0.15/0.17
1MHz band over carrier (VCNTL= 0/0.8)
0.18/0.75
VCNTL= 0.6 V (22-dB total channel gain)
Signal to Noise Ratio (SNR)
dB
VCNTL= 0, LNA = 18 dB, PGA = 24 dB
68
70
59.3
63
VCNTL = 0, LNA = 24 dB, PGA = 24 dB
dBFS
58
Narrow Band SNR
SNR over 2 MHz band around carrier at VCNTL = 0.6 V (22-dB total
gain)
Input Common-mode Voltage
At INP and INM pins
75
77
dBFS
2.4
V
8
kΩ
Input resistance
Preset active termination enabled
Input capacitance
Input Control Voltage
VCNTLP-VCNTLM
Common-mode voltage
VCNTLP and VCNTLM
Gain Range
pF
0
1.5
V
0.75
V
–40
dB
VCNTL= 0.1 to 1.1 V
35
dB/V
Input Resistance
Between VCNTLP and VCNTLM
200
KΩ
Input Capacitance
Between VCNTLP and VCNTLM
1
pF
TGC Response Time
VCNTL= 0 to 1.5 V step function
1.5
10, 15, 20, 30
Settling time for change in LNA gain
Settling time for change in active
termination setting
µs
MHz
14
µs
1
µs
Noise correlation factor is defined as Nc / (Nu + Nc), where Nc is the correlated noise power in single channel; and Nu is the
uncorrelated noise power in single channel. Its measurement follows the below equation, in which the SNR of single channel signal and
the SNR of summed eight channel signal are measured.
NC
10
8CH_SNR
10
10
=
Nu + NC
6
Ω
20
Gain Slope
3rd order-Low-pass Filter
(1)
50/100/200/400
1CH_SNR
1
x
1
-
56
7
10
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ELECTRICAL CHARACTERISTICS (continued)
AVDD_5V = 5V, AVDD = 3.3V, AVDD_ADC = 1.8V, DVDD = 1.8V, AC-coupled with 0.1 µF at INP and bypassed to ground
with 15nF at INM, No active termination, VCNTL= 0 V, fIN= 5 MHz, LNA = 18 dB, PGA = 24 dB, 14 Bit, sample rate = 65 MSPS,
LPF Filter = 15 MHz, low noise mode, VOUT = –1 dBFS, internal 500-Ω CW feedback resistor, CMOS CW clocks, ADC
configured in internal reference mode, Single-ended VCNTL mode, VCNTLM = GND, at ambient temperature TA = 25°C,
unless otherwise noted. Min and max values are specified across full-temperature range with AVDD_5V = 5 V, AVDD = 3.3
V, AVDD_ADC = 1.8 V, DVDD = 1.8 V
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
AC ACCURACY
LPF Bandwidth tolerance
±5%
CH-CH group delay variation
2 to 15 MHz
CH-CH Phase variation
15-MHz signal
0 V < VCNTL< 0.1 V (Dev-to-Dev)
2
ns
11
Degree
±0.5
0.1 V < VCNTL < 1.1 V (Dev-to-Dev)
–0.9
±0.5
0.9
0.1 V < VCNTL < 1.1 V (Dev-to-Dev), Temp = 0°C and 85°C
–1.1
±0.5
1.1
Gain matching
dB
1.1 V < VCNTL < 1.5 V (Dev-to-Dev)
Gain matching
Channel-to-Channel
Output offset
VCNTL = 0, PGA = 30 dB, LNA = 24 dB
±0.5
±0.25
–75
dB
75
LSB
AC PERFORMANCE
HD2
HD3
THD
Second-Harmonic Distortion
Third-Harmonic Distortion
Total Harmonic Distortion
Fin = 2 MHz; VOUT = –1 dBFS
–60
Fin = 5 MHz; VOUT = –1 dBFS
–60
Fin = 5 MHz; VIN = 500 mVpp,
VOUT = –1 dBFS, LNA = 18 dB, VCNTL = 0.88 V
–55
Fin = 5 MHz; VIN = 250 mVpp,
VOUT = –1 dBFS, LNA = 24 dB, VCNTL= 0.88 V
–55
Fin = 2 MHz; VOUT = –1 dBFS
–55
Fin = 5 MHz; VOUT = –1 dBFS
–55
Fin = 5 MHz; VIN = 500 mVpp,
VOUT = –1 dBFS, LNA = 18 dB, VCNTL = 0.88 V
–55
Fin = 5 MHz; VIN = 250 mVpp,
VOUT = –1 dBFS, LNA = 24 dB, VCNTL = 0.88 V
–55
Fin = 2 MHz; VOUT = –1 dBFS
–55
Fin = 5 MHz; VOUT = –1 dBFS
–55
–60
IMD3
Intermodulation distortion
f1 = 5 MHz at –1 dBFS,
f2 = 5.01 MHz at –27 dBFS
XTALK
Cross-talk
Fin = 5 MHz; VOUT = –1 dBFS
Phase Noise
1 kHz off 5 MHz (VCNTL= 0 V)
Input Referred Voltage Noise
Rs = 0 Ω, f = 2 MHz, Rin = High Z, Gain = 24/18/12 dB
High-Pass Filter
–3 dB Cut-off Frequency
dBc
dBc
dBc
dBc
–65
dB
–132
dBc/Hz
0.63/0.70/0.9
nV/rtHz
LNA
LNA linear output
50/100/150/200
kHz
4
Vpp
VCAT+ PGA
VCAT Input Noise
0 dB/–40 dB Attenuation
PGA Input Noise
24 dB/30 dB
-3 dB HPF cut-off Frequency
2/10.5
nV/rtHz
1.75
nV/rtHz
80
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ELECTRICAL CHARACTERISTICS (continued)
AVDD_5V = 5V, AVDD = 3.3V, AVDD_ADC = 1.8V, DVDD = 1.8V, AC-coupled with 0.1 µF at INP and bypassed to ground
with 15nF at INM, No active termination, VCNTL= 0 V, fIN= 5 MHz, LNA = 18 dB, PGA = 24 dB, 14 Bit, sample rate = 65 MSPS,
LPF Filter = 15 MHz, low noise mode, VOUT = –1 dBFS, internal 500-Ω CW feedback resistor, CMOS CW clocks, ADC
configured in internal reference mode, Single-ended VCNTL mode, VCNTLM = GND, at ambient temperature TA = 25°C,
unless otherwise noted. Min and max values are specified across full-temperature range with AVDD_5V = 5 V, AVDD = 3.3
V, AVDD_ADC = 1.8 V, DVDD = 1.8 V
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
CW DOPPLER
en (RTI)
en (RTO)
en (RTI)
en (RTO)
NF
0.8
8 channel mixer, LNA = 24 dB, 62.5-Ω feedback resistor
0.33
1 channel mixer, LNA = 24 dB, 500-Ω feedback resistor
12
8 channel mixer, LNA = 24 dB, 62.5-Ω feedback resistor
5
1 channel mixer, LNA = 18 dB, 500-Ω feedback resistor
1.1
8 channel mixer, LNA = 18 dB, 62.5-Ω feedback resistor
0.5
1 channel mixer, LNA = 18 dB, 500-Ω feedback resistor
8.1
8 channel mixer, LNA = 18 dB, 62.5-Ω feedback resistor
4.0
Rs = 100 Ω, RIN = High Z, fin = 2 MHz (LNA, I/Q mixer and summing
amplifier/filter)
1.8
nV/rtHz
Output voltage noise (CW)
nV/rtHz
Input voltage noise (CW)
nV/rtHz
Output voltage noise (CW)
Noise figure
fCW
1 channel mixer, LNA = 24 dB, 500-Ω feedback resistor
Input voltage noise (CW)
CW Operation Range
(2)
CW Clock frequency
nV/rtHz
dB
CW signal carrier frequency
8
1X CLK (16X mode)
8
16X CLK(16X mode)
128 (3)
4X CLK(4X mode)
MHz
32
AC coupled LVDS clock amplitude
0.7
CLKM_16X-CLKP_16X; CLKM_1X-CLKP_1X
Vpp
AC coupled LVPECL clock amplitude
VCMOS
MHz
1.6
CLK duty cycle
1X and 16X CLKs
Common-mode voltage
Internal provided
33%
66%
2.5
CMOS Input clock amplitude
4
CW Mixer conversion loss
V
5
4
CW Mixer phase noise
1kHz off 2MHz carrier
DR
Input dynamic range
FIN = 2 MHz, LNA = 24/18/12 dB
IMD3
Intermodulation distortion
V
dB
156
dBc/Hz
160/164/165
dBFS/Hz
f1 = 5 MHz, f2 = 5.01 MHz, both tones at –8.5-dBm amplitude, 8
channels summed up in-phase, CW feedback resistor = 87 Ω
–50
dBc
f1 = 5 MHz, f2= 5.01 MHz, both tones at –8.5-dBm amplitude, Single
channel case, CW feed back resistor = 500 Ω
–60
dBc
I/Q Channel gain matching
16X mode
±0.04
dB
I/Q Channel phase matching
16X mode
±0.1
Degree
I/Q Channel gain matching
4X mode
±0.04
dB
I/Q Channel phase matching
4X mode
±0.1
Degree
Image rejection ratio
fin = 2.01 MHz, 300-mV input amplitude, CW clock frequency = 2.00
MHz
–50
dBc
Summing amplifier inputs/outputs
1.5
CW SUMMING AMPLIFIER
VCMO
Common-mode voltage
Summing amplifier output
100 Hz
V
4
Vpp
2
nV/rtHz
1.2
nV/rtHz
1
nV/rtHz
Input referred current noise
2.5
pA/rtHz
Unit gain bandwidth
200
MHz
20
mApp
Input referred voltage noise
1 kHz
2 kHz to 100 MHz
Max output current
Linear operation range
ADC SPECIFICATIONS
Sample rate
SNR
Signal-to-noise ratio
10
65
MSPS
Idle channel SNR of ADC 14b
77
dBFS
REFP
1.5
V
REFM
0.5
V
Internal reference mode
(2)
(3)
8
In the 16X operation mode, the CW operation range is limited to 8 MHz due to the 16X CLK. The maximum clock frequency for the 16X
CLK is 128 MHz. In the 8X, 4X, and 1X modes, higher CW signal frequencies up to 15 MHz can be supported with small degradation in
performance, see application information: CW clock selection. .
After January, 2014, that is date code after 41XXXXX, the CW Clock frequency ( 16X mode) can be supported up to 145 MHz and
approximately 33 to 50% duty cycle based on additional test screening.
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ELECTRICAL CHARACTERISTICS (continued)
AVDD_5V = 5V, AVDD = 3.3V, AVDD_ADC = 1.8V, DVDD = 1.8V, AC-coupled with 0.1 µF at INP and bypassed to ground
with 15nF at INM, No active termination, VCNTL= 0 V, fIN= 5 MHz, LNA = 18 dB, PGA = 24 dB, 14 Bit, sample rate = 65 MSPS,
LPF Filter = 15 MHz, low noise mode, VOUT = –1 dBFS, internal 500-Ω CW feedback resistor, CMOS CW clocks, ADC
configured in internal reference mode, Single-ended VCNTL mode, VCNTLM = GND, at ambient temperature TA = 25°C,
unless otherwise noted. Min and max values are specified across full-temperature range with AVDD_5V = 5 V, AVDD = 3.3
V, AVDD_ADC = 1.8 V, DVDD = 1.8 V
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
VREF_IN Voltage
1.4
V
VREF_IN Current
50
µA
65MSPS at 14 bit
910
External reference mode
ADC input full-scale range
LVDS Rate
2
Vpp
Mbps
POWER DISSIPATION
AVDD Voltage
3.15
3.3
3.6
V
1.7
1.8
1.9
V
4.75
5
5.5
V
1.7
1.8
1.9
V
TGC low noise mode, 65MSPS
153
175
TGC low noise mode, 40MSPS
142
TGC medium power mode, 40MSPS
110
AVDD_ADC Voltage
AVDD_5V Voltage
DVDD Voltage
Total power dissipation per channel
mW/CH
TGC low power mode, 40MSPS
98
TGC low noise mode, no signal
203
TGC medium power mode, no signal
126
TGC low power mode, no signal
235
99
CW-mode, no signal
147
TGC low noise mode, 500-mVpp Input,1% duty cycle
210
TGC medium power mode, 500-mVpp Input, 1% duty cycle
133
TGC low power, 500-mVpp Input, 1% duty cycle
105
170
AVDD (3.3V) Current
mA
CW-mode, 500-mVpp Input
375
TGC mode no signal
16.5
CW Mode no signal, 16X clock = 32 MHz
22
32
AVDD_5V Current
mA
TGC mode, 500mVpp Input,1% duty cycle
16.5
CW-mode, 500mVpp Input
42.5
TGC low noise mode, no signal
93.5
TGC medium power mode, no signal
62
TGC low power mode, no signal
50
TGC low noise mode, 500-mVpp input,1% duty cycle
97
TGC medium power mode, 500-mVpp Input, 1% duty cycle
65
TGC low power mode, 500-mVpp input,1% duty cycle
54
107
VCA Power dissipation
CW Power dissipation
mW/CH
No signal, ADC shutdown CW Mode no signal, 16X clock = 32 MHz
80
mW/CH
500mVpp input, ADC shutdown , 16X clock = 32 MHz
173
AVDD_ADC (1.8 V) Current
65 MSPS
187
205
DVDD (1.8 V) Current
65 MSPS
77
110
mA
ADC Power dissipation/CH
65 MSPS
59
69
mW/CH
50 MSPS
51
40 MSPS
46
20 MSPS
35
Power dissipation in power down mode
25
Complete power-down PDN_Globa l= High
0.6
mW/CH
Power-down response time
Time taken to enter power down
1
µs
Power-up response time
VCA power down
2µs+1% of PDN
time
µs
ADC power down
1
Power supply modulation ratio, AVDD and
AVDD_5V
(4)
PDN_VCA = High, PDN_ADC = High
mA
Complete power down
2.5
ms
fin = 5 MHz, at 50-mVpp noise at 1 kHz on supply (4)
–65
dBc
fin = 5 MHz, at 50-mVpp noise at 50 kHz on supply (4)
–65
dBc
PSMR specification is with respect to input signal amplitude.
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ELECTRICAL CHARACTERISTICS (continued)
AVDD_5V = 5V, AVDD = 3.3V, AVDD_ADC = 1.8V, DVDD = 1.8V, AC-coupled with 0.1 µF at INP and bypassed to ground
with 15nF at INM, No active termination, VCNTL= 0 V, fIN= 5 MHz, LNA = 18 dB, PGA = 24 dB, 14 Bit, sample rate = 65 MSPS,
LPF Filter = 15 MHz, low noise mode, VOUT = –1 dBFS, internal 500-Ω CW feedback resistor, CMOS CW clocks, ADC
configured in internal reference mode, Single-ended VCNTL mode, VCNTLM = GND, at ambient temperature TA = 25°C,
unless otherwise noted. Min and max values are specified across full-temperature range with AVDD_5V = 5 V, AVDD = 3.3
V, AVDD_ADC = 1.8 V, DVDD = 1.8 V
PARAMETER
Power supply rejection ratio
10
TEST CONDITION
MIN
TYP
MAX
UNIT
f = 10 kHz,VCNTL = 0 V (high gain), AVDD
–40
dBc
f = 10 kHz,VCNTL = 0 V (high gain), AVDD_5V
–55
dBc
f = 10 kHz,VCNTL = 1 V (low gain), AVDD
–50
dBc
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SLOS688D – SEPTEMBER 2010 – REVISED JANUARY 2014
DIGITAL CHARACTERISTICS
Typical values are at +25°C, AVDD = 3.3 V, AVDD_5 = 5 V and AVDD_ADC = 1.8 V, DVDD = 1.8 V unless otherwise noted.
Minimum and maximum values are across the full temperature range: TMIN = 0°C to TMAX = +85°C.
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT (1)
DIGITAL INPUTS AND OUTPUTS
VIH
Logic high input voltage
2
3.3
VIL
Logic low input voltage
0
0.3
V
V
Logic high input current
200
µA
Logic low input current
200
µA
5
pF
VOH
Input capacitance
Logic high output voltage
SDOUT pin
DVDD
V
VOL
Logic low output voltage
SDOUT pin
0
V
LVDS OUTPUTS
Output differential voltage
With 100-Ω external differential
termination
Output offset voltage
Common-mode voltage
FCLKP and FCLKM
1X clock rate
10
65
MHz
DCLKP and DCLKM
7X clock rate
70
455
MHz
6X clock rate
60
390
MHz
400
1100
(2)
tsu
Data setup time
th
Data hold time (2)
mV
mV
350
ps
350
ps
ADC INPUT CLOCK
CLOCK frequency
10
Clock duty cycle
45%
Sine-wave, AC-coupled
Clock input amplitude,
differential(VCLKP_ADC–VCLKM_ADC)
Common-mode voltage
(2)
MSPS
55%
0.5
Vpp
LVPECL, AC-coupled
1.6
Vpp
LVDS, AC-coupled
0.7
Vpp
biased internally
Clock input amplitude VCLKP_ADC (singleCMOS CLOCK
ended)
(1)
65
50%
1
1.8
V
Vpp
The DC specifications refer to the condition where the LVDS outputs are not switching, but are permanently at a valid logic level 0 or 1
with 100-Ω external termination.
Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume
that the data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear
as reduced timing margins
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TYPICAL CHARACTERISTICS
AVDD_5V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, AC-coupled with 0.1-µF caps at INP and
15-nF caps at INM, No active termination, VCNTL = 0 V, FIN = 5 MHz, LNA = 18 dB, PGA = 24 dB, 14Bit,
sample rate = 65 MSPS, LPF Filter = 15 MHz, low noise mode, VOUT = –1 dBFS, 500-Ω CW feedback resistor,
CMOS 16X clock, ADC is configured in internal reference mode, Single-ended VCNTL mode, VCNTLM = GND.
at ambient temperature TA = +25°C, unless otherwise noted.
SPACER
45.0
45.0
Low noise
Medium power
Low power
40.0
35.0
35.0
30.0
Gain (dB)
Gain (dB)
30.0
25.0
20.0
20.0
15.0
10.0
10.0
5.0
5.0
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
Vcntl (V)
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Vcntl (V)
Figure 2. Gain vs VCNTL, LNA = 18 dB and PGA = 24 dB
Figure 3. Gain Variation vs Temperature, LNA = 18 dB and
PGA = 24 dB
250
Number of Occurrences
250
Number of Occurrences
25.0
15.0
300
200
150
100
0
200
150
100
50
50
−0.4 −0.3 −0.2 −0.1
0
0.1 0.2
Gain Error (dB)
0.3
0.4
0.5
0.6
Figure 4. Gain Matching Histogram, VCNTL = 0.3 V
(936 channels)
12
−40 deg C
25 deg C
85 deg C
40.0
0
−0.6 −0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5 0.6
Gain Error (dB)
Figure 5. Gain Matching Histogram, VCNTL = 0.6 V
(936 channels)
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SLOS688D – SEPTEMBER 2010 – REVISED JANUARY 2014
TYPICAL CHARACTERISTICS (continued)
60
180
160
Number of Occurrences
Number of Occurrences
50
140
120
100
80
60
40
40
30
20
10
20
0
0
−0.9−0.8−0.7−0.6−0.5−0.4−0.3−0.2−0.1 0
Gain Error (dB)
0.1 0.2 0.3 0.4
−50
Figure 6. Gain Matching Histogram, VCNTL = 0.9 V
(936 channels)
−40
−30
−20
−10
0
10
ADC Output
20
30
40
50
Figure 7. Output Offset Histogram, VCNTL = 0 V
(936 channels)
Impedance Magnitude Response
Impedance Phase Response
10
Open
12000
−10
Phase (Degrees)
10000
Impedance (Ohms)
Open
0
8000
6000
4000
−20
−30
−40
−50
−60
−70
2000
500k
−80
4.5M
8.5M
12.5M
16.5M
−90
500k
20.5M
4.5M
8.5M
Frequency (Hz)
20.5M
Figure 9. Input Impedance Without Active Termination
(Phase)
Impedance Magnitude Response
Impedance Phase Response
500
10
50 Ohms
100 Ohms
200 Ohms
400 Ohms
450
400
350
0
−10
Phase (Degrees)
Impedance (Ohms)
16.5M
Frequency (Hz)
Figure 8. Input Impedance Without Active Termination
(Magnitude)
300
250
200
150
−20
−30
−40
−50
−60
100
−70
50
−80
0
500k
12.5M
4.5M
8.5M
12.5M
16.5M
20.5M
−90
500k
Frequency (Hz)
50 Ohms
100 Ohms
200 Ohms
400 Ohms
4.5M
8.5M
12.5M
16.5M
20.5M
Frequency (Hz)
Figure 10. Input Impedance With Active Termination
(Magnitude)
Figure 11. Input Impedance With Active Termination (Phase)
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TYPICAL CHARACTERISTICS (continued)
LNA INPUT HPF CHARACTERISTICS
5
10MHz
15MHz
20MHz
30MHz
0
0
−3
−6
Amplitude (dB)
Amplitude (dB)
−5
3
−10
−15
−20
−9
−12
−15
−18
−21
−25
−30
01
00
11
10
−24
−27
0
10
20
30
40
50
60
−30
Frequency (MHz)
10
100
500
Frequency (KHz)
Figure 12. Low-Pass Filter Response
Figure 13. LNA High-Pass Filter Response vs Reg59[3:2]
HPF CHARACTERISTICS (LNA+VCA+PGA+ADC)
−144
−148
−5
−150
−10
−15
−20
−25
−30
−152
−154
−156
−158
−160
−162
−164
−168
10
100
−170
100
500
Frequency (KHz)
−144
−144
16X Clock Mode
8X Clock Mode
4X Clock Mode
−148
−150
Phase Noise (dBc/Hz)
−150
Phase Noise (dBc/Hz)
50000
Eight Channel CW PN
−146
PN 1 Ch
PN 8 Ch
−148
−152
−154
−156
−158
−160
−162
−164
−152
−154
−156
−158
−160
−162
−164
−166
−166
−168
−168
1000
10000
Figure 15. CW Phase Noise, Fin = 2 MHz
Phase Noise
−146
−170
100
1000
Offset frequency (Hz)
Figure 14. Full Channel High-Pass Filter Response at
Default Register Setting
10000
50000
−170
100
Frequency Offset (Hz)
1000
10000
50000
Offset frequency (Hz)
Figure 16. CW Phase Noise, Fin = 2 MHz, 1 Channel vs 8
Channel
14
16X Clock Mode
8X Clock Mode
4X Clock Mode
−166
−35
−40
Single Channel CW PN
−146
0
Phase Noise (dBc/Hz)
Amplitude (dB)
5
Figure 17. CW Phase Noise vs Clock Modes, Fin = 2 MHz
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TYPICAL CHARACTERISTICS (continued)
Hz)
40.0
3.5
LNA 12 dB
LNA 18 dB
LNA 24 dB
Input reffered noise (nV
Hz)
50.0
Input reffered noise (nV
60.0
30.0
20.0
10.0
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Vcntl (V)
Hz)
50.0
Input reffered noise (nV
Hz)
Input reffered noise (nV
1.5
1.0
0.5
0.1
0.2
Vcntl (V)
0.3
0.4
4.0
LNA 12 dB
LNA 18 dB
LNA 24 dB
40.0
30.0
20.0
10.0
3.5
LNA 12 dB
LNA 18 dB
LNA 24 dB
3.0
2.5
2.0
1.5
1.0
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Vcntl (V)
0.5
0.0
Figure 20. IRN, PGA = 24 dB and Medium Power Mode
Figure 21. IRN, PGA = 24 dB and Medium Power Mode
70.0
Hz)
60.0
0.1
0.2
Vcntl (V)
0.3
0.4
4.0
LNA 12 dB
LNA 18 dB
LNA 24 dB
50.0
Input reffered noise (nV
Hz)
2.0
Figure 19. IRN, PGA = 24 dB and Low Noise Mode
70.0
Input reffered noise (nV
LNA 12 dB
LNA 18 dB
LNA 24 dB
2.5
0.0
0.0
Figure 18. IRN, PGA = 24 dB and Low Noise Mode
60.0
3.0
40.0
30.0
20.0
10.0
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Vcntl (V)
Figure 22. IRN, PGA = 24 dB and Low Power Mode
3.5
LNA 12 dB
LNA 18 dB
LNA 24 dB
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.1
0.2
Vcntl (V)
0.3
0.4
Figure 23. IRN, PGA = 24 dB and Low Power Mode
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TYPICAL CHARACTERISTICS (continued)
190.0
170.0
300.0
280.0
260.0
240.0
220.0
200.0
180.0
160.0
140.0
120.0
100.0
80.0
60.0
40.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Vcntl (V)
Hz)
LNA 12 dB
LNA 18 dB
LNA 24 dB
Output reffered noise (nV
Output reffered noise (nV
Hz)
220.0
210.0
150.0
130.0
110.0
90.0
70.0
50.0
30.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Vcntl (V)
1.2
LNA 12 dB
LNA 18 dB
LNA 24 dB
1.1
1.0
Hz)
340.0
320.0
300.0
280.0
260.0
240.0
220.0
200.0
180.0
160.0
140.0
120.0
100.0
80.0
60.0
40.0
1.0 1.1 1.2
Figure 25. ORN, PGA = 24 dB and Medium Power Mode
Amplitude (nV
Output reffered noise (nV
Hz)
Figure 24. ORN, PGA = 24 dB and Low Noise Mode
LNA 12 dB
LNA 18 dB
LNA 24 dB
0.9
0.8
0.7
0.6
0.5
0.4
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Vcntl (V)
1
0.3
1.0
1.1 1.2
Figure 26. ORN, PGA = 24 dB and Low Power Mode
2.0
3.0
4.0
5.0 6.0 7.0 8.0
Frequency (MHz)
9.0 10.0 11.0 12.0
Figure 27. IRN, PGA = 24 dB and Low Noise Mode
75.0
180.0
120.0
70.0
SNR (dBFS)
Hz)
140.0
Amplitude (nV
160.0
100.0
80.0
65.0
60.0
60.0
40.0
1.0
24 dB PGA gain
30 dB PGA gain
3.0
5.0
7.0
Frequency (MHz)
9.0
11.0 12.0
Figure 28. ORN, PGA = 24 dB and Low Noise Mode
16
55.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Vcntl (V)
Figure 29. SNR, LNA = 18 dB and Low Noise Mode
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TYPICAL CHARACTERISTICS (continued)
75.0
73.0
Low noise
Low power mode
71.0
69.0
SNR (dBFS)
SNR (dBFS)
70.0
65.0
60.0
67.0
65.0
63.0
61.0
59.0
24 dB PGA gain
30 dB PGA gain
55.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Vcntl (V)
57.0
0
Figure 30. SNR, LNA = 18 dB and Low Power Mode
9.0
8.0
6.0
5.0
4.0
3.0
7.0
4.0
3.0
2.0
1.0
100.0
150.0
200.0
250.0
300.0
350.0
0.0
50.0
400.0
50 ohm act term
100 ohm act term
200 ohm act term
400 ohm act term
Without Termination
5.0
1.0
100.0
Source Impedence (Ω)
250.0
300.0
350.0
400.0
4.5
50 ohm act term
100 ohm act term
200 ohm act term
400 ohm act term
No Termination
Low noise
Low power
Medium power
Noise Figure (dB)
Noise Figure (dB)
200.0
Figure 33. Noise Figure, LNA = 18 dB and Low Noise Mode
8.0
6.0
150.0
Source Impedence (Ω)
Figure 32. Noise Figure, LNA = 12 dB and Low Noise Mode
7.0
12 15 18 21 24 27 30 33 36 39 42
Gain (dB)
6.0
2.0
0.0
50.0
9
10.0
100 ohm act term
200 ohm act term
400 ohm act term
Without Termination
Noise Figure (dB)
Noise Figure (dB)
7.0
6
Figure 31. SNR vs Different Power Modes
9.0
8.0
3
5.0
4.0
3.0
3.5
2.5
2.0
1.0
0.0
50.0
100.0
150.0
200.0
250.0
300.0
350.0
400.0
1.5
50.0
Source Impedence (Ω)
100.0
150.0
200.0
250.0
300.0
350.0
400.0
Source Impedence (Ω)
Figure 34. Noise Figure, LNA = 24 dB and Low Noise Mode
Figure 35. Noise Figure vs Power Modes With 400-Ω
Termination
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TYPICAL CHARACTERISTICS (continued)
4.0
−50
Low noise
Low power
Medium power
Low noise
Medium power
Low power
−52
HD2 (dBc)
Noise Figure (dB)
−54
3.0
2.0
−56
−58
−60
−62
−64
1.0
50.0
100.0
150.0
200.0
250.0
300.0
350.0
−66
400.0
1
2
3
Source Impedence (Ω)
4
5
6
7
8
9
10
Frequency (MHz)
Figure 36. Noise Figure vs Power Modes Without
Termination
Figure 37. HD2 vs Frequency, VIN = 500 mVPP and
VOUT = –1 dBFS
−40
−50
−55
Low noise
Medium power
Low power
−50
HD2 (dBc)
HD3 (dBc)
−60
−65
−60
−70
−70
−80
−80
Low noise
Medium power
Low power
−75
1
2
3
4
5
6
7
8
9
−90
10
6
12
18
Frequency (MHz)
−40
Low noise
Medium power
Low power
−60
−70
−80
Low noise
Medium power
Low power
−50
HD2 (dBc)
−50
HD3 (dBc)
36
Figure 39. HD2 vs Gain, LNA = 12 dB and PGA = 24 dB and
VOUT = –1 dBFS
−40
−60
−70
−80
6
12
18
24
30
36
−90
12
Gain (dB)
18
24
30
36
42
Gain (dB)
Figure 40. HD3 vs Gain, LNA = 12 dB and PGA = 24 dB and
VOUT = –1 dBFS
18
30
Gain (dB)
Figure 38. HD3 vs Frequency, VIN = 500 mVPP and
VOUT = –1 dBFS
−90
24
Figure 41. HD2 vs Gain, LNA = 18 dB and PGA = 24 dB and
VOUT = –1 dBFS
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TYPICAL CHARACTERISTICS (continued)
−40
−40
Low noise
Medium power
Low power
−50
HD2 (dBc)
HD3 (dBc)
−50
−60
−70
−60
−70
−80
−90
Low noise
Medium Power
Low power
−80
12
18
24
30
36
−90
42
18
24
30
Gain (dB)
−50.0
Fin1=2MHz, Fin2=2.01MHz
Fin1=5MHz, Fin2=5.01MHz
Low noise
Medium power
Low power
−54.0
IMD3 (dBFS)
−50
−60
−70
−58.0
−62.0
−66.0
−80
18
21
24
27
30
33
36
39
42
45
−70.0
14.0
48
18.0
Gain (dB)
Figure 44. HD3 vs Gain, LNA = 24 dB and PGA = 24 dB and
VOUT = –1 dBFS
22.0
26.0
30.0
Gain (dB)
34.0
38.0
42.0
Figure 45. IMD3, Fout1 = –7 dBFS and Fout2 = –21 dBFS
PSMR vs SUPPLY FREQUENCY
−50.0
Fin1=2MHz, Fin2=2.01MHz
Fin1=5MHz, Fin2=5.01MHz
−60
Vcntl = 0
Vcntl = 0.3
Vcntl = 0.6
Vcntl = 0.9
−54.0
−58.0
PSMR (dBc)
IMD3 (dBFS)
48
Figure 43. HD2 vs Gain, LNA = 24 dB and PGA = 24 dB and
VOUT = –1 dBFS
−40
HD3 (dBc)
42
Gain (dB)
Figure 42. HD3 vs Gain, LNA = 18 dB and PGA = 24 dB and
VOUT = –1 dBFS
−90
36
−62.0
−65
−70
−66.0
−70.0
14.0
18.0
22.0
26.0
30.0
Gain (dB)
34.0
38.0
42.0
−75
5
10
100
1000 2000
Supply frequency (kHz)
Figure 46. IMD3, Fout1 = –7 dBFS and Fout2 = –7 dBFS
Figure 47. AVDD Power Supply Modulation Ratio, 100 mVPP
Supply Noise With Different Frequencies
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TYPICAL CHARACTERISTICS (continued)
PSMR vs SUPPLY FREQUENCY
3V PSRR vs SUPPLY FREQUENCY
−20
−55
Vcntl = 0
Vcntl = 0.3
Vcntl = 0.6
Vcntl = 0.9
PSRR wrt supply tone (dB)
PSMR (dBc)
−60
Vcntl = 0
Vcntl = 0.3
Vcntl = 0.6
Vcntl = 0.9
−30
−65
−70
−75
−40
−50
−60
−70
−80
5
10
100
−90
1000 2000
5
10
100
Supply frequency (kHz)
Supply frequency (kHz)
Figure 48. AVDD_5V Power Supply Modulation Ratio, 100
mVPP Supply Noise With Different Frequencies
Figure 49. AVDD Power Supply Rejection Ratio, 100 mVPP
Supply Noise With Different Frequencies
5V PSRR vs SUPPLY FREQUENCY
20000.0
−20
Vcntl = 0
Vcntl = 0.3
Vcntl = 0.6
Vcntl = 0.9
−40
16000.0
14000.0
Output Code
PSRR wrt supply tone (dB)
Output Code
Vcntl
18000.0
−30
1000 2000
−50
−60
12000.0
10000.0
8000.0
6000.0
4000.0
−70
2000.0
−80
−90
0.0
0.0
5
10
100
0.5
1.0
1.5
Time (µs)
2.0
2.5
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
−0.1
3.0
Vcntl (V)
−80
1000 2000
Supply frequency (kHz)
Figure 50. AVDD_5V Power Supply Rejection Ratio, 100
mVPP Supply Noise With Different Frequencies
Output Code
Vcntl
16000.0
Output Code
14000.0
12000.0
10000.0
8000.0
6000.0
4000.0
2000.0
0.0
0.0
0.2
0.5
0.8
1.0 1.2 1.5
Time (µs)
1.8
2.0
2.2
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
−0.1
2.5
Figure 52. VCNTL Response Time, LNA = 18 dB and
PGA = 24 dB
20
1.2
1.0
0.8
0.6
0.4
Input (V)
18000.0
Vcntl (V)
20000.0
Figure 51. VCNTL Response Time, LNA = 18 dB and
PGA = 24 dB
0.2
0.0
−0.2
−0.4
−0.6
−0.8
−1.0
−1.2
0.0
2.0
4.0
6.0
8.0 10.0 12.0 14.0 16.0 18.0 20.0
Time (µs)
Figure 53. Pulse Inversion Asymmetrical Positive Input
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TYPICAL CHARACTERISTICS (continued)
1.2
10000.0
1.0
8000.0
0.8
Positive overload
Negative overload
Average
6000.0
0.6
4000.0
Output Code
Input (V)
0.4
0.2
0.0
−0.2
−0.4
2000.0
0.0
−2000.0
−4000.0
−0.6
−6000.0
−0.8
−8000.0
−1.0
−1.2
0.0
2.0
4.0
6.0
8.0 10.0 12.0 14.0 16.0 18.0 20.0
Time (µs)
−10000.0
0.0
Figure 54. Pulse Inversion Asymmetrical Negative Input
3.0
Time (µs)
4.0
5.0
6.0
2000
47nF
15nF
8000
6000
1200
4000
800
2000
0
−2000
400
0
−400
−4000
−800
−6000
−1200
−8000
−1600
0
0.5
1
1.5
2
2.5
3
Time (µs)
3.5
4
4.5
47nF
15nF
1600
Output Code
Output Code
2.0
Figure 55. Pulse Inversion, VIN = 2 VPP, PRF = 1 KHz,
Gain = 21 dB
10000
−10000
1.0
5
Figure 56. Overload Recovery Response vs INM capacitor,
VIN = 50 mVpp/100 µVPP, Max Gain
−2000
1
1.5
2
2.5
3
3.5
Time (µs)
4
4.5
5
Figure 57. Overload Recovery Response vs INM
capacitor(Zoomed), VIN = 50 mVpp/100 µVPP, Max Gain
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TIMING CHARACTERISTICS (1)
Typical values are at 25°C, AVDD_5V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, Differential clock, CLOAD = 5
pF, RLOAD = 100 Ω, 14 Bit, sample rate = 65 MSPS, unless otherwise noted. Minimum and maximum values are across the
full temperature range TMIN = 0°C to TMAX = 85°C with AVDD_5V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V
PARAMETER
ta
TEST CONDITIONS
Aperture delay
Aperture delay
matching
tj
MIN
The delay in time between the rising edge of the input sampling
clock and the actual time at which the sampling occurs
0.7
Across channels within the same device
TYP MAX
3
Fs rms
11/8
Input
clock
cycles
Default, after reset, or / 0 x 2 [12] = 1, LOW_LATENCY = 1
tdelay
Data and frame clock
delay
Input clock rising edge (zero cross) to frame clock rising edge (zero
cross) minus 3/7 of the input clock period (T).
Δtdelay
Delay variation
At fixed supply and 20°C T difference. Device to device
tRISE
Data rise time
0.14
tFALL
Data fall time
Rise time measured from –100 to 100 mV Fall time measured from
100 to –100 mV 10 MHz < fCLKIN < 65MHz
tFCLKRISE
Frame clock rise time
Frame clock fall time
Rise time measured from –100 to 100 mV Fall time measured from
100 to –100 mV 10 MHz < fCLKIN < 65MHz
0.14
tFCLKFALL
Frame clock duty cycle
Zero crossing of the rising edge to zero crossing of the falling edge
tDCLKRISE
Bit clock rise time
tDCLKFALL
Bit clock fall time
Rise time measured from –100 to 100 mV Fall time measured from
100 to –100 mV 10 MHz < fCLKIN < 65MHz
3
5.4
–1
Zero crossing of the rising edge to zero crossing of the falling edge
10MHz < fCLKIN < 65MHz
ps
450
ADC latency
(1)
ns
±150
Aperture jitter
Bit clock duty cycle
UNIT
7
ns
1
ns
ns
0.15
ns
0.15
48%
50%
52%
0.13
ns
0.12
46%
54%
Timing parameters are specified by design and characterization; not production tested.
OUTPUT INTERFACE TIMING (1) (2) (3)
fCLKIN,
Input Clock
Frequency
(1)
(2)
(3)
22
Setup Time (tsu), ns
Data Valid to Bit Clock ZeroCrossing
MAX
Hold Time (th), ns
tPROG = (3/7)x T + tdelay, ns
Bit Clock Zero-Crossing to Data
Invalid
Input Clock Zero-Cross (rising edge)
to Frame Clock Zero-Cross (rising
edge)
MHz
MIN
TYP
MIN
TYP
MIN
TYP
MAX
65
0.24
0.37
0.24
0.38
MAX
11
12
12.5
50
0.41
0.54
0.46
0.57
13
13.9
14.4
40
0.55
0.70
0.61
0.73
15
16
16.7
30
0.87
1.10
0.94
1.1
18.5
19.5
20.1
20
1.30
1.56
1.46
1.6
25.7
26.7
27.3
FCLK timing is the same as for the output data lines. It has the same relation to DCLK as the data pins. Setup and hold are the same
for the data and the frame clock.
Data valid is logic HIGH = +100 mV and logic LOW = –100 mV
Timing parameters are specified by design and characterization; not production tested.
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12-Bit 6x serialization mode
Output Data
CHnOUT
Data rate = 14 x fCLKIN
Bit Clock
DCLK
Freq = 7 x fCLKIN
Frame Clock
FCLK
Freq = fCLKIN
Input Clock
CLKIN
Freq = fCLKIN
Input Signal
D0 D13 D12
D1
(D12) (D13) (D0) (D1)
D11
(D2)
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D6
D5
(D7) (D8)
Output Data Pair
Data bit in LSB First mode
Bit Clock
DCLKP
D13 D12
(D0) (D1)
CHi out
tsu
DCLKM
D4
D3
D2
D1
D0
(D9) (D10) (D11) (D12) (D13)
Data bit in MSB First mode
SAMPLE N-Cd
D8
D7
(D5) (D6)
Cd clock cycles
latency
th
D11 D10
(D2) (D3)
Dn
D7
D6
(D6) (D7)
SAMPLE N-1
D9
D8
(D4) (D5)
Sample
N+Cd
ta
Dn + 1
tsu
th
D5
D4
D3
D2
D1
D0 D13 D12
(D8) (D9) (D10) (D11) (D12) (D13) (D0) (D1)
tPROG
D11 D10
(D2) (D3)
T
D7
D6
(D6) (D7)
SAMPLE N
D9
D8
(D4) (D5)
Sample
N+Cd+1
D10
(D1)
T0434-01
D1
D0 D11
D5
D4
D3
D2
(D8) (D9) (D10) (D11) (D12) (D13) (D0)
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D13
(D0)
D10 D9
(D3) (D4)
ta
Sample N
tPROG
AFE5808
SLOS688D – SEPTEMBER 2010 – REVISED JANUARY 2014
LVDS Setup and Hold Timing
14-Bit 7x serialization mode
Figure 58. LVDS Timing Diagrams
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LVDS Output Interface Description
AFE5808 has LVDS output interface which supports multiple output formats. The ADC resolutions can be
configured as 12 or 14 bit as shown in the LVDS timing diagrams Figure 58. The ADCs in the AFE5808 are
running at 14 bit; 2 LSBs are removed when 12-bit output is selected; and two 0s are added at LSBs when 16-bit
output is selected. Appropriate ADC resolutions can be selected for optimizing system performance-cost
effectiveness. When the devices run at 16bit mode, higher end FPGAs are required to process higher rate of
LVDS data. Corresponding register settings are listed in Table 4.
Table 4. Corresponding Register Settings
LVDS Rate
12 bit (6X DCLK)
14 bit (7X DCLK)
Reg 3 [14:13]
11
00
16 bit (8X DCLK)
01
Reg 4 [2:0]
010
000
000
Description
2 LSBs removed
N/A
2 0s added at LSBs
SERIAL REGISTER OPERATION
Serial Register Write Description
Programming of different modes can be done through the serial interface formed by pins SEN (serial interface
enable), SCLK (serial interface clock), SDATA (serial interface data) and RESET. All these pins have a pull-down
resistor to GND of 20kΩ. Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is
latched at every rising edge of SCLK when SEN is active (low). The serial data is loaded into the register at
every 24th SCLK rising edge when SEN is low. If the word length exceeds a multiple of 24 bits, the excess bits
are ignored. Data can be loaded in multiple of 24-bit words within a single active SEN pulse (there is an internal
counter that counts groups of 24 clocks after the falling edge of SEN). The interface can work with the SCLK
frequency from 20 MHz down to low speeds (few Hertz) and even with non-50% duty cycle SCLK. The data is
divided into two main portions: a register address (8 bits) and the data itself (16 bits), to load on the addressed
register. When writing to a register with unused bits, these should be set to 0. Figure 59 illustrates this process.
Start Sequence
End Sequence
SEN
t6
t7
t1
t2
Data Latched On Rising Edge of SCLK
SCLK
t3
SDATA
A7
A5
A6
A4
A3
A2
A1
A0 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
t4
t5
Start Sequence
End Sequence
RESET
T0384-01
Figure 59. SPI Timing
24
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SPI Timing Characteristics
Minimum values across full temperature range TMIN = 0°C to TMAX = 85°C, AVDD_5V = 5 V, AVDD = 3.3 V,
AVDD_ADC = 1.8 V, DVDD = 1.8 V
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
t1
SCLK period
50
ns
t2
SCLK high time
20
ns
t3
SCLK low time
20
ns
t4
Data setup time
5
ns
t5
Data hold time
5
ns
t6
SEN fall to SCLK rise
8
ns
t7
Time between last SCLK rising edge to SEN rising edge
t8
SDOUT Delay
8
ns
12
20
28
ns
Register Readout
The device includes an option where the contents of the internal registers can be read back. This may be useful
as a diagnostic test to verify the serial interface communication between the external controller and the AFE.
First, the bit (Reg0[1]) needs to be set to '1'. Then user should initiate a
serial interface cycle specifying the address of the register (A7 to A0) whose content has to be read. The data
bits are "don’t care". The device will output the contents (D15-D0) of the selected register on the SDOUT pin.
SDOUT has a typical delay t8 of 20 ns from the falling edge of the SCLK. For a lower speed, SCLK, SDOUT can
be latched on the rising edge of SCLK. For higher speed, SCLK, for example, the SCLK period lesser than 60
ns, it would be better to latch the SDOUT at the next falling edge of SCLK. The following timing diagram shows
this operation (the time specifications follow the same information provided. In the readout mode, users still can
access the through SDATA/SCLK/SEN. To enable serial register writes, set
the bit back to '0'.
Start Sequence
End Sequence
SEN
t6
t7
t1
t2
SCLK
t3
A7
SDATA
A6
A5
A4
A3
A2
A1
t4
A0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D6
D5
D4
D3
D2
D1
D0
t8
t5
D15 D14 D13 D12 D11 D10 D9
SDOUT
D8
D7
Figure 60. Serial Interface Register Read
The AFE5808 SDOUT buffer is tri-stated and will get enabled only when 0[1] (REGISTER READOUT ENABLE)
is enabled. SDOUT pins from multiple AFE5808s can be tied together without any pull-up resistors. Level shifter
SN74AUP1T04 can be used to convert 1.8-V logic to 2.5-V/3.3-V logics if needed.
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t1
AVDD
AVDD_5V
AVDD_ADC
t2
DVDD
t3
t4
t7
t5
RESET
t6
Device Ready for
Serial Register Write
SEN
Start of Clock
Device Ready for
Data Conversion
CLKP_ADC
t8
10 µs < t1 < 50 ms, 10 µs < t2 < 50 ms, –10 ms < t3 < 10 ms, t4 > 10 ms, t5 > 100 ns, t6 > 100 ns, t7 > 10 ms,
and t8 > 100 µs.
The AVDDx and DVDD power-on sequence does not matter as long as –10 ms < t3 < 10 ms. Similar considerations
apply while shutting down the device.
Figure 61. Recommended Power-up Sequencing and Reset Timing
26
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SLOS688D – SEPTEMBER 2010 – REVISED JANUARY 2014
Register Map
A reset process is required at the AFE5808 initialization stage. Initialization can be done in one of two ways:
1. Through a hardware reset, by applying a positive pulse in the RESET pin
2. Through a software reset, using the serial interface, by setting the SOFTWARE RESET bit to high. Setting
this bit initializes the internal registers to the respective default values (all zeros) and then self-resets the
SOFTWARE RESET bit to low. In this case, the RESET pin can stay low (inactive).
After reset, all ADC and VCA registers are set to ‘0’, that is default settings. During register programming, all
reserved/unlisted register bits need to be set as ‘0’. Register settings are maintained when the AFE5808 is in
either partial power down mode or complete power down mode.
ADC Register Map
Table 5. ADC Register Map
ADDRESS
(DEC)
ADDRESS
(HEX)
DEFAUL
T
VALUE
0[0]
0x0[0]
0
SOFTWARE_RESET
0: Normal operation;
1: Resets the device and self-clears the bit to '0'
0[1]
0x0[1]
0
REGISTER_READOUT_ENABLE
0:Disables readout;
1: enables readout of register at SDOUT Pin
1[0]
0x1[0]
0
ADC_COMPLETE_PDN
0: Normal
1: Complete Power down
1[1]
0x1[1]
0
LVDS_OUTPUT_DISABLE
0: Output Enabled;
1: Output disabled
1[9:2]
0x1[9:2]
0
ADC_PDN_CH
0: Normal operation;
1: Power down. Power down Individual ADC channels.
1[9]→CH8…1[2]→CH1
1[10]
0x1[10]
0
PARTIAL_PDN
0: Normal Operation;
1: Partial Power Down ADC
1[11]
0x1[11]
0
LOW_FREQUENCY_
NOISE_SUPPRESSION
0: No suppression;
1: Suppression Enabled
1[13]
0x1[13]
0
EXT_REF
0: Internal Reference;
1: External Reference. VREF_IN is used. Both 3[15] and 1[13] should be set
as 1 in the external reference mode
1[14]
0x1[14]
0
LVDS_OUTPUT_RATE_2X
0: 1x rate;
1: 2x rate. Combines data from 2 channels on 1 LVDS pair. When ADC clock
rate is low, this feature can be used
1[15]
0x1[15]
0
SINGLE-ENDED_CLK_MODE
0: Differential clock input;
1: Single-ended clock input
2[2:0]
0x2[2:0]
0
RESERVED
Set to 0
2[10:3]
0x2[10:3]
0
POWER-DOWN_LVDS
0: Normal operation;
1: PDN Individual LVDS outputs. 2[10]→CH8…2[3]→CH1
2[11]
0x2[11]
0
AVERAGING_ENABLE
0: No averaging;
1: Average 2 channels to increase SNR
2[12]
0x2[12]
0
LOW_LATENCY
0: Default Latency with digital features supported , 11 cycle latency
1: Low Latency with digital features bypassed., 8 cycle latency
2[15:13]
0x2[15:13]
0
TEST_PATTERN_MODES
000: Normal operation;
001: Sync;
010: De-skew;
011: Custom;
100:All 1s;
101: Toggle;
110: All 0s;
111: Ramp
3[7:0]
0x3[7:0]
0
INVERT_CHANNELS
0: No inverting;
1:Invert channel digital output. 3[7]→CH8;3[0]→CH1
3[8]
0x3[8]
0
CHANNEL_OFFSET_
SUBSTRACTION_ENABLE
0: No offset subtraction;
1: Offset value Subtract Enabled
3[9:11]
0x3[9:11]
0
RESERVED
Set to 0
FUNCTION
DESCRIPTION
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Table 5. ADC Register Map (continued)
ADDRESS
(DEC)
ADDRESS
(HEX)
DEFAUL
T
VALUE
3[12]
0x3[12]
0
DIGITAL_GAIN_ENABLE
0: No digital gain;
1: Digital gain Enabled
3[14:13]
0x3[14:13]
0
SERIALIZED_DATA_RATE
Serialization factor
00: 14x
01: 16x
10: reserved
11: 12x
when 4[1] = 1. In the 16x serialization rate, two 0s are filled at two LSBs (see
Table 4)
3[15]
0x3[15]
0
ENABLE_EXTERNAL_
REFERENCE_MODE
0: Internal reference mode;
1: Set to external reference mode
Note: both 3[15] and 1[13] should be set as 1 when configuring the device in
the external reference mode
4[1]
0x4[1]
0
ADC_RESOLUTION_SELECT
0: 14bit;
1: 12bit
4[3]
0x4[3]
0
ADC_OUTPUT_FORMAT
0: 2's complement;
1: Offset binary
4[4]
0x4[4]
0
LSB_MSB_FIRST
0: LSB first;
1: MSB first
5[13:0]
0x5[13:0]
0
CUSTOM_PATTERN
Custom pattern data for LVDS output (2[15:13] = 011)
13[9:0]
0xD[9:0]
0
OFFSET_CH1
Value to be subtracted from channel 1 code
13[15:11]
0xD[15:11]
0
DIGITAL_GAIN_CH1
0dB to 6dB in 0.2dB steps
15[9:0]
0xF[9:0]
0
OFFSET_CH2
value to be subtracted from channel 2 code
15[15:11]
0xF[15:11]
0
DIGITAL_GAIN_CH2
0dB to 6dB in 0.2dB steps
17[9:0]
0x11[9:0]
0
OFFSET_CH3
value to be subtracted from channel 3 code
17[15:11]
0x11[15:11]
0
DIGITAL_GAIN_CH3
0dB to 6dB in 0.2dB steps
19[9:0]
0x13[9:0]
0
OFFSET_CH4
value to be subtracted from channel 4 code
19[15:11]
0x13[15:11]
0
DIGITAL_GAIN_CH4
0dB to 6dB in 0.2dB steps
21[0]
0x15[0]
0
DIGITAL_HPF_FILTER_ENABLE
_ CH1-4
0: Disable the digital HPF filter;
1: Enable for 1-4 channels
21[4:1]
0x15[4:1]
0
DIGITAL_HPF_FILTER_K_CH1-4
Set K for the high-pass filter (k from 2 to 4, that is, 0010B to 0100B).
This group of four registers controls the characteristics of a digital high-pass
transfer function applied to the output data, following the formula:
y(n) = 2k/(2k + 1) [x(n) – x(n – 1) + y(n – 1)] (please see Table 6)
25[9:0]
0x19[9:0]
0
OFFSET_CH8
value to be subtracted from channel 8 code
25[15:11]
0x19[15:11]
0
DIGITAL_GAIN_CH8
0dB to 6dB in 0.2dB steps
27[9:0]
0x1B[9:0]
0
OFFSET_CH7
value to be subtracted from channel 7 code
27[15:11]
0x1B[15:11]
0
DIGITAL_GAIN_CH7
0dB to 6dB in 0.2dB steps
29[9:0]
0x1D[9:0]
0
OFFSET_CH6
value to be subtracted from channel 6 code
29[15:11]
0x1D[15:11]
0
DIGITAL_GAIN_CH6
0dB to 6dB in 0.2dB steps
31[9:0]
0x1F[9:0]
0
OFFSET_CH5
value to be subtracted from channel 5 code
31[15:11]
0x1F[15:11]
0
DIGITAL_GAIN_CH5
0dB to 6dB in 0.2dB steps
33[0]
0x21[0]
0
DIGITAL_HPF_FILTER_ENABLE
_ CH5-8
0: Disable the digital HPF filter;
1: Enable for 5-8 channels
33[4:1]
0x21[4:1]
0
DIGITAL_HPF_FILTER_K_CH5-8
Set K for the high-pass filter (k from 2 to 4, 0010B to 0100B)
This group of four registers controls the characteristics of a digital high-pass
transfer function applied to the output data, following the formula:
y(n) = 2k/(2k + 1) [x(n) – x(n – 1) + y(n – 1)] (please see Table 6)
28
FUNCTION
DESCRIPTION
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AFE5808 ADC Register/Digital Processing Description
The ADC in the AFE5808 has extensive digital processing functionalities which can be used to enhance
ultrasound system performance. The digital processing blocks are arranged as in Figure 62.
ADC
Output
12/14b
Channel
Average
Default=No
Digital
Gain
Default=0
Digital HPF
Default = No
12/14b
Final
Digital
Output
Digital Offset
Default=No
Figure 62. ADC Digital Block Diagram
AVERAGING_ENABLE: Address: 2[11]
When set to 1, two samples, corresponding to two consecutive channels, are averaged (channel 1 with 2, 3 with
4, 5 with 6, and 7 with 8). If both channels receive the same input, the net effect is an improvement in SNR. The
averaging is performed as:
• Channel 1 + channel 2 comes out on channel 3
• Channel 3 + channel 4 comes out on channel 4
• Channel 5 + channel 6 comes out on channel 5
• Channel 7 + channel 8 comes out on channel 6
ADC_OUTPUT_FORMAT: Address: 4[3]
The ADC output, by default, is in 2’s-complement mode. Programming the ADC_OUTPUT_FORMAT bit to 1
inverts the MSB, and the output becomes straight-offset binary mode.
DIGITAL_GAIN_ENABLE: Address: 3[12]
Setting this bit to 1 applies to each channel i the corresponding gain given by DIGTAL_GAIN_CHi . The
gain is given as 0dB + 0.2dB × DIGTAL_GAIN_CHi. For instance, if DIGTAL_GAIN_CH5 = 3,
channel 5 is increased by 0.6dB gain. DIGTAL_GAIN_CHi = 31 produces the same effect as
DIGTAL_GAIN_CHi = 30, setting the gain of channel i to 6dB.
DIGITAL_HPF_ENABLE
• CH1-4: Address 21[0]
• CH5-8: Address 33[0]
DIGITAL_HPF_FILTER_K_CHX
• CH1-4: Address 21[4:1]
• CH5-8: Address 3[4:1]
This group of registers controls the characteristics of a digital high-pass transfer function applied to the output
data, following Equation 1.
y (n ) =
2k
2k + 1
éë x (n ) - x (n - 1) + y (n - 1)ùû
(1)
These digital HPF registers (one for the first four channels and one for the second group of four channels)
describe the setting of K. The digital high pass filter can be used to suppress low frequency noise which
commonly exists in ultrasound echo signals. The digital filter can significantly benefit near field recovery time due
to T/R switch low frequency response. Table 6 shows the cut-off frequency vs K.
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Table 6. Digital HPF –1dB Corner Frequency vs K and Fs
k
40 MSPS
50 MSPS
65 MSPS
2
2780 KHz
3480 KHz
4520 KHz
3
1490 KHz
1860 KHz
2420 KHz
4
770 KHz
960 KHz
1250 KHz
LOW_FREQUENCY_NOISE_SUPPRESSION: Address: 1[11]
The low-frequency noise suppression mode is especially useful in applications where good noise performance is
desired in the frequency band of 0MHz to 1MHz (around dc). Setting this mode shifts the low-frequency noise of
the AFE5808 to approximately Fs/2, thereby moving the noise floor around dc to a much lower value. Register bit
1[11] is used for enabling or disabling this feature. When this feature is enabled, power consumption of the
device will be increased slightly by approximate 1mW/CH.
LVDS_OUTPUT_RATE_2X: Address: 1[14]
The output data always uses a DDR format, with valid/different bits on the positive as well as the negative edges
of the LVDS bit clock, DCLK. The output rate is set by default to 1X (LVDS_OUTPUT_RATE_2X = 0), where
each ADC has one LVDS stream associated with it. If the sampling rate is low enough, two ADCs can share one
LVDS stream, in this way lowering the power consumption devoted to the interface. The unused outputs will
output zero. To avoid consumption from those outputs, no termination should be connected to them. The
distribution on the used output pairs is done in the following way:
• Channel 1 and channel 2 come out on channel 3. Channel 1 comes out first
• Channel 3 and channel 4 come out on channel 4. Channel 3 comes out first
• Channel 5 and channel 6 come out on channel 5. Channel 5 comes out first
• Channel 7 and channel 8 come out on channel 6. Channel 7 comes out first
CHANNEL_OFFSET_SUBSTRACTION_ENABLE: Address: 3[8]
Setting this bit to 1 enables the subtraction of the value on the corresponding OFFSET_CHx (offset for
channel i) from the ADC output. The number is specified in 2s-complement format. For example,
OFFSET_CHx = 11 1000 0000 means subtract –128. For OFFSET_CHx = 00 0111 1111 the effect is
to subtract 127. In effect, both addition and subtraction can be performed. Note that the offset is applied before
the digital gain (see DIGITAL_GAIN_ENABLE). The whole data path is 2s-complement throughout internally, with
digital gain being the last step. Only when ADC_OUTPUT_FORMAT = 1 (straight binary output format) is the 2scomplement word translated into offset binary at the end.
SERIALIZED_DATA_RATE: Address: 3[14:13]
Please see Table 4 for detail description.
30
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TEST_PATTERN_MODES: Address: 2[15:13]
The AFE5808 can output a variety of test patterns on the LVDS outputs. These test patterns replace the normal
ADC data output. The device may also be made to output 6 preset patterns:
1. Ramp: Setting Register 2[15:13]=111causes all the channels to output a repeating full-scale ramp pattern.
The ramp increments from zero code to full-scale code in steps of 1 LSB every clock cycle. After hitting the
full-scale code, it returns back to zero code and ramps again.
2. Zeros: The device can be programmed to output all zeros by setting Register 2[15:13]=110;
3. Ones: The device can be programmed to output all 1s by setting Register 2[15:13]=100;
4. Deskew Patten: When 2[15:13] = 010; this mode replaces the 14-bit ADC output with the 01010101010101
word.
5. Sync Pattern: When 2[15:13] = 001, the normal ADC output is replaced by a fixed 11111110000000 word.
6. Toggle: When 2[15:13] = 101, the normal ADC output is alternating between 1's and 0's. The start state of
ADC word can be either 1's or 0's.
7. Custom Pattern: It can be enabled when 2[15:13]=011;. Users can write the required VALUE into register
bits which is Register 5[13:0]. Then the device will output VALUE at its outputs,
about 3 to 4 ADC clock cycles after the 24th rising edge of SCLK. So, the time taken to write one value is 24
SCLK clock cycles + 4 ADC clock cycles. To change the customer pattern value, users can repeat writing
Register 5[13:0] with a new value. Due to the speed limit of SPI, the refresh rate of the custom pattern may
not be high. For example, 128 points custom pattern will take approximately 128 x (24 SCLK clock cycles + 4
ADC clock cycles).
NOTE
Only one of the above patterns can be active at any given instant.
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VCA Register Map
Table 7. VCA Register Map
DEFAU
ADDRESS ADDRESS
LT
FUNCTION
(DEC)
(HEX)
VALUE
DESCRIPTION
51[0]
0x33[0]
0
RESERVED
0
51[3:1]
0x33[3:1]
0
LPF_PROGRAMMABILITY
000:
010:
011:
100:
51[4]
0x33[4]
0
PGA_INTEGRATOR_DISABLE
(PGA_HPF_DISABLE)
0: Enable
1: Disables offset integrator for PGA. Please see explanation
for the PGA integrator function in APPLICATION
INFORMATION section
51[7:5]
0x33[7:5]
0
PGA_CLAMP_LEVEL
Low Noise mode: 53[11:10] = 00
000: –2 dBFS
010: 0 dBFS
1XX: Clamp is disabled
Low power/Medium Power mode; 53[11:10] = 01/10
100: –2 dBFS
110: 0 dBFS
0XX: clamp is disabled
Note: the clamp circuit makes sure that PGA output is in linear
range. For example, at 000 setting, PGA output HD3 will be
worsen by 3 dB at –2 dBFS ADC input. In normal operation,
clamp function can be set as 000 in the low noise mode. The
maximum PGA output level can exceed 2Vpp with the clamp
circuit enabled. In the low power and medium power modes,
PGA_CLAMP is disabled for saving power if 51[7] = 0.
51[13]
0x33[13]
0
PGA_GAIN_CONTROL
0:24 dB;
1:30 dB
52[4:0]
0x34[4:0]
0
ACTIVE_TERMINATION_
INDIVIDUAL_RESISTOR_CNTL
SeeTable 9 Reg 52[5] should be set as '1' to access these bits
52[5]
0x34[5]
0
ACTIVE_TERMINATION_
INDIVIDUAL_RESISTOR_ENABLE
0: Disables;
1: Enables internal active termination individual resistor control
52[7:6]
0x34[7:6]
0
PRESET_ACTIVE_ TERMINATIONS
00: 50 Ω,
01: 100 Ω,
10: 200 Ω,
11: 400 Ω
(Note: the device will adjust resistor mapping (52[4:0])
automatically. 50 Ω active termination is NOT supported in 12dB LNA setting. Instead, '00' represents high impedance mode
when LNA gain is 12 dB)
52[8]
0x34[8]
0
ACTIVE TERMINATION ENABLE
0: Disables;
1: Enables active termination
52[10:9]
0x34[10:9]
0
LNA_INPUT_CLAMP_SETTING
00: Auto setting (Recommended for most cases. Clamp level
can be set automatically depending LNA gain. 350mVpp when
LNA = 24dB, 600mVpp when LNA = 18 dB, 1.15 Vpp when
LNA = 12 dB)
01: 1.5 Vpp,
10: 1.15 Vpp,
11: 0.6 Vpp
52[11]
0x34[11]
0
RESERVED
Set to 0
52[12]
0x34[12]
0
LNA_INTEGRATOR_DISABLE
(LNA_HPF_DISABLE)
0: Enables;
1: Disables offset integrator for LNA. Please see the
explanation for this function in the following section
52[14:13]
0x34[14:1
3]
0
LNA_GAIN
00: 18 dB;
01: 24 dB;
10: 12 dB;
11: Reserved
32
15
20
30
10
MHz,
MHz,
MHz,
MHz
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Table 7. VCA Register Map (continued)
DEFAU
ADDRESS ADDRESS
LT
FUNCTION
(DEC)
(HEX)
VALUE
DESCRIPTION
52[15]
0x34[15]
0
LNA_INDIVIDUAL_CH_CNTL
0: Disable;
1: Enable LNA individual channel control. See Register 57 for
details
53[7:0]
0x35[7:0]
0
PDN_CH
0: Normal operation;
1: Powers down corresponding channels. Bit7→CH8,
Bit6→CH7…Bit0→CH1. PDN_CH will shut down whichever
blocks are active depending on TGC mode or CW mode
53[8]
0x35[8]
0
RESERVED
Set to 0
53[9]
0x35[9]
0
RESERVED
Set to 0
53[10]
0x35[10]
0
LOW_POWER
0: Low noise mode;
1: Sets to low power mode (53[11] = 0). At 30 dB PGA, total
chain gain may slightly change.
See typical characteristics
53[11]
0x35[11]
0
MED_POWER
0: Low noise mode;
1: Sets to medium power mode(53[10] = 0). At 30 dB PGA,
total chain gain may slightly change.
See typical characteristics
53[12]
0x35[12]
0
PDN_VCAT_PGA
0: Normal operation;
1: Powers down VCAT (voltage-controlled-attenuator) and PGA
53[13]
0x35[13]
0
PDN_LNA
0: Normal operation;
1: Powers down LNA only
53[14]
0x35[14]
0
VCA_PARTIAL_PDN
0: Normal operation;
1: Powers down LNA, VCAT, and PGA partially(fast wake
response)
53[15]
0x35[15]
0
VCA_COMPLETE_PDN
0: Normal operation;
1: Powers down LNA, VCAT, and PGA completely (slow wake
response). This bit can overwrite 53[14].
54[4:0]
0x36[4:0]
0
CW_SUM_AMP_GAIN_CNTL
Selects Feedback resistor for the CW Amplifier as per Table 9
below
54[5]
0x36[5]
0
CW_16X_CLK_SEL
0: Accepts differential clock;
1: Accepts CMOS clock
54[6]
0x36[6]
0
CW_1X_CLK_SEL
0: Accepts CMOS clock;
1: Accepts differential clock
54[7]
0x36[7]
0
RESERVED
Set to 0
54[8]
0x36[8]
0
CW_TGC_SEL
0: TGC Mode;
1 : CW Mode
Note : VCAT and PGA are still working in CW mode. They
should be powered down separately through 53[12]
54[9]
0x36[9]
0
CW_SUM_AMP_ENABLE
0: enables CW summing amplifier;
1: disables CW summing amplifier
Note: 54[9] is only effective in CW mode.
54[11:10]
0x36[11:1
0]
0
CW_CLK_MODE_SEL
00: 16X mode;
01: 8X mode;
10: 4X mode;
11: 1X mode
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Table 7. VCA Register Map (continued)
DEFAU
ADDRESS ADDRESS
LT
FUNCTION
(DEC)
(HEX)
VALUE
DESCRIPTION
55[3:0]
0x37[3:0]
0
CH1_CW_MIXER_PHASE
55[7:4]
0x37[7:4]
0
CH2_CW_MIXER_PHASE
55[11:8]
0x37[11:8]
0
CH3_CW_MIXER_PHASE
55[15:12]
0x37[15:1
2]
0
CH4_CW_MIXER_PHASE
56[3:0]
0x38[3:0]
0
CH5_CW_MIXER_PHASE
56[7:4]
0x38[7:4]
0
CH6_CW_MIXER_PHASE
56[11:8]
0x38[11:8]
0
CH7_CW_MIXER_PHASE
56[15:12]
0x38[15:1
2]
0
CH8_CW_MIXER_PHASE
57[1:0]
0x39[1:0]
0
CH1_LNA_GAIN_CNTL
57[3:2]
0x39[3:2]
0
CH2_LNA_GAIN_CNTL
0000→1111, 16 different phase delays, see Table 13
00: 18 dB;
01: 24 dB;
10: 12 dB;
11: Reserved
REG52[15] should be set as '1'
57[5:4]
0x39[5:4]
0
CH3_LNA_GAIN_CNTL
57[7:6]
0x39[7:6]
0
CH4_LNA_GAIN_CNTL
00: 18 dB;
01: 24 dB;
10: 12 dB;
11: Reserved
REG52[15] should be set as '1'
57[9:8]
0x39[9:8]
0
CH5_LNA_GAIN_CNTL
57[11:10]
0x39[11:1
0]
0
CH6_LNA_GAIN_CNTL
57[13:12]
0x39[13:1
2]
0
CH7_LNA_GAIN_CNTL
57[15:14]
0x39[15:1
4]
0
CH8_LNA_GAIN_CNTL
59[3:2]
0x3B[3:2]
0
HPF_LNA
00: 100 kHz;
01: 50 kHz;
10: 200 kHz;
11: 150 kHz with 0.015 µF on INMx
59[6:4]
0x3B[6:4]
0
DIG_TGC_ATT_GAIN
000: 0dB attenuation;
001: 6dB attenuation;
N: ~N×6dB attenuation when 59[7] = 1
59[7]
0x3B[7]
0
DIG_TGC_ATT
0: disable digital TGC attenuator;
1: enable digital TGC attenuator
59[8]
0x3B[8]
0
CW_SUM_AMP_PDN
0: Power down;
1: Normal operation
Note: 59[8] is only effective in TGC test mode.
59[9]
0x3B[9]
0
PGA_TEST_MODE
0: Normal CW operation;
1: PGA outputs appear at CW outputs
AFE5808 VCA Register Description
LNA Input Impedances Configuration (Active Termination Programmability)
Different LNA input impedances can be configured through the register 52[4:0]. By enabling and disabling the
feedback resistors between LNA outputs and ACTx pins, LNA input impedance is adjustable accordingly. Table 8
describes the relationship between LNA gain and 52[4:0] settings. The input impedance settings are the same for
both TGC and CW paths.
The AFE5808 also has 4 preset active termination impedances as described in 52[7:6]. An internal decoder is
used to select appropriate resistors corresponding to different LNA gain.
The input impedance of AFE can be programmed through Register 52[8:0]. Each bit of Register 52[4:0] controls
one active termination resistor. The below tables indicate the norminal impedance values when individual active
termination resistors are selected. More details can be found in Active Termination. Table 9 shows the
corresponding impedances under different Register 52[4:0] values, while Table 10 shows the Register 52[4:0]
settings under different impedances.
34
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NOTE
Table 9 and Table 10 show norminal input impedance values. Due to silicon process
varation, the actual values can vary some.
Table 8. Register 52[4:0] Description
52[4:0]/0x34[4:0]
FUNCTION
00000
No feedback resistor enabled
00001
Enables 450-Ω feedback resistor
00010
Enables 900-Ω feedback resistor
00100
Enables 1800-Ω feedback resistor
01000
Enables 3600-Ω feedback resistor
10000
Enables 4500-Ω feedback resistor
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Table 9. Register 52[4:0] vs LNA Input Impedances
52[4:0]/0x34[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
LNA:12dB
High Z
150 Ω
300 Ω
100 Ω
600 Ω
120 Ω
200 Ω
86 Ω
LNA:18dB
High Z
90 Ω
180 Ω
60 Ω
360 Ω
72 Ω
120 Ω
51 Ω
LNA:24dB
High Z
50 Ω
100 Ω
33 Ω
200 Ω
40 Ω
66.67 Ω
29 Ω
52[4:0]/0x34[4:0]
01000
01001
01010
01011
01100
01101
01110
01111
LNA:12dB
1200 Ω
133 Ω
240 Ω
92 Ω
400 Ω
109 Ω
171 Ω
80 Ω
LNA:18dB
720 Ω
80 Ω
144 Ω
55 Ω
240 Ω
65 Ω
103 Ω
48 Ω
LNA:24dB
400 Ω
44 Ω
80 Ω
31 Ω
133 Ω
36 Ω
57 Ω
27 Ω
52[4:0]/0x34[4:0]
10000
10001
10010
10011
10100
10101
10110
10111
LNA:12dB
1500 Ω
136 Ω
250 Ω
94 Ω
429 Ω
111 Ω
176 Ω
81 Ω
LNA:18dB
900 Ω
82 Ω
150 Ω
56 Ω
257 Ω
67 Ω
106 Ω
49 Ω
LNA:24dB
500 Ω
45 Ω
83 Ω
31 Ω
143 Ω
37 Ω
59 Ω
27 Ω
52[4:0]/0x34[4:0]
11000
11001
11010
11011
11100
11101
11110
11111
LNA:12dB
667 Ω
122 Ω
207 Ω
87 Ω
316 Ω
102 Ω
154 Ω
76 Ω
LNA:18dB
400 Ω
73 Ω
124 Ω
52 Ω
189 Ω
61 Ω
92 Ω
46 Ω
LNA:24dB
222 Ω
41 Ω
69 Ω
29 Ω
105 Ω
34 Ω
51 Ω
25 Ω
36
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Table 10. LNA Input Impedances vs. Register 52[4:0]
Z
(Ω)
LNA:12dB
LNA:18dB
LNA:24dB
Z
(Ω)
25
11111
67
27
10111/011
11
69
29
00111/110
11
72
00101
150
00001
31
01011/100
11
73
11001
154
11110
33
00011
76
11111
171
01110
34
11101
80
01111
176
10110
36
01101
81
10111
37
10101
82
40
00101
83
200
00110
41
11001
86
00111
207
11010
44
01001
87
11011
222
10001
90
45
LNA:12dB
10010
01011
48
01111
94
10011
49
10111
100
00011
11101
102
00111/111
10
103
52
11011
105
55
01011
106
56
10011
57
59
LNA:12dB
144
00010
189
11100
01010
10010
257
00010
316
11100
360
00100
400
01100
429
10100
109
01101
500
111
10101
600
00100
10110
667
11000
00101
122
11001
61
11101
124
65
01101
00110
00110
11010
133
01001
136
10001
01100
01100
10100
300
01110
120
00100
11000
250
11100
10010
180
240
00010
LNA:24dB
01010
11110
10110
00011
LNA:18dB
10100
00001
01110
60
66.7
01010
10001
92
00001
01001
Z
(Ω)
143
11010
11111
51
LNA:24dB
10101
46
50
LNA:18dB
11000
01000
10000
720
01000
900
10000
1200 01000
1500 10000
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Programmable Gain for CW Summing Amplifier
Different gain can be configured for the CW summing amplifier through the register 54[4:0]. By enabling and
disabling the feedback resistors between the summing amplifier inputs and outputs, the gain is adjustable
accordingly to maximize the dynamic range of CW path. Table 11 describes the relationship between the
summing amplifier gain and 54[4:0] settings.
Table 11. Register 54[4:0] Description
54[4:0]/0x36[4:0]
FUNCTION
00000
No feedback resistor
00001
Enables 250-Ω feedback resistor
00010
Enables 250-Ω feedback resistor
00100
Enables 500-Ω feedback resistor
01000
Enables 1000-Ω feedback resistor
10000
Enables 2000-Ω feedback resistor
Table 12. Register 54[4:0] vs Summing Amplifier Gain
54[4:0]/0x36[4:0]
CW I/V Gain
54[4:0]/0x36[4:0]
CW I/V Gain
54[4:0]/0x36[4:0]
CW I/V Gain
54[4:0]/0x36[4:0]
CW I/V Gain
00000
00001
00010
00011
00100
00101
00110
00111
N/A
0.50
0.50
0.25
1.00
0.33
0.33
0.20
01000
01001
01010
01011
01100
01101
01110
01111
2.00
0.40
0.40
0.22
0.67
0.29
0.29
0.18
10000
10001
10010
10011
10100
10101
10110
10111
4.00
0.44
0.44
0.24
0.80
0.31
0.31
0.19
11000
11001
11010
11011
11100
11101
11110
11111
1.33
0.36
0.36
0.21
0.57
0.27
0.27
0.17
Programmable Phase Delay for CW Mixer
Accurate CW beamforming is achieved through adjusting the phase delay of each channel. In the AFE5808, 16
different phase delays can be applied to each LNA output; and it meets the standard requirement of typical
1
λ
ultrasound beamformer, that is 16 beamformer resolution. Table 11 describes the relationship between the
phase delays and the register 55 and 56 settings.
Table 13. CW Mixer Phase Delay vs Register Settings
CH1 - 55[3:0], CH2 - 55[7:4], CH3 - 55[11:8], CH4 - 55[15:12],
CH5- 56[3:0], CH6 - 56[7:4], CH7 - 56[11:8], CH8 - 56[15:12],
CHX_CW_MIXER_PHASE
PHASE SHIFT
0000
0001
0010
0011
0100
0101
0110
0111
0
22.5°
45°
67.5°
90°
112.5°
135°
157.5°
CHX_CW_MIXER_PHASE
1000
1001
1010
1011
1100
1101
1110
1111
PHASE SHIFT
180°
202.5°
225°
247.5°
270°
292.5°
315°
337.5°
38
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THEORY OF OPERATION
AFE5808 OVERVIEW
The AFE5808 is a highly integrated Analog Front-End (AFE) solution specifically designed for ultrasound
systems in which high performance and small size are required. The AFE5808 integrates a complete time-gaincontrol (TGC) imaging path and a continuous wave Doppler (CWD) path. It also enables users to select one of
various power/noise combinations to optimize system performance. The AFE5808 contains eight channels; each
channels includes a Low-Noise Amplifier (LNA), a Voltage Controlled Attenuator (VCAT), a Programmable Gain
Amplifier (PGA), a Low-pass Filter (LPF), a 14-bit Analog-to-Digital Converter (ADC), and a CW mixer.
In addition, multiple features in the AFE5808 are suitable for ultrasound applications, such as active termination,
individual channel control, fast power up/down response, programmable clamp voltage control, fast and
consistent overload recovery, and so forth. Therefore the AFE5808 brings premium image quality to
ultra–portable, handheld systems all the way up to high-end ultrasound systems. Its simplified function block
diagram is listed in Figure 63.
SPI IN
AFE5808 (1 of 8 Channels)
LNA
VCAT
0 to -40dB
16 Phases
Generator
CW Mixer
PGA
24, 30dB
LNA IN
16X CLK
1X CLK
SPI OUT
SPI Logic
16X8
Crosspoint SW
rd
3 LP Filter
10, 15, 20,
30 MHz
14Bit
ADC
Summing
Amplifier
Reference
Reference
CW I/Q Vout
Differential
TGC Vcntl
EXT/INT
REFs
LVDS
1X CLK
Figure 63. Functional Block Diagram
LOW-NOISE AMPLIFIER (LNA)
In many high-gain systems, a low noise amplifier is critical to achieve overall performance. Using a new
proprietary architecture, the LNA in the AFE5808 delivers exceptional low-noise performance, while operating on
a very low quiescent current compared to CMOS-based architectures with similar noise performance. The LNA
performs single-ended input to differential output voltage conversion. It is configurable for a programmable gain
of 24/18/12 dB and its input-referred noise is only 0.63/0.70/0.9 nV/√Hz respectively. Programmable gain settings
result in a flexible linear input range up to 1 Vpp, realizing high signal handling capability demanded by new
transducer technologies. Larger input signal can be accepted by the LNA; however the signal can be distorted
since it exceeds the LNA’s linear operation region. Combining the low noise and high input range, a wide input
dynamic range is achieved consequently for supporting the high demands from various ultrasound imaging
modes.
The LNA input is internally biased at approximately +2.4 V; the signal source should be ac-coupled to the LNA
input by an adequately-sized capacitor, for example ≥ 0.1 µF. To achieve low DC offset drift, the AFE5808
incorporates a DC offset correction circuit for each amplifier stage. To improve the overload recovery, an
integrator circuit is used to extract the DC component of the LNA output and then fed back to the LNA’s
complementary input for DC offset correction. This DC offset correction circuit has a high-pass response and can
be treated as a high-pass filter. The effective corner frequency is determined by the capacitor CBYPASS connected
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at INM. With larger capacitors, the corner frequency is lower. For stable operation at the highest HP filer cut-off
frequency, a ≥ 15-nF capacitor can be selected. This corner frequency scales almost linearly with the value of
the CBYPASS. For example, 15 nF gives a corner frequency of approximately 100 kHz, while 47 nF can give an
effective corner frequency of 33 kHz. The DC offset correction circuit can also be disabled/enabled through
register 52[12].
The AFE5808 can be terminated passively or actively. Active termination is preferred in ultrasound application for
reducing reflection from mismatches and achieving better axial resolution without degrading noise figure too
much. Active termination values can be preset to 50, 100, 200, and 400 Ω; other values also can be programmed
by users through register 52[4:0]. A feedback capacitor is required between ACTx and the signal source as
Figure 64 shows. On the active termination path, a clamping circuit is also used to create a low impedance path
when overload signal is seen by the AFE5808. The clamp circuit limits large input signals at the LNA inputs and
improves the overload recovery performance of the AFE5808. The clamp level can be set to 350mVPP, 600
mVPP, 1.15 VPP automatically depending on the LNA gain settings when register 52[10:9] = 0. Other clamp
voltages, such as 1.15 VPP, 0.6 VPP, and 1.5 VPP, are also achievable by setting register 52[10:9]. This clamping
circuit is also designed to obtain good pulse inversion performance and reduce the impact from asymmetric
inputs.
AFE
CLAMP
CACT
ACTx
CIN
INPx
CBYPASS
INMx
Input
LNAx
Optional
Diodes
DC Offset
Correction
S0498-01
Figure 64. AFE5808 LNA With DC Offset Correction Circuit
VOLTAGE-CONTROLLED ATTENUATOR
The voltage-controlled attenuator is designed to have a linear-in-dB attenuation characteristic; that is, the
average gain loss in dB (refer to Figure 2) is constant for each equal increment of the control voltage (VCNTL) as
shown in Figure 65. A differential control structure is used to reduce common mode noise. A simplified attenuator
structure is shown in the following Figure 65 and Figure 66.
The attenuator is essentially a variable voltage divider that consists of the series input resistor (RS) and seven
shunt FETs placed in parallel and controlled by sequentially activated clipping amplifiers (A1 through A7). VCNTL
is the effective difference between VCNTLP and VCNTLM. Each clipping amplifier can be understood as a
specialized voltage comparator with a soft transfer characteristic and well-controlled output limit voltage.
Reference voltages V1 through V7 are equally spaced over the 0-V to 1.5-V control voltage range. As the control
voltage increases through the input range of each clipping amplifier, the amplifier output rises from a voltage
where the FET is nearly OFF to VHIGH where the FET is completely ON. As each FET approaches its ON state
and the control voltage continues to rise, the next clipping amplifier/FET combination takes over for the next
portion of the piecewise-linear attenuation characteristic. Thus, low control voltages have most of the FETs
turned OFF, producing minimum signal attenuation. Similarly, high control voltages turn the FETs ON, leading to
maximum signal attenuation. Therefore, each FET acts to decrease the shunt resistance of the voltage divider
formed by Rs and the parallel FET network.
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Additionally, a digitally controlled TGC mode is implemented to achieve better phase-noise performance in the
AFE5808. The attenuator can be controlled digitally instead of the analog control voltage VCNTL. This mode can
be set by the register bit 59[7]. The variable voltage divider is implemented as a fixed series resistance and FET
as the shunt resistance. Each FET can be turned ON by connecting the switches SW1-7. Turning on each of the
switches can give approximately 6dB of attenuation. This can be controlled by the register bits 59[6:4]. This
digital control feature can eliminate the noise from the VCNTL circuit and ensure the better SNR and phase noise
for TGC path.
A1 - A7 Attenuator Stages
Attenuator
Input
RS
Attenuator
Output
Q1
VB
A1
Q2
A1
Q3
A1
C1
C2
V1
Q4
A1
C3
V2
Q5
A1
C4
V3
Q6
A1
C5
V4
Q7
A1
C6
V5
C7
V6
V7
VCNTL
C1 - C8 Clipping Amplifiers
Control
Input
Figure 65. Simplified Voltage Controlled Attenuator (Analog Structure)
Attenuator
Input
RS
Attenuator
Output
Q1
Q2
Q3
Q4
Q5
SW5
SW6
Q6
Q7
VB
SW1
SW2
SW3
SW4
SW7
VHIGH
Figure 66. Simplified Voltage Controlled Attenuator (Digital Structure)
The voltage controlled attenuator’s noise follows a monotonic relationship to the attenuation coefficient. AAt
higher attenuation, the input-referred noise is higher and vice-versa. The attenuator’s noise is then amplified by
the PGA and becomes the noise floor at ADC input. In the attenuator’s high attenuation operating range, that is
VCNTL is high, the attenuator’s input noise may exceed the LNA’s output noise; the attenuator then becomes the
dominant noise source for the following PGA stage and ADC. Therefore the attenuator’s noise should be
minimized compared to the LNA output noise. The AFE5808’s attenuator is designed for achieving very low
noise even at high attenuation (low channel gain) and realizing better SNR in near field. The input referred noise
for different attenuations is listed in the below table:
Table 14. Voltage-Controlled-Attenuator noise vs Attenuation
Attenuation (dB)
Attenuator Input Referred noise (nV/rtHz)
–40
10.5
–36
10
–30
9
–24
8.5
–18
6
–12
4
–6
3
0
2
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PROGRAMMABLE GAIN AMPLIFIER (PGA)
After the voltage controlled attenuator, a programmable gain amplifier can be configured as 24 or 30 dB with a
constant input referred noise of 1.75 nV/rtHz. The PGA structure consists of a differential voltage-to-current
converter with programmable gain, clamping circuits, a transimpedance amplifier with a programmable low-pass
filter, and a DC offset correction circuit. Its simplified block diagram is shown in Figure 67.
CLAMP
From attenuator
To ADC
I/V
LPF
V/I
CLAMP
DC Offset
Correction Loop
Figure 67. Simplified Block Diagram of PGA
Low input noise is always preferred in a PGA and its noise contribution should not degrade the ADC SNR too
much after the attenuator. At the minimum attenuation (used for small input signals), the LNA noise dominates; at
the maximum attenuation (large input signals), the PGA and ADC noise dominates. Thus 24-dB gain of PGA
achieves better SNR as long as the amplified signals can exceed the noise floor of the ADC.
The PGA clamping circuit can be enabled (register 51) to improve the overload recovery performance of the
AFE. If we measure the standard deviation of the output just after overload, for 0.5 V VCNTL, it is about 3.2 LSBs
in normal case, i.e the output is stable in about 1 clock cycle after overload. With the clamp disabled, the value
approaches 4 LSBs meaning a longer time duration before the output stabilizes; however, with the clamp
enabled, there will be degradation in HD3 for PGA output levels > –2 dBFS. For example, for a –2 dBFS output
level, the HD3 degrades by approximately 3 dB.
The AFE5808 integrates an anti-aliasing filter in the form of a programmable low-pass filter (LPF) in the
transimpedance amplifier. The LPF is designed as a differential, active, 3rd order filter with a typical 18 dB per
octave roll-off. Programmable through the serial interface, the –1dB frequency corner can be set to one of 10, 15,
20, and 30 MHz. The filter bandwidth is set for all channels simultaneously.
A selectable DC offset correction circuit is implemented in the PGA as well. This correction circuit is similar to the
one used in the LNA. It extracts the DC component of the PGA outputs and feeds back to the PGA’s
complimentary inputs for DC offset correction. This DC offset correction circuit also has a high-pass response
with a cut-off frequency of 80 kHz.
ANALOG TO DIGITAL CONVERTER
The analog-to-digital converter (ADC) of the AFE5808 employs a pipelined converter architecture that consists of
a combination of multi-bit and single-bit internal stages. Each stage feeds its data into the digital error correction
logic, ensuring excellent differential linearity and no missing codes at the 14-bit level. The 14 bits given out by
each channel are serialized and sent out on a single pair of pins in LVDS format. All eight channels of the
AFE5808 operate from a common input clock (CLKP/M). The sampling clocks for each of the eight channels are
generated from the input clock using a carefully matched clock buffer tree. The 14x clock required for the
serializer is generated internally from the CLKP/M pins. A 7x and a 1x clock are also given out in LVDS format,
along with the data, to enable easy data capture. The AFE5808 operates from internally-generated reference
voltages that are trimmed to improve the gain matching across devices. The nominal values of REFP and REFM
are 1.5 V and 0.5 V, respectively. Alternately, the device also supports an external reference mode that can be
enabled using the serial interface.
Using serialized LVDS transmission has multiple advantages, such as a reduced number of output pins (saving
routing space on the board), reduced power consumption, and reduced effects of digital noise coupling to the
analog circuit inside the AFE5808.
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CONTINUOUS-WAVE (CW) BEAMFORMER
Continuous-wave Doppler is a key function in mid-end to high-end ultrasound systems. Compared to the TGC
mode, the CW path needs to handle high dynamic range along with strict phase noise performance. CW
beamforming is often implemented in analog domain due to the mentioned strict requirements. Multiple
beamforming methods are being implemented in ultrasound systems, including passive delay line, active mixer,
and passive mixer. Among all of them, the passive mixer approach achieves optimized power and noise. It
satisfies the CW processing requirements, such as wide dynamic range, low phase noise, accurate gain and
phase matching.
A simplified CW path block diagram and an in-phase or quadrature (I/Q) channel block diagram are illustrated
below respectively. Each CW channel includes a LNA, a voltage-to-current converter, a switch-based mixer, a
shared summing amplifier with a low-pass filter, and clocking circuits. All blocks include well-matched in-phase
and quadrature channels to achieve good image frequency rejection as well as beamforming accuracy. As a
result, the image rejection ratio from an I/Q channel is better than –46 dBc, which is desired in ultrasound
systems.
I-CLK
LNA1
Voltage to
Current
Converter
I-CH
Q-CH
Q-CLK
Sum Amp
with LPF
1×fcw CLK
I-CH
Clock
Distribution
Circuits
Q-CH
N×fcw CLK
Sum Amp
with LPF
I-CLK
LNA8
Voltage to
Current
Converter
I-CH
Q-CH
Q-CLK
Figure 68. Simplified Block Diagram of CW Path
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ACT1
500Ω
IN1
INPUT1
INM1
Mixer Clock 1
LNA1
Cext
500Ω
ACT2
500Ω
IN2
INPUT2
INM2
Mixer Clock 2
CW_AMPINM
LNA2
500Ω
Rint/Rext
CW_OUTP
I/V Sum
Amp
10Ω
10Ω
CW _AMPINP
Rint/Rext
CW_OUTM
Cext
CW I or Q CHANNEL
Structure
ACT8
500Ω
IN8
INPUT8
INM8
Mixer Clock 8
LNA8
500Ω
Note: the 10~15Ω resistors at CW_AMPINM/P are due to internal IC routing and can create slight attenuation.
Figure 69. A Complete In-phase or Quadrature Phase Channel
The CW mixer in the AFE5808 is passive and switch based; passive mixer adds less noise than active mixers. It
achieves good performance at low power. The below illustration and equations describe the principles of mixer
operation, where Vi(t), Vo(t), and LO(t) are input, output, and local oscillator (LO) signals for a mixer respectively.
The LO(t) is square-wave based and includes odd harmonic components as the below equation expresses:
Vi(t)
Vo(t)
LO(t)
Figure 70. Block Diagram of Mixer Operation
Vi(t) = sin (w0 t + wd t + j ) + f (w0 t )
4é
1
1
ù
sin (w0 t ) + sin (3w0 t ) + sin (5w0 t )...ú
ê
3
5
pë
û
2
Vo(t) = éëcos (wd t + f ) - cos (2w0 t - wd t + f )...ùû
p
LO(t) =
44
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From the above equations, the 3rd and 5th order harmonics from the LO can interface with the 3rd and 5th order
harmonic signals in the Vi(t); or the noise around the 3rd and 5th order harmonics in the Vi(t). Therefore the
mixer’s performance is degraded. In order to eliminate this side effect due to the square-wave demodulation, a
proprietary harmonic suppression circuit is implemented in the AFE5808. The 3rd and 5th harmonic components
from the LO can be suppressed by over 12 dB. Thus the LNA output noise around the 3rd and 5th order harmonic
bands will not be down-converted to base band. Hence, better noise figure is achieved. The conversion loss of
the mixer is about –4 dB which is derived from
20log10
2
p
The mixed current outputs of the 8 channels are summed together internally. An internal low noise operational
amplifier is used to convert the summed current to a voltage output. The internal summing amplifier is designed
to accomplish low power consumption, low noise, and ease of use. CW outputs from multiple AFE5808s can be
further combined on system board to implement a CW beamformer with more than 8 channels. More detail
information can be found in the application information section.
Multiple clock options are supported in the AFE5808 CW path. Two CW clock inputs are required: N × ƒcw clock
and 1 × ƒcw clock, where ƒcw is the CW transmitting frequency and N could be 16, 8, 4, or 1. Users have the
flexibility to select the most convenient system clock solution for the AFE5808. In the 16 × ƒcw and 8 × ƒcw
modes, the 3rd and 5th harmonic suppression feature can be supported. Thus the 16 × ƒcw and 8 × ƒcw modes
achieves better performance than the 4 × ƒcw and 1 × ƒcw modes
16 × ƒcw Mode
The 16 × ƒcw mode achieves the best phase accuracy compared to other modes. It is the default mode for CW
operation. In this mode, 16 × ƒcw and 1 × ƒcw clocks are required. 16 × fcw generates LO signals with 16
accurate phases. Multiple AFE5808s can be synchronized by the 1 × ƒcw , that is LO signals in multiple AFEs
can have the same starting phase. The phase noise spec is critical only for 16X clock. 1X clock is for
synchronization only and doesn’t require low phase noise. Please see the phase noise requirement in the section
of application information.
The top level clock distribution diagram is shown in the below Figure 71. Each mixer's clock is distributed through
a 16 × 8 cross-point switch. The inputs of the cross-point switch are 16 different phases of the 1x clock. It is
recommended to align the rising edges of the 1 x ƒcw and 16 x ƒcw clocks.
The cross-point switch distributes the clocks with appropriate phase delay to each mixer. For example, Vi(t) is a
1
received signal with a delay of 16
T
, a delayed LO(t) should be applied to the mixer in order to compensate for
1
2p
T
16
16
the
delay. Thus a 22.5⁰ delayed clock, that is
, is selected for this channel. The mathematic calculation is
expressed in the following equations:
é æ
ù
1 ö
Vi(t) = sin êw0 ç t +
÷ + wd t ú = sin [w0 t + 22.5° + wd t ]
ëê è 16 f0 ø
ûú
LO(t) =
é æ
4
1 öù 4
sin êw0 ç t +
÷ ú = sin [w0 t + 22.5°]
p
êë è 16 f0 ø úû p
Vo(t) =
2
cos (wd t ) + f (wn t )
p
(3)
Vo(t) represents the demodulated Doppler signal of each channel. When the doppler signals from N channels are
summed, the signal to noise ratio improves.
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Fin 16X Clock
www.ti.com
INV
D Q
Fin 1X Clock
Fin 1X Clock
16 Phase Generator
1X Clock
Phase 0º
1X Clock
Phase 22.5º
SPI
1X Clock
Phase 292.5º
1X Clock
Phase 315º
1X Clock
Phase 337.5º
16-to-8 Cross Point Switch
Mixer 1
1X Clock
Mixer 2
1X Clock
Mixer 3
1X Clock
Mixer 6
1X Clock
Mixer 7
1X Clock
Mixer 8
1X Clock
Figure 71.
Figure 72. 1x and 16x CW Clock Timing
8 × ƒcw and 4 × ƒcw Modes
8 × ƒcw and 4 × ƒcw modes are alternative modes when higher frequency clock solution (that is 16 × ƒcw clock) is
not available in system. The block diagram of these two modes is shown below.
46
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Good phase accuracy and matching are also maintained. Quadature clock generator is used to create in-phase
and quadrature clocks with exact 90° phase difference. The only difference between 8 × ƒcw and 4 × ƒcw modes
is the accessibility of the 3rd and 5th harmonic suppression filter. In the 8 × ƒcw mode, the suppression filter can
1
be supported. In both modes, 16
T
phase delay resolution is achieved by weighting the in-phase and quadrature
1
T
16
paths correspondingly. For example, if a delay of
or 22.5° is targeted, the weighting coefficients should
follow the below equations, assuming Iin and Qin are sin(ω0t) and cos(ω0t) respectively:
æ
1 ö
æ 2p ö
æ 2p ö
Idelayed (t) = Iin cos ç ÷ + Qin sin ç ÷ = Iin ç t +
÷
è 16 ø
è 16 ø
è 16 f0 ø
æ
1 ö
æ 2p ö
æ 2p ö
Qdelayed (t) = Qin cos ç ÷ - Iin sin ç ÷ = Qin ç t +
÷
è 16 ø
è 16 ø
è 16 f0 ø
(4)
Therefore after I/Q mixers, phase delay in the received signals is compensated. The mixers’ outputs from all
channels are aligned and added linearly to improve the signal to noise ratio. It is preferred to have the 4 × ƒcw or
8 × ƒcw and 1 × ƒcw clocks aligned both at the rising edge.
INV
4X/8X Clock
I/Q CLK
Generator
D Q
1X Clock
LNA2~8
In-phase
CLK
Summed
In-Phase
Quadrature
CLK
I/V
Weight
Weight
LNA1
I/V
Weight
Summed
Quadrature
Weight
Figure 73. 8 X ƒcw and 4 X ƒcw Block Diagram
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Figure 74. 8 x ƒcw and 4 x ƒcw Timing Diagram
1 × ƒcw Mode
1
T
The 1x ƒcw mode requires in-phase and quadrature clocks with low phase noise specifications. The 16 phase
delay resolution is also achieved by weighting the in-phase and quadrature signals as described in the 8 × ƒcw
and 4 × ƒcw modes.
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Syncronized I/Q
CLOCKs
LNA2~8
In-phase
CLK
Summed
In-Phase
Quadrature
CLK
I/V
Weight
Weight
LNA1
I/V
Weight
Summed
Quadrature
Weight
Figure 75. Block Diagram of 1 x ƒcw mode
EQUIVALENT CIRCUITS
CM
CM
(a) INP
(b) INM
(c) ACT
S0492-01
Figure 76. Equivalent Circuits of LNA inputs
S0493-01
Figure 77. Equivalent Circuits of VCNTLP/M
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VCM
5 kΩ
5 kΩ
CLKP
CLKM
(a) CW 1X and 16X Clocks
(b) ADC Input Clocks
S0494-01
Figure 78. Equivalent Circuits of Clock Inputs
(a) CW_OUTP/M
(b) CW_AMPINP/M
S0495-01
Figure 79. Equivalent Circuits of CW Summing Amplifier Inputs and Outputs
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+
–
Low
+Vdiff
High
AFE5808
OUTP
+
–
–Vdiff
+
–
High
Vcommon
Low
External
100-W Load
Rout
OUTM
Switch impedance is
nominally 50 W (±10%)
S0496-01
Figure 80. Equivalent Circuits of LVDS Outputs
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APPLICATION INFORMATION
IN CH1
IN CH2
IN CH3
IN CH4
IN CH5
IN CH6
IN CH7
IN CH8
1.4V
0.1μF
N*0.1μF
AVSS
DVDD
1.8VD
N*0.1μF
DVSS
D1P
0.1μF
IN1P
D1M
0.1μF
15nF
IN1M
D2P
0.1μF
1μF
ACT2
D2M
0.1μF
IN2P
D3P
15nF
IN2M
D3M
1μF
ACT3
D4P
0.1μF
CLKP_1X
0.1μF
CLKM_1X
0.1μF
IN3P
D4M
15nF
IN3M
D5P
1μF
ACT4
D5M
0.1μF
IN4P
D6P
15nF
IN4M
D6M
1μF
ACT5
0.1μF
IN5P
15nF
IN5M
1μF
ACT6
0.1μF
IN6P
15nF
IN6M
1μF
ACT7
CLKP
CLKM
0.1μF CLKP_16X
0.1μF
CLKM_16X
AFE5808
CLOCK
INPUTS
SOUT
SDATA
SCLK
D7P
SEN
AFE5808
D7M
AFE5808
RESET
D8P
PDN_VCA
D8M
ANALOG INPUTS
ANALOG OUTPUTS
REF/BIAS DECOUPLING
LVDS OUTPUTS
PDN_GLOBAL
DCLKM
FCLKP
OTHER
AFE5808
OUTPUT
FCLKM
IN7P
15nF
IN7M
CW_IP_AMPINP
REXT (optional)
1μF
ACT8
CW_IP_OUTM
CCW
0.1μF
IN8P
CW_IP_AMPINM
REXT (optional)
15nF
IN8M
CW_IP_OUTP
CCW
OTHER
AFE5808
OUTPUT
CVCNTL
470pF
VCNTLP
VCNTLM
CVCNTL
470pF
VREF_IN
DIGITAL
INPUTS
PDN_ADC
DCLKP
0.1μF
VHIGH
RVCNTL
200Ω
N*0.1μF
AVSS
10μF
ACT1
CM_BYP
VCNTLM IN
1.8VA
1μF
1μF
VCNTLP IN
10μF
Clock termination
depends on clock types
LVDS, PECL, or CMOS
1μF
RVCNTL
200Ω
3.3VA
AVDD_ADC
0.1μF
AVSS
10μF
AVDD
5VA
AVDD_5V
10μF
OTHER
AFE5808
OUTPUT
CW_QP_AMPINP
CW_QP_OUTM
CCW
CW_QP_AMPINM
REXT (optional)
CW_QP_OUTP
CCW
REFM
CAC R
SUM
CAC RSUM
CAC R
SUM
TO
SUMMING
AMP
CAC RSUM
CAC R
SUM
CAC RSUM
CAC R
SUM
REXT (optional)
TO
SUMMING
AMP
DNCs
REFP
AVSS
DVSS
OTHER
AFE5808
OUTPUT
CAC RSUM
S0497-01
Figure 81. Application Circuit
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A typical application circuit diagram is listed above. The configuration for each block is discussed below.
LNA CONFIGURATION
LNA Input Coupling and Decoupling
The LNA closed-loop architecture is internally compensated for maximum stability without the need of external
compensation components. The LNA inputs are biased at 2.4 V and AC coupling is required. A typical input
configuration is shown in Figure 82. CIN is the input AC coupling capacitor. CACT is a part of the active termination
feedback path. Even if the active termination is not used, the CACT is required for the clamp functionality.
Recommended values for CACT ≥ 1 µF and CIN are ≥ 0.1 µF. A pair of clamping diodes is commonly placed
between the T/R switch and the LNA input. Schottky diodes with suitable forward drop voltage (for example, the
BAT754/54 series, the BAS40 series, the MMBD7000 series, or similar) can be considered depending on the
transducer echo amplitude.
AFE
CLAMP
CACT
ACTx
CIN
INPx
CBYPASS
INMx
Input
LNAx
Optional
Diodes
DC Offset
Correction
S0498-01
Figure 82. LNA Input Configurations
This architecture minimizes any loading of the signal source that may otherwise lead to a frequency-dependent
voltage divider. The closed-loop design yields very low offsets and offset drift. CBYPASS (≥ 0.015 µF) is used to set
the high-pass filter cut-off frequency and decouple the complimentary input. Its cut-off frequency is inversely
proportional to the CBYPASS value, The HPF cut-off frequency can be adjusted through the register 59[3:2] a
Table 15 lists. Low frequency signals at T/R switch output, such as signals with slow ringing, can be filtered out.
In addition, the HPF can minimize system noise from DC-DC converters, pulse repetition frequency (PRF)
trigger, and frame clock. Most ultrasound systems’ signal processing unit includes digital high-pass filters or
band-pass filters (BPFs) in FPGAs or ASICs. Further noise suppression can be achieved in these blocks. In
addition, a digital HPF is available in the AFE5808 ADC. If low frequency signal detection is desired in some
applications, the LNA HPF can be disabled.
Table 15. LNA HPF Settings (CBYPASS = 15 nF)
Reg59[3:2] (0x3B[3:2])
Frequency
00
100 KHz
01
50 KHz
10
200 KHz
11
150 KHz
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CM_BYP and VHIGH pins, which generate internal reference voltages, need to be decoupled with ≥ 1-µF
capacitors. Bigger bypassing capacitors (> 2.2 µF) may be beneficial if low frequency noise exists in system.
LNA Noise Contribution
The noise spec is critical for LNA and it determines the dynamic range of entire system. The LNA of the
AFE5808 achieves low power and an exceptionally low-noise voltage of 0.63 nV/√Hz, and a low current noise of
2.7 pA/√Hz.
Typical ultrasonic transducer’s impedance Rs varies from tens of ohms to several hundreds of ohms. Voltage
noise is the dominant noise in most cases; however, the LNA current noise flowing through the source
impedance (Rs) generates additional voltage noise.
2
2
LNA _ Noise total = VLNAnoise
+ R2s ´ ILNAnoise
(5)
The AFE5808 achieves low noise figure (NF) over a wide range of source resistances as shown in Figure 32,
Figure 33, andFigure 34.
Active Termination
In ultrasound applications, signal reflection exists due to long cables between transducer and system. The
reflection results in extra ringing added to echo signals in PW mode. Since the axial resolution depends on echo
signal length, such ringing effect can degrade the axial resolution. Hence, either passive termination or active
termination, is preferred if good axial resolution is desired. Figure 83 shows three termination configurations:
Rs
LNA
(a) No Termination
Rf
Rs
LNA
(b) Active Termination
Rs
Rt
LNA
(c) Passive Termination
S0499-01
Figure 83. Termination Configurations
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Under the no termination configuration, the input impedance of the AFE5808 is about 6 kΩ (8K//20pF) at 1 MHz.
Passive termination requires external termination resistor Rt, which contributes to additional thermal noise.
The LNA supports active termination with programmable values, as shown in Figure 84 .
450Ω
900Ω
1800Ω
ACTx
3600Ω
4500Ω
INPx
Input
INMx
LNAx
AFE
S0500-01
Figure 84. Active Termination Implementation
The AFE5808 has four pre-settings 50,100, 200, and 400 Ω, which are configurable through the registers. Other
termination values can be realized by setting the termination switches shown in the above figure. Register [52] is
used to enable these switches. The input impedance of the LNA under the active termination configuration
approximately follows:
ZIN =
Rf
AnLNA
1+
2
(6)
Table 8 lists the LNA RINs under different LNA gains. System designers can achieve fine tuning for different
probes.
The equivalent input impedance is given by Equation 7 where RIN (8K) and CIN (20 pF) are the input resistance
and capacitance of the LNA.
ZIN =
Rf
/ /CIN / /RIN
AnLNA
1+
2
(7)
Therefore, the ZIN is frequency dependent and it decreases as frequency increases shown in Figure 10. Since 2
MHz to approximately 10 MHz is the most commonly used frequency range in medical ultrasound, this rolling-off
effect doesn’t impact system performance greatly. Active termination can be applied to both CW and TGC
modes. Since each ultrasound system includes multiple transducers with different impedances, the flexibility of
impedance configuration is a great plus.
Figure 32, Figure 33, andFigure 34 shows the NF under different termination configurations. It indicates that no
termination achieves the best noise figure; active termination adds less noise than passive termination. Thus
termination topology should be carefully selected based on each use scenario in ultrasound.
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LNA Gain Switch Response
The LNA gain is programmable through SPI. The gain switching time depends on the SPI speed as well as the
LNA gain response time. During the switching, glitches might occur and they can appear as artifacts in images.
LNA gain switching in a single imaging line may not be preferred, although digital signal processing might be
used here for glitch suppression.
VOLTAGE-CONTROLLED-ATTENUATOR
The attenuator in the AFE5808 is controlled by a pair of differential control inputs, the VCNTLM/P pins. The
differential control voltage spans from 0 to 1.5 V. This control voltage varies the attenuation of the attenuator
based on its linear-in-dB characteristic. Its maximum attenuation (minimum channel gain) appears at VCNTLP –
VCNTLM = 1.5 V, and minimum attenuation (maximum channel gain) occurs at VCNTLP- VCNTLM = 0. The
typical gain range is 40dB and remains constant, independent of the PGA setting.
When only single-ended VCNTL signal is available, this 1.5 VPP signal can be applied on the VCNTLP pin with
the VCNTLM pin connected to ground. As shown in Figure 85, the TGC gain curve is inversely proportional to
the VCNTLP – VCNTLM.
1.5V
VCNTLP
VCNTLM = 0V
X+40dB
TGC Gain
XdB
(a) Single-Ended Input at VCNTLP
1.5V
VCNTLP
0.75V
VCNTLM
0V
X+40dB
TGC Gain
XdB
(b) Differential Inputs at VCNTLP and VCNTLM
W0004-01
Figure 85. VCNTLP and VCNTLM Configurations
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As discussed in the theory of operation, the attenuator architecture uses seven attenuator segments that are
equally spaced in order to approximate the linear-in-dB gain-control slope. This approximation results in a
monotonic slope; the gain ripple is typically less than ±0.5dB.
The control voltage input (VCNTLM/P pins) represents a high-impedance input. The VCNTLM/P pins of multiple
AFE5808 devices can be connected in parallel with no significant loading effects. When the voltage level (VCNTLPVCNTLM) is above 1.5 V or below 0 V, the attenuator continues to operate at its maximum attenuation level or
minimum attenuation level respectively. It is recommended to limit the voltage from –0.3 to 2 V.
When the AFE5808 operates in CW mode, the attenuator stage remains connected to the LNA outputs.
Therefore, TI recommends to power down the VCA using the PDN_VCA register bit. In this case, VCNTLP-VCNTLM
voltage does not matter.
The AFE5808 gain-control input has a –3dB bandwidth of approximately 800KHz. This wide bandwidth, although
useful in many applications (for example, fast VCNTL response), can also allow high-frequency noise to modulate
the gain control input and finally affect the Doppler performance. In practice, this modulation can easily be
avoided by additional external filtering (RVCNTL and CVCNTL) at VCNTLM/P pins as Figure 80 shows. However, the
external filter's cutoff frequency cannot be kept too low as this results in low gain response time. Without external
filtering, the gain control response time is typically less than 1 μs to settle within 10% of the final signal level of 1
VPP (–6 dBFS) output as indicated in Figure 51 and Figure 52.
Typical VCNTLM/P signals are generated by an 8bit to 12bit 10MSPS digital to analog converter (DAC) and a
differential operation amplifier. TI’s DACs, such as TLV5626 and DAC7821/11 (10MSPS/12bit), could be used to
generate TGC control waveforms. Differential amplifiers with output common mode voltage control (for example,
THS4130 and OPA1632) can connect the DAC to the VCNTLM/P pins. The buffer amplifier can also be configured
as an active filter to suppress low frequency noise. The VCNTLM/P circuit shall achieve low noise in order to
prevent the VCNTLM/P noise being modulated to RF signals. TI recommends that VCNTLM/P noise is below 25
nV/rtHz at 1 KHz and 5 nV/rtHz at 50 kHz.In high channel count premium systems, the VCNTLM/P noise
requirement is higher."
More information can be found in the literatures SLOS318F and SBAA150. The VCNTL vs Gain curves can be
found in Figure 2. The below table also shows the absolute gain vs. VCNTL, which may help program DAC
correspondingly.
In PW Doppler and color Doppler modes, VCNTL noise should be minimized to achieve the best close-in phase
noise and SNR. Digital VCNTL feature is implemented to address this need in the AFE5808. In the digital VCNTL
mode, no external VCNTL is needed.
Table 16. VCNTLP–VCNTLM vs Gain Under Different LNA and PGA Gain Settings (Low Noise Mode)
VCNTLP–VCNTLM
(V)
Gain (dB)
LNA = 12 dB
PGA = 24 dB
Gain (dB)
LNA = 18 dB
PGA = 24 dB
Gain (dB)
LNA = 24 dB
PGA = 24 dB
Gain (dB)
LNA = 12 dB
PGA = 30 dB
Gain (dB)
LNA = 18 dB
PGA = 30 dB
Gain (dB)
LNA = 24 dB
PGA = 30 dB
0
36.45
42.45
48.45
42.25
48.25
54.25
0.1
33.91
39.91
45.91
39.71
45.71
51.71
0.2
30.78
36.78
42.78
36.58
42.58
48.58
0.3
27.39
33.39
39.39
33.19
39.19
45.19
0.4
23.74
29.74
35.74
29.54
35.54
41.54
0.5
20.69
26.69
32.69
26.49
32.49
38.49
0.6
17.11
23.11
29.11
22.91
28.91
34.91
0.7
13.54
19.54
25.54
19.34
25.34
31.34
0.8
10.27
16.27
22.27
16.07
22.07
28.07
0.9
6.48
12.48
18.48
12.28
18.28
24.28
1.0
3.16
9.16
15.16
8.96
14.96
20.96
1.1
–0.35
5.65
11.65
5.45
11.45
17.45
1.2
–2.48
3.52
9.52
3.32
9.32
15.32
1.3
–3.58
2.42
8.42
2.22
8.22
14.22
1.4
–4.01
1.99
7.99
1.79
7.79
13.79
1.5
–4
2
8
1.8
7.8
13.8
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CW OPERATION
CW Summing Amplifier
In order to simplify CW system design, a summing amplifier is implemented in the AFE5808 to sum and convert
8-channel mixer current outputs to a differential voltage output. Low noise and low power are achieved in the
summing amplifier while maintaining the full dynamic range required in CW operation.
This summing amplifier has 5 internal gain adjustment resistors which can provide 32 different gain settings
(register 54[4:0], Figure 84 and Table 11). System designers can easily adjust the CW path gain depending on
signal strength and transducer sensitivity. For any other gain values, an external resistor option is supported. The
gain of the summation amplifier is determined by the ratio between the 500Ω resistors after LNA and the internal
or external resistor network REXT/INT. Thus the matching between these resistors plays a more important role than
absolute resistor values. Better than 1% matching is achieved on chip. Due to process variation, the absolute
resistor tolerance could be higher. If external resistors are used, the gain error between I/Q channels or among
multiple AFEs may increase. It is recommended to use internal resistors to set the gain in order to achieve better
gain matching (across channels and multiple AFEs). With the external capacitor CEXT , this summing amplifier
has 1st order LPF response to remove high frequency components from the mixers, such as 2f0±fd. Its cut-off
frequency is determined by:
fHP =
1
2pRINT/EXT CEXT
(8)
Note that when different gain is configured through register 54[4:0], the LPF response varies as well.
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CEXT
REXT
250Ω
250Ω
RINT
500Ω
1000Ω
2000Ω
CW_AMPINP
CW_AMPINM
CW_OUTM
I/V Sum
Amp
CW_OUTP
250Ω
250Ω
500Ω
RINT
1000Ω
2000Ω
REXT
CEXT
S0501-01
Figure 86. CW Summing Amplifier Block Diagram
Multiple AFE5808s are usually utilized in parallel to expand CW beamformer channel count. These AFE5808s’
CW outputs can be summed and filtered externally further to achieve desired gain and filter response. AC
coupling capacitors CAC are required to block DC component of the CW carrier signal. CAC can vary from 1 to
10 μF depending on the desired low frequency Doppler signal from slow blood flow. Multiple AFE5808s’ I/Q
outputs can be summed together with a low noise external differential amplifiers before 16/18-bit differential
audio ADCs. TI’s ultralow noise differential precision amplifier OPA1632 and THS4130 are suitable devices.
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AFE No.4
AFE No.3
AFE No.2
ACT1
500 Ω
INP1
INPUT1
INM1
AFE No.1
Mixer 1
Clock
LNA1
500 Ω
ACT2
500 Ω
INP2
INPUT2
INM2
Ext Sum
Amp
Cext
Mixer 2
Clock
Rint/Rext
CW_AMPINP
CW_AMPINM
LNA2
I/V Sum
Amp
CW_OUTM
CW_OUTP
Rint/Rext
500 Ω
CAC
RSUM
Cext
CW I or Q CHANNEL
Structure
ACT8
500 Ω
INP8
INPUT8
INM8
Mixer 8
Clock
LNA8
500 Ω
S0502-01
Figure 87. CW circuit with Multiple AFE5808s
NOTE
The local oscillator inputs of the passive mixer are cos(ωt) for I-CH and sin(ωt) for Q-CH
respectively. Depending on users' CW Doppler complex FFT processing, swapping I/Q
channels in FPGA or DSP may be needed in order to get correct blood flow directions.
The CW I/Q channels are well matched internally to suppress image frequency components in Doppler spectrum.
Low tolerance components and precise operational amplifiers should be used for achieving good matching in the
external circuits as well.
CW Clock Selection
The AFE5808 can accept differential LVDS, LVPECL, and other differential clock inputs as well as single-ended
CMOS clock. An internally generated VCM of 2.5 V is applied to CW clock inputs, that is CLKP_16X/ CLKM_16X
and CLKP_1X/ CLKM_1X. Since this 2.5 V VCM is different from the one used in standard LVDS or LVPECL
clocks, AC coupling is required between clock drivers and the AFE5808 CW clock inputs. When CMOS clock is
used, CLKM_1X and CLKM_16X should be tied to ground. Common clock configurations are illustrated in
Figure 88. Appropriate termination is recommended to achieve good signal integrity.
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3.3 V
130 Ω
83 Ω
CDCM7005
CDCE7010
3.3 V 0.1 μF
AFE
CLOCKs
0.1 μF
130 Ω
LVPECL
(a) LVPECL Configuration
100 Ω
CDCE72010
0.1 μF
0.1 μF
AFE
CLOCKs
LVDS
(b) LVDS Configuration
0.1μF
0.1μF
0.1μF
CLOCK
SOURCE
AFE
CLOCKs
50 Ω
0.1μF
(c) Transformer Based Configuration
CMOS CLK
Driver
AFE
CMOS CLK
CMOS
(d) CMOS Configuration
S0503-01
Figure 88. Clock Configurations
The combination of the clock noise and the CW path noise can degrade the CW performance. The internal
clocking circuit is designed for achieving excellent phase noise required by CW operation. The phase noise of
the AFE5808 CW path is better than 155 dBc/Hz at 1-kHz offset. Consequently the phase noise of the mixer
clock inputs needs to be better than 155 dBc/Hz.
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In the 16/8/4 × ƒcw operations modes, low phase noise clock is required for 16/8/4 × ƒcw clocks (that is
CLKP_16X/ CLKM_16X pins) in order to maintain good CW phase noise performance. The 1 × ƒcw clock (that is
CLKP_1X/ CLKM_1X pins) is only used to synchronize the multiple AFE5808 chips and is not used for
demodulation. Thus 1 × ƒcw clock’s phase noise is not a concern. However, in the 1 × ƒcw operation mode, low
phase noise clocks are required for both CLKP_16X/ CLKM_16X and CLKP_1X/ CLKM_1X pins since both of
them are used for mixer demodulation. In general, higher slew rate clock has lower phase noise; thus clocks with
high amplitude and fast slew rate are preferred in CW operation. In the CMOS clock mode, 5V CMOS clock can
achieve the highest slew rate.
Clock phase noise can be improved by a divider as long as the divider’s phase noise is lower than the target
phase noise. The phase noise of a divided clock can be improved approximately by a factor of 20logN dB where
N is the dividing factor of 16, 8, or 4. If the target phase noise of mixer LO clock 1׃cw is 160 dBc/Hz at 1 kHz off
carrier, the 16 × ƒcw clock phase noise should be better than 160 – 20log16 = 136 dBc/Hz. TI’s jitter cleaners
LMK048X/CDCM7005/CDCE72010 exceed this requirement and can be selected for the AFE5808. In the 4X/1X
modes, higher quality input clocks are expected to achieve the same performance since N is smaller. Thus the
16X mode is a preferred mode since it reduces the phase noise requirement for system clock design. In addition,
the phase delay accuracy is specified by the internal clock divider and distribution circuit. Note in the 16X
operation mode, the CW operation range is limited to 8 MHz due to the 16X CLK. The maximum clock frequency
for the 16X CLK is 128 MHz. In the 8X, 4X, and 1X modes, higher CW signal frequencies up to 15 MHz can be
supported with small degradation in performance, for example the phase noise is degraded by 9 dB at 15 MHz,
compared to 2 MHz.
As the channel number in a system increases, clock distribution becomes more complex. It is not preferred to
use one clock driver output to drive multiple AFEs since the clock buffer’s load capacitance increases by a factor
of N. As a result, the falling and rising time of a clock signal is degraded. A typical clock arrangement for multiple
AFE5808s is illustrated in Figure 89. Each clock buffer output drives one AFE5808 in order to achieve the best
signal integrity and fastest slew rate, that is better phase noise performance. When clock phase noise is not a
concern, for example, the 1 × ƒcw clock in the 16/8/4 × ƒcw operation modes, one clock driver output may excite
more than one AFE5808s. Nevertheless, special considerations should be applied in such a clock distribution
network design. In typical ultrasound systems, it is preferred that all clocks are generated from a same clock
source, such as 16 × ƒcw , 1 × ƒcw clocks, audio ADC clocks, RF ADC clock, pulse repetition frequency signal,
frame clock, and so forth. By doing this, interference due to clock asynchronization can be minimized.
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FPGA Clock/
Noisy Clock
n×16×CW Freq
LMK048X
CDCE72010
CDCM7005
16X CW
CLK
1X CW
CLK
CDCLVP1208
LMK0030X
LMK01000
CDCLVP1208
LMK0030X
LMK01000
AFE
AFE
AFE
AFE
8 Synchronized
1X CW CLKs
AFE
AFE
AFE
AFE
8 Synchronized
16 X CW CLKs
B0436-01
Figure 89. CW Clock Distribution
CW Supporting Circuits
As a general practice in CW circuit design, in-phase and quadrature channels should be strictly symmetrical by
using well matched layout and high accuracy components.
In systems, additional high-pass wall filters (20 to 500 Hz) and low-pass audio filters (10 to 100 kHz) with multiple
poles are usually needed. Since CW Doppler signal ranges from 20 Hz to 20 kHz, noise under this range is
critical. Consequently low noise audio operational amplifiers are suitable to build these active filters for CW postprocessing, for example, OPA1632 or OPA2211. More filter design techniques can be found from www.ti.com,
for example, TI’s active filter design tool http://focus.ti.com/docs/toolsw/folders/print/filter-designer.html
The filtered audio CW I/Q signals are sampled by audio ADCs and processed by DSP or PC. Although CW
signal frequency is from 20 Hz to 20 kHz, higher sampling rate ADCs are still preferred for further decimation and
SNR enhancement. Due to the large dynamic range of CW signals, high resolution ADCs (≥ 16 bit) are required,
such as ADS8413 (2 MSPS/16 bit/92 dBFS SNR) and ADS8472 (1 MSPS/16 bit/95 dBFS SNR). ADCs for inphase and quadature-phase channels must be strictly matched, not only amplitude matching but also phase
matching, in order to achieve the best I/Q matching. In addition, the in-phase and quadrature ADC channels must
be sampled simultaneously.
ADC OPERATION
ADC Clock Configurations
To ensure that the aperture delay and jitter are the same for all channels, the AFE5808 uses a clock tree
network to generate individual sampling clocks for each channel. The clock, for all the channels, are matched
from the source point to the sampling circuit of each of the eight internal ADCs. The variation on this delay is
described in the aperture delay parameter of the output interface timing. Its variation is given by the aperture jitter
number of the same table.
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FPGA Clock/
Noisy Clock
n × (20 to 65)MHz
TI Jitter Cleaner
LMK048X
CDCE72010
CDCM7005
20 to 65 MHz
ADC CLK
CDCLVP1208
LMK0030X
LMK01000
CDCE72010 has 10
outputs thus the buffer
may not be needed for
64CH systems
AFE
AFE
AFE
AFE
AFE
AFE
AFE
AFE
8 Synchronized
ADC CLKs
B0437-01
Figure 90. ADC Clock Distribution Network
The AFE5808 ADC clock input can be driven by differential clocks (sine wave, LVPECL or LVDS) or singled
clocks (LVCMOS) similar to CW clocks as shown in Figure 88. In the single-end case, TI recommends the use of
low jitter square signals (LVCMOS levels, 1.8-V amplitude). Please see TI document SLYT075 for further details
on the theory.
The jitter cleaner LMK048X/CDCM7005/CDCE72010 is suitable to generate the AFE5808’s ADC clock and
ensure the performance for the14bit ADC with 77-dBFS SNR. A clock distribution network is shown in Figure 90.
ADC Reference Circuit
The ADC’s voltage reference can be generated internally or provided externally. When the internal reference
mode is selected, the REFP/M becomes output pins and should be floated. When 3[15] = 1 and 1[13] = 1, the
device is configured to operate in the external reference mode in which the VREF_IN pin should be driven with a
1.4-V reference voltage and REFP/M must be left open. Since the input impedance of the VREF_IN is high, no
special drive capability is required for the 1.4-V voltage reference
The digital beam-forming algorithm in an ultrasound system relies on gain matching across all receiver channels.
A typical system would have about 12 octal AFEs on the board. In such a case, it is critical to ensure that the
gain is matched, essentially requiring the reference voltages seen by all the AFEs to be the same. Matching
references within the eight channels of a chip is done by using a single internal reference voltage buffer.
Trimming the reference voltages on each chip during production ensures that the reference voltages are wellmatched across different chips. When the external reference mode is used, a solid reference plane on a printed
circuit board can ensure minimal voltage variation across devices. More information on voltage reference design
can be found in the document SLYT339. The dominant gain variation in the AFE5808 comes from the VCA gain
variation. The gain variation contributed by the ADC reference circuit is much smaller than the VCA gain
variation. Hence, in most systems, using the ADC internal reference mode is sufficient to maintain good gain
matching among multiple AFE5808s. In addition, the internal reference circuit without any external components
achieves satisfactory thermal noise and phase noise performance.
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POWER MANAGEMENT
Power/Performance Optimization
The AFE5808 has options to adjust power consumption and meet different noise performances. This feature
would be useful for portable systems operated by batteries when low power is more desired. See the
characteristics information listed in the table of electrical characteristics as well as the typical characteristic plots.
Power Management Priority
Power management plays a critical role to extend battery life and ensure long operation time. The AFE5808 has
fast and flexible power down/up control which can maximize battery life. The AFE5808 can be powered-down or
powered-up through external pins or internal registers. The following table indicates the affected circuit blocks
and priorities when the power management is invoked. The higher priority controls can overwrite the lower
priority ones. In the device, all the power down controls are logically ORed to generate final power down for
different blocks. Thus, the higher priority controls can cover the lower priority controls
Table 17. Power Management Priority
Name
Blocks
Priority
Pin
PDN_GLOBAL
All
High
Pin
PDN_VCA
LNA + VCAT+ PGA
Medium
Register
VCA_PARTIAL_PDN
LNA + VCAT+ PGA
Low
Register
VCA_COMPLETE_PDN
LNA + VCAT+ PGA
Medium
Pin
PDN_ADC
ADC
Medium
Register
ADC_PARTIAL_PDN
ADC
Low
Register
ADC_COMPLETE_PDN
ADC
Medium
Register
PDN_VCAT_PGA
VCAT + PGA
Lowest
Register
PDN_LNA
LNA
Lowest
Partial Power-Up and Power-Down Mode
The partial power-up and power-down mode is also called as fast power-up and power-down mode. In this mode,
most amplifiers in the signal path are powered down, while the internal reference circuits remain active as well as
the LVDS clock circuit, that is the LVDS circuit still generates its frame and bit clocks.
The partial power down function allows the AFE5808 to be wake up from a low-power state quickly. This
configuration ensures that the external capacitors are discharged slowly; thus a minimum wake-up time is
needed as long as the charges on those capacitors are restored. The VCA wake-up response is typically about 2
μs or 1% of the power down duration whichever is larger. The longest wake-up time depends on the capacitors
connected at INP and INM, as the wake-up time is the time required to recharge the caps to the desired
operating voltages. For 0.1 μF at INP and 15 nF at INM can give a wake-up time of 2.5 ms. For larger capacitors
this time will be longer. The ADC wake-up time is about 1 μs. Thus the AFE5808 wake-up time is more
dependent on the VCA wake-up time. This also assumes that the ADC clock has been running for at least 50 µs
before normal operating mode resumes. The power-down time is instantaneous, less than 1.0 µs.
This fast wake-up response is desired for portable ultrasound applications in which the power saving is critical.
The pulse repetition frequency of a ultrasound system could vary from 50 kHz to 500 Hz, while the imaging depth
(that is the active period for a receive path) varies from 10 μs to hundreds of µs. The power saving can be pretty
significant when a system’s PRF is low. In some cases, only the VCA would be powered down while the ADC
keeps running normally to ensure minimal impact to FPGAs.
In the partial power-down mode, the AFE5808 typically dissipates only 26 mW/ch, representing an 80% power
reduction compared to the normal operating mode. This mode can be set using either pins (PDN_VCA and
PDN_ADC) or register bits (VCA_PARTIAL_PDN and ADC_PARTIAL_PDN).
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Complete Power-Down Mode
To achieve the lowest power dissipation of 0.7 mW/CH, the AFE5808 can be placed into a complete power-down
mode. This mode is controlled through the registers ADC_COMPLETE_PDN, VCA_COMPLETE_PDN or
PDN_GLOBAL pin. In the complete power-down mode, all circuits including reference circuits within the
AFE5808 are powered down; and the capacitors connected to the AFE5808 are discharged. The wake-up time
depends on the time needed to recharge these capacitors. The wake-up time depends on the time that the
AFE5808 spends in shutdown mode. 0.1 μF at INP and 15 nF at INM can give a wake-up time close to 2.5 ms.
Power Saving in CW Mode
Usually only half the number of channels in a system are active in the CW mode. Thus the individual channel
control through ADC_PDN_CH and VCA_PDN_CH can power down unused channels and save
power consumption greatly. Under the default register setting in the CW mode, the voltage controlled attenuator,
PGA, and ADC are still active. During the debug phase, both the PW and CW paths can be running
simultaneously. In real operation, these blocks need to be powered down manually.
TEST MODES
The AFE5808 includes multiple test modes to accelerate system development. The ADC test modes have been
discussed in the register description section.
The VCA has a test mode in which the CH7 and CH8 PGA outputs can be brought to the CW pins. By monitoring
these PGA outputs, the functionality of VCA operation can be verified. The PGA outputs are connected to the
virtual ground pins of the summing amplifier (CW_IP_AMPINM/P, CW_QP_AMPINM/P) through 5-kΩ resistors.
The PGA outputs can be monitored at the summing amplifier outputs when the LPF capacitors CEXT are
removed. Please note that the signals at the summing amplifier outputs are attenuated due to the 5-kΩ resistors.
The attenuation coefficient is RINT/EXT / 5 kΩ
If users would like to check the PGA outputs without removing CEXT, an alternative way is to measure the PGA
outputs directly at the CW_IP_AMPINM/P and CW_QP_AMPINM/P when the CW summing amplifier is powered
down
Some registers are related to this test mode. PGA Test Mode Enable: Reg59[9]; Buffer Amplifier Power Down
Reg59[8]; and Buffer Amplifier Gain Control Reg54[4:0]. Based on the buffer amplifier configuration, the registers
can be set in different ways:
Configuration 1:
In this configuration, the test outputs can be monitored at CW_AMPINP/M
• Reg59[9] = 1; Test mode enabled
• Reg59[8] = 0; Buffer amplifier powered down
Configuration 2:
In this configuration, the test outputs can be monitored at CW_OUTP/M
• Reg59[9] = 1; Test mode enabled
• Reg59[8] = 1; Buffer amplifier powered on
• Reg54[4:0] = 10H; Internal feedback 2K resistor enabled. Different values can be used as well
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PGA_P
Cext
5K
ACT
500 Ω
INP
INPUT
INM
Mixer
Clock
Rint/Rext
CW_AMPINP
CW_AMPINM
LNA
500 Ω
CW_OUTM
I/V Sum
Amp
Rint/Rext
CW_OUTP
5K
Cext
PGA_M
S0504-01
Figure 91. AFE5808 PGA Test Mode
POWER SUPPLY, GROUNDING AND BYPASSING
In a mixed-signal system design, power supply and grounding design plays a significant role. The AFE5808
distinguishes between two different grounds: AVSS (Analog Ground) and DVSS (digital ground). In most cases, it
should be adequate to lay out the printed circuit board (PCB) to use a single ground plane for the AFE5808.
Care should be taken that this ground plane is properly partitioned between various sections within the system to
minimize interactions between analog and digital circuitry. Alternatively, the digital (DVDD) supply set consisting
of the DVDD and DVSS pins can be placed on separate power and ground planes. For this configuration, the
AVSS and DVSS grounds should be tied together at the power connector in a star layout. In addition, optical
isolator or digital isolators, such as ISO7240, can separate the analog portion from the digital portion completely.
Consequently they prevent digital noise to contaminate the analog portion. Table 17 lists the related circuit blocks
for each power supply.
Table 18. Supply vs Circuit Blocks
Power Supply
Ground
Circuit Blocks
AVDD (3.3VA)
AVSS
LNA, attenuator, PGA with clamp
and BPF, reference circuits, CW
summing amplifier, CW mixer,
VCA SPI
AVDD_5V (5VA)
AVSS
LNA, CW clock circuits, reference
circuits
AVDD_ADC (1.8VA)
AVSS
ADC analog and reference
circuits
DVDD (1.8VD)
DVSS
LVDS and ADC SPI
All bypassing and power supplies for the AFE5808 should be referenced to their corresponding ground planes.
All supply pins should be bypassed with 0.1-µF ceramic chip capacitors (size 0603 or smaller). In order to
minimize the lead and trace inductance, the capacitors should be located as close to the supply pins as possible.
Where double-sided component mounting is allowed, these capacitors are best placed directly under the
package. In addition, larger bipolar decoupling capacitors 2.2 to 10 µF, effective at lower frequencies) may also
be used on the main supply pins. These components can be placed on the PCB in proximity (< 0.5 inch or 12.7
mm) to the AFE5808 itself.
The AFE5808 has a number of reference supplies needed to be bypassed, such CM_BYP and VHIGH. These
pins should be bypassed with at least 1 µF; higher value capacitors can be used for better low-frequency noise
suppression. For best results, choose low-inductance ceramic chip capacitors (size 0402, > 1 µF) and place
them as close as possible to the device pins.
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High-speed mixed signal devices are sensitive to various types of noise coupling. One primary source of noise is
the switching noise from the serializer and the output buffer/drivers. For the AFE5808, care has been taken to
ensure that the interaction between the analog and digital supplies within the device is kept to a minimal amount.
The extent of noise coupled and transmitted from the digital and analog sections depends on the effective
inductances of each of the supply and ground connections. Smaller effective inductance of the supply and
ground pins leads to improved noise suppression. For this reason, multiple pins are used to connect each supply
and ground sets. It is important to maintain low inductance properties throughout the design of the PCB layout by
use of proper planes and layer thickness.
BOARD LAYOUT
Proper grounding and bypassing, short lead length, and the use of ground and power-supply planes are
particularly important for high-frequency designs. Achieving optimum performance with a high-performance
device such as the AFE5808 requires careful attention to the PCB layout to minimize the effects of board
parasitics and optimize component placement. A multilayer PCB usually ensures best results and allows
convenient component placement. In order to maintain proper LVDS timing, all LVDS traces should follow a
controlled impedance design. In addition, all LVDS trace lengths should be equal and symmetrical; TI
recommends to keep trace length variations less than 150 mil (0.150 inch or 3.81 mm).
To avoid noise coupling through supply pins, TI recommends to keep sensitive input pins, such as INM,
INP, ACT pins aways from the AVDD 3.3 V and AVDD_5V planes. For example, either the traces or vias
connected to these pins should NOT be routed across the AVDD 3.3 V and AVDD_5V planes, that is to
avoid power planes under INM, INP, and ACT pins.
In addition, appropriate delay matching should be considered for the CW clock path, especially in systems with
high channel count. For example, if clock delay is half of the 16x clock period, a phase error of 22.5°C could
exist. Thus the timing delay difference among channels contributes to the beamformer accuracy.
Additional details on BGA PCB layout techniques can be found in the Texas Instruments Application Report
MicroStar BGA Packaging Reference Guide (SSYZ015), which can be downloaded from www.ti.com.
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REVISION HISTORY
Changes from Revision C (April 2012) to Revision D
Page
•
Corrected column titles in Absolute Maximum Ratings table ............................................................................................... 3
•
Changed pin description of CLKM_16X from "In the 1X CW clock mode, this pin becomes the quadrature-phase 1X
CLKM for the CW mixer" to "... in-phase 1X CLKM for the CW mixer" ................................................................................ 4
•
Changed pin description of CLKP_16X from "In the 1X CW clock mode, this pin becomes the quadrature-phase 1X
CLKP for the CW mixer" to "... in-phase 1X CLKP for the CW mixer" ................................................................................. 4
•
Changed pin description of CLKM_1X from "In the 1X CW clock mode, this pin becomes the in-phase 1X CLKP for
the CW mixer" to "... quadrature-phase 1X CLKP for the CW mixer" .................................................................................. 4
•
Changed pin description of CLKP_1X from "In the 1X CW clock mode, this pin becomes the in-phase 1X CLKP for
the CW mixer" to "... quadrature-phase 1X CLKP for the CW mixer" .................................................................................. 4
•
Changed CLK duty cycle from "35%~65%" to "33% to 66%" ............................................................................................... 8
•
Changed Input Clock to Bit Clock and deleted "(for output data and frame clock)" ........................................................... 22
•
Changed Input Clock to Bit Clock and deleted "(for output data and frame clock)" ........................................................... 22
•
Changed SPI pull down resistors from "100 kΩ" to "20 kΩ". .............................................................................................. 24
•
Corrected a typo in Reg0x2[15:13], i.e. changed 0x2[15:3] to 0x2[15:13] ......................................................................... 27
•
Combined Reg 0x33[6:5] and 0x33[7] and added notes to PGA_CLAMP_LEVEL: "The maximum PGA output level
can exceed 2Vpp with the clamp circuit enabled. In the low power and medium power modes, PGA_CLAMP is
disabled for saving power if 51[7] = 0". ............................................................................................................................... 32
•
Added and reorganized Description of LNA Input Impedances Configuration ................................................................... 34
•
Added Table 10 .................................................................................................................................................................. 37
•
Changed "10 Ω" to "approximately 10- to 15-Ω " in Figure 69 ........................................................................................... 44
•
Updated Figure 72 .............................................................................................................................................................. 46
•
Updated Figure 74 .............................................................................................................................................................. 48
•
Added back-to-back diodes in Figure 82 ............................................................................................................................ 53
•
Added text "TI recommends that VCNTLM/P noise is below 25 nV/rtHz at 1 kHz and 5 nV/rtHz at 50 kHz. In high
channel count premium systems, the VCNTLM/P noise requirement is higher." ............................................................... 57
•
Added a note "The local oscillator inputs of the passive mixer are cos(ωt) for I-CH and sin(ωt) for Q-CH " .................... 60
•
Added LMK048X into the CW clock application information section. ................................................................................. 62
•
Updated Figure 89 to include LMK devices. ....................................................................................................................... 63
•
Updated Figure 90 to include LMK devices ........................................................................................................................ 64
•
Added LMK048X into the ADC clock application information section. ............................................................................... 64
•
Deleted "VREF_IN" from "The AFE5808 has a number of reference supplies needed to be bypassed." ......................... 67
•
Added "To avoid noise coupling through supply pins, TI recommends to keep sensitive input pins, such as INM,
INP, ACT pins aways from the AVDD 3.3 V and AVDD_5V planes. For example, either the traces or vias connected
to these pins should NOT be routed across the AVDD 3.3 V and AVDD_5V planes, that is to avoid power planes
under INM, INP, and ACT pins." in BOARD LAYOUT ........................................................................................................ 68
Changes from Revision B (August 2011) to Revision C
Page
•
Changed the data sheet title From: 8-Channel Ultrasound Analog Front End for Ultrasound... To: 8-Channel
Ultrasound Analog Front End ............................................................................................................................................... 1
•
Added the AFE5808A Note to the Description text .............................................................................................................. 2
•
Added pin compatible devices AFE5803 and AFE5808A to the Description text ................................................................ 2
•
Chnaged the Noise figure TYP value for Rs= 100 Ω From: 5.3/3.1/3.6 To: 5.3/3.1/2.3 ....................................................... 6
•
Added footnote for CW Operation Range ............................................................................................................................. 8
•
Added "After January, 2014, that is date code after 41XXXXX, the CW Clock frequency ( 16X mode) can be
supported up to 145 MHz and approximately 33 to 50% duty cycle based on additional test screening." .......................... 8
•
Changed the tdelay Test Condiitons From: Input clock rising edge (zero cross) to frame clock rising edge (zero cross)
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AFE5808
SLOS688D – SEPTEMBER 2010 – REVISED JANUARY 2014
www.ti.com
minus half the input clock period (T). To: Input clock rising edge (zero cross) to frame clock rising edge (zero cross)
minus 3/7 of the input clock period (T). .............................................................................................................................. 22
•
Added text to the Register Map section: "Register settings are maintained when the AFE5808 is in either partial
power down mode or complete power down mode." .......................................................................................................... 27
•
Changed Table 6 ................................................................................................................................................................ 30
•
Changed the CHANNEL_OFFSET_SUBSTRACTION_ENABLE: Address: 3[8] text ........................................................ 30
•
Added Note: 54[9] is only effective in CW mode. ............................................................................................................... 33
•
Added Note: 59[8] is only effective in TGC test mode. ....................................................................................................... 34
•
Changed Figure 64 ............................................................................................................................................................. 40
•
Changed Figure 69 ............................................................................................................................................................. 44
•
Added text to the LNA Input Coupling and Decoupling section .......................................................................................... 53
•
Added text to the CW Clock Selection section ................................................................................................................... 62
•
Changed the TEST MODES section .................................................................................................................................. 66
Changes from Revision A (December 2010) to Revision B
Page
•
Added text to the pin Description for B9~ B2 (ACT1...ACT8) .............................................................................................. 4
•
Added text to the L4 and M4 Pin Descriptions ..................................................................................................................... 5
•
Changed the ELECTRICAL CHARACTERISTICS condition statement ............................................................................... 6
•
Changed the Common-mode voltage values From: MIN 0.75 V / MAX 1 V To: 0.75 V TYP .............................................. 6
•
Added Note 1 ........................................................................................................................................................................ 6
•
Changed the ELECTRICAL CHARACTERISTICS condition statement ............................................................................... 7
•
Changed the Gain Matching Test Conditions From: 0.1 V < VCNTL < 1.3 V (Dev-to-Dev) To: 0.1 V < VCNTL < 1.1
V (Dev-to-Dev). ..................................................................................................................................................................... 7
•
Added to the Gain Matching Test Conditions: 0.1 V < VCNTL < 1.1 V (Dev-to-Dev), Temp = 0°C and 85°C .................... 7
•
Changed the Gain Matching Test Conditions From: 1.3 V < VCNTL < 1.5 V (Dev-to-Dev) To: 1.1 V < VCNTL< 1.5 V
(Dev-to-Dev). ........................................................................................................................................................................ 7
•
Changed the Output Offset values From: MIN = –60 LSB / MAX = 60 LSB To: MIN = –75 LSB / MAX = 75 LSB ............. 7
•
Changed the ELECTRICAL CHARACTERISTICS condition statement ............................................................................... 8
•
Changed en (RTO) and en (RTI) Test Conditions From: LNA = 24 dB To: 18 dB ............................................................... 8
•
Changed the ELECTRICAL CHARACTERISTICS condition statement ............................................................................... 9
•
Changed the AVDD (3.3V) Current - TGC low noise mode, no signal Max value From: 225 mA To: 235 mA ................... 9
•
Changed the ELECTRICAL CHARACTERISTICS condition statement ............................................................................. 10
•
Changed the TYPICAL CHARACTERISTICS condition statement .................................................................................... 12
•
Changed all –40°C to 85°C To 0°C to 85°C ....................................................................................................................... 22
•
Changed the ADC latency test Conditions and Typ value. ................................................................................................ 22
•
Changed Figure 58 ............................................................................................................................................................. 23
•
Added t8 to the SPI Timing Characteristics table ................................................................................................................ 25
•
Updated the SDOUT description in the Register Readout section ..................................................................................... 25
•
Changed Figure 60 ............................................................................................................................................................. 25
•
Changed the Text Note following Figure 61 ....................................................................................................................... 26
•
Changed the LOW_LATENCY Desctiption ......................................................................................................................... 27
•
Changed the VOLTAGE-CONTROLLED-ATTENUATOR. Deleted the last sentence of paragraph two ........................... 56
•
Changed Figure 85, Removed the Single-Ended Input at VCNTLM image ....................................................................... 56
•
Changed the ADC Reference Circuit section. Added text to the end of paragraph two .................................................... 64
•
Changed the Power Management Priority section. Added text to the end of paragraph ................................................... 65
•
Changed the Priority column in Table 17 ........................................................................................................................... 65
70
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Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: AFE5808
AFE5808
www.ti.com
SLOS688D – SEPTEMBER 2010 – REVISED JANUARY 2014
Changes from Original (September 2010) to Revision A
•
Page
Changed From: Product Preview To: Production Data ........................................................................................................ 1
Submit Documentation Feedback
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: AFE5808
71
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
AFE5808ZCF
ACTIVE
NFBGA
ZCF
135
160
RoHS & Green
SNAGCU
Level-3-260C-168 HR
0 to 70
AFE5808
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
