AFE5818ZBV

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 AFE5818 16-Channel, Ultrasound, Analog Front-End with 140-mW/Channel Power, 0.75-nV/√Hz Noise, 14-Bit, 65-MSPS or 12-Bit, 80-MSPS ADC, and Passive CW Mixer 1 1 Features • • • • • • • • • • • • 16-Channel, Complete Analog Front-End: – LNA, VCAT, PGA, LPF, ADC, and CW Mixer LNA with Programmable Gain: – Gain: 24 dB, 18 dB, and 12 dB – Linear Input Range: 0.25 VPP, 0.5 VPP, and 1 VPP – Input-Referred Noise: 0.63 nV/√Hz, 0.7 nV/√Hz, and 0.9 nV/√Hz – Programmable Active Termination Voltage-Controlled Attenuator (VCAT): 40 dB Programmable Gain Amplifier (PGA): 24 dB and 30 dB Total Signal Chain Gain: 54 dB (max) 3rd-Order, Linear-Phase LPF: – 10 MHz, 15 MHz, 20 MHz, 30 MHz, 35 MHz, and 50 MHz Analog-to-Digital Converter (ADC): – 14-Bit ADC: 75-dBFS SNR at 65 MSPS – 12-Bit ADC: 72-dBFS SNR at 80 MSPS LVDS Interface Maximum Speed of 1 Gbps Noise and Power Optimizations (Full-Channel): – 140 mW/Ch at 0.75 nV/√Hz, 65 MSPS – 91.5 mW/Ch at 1.1 nV/√Hz, 40 MSPS – 80 mW/Ch at CW Mode Excellent Device-to-Device Gain Matching: – ±0.5 dB (typical) and ±1.1 dB (max) Low Harmonic Distortion Fast and Consistent Overload Recovery • • Passive Mixer for CWD: – Low Close-In Phase Noise: –156 dBc/Hz at 1 kHz Off 2.5-MHz Carrier – Phase Resolution: λ / 16 – Supports 16X, 8X, 4X, and 1X CW Clocks – 12-dB Suppression on 3rd and 5th Harmonics – CWD High-Pass Filter Rejects Undesired LowFrequency Signals < 1 kHz Small Package: 15-mm × 15-mm NFBGA-289 2 Applications • • • • Medical Ultrasound Imaging Nondestructive Evaluation Equipment Sonar Imaging Equipment Multichannel, High-Speed Data Acquisition 3 Description The AFE5818 is a highly-integrated, analog front-end (AFE) solution specifically designed for ultrasound systems where high performance and small size are required. The device integrates a complete time-gaincontrol (TGC) imaging path and a continuous wave Doppler (CWD) path. The device also allows various power and noise combinations to be selected to optimize system performance. Therefore, the AFE5818 is a suitable ultrasound AFE solution for high-end and portable systems Device Information(1) PART NUMBER AFE5818 PACKAGE BODY SIZE (NOM) NFBGA (289) 15.00 mm × 15.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Block Diagram Device (1 of 16 Channels) SPI IN SPI OUT SPI Logic VCAT 0 dB to -40 dB LNA PGA 24, 30 dB LNA IN 3rd-Order LPF with 10, 15, 20, 30, 35, and 50 MHz 12-, 14-Bit ADC LVDS 16X CLK 16 Phases Generator CW Mixer Summing Amplifier Reference Reference 1X CLK 16 x 8 Crosspoint SW 1X CLK CW I/Q VOUT Differential TGC VCNTL 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. 1 Applications ........................................................... 1 Description ............................................................. 1 Revision History..................................................... 2 Description (continued)......................................... 4 Device Comparison Table..................................... 5 Pin Configuration and Functions ......................... 6 Specifications....................................................... 11 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 9 Absolute Maximum Ratings .................................... ESD Ratings............................................................ Recommended Operating Conditions..................... Thermal Information ................................................ Electrical Characteristics......................................... Digital Characteristics ............................................. Output Interface Timing .......................................... Serial Interface Timing Characteristics .................. Typical Characteristics ............................................ 11 11 12 12 13 19 20 21 22 Detailed Description ............................................ 33 9.1 9.2 9.3 9.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 33 34 35 72 9.5 Programming........................................................... 76 10 Application and Implementation........................ 78 10.1 10.2 10.3 10.4 Application Information.......................................... Typical Application ............................................... Do's and Don'ts ..................................................... Initialization Set Up ............................................... 78 78 82 82 11 Power Supply Recommendations ..................... 83 11.1 Power Sequencing and Initialization ..................... 83 12 Layout................................................................... 84 12.1 Layout Guidelines ................................................. 84 12.2 Layout Example .................................................... 85 13 Register Maps...................................................... 91 13.1 Serial Register Map .............................................. 91 14 Device and Documentation Support ............... 149 14.1 14.2 14.3 14.4 14.5 Documentation Support ...................................... Trademarks ......................................................... Electrostatic Discharge Caution .......................... Export Control Notice.......................................... Glossary .............................................................. 149 149 149 149 149 15 Mechanical, Packaging, and Orderable Information ......................................................... 150 15.1 Tray Information .................................................. 151 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (July 2015) to Revision B Page • Changed literature number to release full document to web.................................................................................................. 1 • Deleted AFE58JD18 from document ..................................................................................................................................... 1 • Added Device Comparison Table........................................................................................................................................... 5 • Changed the common-mode voltage value from 1.5 V to 2.5 V in the descriptions of the CLKM_1X , CLKP_1X, CLKM_16X , and CLKP_16X, rows in the Pin Functions table .............................................................................................. 7 • Changed the pulldown resistor value from 100 kΩ to 20-kΩ in the description of the TX_TRIG pin in the Pin Functions table ..................................................................................................................................................................... 10 • Changed Absolute Maximum Ratings table: deleted Voltage at digital inputs row and added Voltage at all digital inputs except CW clocks and Voltage at CW clock input pins rows .................................................................................... 11 • Changed the typical specifications of last four rows of TGC Full-Signal Channel, Channel-to-channel noise correlation factor parameter in the Electrical Characteristics table ..................................................................................... 14 • Changed test conditions of second row in Power Dissipation, CW mode parameter in the Electrical Characteristics table ..................................................................................................................................................................................... 18 • Changed SDATA to SDIN in title of CMOS Digital Inputs section in the Digital Characteristics table ................................ 19 • Changed typical specification from 25 to 50 in zo parameter of Digital Characteristics table .............................................. 19 • Changed typical specifications of ADC Timing, Cd parameter in Output Interface Timing table.......................................... 20 • Changed Figure 1................................................................................................................................................................. 21 • Changed Figure 56 and Figure 57 ....................................................................................................................................... 31 • Changed input to Serial Interface block from SDATA to SDIN in Functional Block Diagram .............................................. 34 • Changed Figure 84: changed values of t_setup and t_hold ................................................................................................ 55 • Deleted Setup and Hold Time Constraints for a Hardware RESET figure and associated description because this data was determined to be misleading ................................................................................................................................ 55 • Changed input to Serial Interface block from SDATA to SDIN in Figure 98 ........................................................................ 68 2 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 Revision History (continued) • Changed input to Serial Interface block from SDATA to SDIN in Figure 99 ........................................................................ 69 • Changed Test Patterns section to improve clarity................................................................................................................ 72 • Changed AFE8 to AFE4 in Figure 103................................................................................................................................. 78 • Added footnote to Figure 104 ............................................................................................................................................... 79 • Changed Figure 108............................................................................................................................................................. 85 • Changed SDATA to SDIN in list of SPI control signals in first paragraph of Serial Register Map section .......................... 91 • Changed bit type from R/W to W in Register 0 ................................................................................................................... 92 • Changed CUSTOM_PATTERN[13:0] to CUSTOM_PATTERN[15:0] in register address 5 of Table 14 ............................. 93 • Changed Register 5 in the ADC Register Map section ........................................................................................................ 99 Changes from Original (February 2015) to Revision A Page • Added AFE58JD18 to document ............................................................................................................................................ 1 • Changed Voltage-Controlled Attenuator (VCAT), LVDS Interface Maximum Speed, and Noise and Power Optimizations (Full-Channel) Features bullets ....................................................................................................................... 1 • Deleted second to last Passive Mixer sub-bullet in Features section ................................................................................... 1 • Added AFE58JD18-specific Features bullets ......................................................................................................................... 1 • Changed Output Interface and Digital I/Q Demodulator column titles in Device Information table........................................ 1 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 3 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 5 Description (continued) The AFE5818 has a total of 16 channels, with each channel consisting of a voltage-controlled amplifier (VCA), a simultaneous sampling 14-bit and 12-bit analog-to-digital converter (ADC), and a continuous wave (CW) mixer. The VCA includes a low-noise amplifier (LNA), a voltage-controlled attenuator (VCAT), a programmable gain amplifier (PGA), and a low-pass filter (LPF). LNA gain is programmable and supports 250-mVPP to 1-VPP input signals and programmable active termination. The ultra-low noise VCAT provides an attenuation control range of 40 dB and improves overall low-gain SNR, which benefits harmonic and near-field imaging. The PGA provides gain options of 24 dB and 30 dB. In front of the ADC, an LPF can be configured at 10 MHz, 15 MHz, 20 MHz, 30 MHz, 35 MHz, or 50 MHz to support ultrasound applications with different frequencies. The AFE5818 also integrates a low-power passive mixer and a low-noise summing amplifier to create an on-chip CWD beamformer. 16 selectable phase delays can be applied to each analog input signal. Furthermore, a unique third- and fifth-order harmonic suppression filter is implemented to enhance CW sensitivity The high-performance, 14-bit ADC achieves 75-dBFS SNR. This ADC ensures excellent SNR at low-chain gain. The device can operate at maximum speeds of 65 MSPS and 80 MSPS, providing a 14-bit and a 12-bit output, respectively. The ADC low-voltage differential signaling (LVDS) outputs enable a flexible system integration that is desirable for miniaturized systems. The AFE5818 also allows various power and noise combinations to be selected to optimize system performance. Therefore, the AFE5818 is a suitable ultrasound AFE solution for both high-end and portable systems. The AFE5818 is available in a 15-mm × 15-mm NFBGA-289 package (ZBV package, S-PBGA-N289) and are specified for operation from –40°C to 85°C. The devices are also pin-to-pin compatible with the AFE5816 device family. 4 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 6 Device Comparison Table DEVICE PACKAGE BODY SIZE (NOM) AFE5816 16-channel, ultrasound, analog front-end (AFE) with 90-mW/channel, 1-nV/√Hz noise, 14-bit, 65-MSPS or 12-bit, 80-MSPS ADC and passive CW mixer NFBGA (289) 15.00 mm × 15.00 mm AFE5812 Fully integrated, 8-channel ultrasound AFE with passive CW mixer, and digital I/Q demodulator, 0.75 nV/√Hz, 14 and 12 bits, 65 MSPS, 180 mW/ch NFBGA (135) 15.00 mm × 9.00 mm AFE5809 8-channel ultrasound AFE with passive CW mixer, and digital I/Q demodulator, 0.75 nV/√Hz, 14 and 12 bits, 65 MSPS, 158 mW/ch NFBGA (135) 15.00 mm × 9.00 mm AFE5808A 8-channel ultrasound AFE with passive CW mixer, 0.75 nV/√Hz, 14 and 12 bits, 65 MSPS, 158 mW/ch NFBGA (135) 15.00 mm × 9.00 mm AFE5807 8-channel ultrasound AFE with passive CW mixer, 1.05 nV/√Hz, 12 bits, 80 MSPS, 117 mW/ch NFBGA (135) 15.00 mm × 9.00 mm AFE5803 8-channel ultrasound AFE, 0.75 nV/√Hz, 14 and 12 bits, 65 MSPS, 158 mW/ch NFBGA (135) 15.00 mm × 9.00 mm AFE5805 8-channel ultrasound AFE, 0.85 nV/√Hz, 12 bits, 50 MSPS, 122 mW/ch NFBGA (135) 15.00 mm × 9.00 mm AFE5804 8-channel ultrasound AFE, 1.23 nV/√Hz, 12 bits, 50 MSPS, 101 mW/ch NFBGA (135) 15.00 mm × 9.00 mm AFE5801 8-channel variable-gain amplifier (VGA) with octal high-speed ADC, 5.5 nV/√Hz, 12 bits, 65 MSPS, 65 mW/ch VQFN (64) 9.00 mm × 9.00 mm AFE5851 16-channel VGA with high-speed ADC, 5.5 nV/√Hz, 12 bits, 32.5 MSPS, 39 mW/ch VQFN (64) 9.00 mm × 9.00 mm VCA5807 8-channel voltage-controlled amplifier for ultrasound with passive CW mixer, 0.75 nV/√Hz, 99 mW/ch HTQFP (80) 14.00 mm × 14.00 mm VCA8500 8-channel, ultralow-power VGA with low-noise pre-amp, 0.8 nV/√Hz, 65 mW/ch VQFN (64) 9.00 mm × 9.00 mm ADS5294 Octal-channel, 14-bit, 80-MSPS ADC, 75-dBFS SNR, 77 mW/ch HTQFP (80) 14.00 mm × 14.00 mm ADS5292 Octal-channel, 12-bit, 80-MSPS ADC, 70-dBFS SNR, 66 mW/ch HTQFP (80) 14.00 mm × 14.00 mm ADS5295 Octal-channel, 12-bit, 100-MSPS ADC, 70.6-dBFS SNR, 80 mW/ch HTQFP (80) 14.00 mm × 14.00 mm VQFN (64) 9.00 mm × 9.00 mm ADS5296A DESCRIPTION 10-bit, 200-MSPS, 4-channel, 61-dBFS SNR, 150-mW/ch and 12-bit, 80-MSPS, 8-channel, 70-dBFS SNR, 65-mW/ch ADC Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 5 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 7 Pin Configuration and Functions ZBV Package NFBGA-289 Top View 1 2 3 4 A INP16 INP15 INP14 INP13 INP12 INP11 INP10 B ACT16 ACT15 ACT14 ACT13 ACT12 ACT11 C INM16 INM15 INM14 INM13 INM12 INM11 D CW_DC_ INM_IP CW_DC_ INP_IP CW_IP_ AMPINM CW_IP_ AMPINP CM_BYP1 AVDD_5V AVDD_5V AVDD_5V AVDD_5V AVDD_5V AVDD_5V AVDD_5V E CW_DC _OUTP_ IP CW_DC _OUTM_ IP CW_IP_ OUTP CW_IP_ OUTM CM_BYP2 AVDD _3P3 AVDD _3P3 AVSS AVSS AVSS AVDD _3P3 F CW_DC _OUTP_ QP CW_DC _OUTM_ QP CW_QP_ OUTP CW_QP_ OUTM VHIGH1 AVDD _3P3 AVDD _3P3 AVSS AVSS AVSS G CW_DC_ INM_QP CW_DC_ INP_QP CW_QP_ AMPINM CW_QP_ AMPINP VHIGH2 AVDD _3P3 AVDD _3P3 AVSS AVSS H AVSS AVSS AVSS VCNTLP NC AVDD _3P3 AVDD _3P3 AVSS J ADC_ CLKP ADC_ CLKM AVSS VCNTLM NC AVDD _3P3 AVDD _3P3 K AVSS AVSS AVSS NC NC AVDD _3P3 L NC NC DVDD_ 1P2 NC AVDD _1P8 M NC NC DVSS DVDD_ 1P2 N NC DVDD_ 1P2 DVDD_ 1P2 P NC DVDD_ 1P2 DVDD_ 1P2 R NC T NC DOUTM 16 DOUTM 15 DOUTM 14 U NC NC NC NC 6 9 10 11 12 13 14 15 16 17 INP9 NC INP8 INP7 INP6 INP5 INP4 INP3 INP2 INP1 ACT10 ACT9 NC ACT8 ACT7 ACT6 ACT5 ACT4 ACT3 ACT2 ACT1 INM10 INM9 NC INM8 INM7 INM6 INM5 INM4 INM3 INM2 INM1 NC NC AVSS AVSS AVSS AVDD _3P3 AVDD _3P3 AVDD _3P3 AVSS CLKP_ 16X CLKM_ 16X AVDD _3P3 AVDD _3P3 AVDD _3P3 AVDD _3P3 AVSS AVSS AVSS AVSS AVDD _3P3 AVDD _3P3 NC NC AVSS AVSS AVSS AVDD _3P3 AVDD _3P3 NC NC NC SDOUT NC AVSS AVSS AVSS AVDD _3P3 AVDD _3P3 NC NC NC NC SCLK AVDD _3P3 AVSS AVSS AVSS AVDD _3P3 AVDD _3P3 NC NC NC NC SEN AVDD _1P8 AVDD _1P8 AVSS AVSS AVSS AVDD _1P8 AVDD _1P8 AVDD _1P8 NC NC SDIN RESET DVDD_ 1P2 DVDD_ 1P2 DVSS DVSS DVSS DVSS DVSS DVDD_ 1P2 DVDD_ 1P2 DVDD_ 1P2 TX_TRIG PDN_ GBL PDN_ FAST DVDD_ 1P2 DVDD_ 1P2 DVDD_ 1P2 DVSS DVSS DVSS DVSS DVSS DVDD_ 1P2 DVDD_ 1P2 DVDD_ 1P2 DVDD_ 1P2 DVDD_ 1P2 NC DVDD_ 1P8 DVDD_ 1P8 DVDD_ 1P8 DVDD_ 1P8 DVSS DVSS DVSS DVDD_ 1P8 DVDD_ 1P8 DVDD_ 1P8 DVDD_ 1P8 DVDD_ 1P2 DVDD_ 1P2 NC NC DOUTM 11 DOUTP11 FCLKM NC FCLKP DOUTM6 DOUTP6 NC DOUTP3 DOUTP2 DOUTP1 NC DOUTP9 DCLKP DOUTP8 DOUTP7 DOUTP5 DOUTP4 DOUTM3 DOUTM2 DOUTM1 NC DOUTM9 DCLKM DOUTM8 DOUTM7 DOUTM5 DOUTM4 NC NC NC NC DOUTP16 DOUTP15 DOUTP14 5 6 7 DOUTP13 DOUTP12 DOUTP10 DOUTM 13 DOUTM 12 DOUTM 10 8 Submit Documentation Feedback CLKM_1X CLKP_1X Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 Pin Functions PIN NAME NO. ACT16 B1 ACT15 B2 ACT14 B3 ACT13 B4 ACT12 B5 ACT11 B6 ACT10 B7 ACT9 B8 ACT8 B10 ACT7 B11 ACT6 B12 ACT5 B13 ACT4 B14 ACT3 B15 ACT2 B16 ACT1 B17 I/O DESCRIPTION I Active-termination input pins for channels 1 to 16. 1-μF capacitors are recommended. Bias voltage = 1.5 V. ADC_CLKM (1) J2 I Differential clock input pin, negative. A single-ended clock is also supported. Connect ADC_CLKM to dc ground when using a single-ended clock. (Common-mode voltage = 0.7 V.) ADC_CLKP J1 I Differential clock input pin, positive. A single-ended clock is also supported. Connect the ADC clock to the ADC_CLKP pin in a single-ended clock. (Common-mode voltage = 0.7 V.) AVDD_1P8 L5-L7, L11-L13 I 1.8-V analog supply pins for the ADC AVDD_3P3 E6, E7, E11-E14, F6, F7, F11-F14, G6, G7, G11, G12, H6, H7, H11, H12, J6, J7, J11, J12, K6, K7, K11, K12 I 3.3-V analog supply pins for the low-noise amplifier (LNA), voltage-controlled attenuator (VCAT), programmable gain amplifier (PGA), low-pass filter (LPF), and continuous wave (CW) blocks D6-D12 I 5-V analog supply pins for the LNA, VCAT, PGA, LPF, and CW blocks D15-D17, E8-E10, E15, F8-F10, F15F17, G8-G10, G15, H1-H3, H8-H10, J3, J8-J10, K1-K3, K8-K10, L8-L10 I Analog ground pins I Differential clock inputs for the 1X CW clock, negative. In differential mode, the device forces a 2.5-V common-mode voltage on this pin. A single-ended clock is also supported. In single-ended clock mode, the CLKM_1X pin is internally pulled to ground. In 1X clock mode, this pin is the quadrate-phase 1X CLKM for the CW mixer. When CW mode is not used, this pin can be left floated. I Differential clock inputs for the 1X CW clock, positive. In differential mode, the device forces a 2.5-V common-mode voltage on this pin. A single-ended clock is also supported. Connect the 1X CW clock to the CLKP_1X pin in a single-ended clock. In 1X clock mode, this pin is the quadrate-phase 1X CLKP for the CW mixer. When CW mode is not used, this pin can be left floated. I Differential clock inputs for the 32X, 16X, 8X, and 4X CW clocks, negative. In differential mode, the device forces a 2.5-V common-mode voltage on this pin. A single-ended clock is also supported. In single-ended clock mode, the CLKM_16X pin is internally pulled to ground. In 1X CW clock mode, this pin becomes the in-phase 1X CLKM for the CW mixer. When CW mode is not used, this pin can be floated. I Differential clock inputs for the 32X, 16X, 8X, and 4X CW clocks, positive. A single-ended clock is also supported. Connect the 16X CW clock to the CLKP_16X pin in a single-ended clock. In 1X CW clock mode, this pin becomes the in-phase 1X CLKP for the CW mixer. In differential mode, the device forces a 2.5-V common-mode voltage on this pin. When CW mode is not used, this pin can be floated. O Bypass to ground with a ≥ 1-μF capacitor. To suppress ultra low-frequency noise, a 10-μF capacitor can be used. Bias voltage = 1.5 V. AVDD_5V AVSS CLKM_1X CLKP_1X CLKM_16X G16 G17 E17 CLKP_16X E16 CM_BYP1 D5 CM_BYP2 E5 (1) M = negative, P = positive. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 7 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com Pin Functions (continued) PIN NAME NO. CW_DC_INM_IP D1 CW_DC_INP_IP D2 CW_DC_INM_QP G1 CW_DC_INP_QP G2 CW_DC_OUTM_IP E2 CW_DC_OUTP_IP E1 CW_DC_OUTM_QP F2 CW_DC_OUTP_QP F1 CW_IP_AMPINM D3 CW_IP_AMPINP D4 CW_IP_OUTM E4 CW_IP_OUTP E3 CW_QP_AMPINM G3 CW_QP_AMPINP G4 CW_QP_OUTM F4 CW_QP_OUTP F3 DCLKM U9 DCLKP T9 DOUTM1 T16 DOUTP1 R16 DOUTM2 T15 DOUTP2 R15 DOUTM3 T14 DOUTP3 R14 DOUTM4 U13 DOUTP4 T13 DOUTM5 U12 DOUTP5 T12 DOUTM6 R11 DOUTP6 R12 DOUTM7 U11 DOUTP7 T11 DOUTM8 U10 DOUTP8 T10 DOUTM9 U8 DOUTP9 T8 DOUTM10 U7 DOUTP10 T7 DOUTM11 R6 DOUTP11 R7 DOUTM12 U6 DOUTP12 T6 8 I/O DESCRIPTION I In-phase CW high-pass filter differential inputs. An external capacitor must be connected between CW_DC_INM_IP, CW_DC_OUTP_IP and CW_DC_INP_IP, CW_DC_OUTM_IP. When CW high-pass filter (HPF) mode is not used, these pins can be floated. Bias voltage = 1.5 V. I Quadrature-phase CW high-pass filter differential inputs. An external capacitor must be connected between CW_DC_INM_QP, CW_DC_OUTP_QP and CW_DC_INP_QP, CW_DC_OUTM_QP. When CW HPF mode is not used, these pins can be floated. Bias voltage = 1.5 V. O In-phase CW high-pass filter differential outputs. An external capacitor must be connected between CW_DC_INM_IP, CW_DC_OUTP_IP and CW_DC_INP_IP, CW_DC_OUTM_IP. When CW HPF mode is not used, these pins can be floated. Bias voltage = 1.5 V. O Quadrature-phase CW high-pass filter differential outputs. An external capacitor must be connected between CW_DC_INM_QP, CW_DC_OUTP_QP and CW_DC_INP_QP, CW_DC_OUTM_QP. When CW HPF mode is not used, these pins can be floated. Bias voltage = 1.5 V. I In-phase CW summing amplifier differential inputs. An external capacitor must be connected between CW_IP_AMPINM, CW_IP_OUTP and CW_IP_AMPINP, CW_IP_OUTM. When CW HPF mode is not used, these pins can be floated. Bias voltage = 1.5 V. O In-phase CW summing amplifier differential outputs. An external capacitor must be connected between CW_IP_AMPINM, CW_IP_OUTP and CW_IP_AMPINP, CW_IP_OUTM. When CW HPF mode is not used, these pins can be floated. Bias voltage = 1.5 V. I Quadrature-phase CW summing amplifier differential inputs. An external capacitor must be connected between CW_QP_AMPINM, CW_QP_OUTP and CW_QP_AMPINP, CW_QP_OUTM. When CW mode is not used, these pins can be floated. Bias voltage = 1.5 V. O Quadrature-phase CW summing amplifier differential outputs. An external capacitor must be connected between CW_QP_AMPINM, CW_QP_OUTP and CW_QP_AMPINP, CW_QP_OUTM. When CW mode is not used, these pins can be floated. Bias voltage = 1.5 V. O Low-voltage differential signaling (LVDS) serialized data clock outputs (receiver bit alignment) O LVDS serialized differential data outputs for channel 1 O LVDS serialized differential data outputs for channel 2 O LVDS serialized differential data outputs for channel 3 O LVDS serialized differential data outputs for channel 4 O LVDS serialized differential data outputs for channel 5 O LVDS serialized differential data outputs for channel 6 O LVDS serialized differential data outputs for channel 7 O LVDS serialized differential data outputs for channel 8 O LVDS serialized differential data outputs for channel 9 O LVDS serialized differential data outputs for channel 10 O LVDS serialized differential data outputs for channel 11 O LVDS serialized differential data outputs for channel 12 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 Pin Functions (continued) PIN NAME NO. DOUTM13 U5 DOUTP13 T5 DOUTM14 T4 DOUTP14 R4 DOUTM15 T3 DOUTP15 R3 I/O DESCRIPTION O LVDS serialized differential data outputs for channel 13 O LVDS serialized differential data outputs for channel 14 O LVDS serialized differential data outputs for channel 15 O LVDS serialized differential data outputs for channel 16 DOUTM16 T2 DOUTP16 R2 DVDD_1P2 L3, M4-M6, M12-M14, N2-N6, N12N16, P2, P3, P15, P16 I 1.2-V digital supply pins for the ADC digital block DVDD_1P8 P4-P7, P11-P14 I 1.8-V digital supply pins for the ADC digital, digital I/Os, phase-locked loop (PLL), and LVDS interface blocks M3, M7-M11, N7-N11, P8-P10 I ADC digital ground O LVDS serialized frame clock outputs (receiver word alignment) DVSS FCLKM R8 FCLKP R10 INM1 C17 I Complimentary analog inputs for channel 1. Place a ≥ 15-nF capacitor to ground. The HPF response of the LNA depends on the capacitors. Bias voltage = 2.2 V. INP1 A17 I Analog inputs for channel 1. AC-couple to inputs with 0.1-μF capacitors. Bias voltage = 2.2 V. INM2 C16 I Complimentary analog inputs for channel 2. Place a ≥ 15-nF capacitor to ground. The HPF response of the LNA depends on the capacitors. Bias voltage = 2.2 V. INP2 A16 I Analog inputs for channel 2. AC-couple to inputs with 0.1-μF capacitors. Bias voltage = 2.2 V. INM3 C15 I Complimentary analog inputs for channel 3. Place a ≥ 15-nF capacitor to ground. The HPF response of the LNA depends on the capacitors. Bias voltage = 2.2 V. INP3 A15 I Analog inputs for channel 3. AC-couple to inputs with 0.1-μF capacitors. Bias voltage = 2.2 V. INM4 C14 I Complimentary analog inputs for channel 4. Place a ≥ 15-nF capacitor to ground. The HPF response of the LNA depends on the capacitors. Bias voltage = 2.2 V. INP4 A14 I Analog inputs for channel 4. AC-couple to inputs with 0.1-μF capacitors. Bias voltage = 2.2 V. INM5 C13 I Complimentary analog inputs for channel 5. Place a ≥ 15-nF capacitor to ground. The HPF response of the LNA depends on the capacitors. Bias voltage = 2.2 V. INP5 A13 I Analog inputs for channel 5. AC-couple to inputs with 0.1-μF capacitors. Bias voltage = 2.2 V. INM6 C12 I Complimentary analog inputs for channel 6. Place a ≥ 15-nF capacitor to ground. The HPF response of the LNA depends on the capacitors. Bias voltage = 2.2 V. INP6 A12 I Analog inputs for channel 6. AC-couple to inputs with 0.1-μF capacitors. Bias voltage = 2.2 V. INM7 C11 I Complimentary analog inputs for channel 7. Place a ≥ 15-nF capacitor to ground. The HPF response of the LNA depends on the capacitors. Bias voltage = 2.2 V. INP7 A11 I Analog inputs for channel 7. AC-couple to inputs with 0.1-μF capacitors. Bias voltage = 2.2 V. INM8 C10 I Complimentary analog inputs for channel 8. Place a ≥ 15-nF capacitor to ground. The HPF response of the LNA depends on the capacitors. Bias voltage = 2.2 V. INP8 A10 I Analog inputs for channel 8. AC-couple to inputs with 0.1-μF capacitors. Bias voltage = 2.2 V. INM9 C8 I Complimentary analog inputs for channel 9. Place a ≥ 15-nF capacitor to ground. The HPF response of the LNA depends on the capacitors. Bias voltage = 2.2 V. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 9 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com Pin Functions (continued) PIN NAME NO. I/O DESCRIPTION INP9 A8 I Analog inputs for channel 9. AC-couple to inputs with 0.1-μF capacitors. Bias voltage = 2.2 V. INM10 C7 I Complimentary analog inputs for channel 10. Place a ≥ 15-nF capacitor to ground. The HPF response of the LNA depends on the capacitors. Bias voltage = 2.2 V. INP10 A7 I Analog inputs for channel 10. AC-couple to inputs with 0.1-μF capacitors. Bias voltage = 2.2 V. INM11 C6 I Complimentary analog inputs for channel 11. Place a ≥ 15-nF capacitor to ground. The HPF response of the LNA depends on the capacitors. Bias voltage = 2.2 V. INP11 A6 I Analog inputs for channel 11. AC-couple to inputs with 0.1-μF capacitors. Bias voltage = 2.2 V. INM12 C5 I Complimentary analog inputs for channel 12. Place a ≥ 15-nF capacitor to ground. The HPF response of the LNA depends on the capacitors. Bias voltage = 2.2 V. INP12 A5 I Analog inputs for channel 12. AC-couple to inputs with 0.1-μF capacitors. Bias voltage = 2.2 V. INM13 C4 I Complimentary analog inputs for channel 13. Place a ≥ 15-nF capacitor to ground. The HPF response of the LNA depends on the capacitors. Bias voltage = 2.2 V. INP13 A4 I Analog inputs for channel 13. AC-couple to inputs with 0.1-μF capacitors. Bias voltage = 2.2 V. INM14 C3 I Complimentary analog inputs for channel 14. Place a ≥ 15-nF capacitor to ground. The HPF response of the LNA depends on the capacitors. Bias voltage = 2.2 V. INP14 A3 I Analog inputs for channel 14. AC-couple to inputs with 0.1-μF capacitors. Bias voltage = 2.2 V. INM15 C2 I Complimentary analog inputs for channel 15. Place a ≥ 15-nF capacitor to ground. The HPF response of the LNA depends on the capacitors. Bias voltage = 2.2 V. INP15 A2 I Analog inputs for channel 15. AC-couple to inputs with 0.1-μF capacitors. Bias voltage = 2.2 V. INM16 C1 I Complimentary analog inputs for channel 16. Place a ≥ 15-nF capacitor to ground. The HPF response of the LNA depends on the capacitors. Bias voltage = 2.2 V. INP16 A1 I Analog inputs for channel 16. AC-couple to inputs with 0.1-μF capacitors. Bias voltage = 2.2 V. A9, B9, C9, D13, D14, G13, G14, H5, H13-H15, H17, J5, J13-J16, K4, K5, K13-K16, L1, L2, L4, L14, L15, M1, M2, N1, N17, P1, P17, R1, R5, R9, R13, R17, T1, T17, U1-U4,U14-U17 — PDN_FAST M17 I Partial power-down control pin for the entire device with an internal 16-kΩ pulldown resistor; active high. Note that a 1.8-V logic level is recommended. PDN_GBL M16 I Global (complete) power-down control pin for the entire device with an internal 16-kΩ pulldown resistor; active high. Note that a 1.8-V logic level is required. RESET L17 I Hardware reset pin with an internal 16-kΩ pulldown resistor; active high. Note that a 1.8-V logic level is required. SCLK J17 I Serial interface clock pin with an internal 16-kΩ pulldown resistor. Note that a 1.8-V logic level is required. SDIN L16 I Serial interface data pin with an internal 16-kΩ pulldown resistor. Note that a 1.8-V logic level is required. SDOUT H16 O Serial interface readout pin for channels 1 to 16. This pin is in tri-state by default. Note that a 1.8-V logic level is required. SEN K17 I Serial interface enable, active low. This pin has a 16-kΩ pullup resistor. Note that a 1.8-V logic level is required. TX_TRIG M15 I This pin synchronizes test patterns across devices. This pin has a 20-kΩ pulldown resistor. Note that a 1.8-V logic level is required. NC 10 Unused pins. Do not connect. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 Pin Functions (continued) PIN NAME NO. VCNTLM J4 VCNTLP H4 VHIGH1 F5 VHIGH2 G5 I/O DESCRIPTION I Differential attenuation control pins O Bypass to ground with a ≥ 1-μF capacitor. Bias voltage = 1 V. 8 Specifications 8.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) Supply voltage MIN MAX AVDD_1P8 –0.3 2.2 AVDD_3P3 –0.3 3.9 AVDD_5V –0.3 6 DVDD_1P2 –0.3 1.35 DVDD_1P8 –0.3 2.2 UNIT V Voltage at analog inputs –0.3 minimum [3.6, AVDD_3P3 + 0.3] V Voltage at all digital inputs except CW clocks –0.3 minimum [2.2, DVDD_1P8 + 0.3] V Voltage at CW clock input pins –0.3 minimum [6, AVDD_5V + 0.3] V Peak solder temperature (2) Temperature (1) (2) 260 Maximum junction temperature (TJ), any condition 105 Operating, TA –40 85 Storage, Tstg –55 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Device complies with JSTD-020D. 8.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) Charged device model (CDM), per JEDEC specification JESD22-C101 (2) UNIT ±1000 ±250 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 11 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 8.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) PARAMETER MIN MAX AVDD_1P8 voltage 1.7 1.9 V AVDD_3P3 voltage 3.15 3.6 V AVDD_5V voltage 4.75 5.25 V DVDD_1P2 voltage 1.15 1.25 V DVDD_1P8 voltage V 1.7 1.9 VCNTLP – VCNTLM 0 1.5 Sample rate 5 80 (1) –40 85 Ambient temperature, TA (1) UNIT V MHz °C The maximum speed supported is a function of ADC resolution. The number specified is for 12-bit mode. 8.4 Thermal Information AFE5818 THERMAL METRIC (1) ZBV (NFBGA) UNIT 289 PINS RθJA Junction-to-ambient thermal resistance 28.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 5.3 °C/W RθJB Junction-to-board thermal resistance 13.8 °C/W ψJT Junction-to-top characterization parameter 0.6 °C/W ψJB Junction-to-board characterization parameter 13.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) 12 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 8.5 Electrical Characteristics At TA = 25°C, AVDD_1P8 = 1.8 V, AVDD_3P3 = 3.3 V, AVDD_5V = 5 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, accoupled with a 0.1-µF capacitor at INP, 15-nF capacitor to ground at INM, no active termination, VCNTLP = VCNTLM = 0 V, LNA = 18 dB, PGA = 24 dB, LPF filter = 15 MHz, low-noise mode, internal 500-Ω CW feedback resistor, 14-bit ADC resolution, ADC_CLKP and ADC_CLKM = 50-MHz differential, LVDS mode to capture ADC data, input signal frequency fIN = 5 MHz, and output amplitude VOUT = –1 dBFS, unless otherwise noted. Minimum and maximum values are specified across the full temperature range. PARAMETER TEST CONDITION MIN TYP MAX UNIT TGC FULL-SIGNAL CHANNEL (VGA + LPF + ADC) Low-noise mode, RS = 0 Ω, f = 2 MHz, PGA = 24 dB Low-noise mode, RS = 0 Ω, f = 2 MHz, PGA = 30 dB Low-power mode, RS = 0 Ω, f = 2 MHz, PGA = 24 dB en (RTI) Input voltage noise over LNA gain Low-power mode, RS = 0 Ω, f = 2 MHz, PGA = 30 dB Medium-power mode, RS = 0 Ω, f = 2 MHz, PGA = 24 dB Medium-power mode, RS = 0 Ω, f = 2 MHz, PGA = 30 dB Input-referred current noise 0.76 LNA = 18 dB 0.87 LNA = 12 dB 1.19 LNA = 24 dB 0.75 LNA = 18 dB 0.84 LNA = 12 dB 1.15 LNA = 24 dB 1.1 LNA = 18 dB 1.2 LNA = 12 dB 1.7 LNA = 24 dB 1.1 LNA = 18 dB 1.2 LNA = 12 dB 1.6 LNA = 24 dB 1 LNA = 18 dB 1.1 LNA = 12 dB 1.3 LNA = 24 dB 0.95 LNA = 18 dB 1 LNA = 12 dB 1.25 Low-noise mode 3.2 Medium-power mode 2.7 Low-power mode 2.3 LNA = 18 dB, RS = 50 Ω, no active termination NF LNA = 24 dB Noise figure LNA = 18 dB, RS = 400 Ω, no active termination Low-noise mode 2.4 Medium-power mode 3.2 Low-power mode 3.7 Low-noise figure mode 3.4 Low-noise mode 1.2 Medium-power mode 1.2 Low-power mode LNA gain = 24 dB Maximum linear input voltage Input clamp voltage in auto clamp mode dB 0.83 250 LNA gain = 18 dB 500 LNA gain = 12 dB 1000 LNA gain = 24 dB 350 LNA gain = 18 dB 600 LNA gain = 12 dB 1150 mVPP mVPP 24 Low-noise mode 30 PGA gain Medium-power and low-power modes LNA = 24 dB, PGA = 30 dB, low-noise mode Total gain pA/√Hz 1.2 Low-noise figure mode VMAX nV/√Hz 24 27.5 54 LNA = 24 dB, PGA = 30 dB, medium-power mode 51.5 LNA = 24 dB, PGA = 30 dB, low-power mode 51.5 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 dB dB 13 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com Electrical Characteristics (continued) At TA = 25°C, AVDD_1P8 = 1.8 V, AVDD_3P3 = 3.3 V, AVDD_5V = 5 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, accoupled with a 0.1-µF capacitor at INP, 15-nF capacitor to ground at INM, no active termination, VCNTLP = VCNTLM = 0 V, LNA = 18 dB, PGA = 24 dB, LPF filter = 15 MHz, low-noise mode, internal 500-Ω CW feedback resistor, 14-bit ADC resolution, ADC_CLKP and ADC_CLKM = 50-MHz differential, LVDS mode to capture ADC data, input signal frequency fIN = 5 MHz, and output amplitude VOUT = –1 dBFS, unless otherwise noted. Minimum and maximum values are specified across the full temperature range. PARAMETER TEST CONDITION MIN TYP MAX UNIT TGC FULL-SIGNAL CHANNEL (continued) Without a signal Channel-to-channel noise correlation factor (1) –20 With a signal, full band With a signal, 1-MHz band over carrier SNR Signal-to-noise ratio VCNTLP = 0 V –10 VCNTLP = 0.8 V –10 VCNTLP = 0 V –10 VCNTLP = 0.8 V –3.75 VCNTLP = 0.6 V (22-dB total channel gain) 65.7 68.5 VCNTLP = 0 V, LNA = 18 dB, PGA = 24 dB 59.3 62.5 VCNTLP = 0 V, LNA = 24 dB, PGA = 24 dB Narrow-band SNR SNR over 2-MHz band around carrier at VCNTLP = 0.6 V (22-dB total gain) Input common-mode voltage At INP and INM pins dB dBFS 58 73.8 At dc 77 dBFS 2.2 V 8 kΩ 50 Input resistance 100 Preset active termination enabled (2), across GBL_ACTIVE_TERM (register 196, bits 7-6) register settings; see Table 74 Ω 200 400 Input capacitance 20 Input control voltage VCNTLP – VCNTLM 0 Common-mode voltage VCNTLP and VCNTLM Tolerable noise at VCNTLP – VCNTLM For summation of 16 channels; see Figure 69 6 For summation of 64 channels; see Figure 69 3 0.75 Gain range pF 1.5 V V nV/√Hz –40 dB 35 dB/V Between VCNTLP and VCNTLM 200 kΩ Between VCNTLP and VCNTLM 1 pF 1.5 µs Gain slope VCNTLP = 0.1 V to 0.9 V Input resistance Input capacitance TGC response time VCNTLP = 0-V to 1.5-V step function 10 15 3rd-order, low-pass filter –1-dB cutoff frequency across LPF_RPOG (register 195, bits 3-0) register settings; see Table 72 20 30 MHz 35 50 Settling time (1) (2) 14 For change in LNA gain 14 For change in active termination setting 10 µs The noise-correlation factor is defined as 10 × log10[Nc / (Nu + Nc)], where Nc is the correlated noise power in a single channel and Nu is the uncorrelated noise power in a single channel. The noise-correlation factor measurement is described by the equation: Nc / (Nu + Nc) = N_16CH / N_1CH / 240 – 1 / 15, where N_16CH is the noise power of the summed 16 channels and N_1CH is the noise power of one channel. Total device input impedance is given by the parallel combination of the mentioned active termination resistance and a passive resistance of 15 kΩ. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 Electrical Characteristics (continued) At TA = 25°C, AVDD_1P8 = 1.8 V, AVDD_3P3 = 3.3 V, AVDD_5V = 5 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, accoupled with a 0.1-µF capacitor at INP, 15-nF capacitor to ground at INM, no active termination, VCNTLP = VCNTLM = 0 V, LNA = 18 dB, PGA = 24 dB, LPF filter = 15 MHz, low-noise mode, internal 500-Ω CW feedback resistor, 14-bit ADC resolution, ADC_CLKP and ADC_CLKM = 50-MHz differential, LVDS mode to capture ADC data, input signal frequency fIN = 5 MHz, and output amplitude VOUT = –1 dBFS, unless otherwise noted. Minimum and maximum values are specified across the full temperature range. PARAMETER TEST CONDITION MIN TYP MAX UNIT AC ACCURACY LPF bandwidth tolerance ±5% Channel-to-channel group delay variation 2 MHz to 15 MHz Channel-to-channel phase variation 15-MHz signal 0 V < VCNTLP < 0.1 V (device-to-device) Gain matching 2 ns 11 Degrees ±0.5 0.1 V < VCNTLP < 1.1 V (device-to-device) –1.1 1.1 V < VCNTLP < 1.5 V (device-to-device) ±0.5 1.1 dB 120 LSB ±0.5 Output offset –120 AC PERFORMANCE HD2 HD3 Second-harmonic distortion Third-harmonic distortion Input frequency = 2 MHz, output amplitude = –1 dBFS –60 Input frequency = 5 MHz, output amplitude = –1 dBFS –60 Input frequency = 5 MHz, output amplitude = –1 dBFS, input amplitude = 500 mVPP, LNA = 18 dB, VCNTLP = 0.88 V –55 Input frequency = 5 MHz, output amplitude = –1 dBFS, input amplitude = 250 mVPP, LNA = 24 dB, VCNTLP = 0.88 V –55 Input frequency = 2 MHz, output amplitude = –1 dBFS –55 Input frequency = 5 MHz, output amplitude = –1 dBFS –55 Input frequency = 5 MHz, output amplitude = –1 dBFS, input amplitude = 500 mVPP, LNA = 18 dB, VCNTLP = 0.88 V –55 Input frequency = 5 MHz, output amplitude = –1 dBFS, input amplitude = 250 mVPP, LNA = 24 dB, VCNTLP = 0.88 V –55 Input frequency = 2 MHz, output amplitude = –1 dBFS –55 Input frequency = 5 MHz, output amplitude = –1 dBFS –55 –60 THD Total harmonic distortion IMD3 Intermodulation distortion Input frequency 1 = 5 MHz at –1 dBFS, input frequency 2 = 5.01 MHz at –27 dBFS Fundamental crosstalk Signal applied to single channel Phase noise 1 kHz off 5-MHz carrier (VCNTLP = 0 V) dBc dBc dBc dBc -60 –132 dBFS dBc/√Hz LOW-NOISE AMPLIFIER (LNA) 16 HPF High-pass filter –3-dB cutoff frequency for INMx capacitor = 15 nF, across LNA_HPF_PROG (register 203, bits 3-2) and RED_LNA_HPF_3X (register 205, bit 8) register settings; see Table 89 and Table 91 50 100 kHz 150 200 Input-referred voltage noise RS = 0 Ω, f = 2 MHz, RIN = high-Z LNA gain = 24 dB 0.63 LNA gain = 18 dB 0.70 LNA gain = 12 dB 0.9 LNA linear output nV/√Hz 4 VPP VCAT + PGA VCAT input noise PGA input noise 0-dB attenuation 2 –40-dB attenuation 10.5 24-dB and 30-dB attenuation 1.75 –3-dB HPF cutoff frequency nV/√Hz nV/√Hz 80 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 kHz 15 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com Electrical Characteristics (continued) At TA = 25°C, AVDD_1P8 = 1.8 V, AVDD_3P3 = 3.3 V, AVDD_5V = 5 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, accoupled with a 0.1-µF capacitor at INP, 15-nF capacitor to ground at INM, no active termination, VCNTLP = VCNTLM = 0 V, LNA = 18 dB, PGA = 24 dB, LPF filter = 15 MHz, low-noise mode, internal 500-Ω CW feedback resistor, 14-bit ADC resolution, ADC_CLKP and ADC_CLKM = 50-MHz differential, LVDS mode to capture ADC data, input signal frequency fIN = 5 MHz, and output amplitude VOUT = –1 dBFS, unless otherwise noted. Minimum and maximum values are specified across the full temperature range. PARAMETER TEST CONDITION MIN TYP MAX UNIT CW DOPPLER en (RTI) en (RTO) NF Input voltage noise (CW) Output voltage noise (CW) Noise figure CW operating range 1 channel mixer, LNA = 24 dB, 500-Ω external feedback resistor 0.98 16 channel mixers, LNA = 24 dB, 32-Ω external feedback resistor 0.31 1 channel mixer, LNA = 18 dB, 500-Ω external feedback resistor 1.31 16 channel mixers, LNA = 18 dB, 32-Ω external feedback resistor 0.5 1 channel mixer, LNA = 24 dB, 500-Ω external feedback resistor 13.3 16 channel mixers, LNA = 24 dB, 32-Ω external feedback resistor 3.56 1 channel mixer, LNA = 18 dB, 500-Ω external feedback resistor 8.85 16 channel mixers, LNA = 18 dB, 32-Ω external feedback resistor 2.86 RS = 100 Ω, RIN = high-Z, fIN = 2 MHz, 1 channel, LNA = 18 dB 3.18 RS = 100 Ω, RIN = high-Z, fIN = 2 MHz, 16 channels, LNA = 18 dB 6.15 CW signal carrier frequency CW clock frequency CLK duty cycle 1X and 16X CLKs Common-mode voltage Internally provided 0.2 IMD3 Input dynamic range Intermodulation distortion VPP 65% 2.5 4 1 kHz off 2-MHz carrier (16X mode, 1 channel) 156 1 kHz off 2-MHz carrier (16X mode, 16 channel) 161 Input frequency = 2.5 MHz LNA = 24 dB 159.1 LNA = 18 dB 162.6 LNA = 12 dB 164.4 f1 = 5 MHz, f2 = 5.01 MHz, both tones at –16-dBm amplitude, 16 channels summed up in-phase, CW feedback resistor = 32 Ω –50 f1 = 5 MHz, f2 = 5.01 MHz, both tones at –16-dBm amplitude, single channel summed up in-phase, CW feedback resistor = 500 Ω –60 V dB dBc/Hz dBFS/Hz dBc I/Q channel gain matching 16X mode ±0.04 4X mode ±0.04 I/Q channel phase matching 16X mode ±0.01 4X mode ±0.01 –50 Submit Documentation Feedback V 5 4 Image rejection ratio 16 0.35 35% CW mixer conversion loss DR MHz 32 VCMOS CMOS input clock amplitude CW mixer phase noise MHz 128 CLKP_16X, CLKM_16X (4X mode) CLKM_1X, CLKP_1X and CLKM_16X, CLKP_16X dB 8 CLKP_16X, CLKM_16X (16X mode) Clock amplitude (ac-coupled) nV/√Hz 8 CLKP_1X, CLKM_1X (16X mode) CWCLK nV/√Hz dB Degrees dBc Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 Electrical Characteristics (continued) At TA = 25°C, AVDD_1P8 = 1.8 V, AVDD_3P3 = 3.3 V, AVDD_5V = 5 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, accoupled with a 0.1-µF capacitor at INP, 15-nF capacitor to ground at INM, no active termination, VCNTLP = VCNTLM = 0 V, LNA = 18 dB, PGA = 24 dB, LPF filter = 15 MHz, low-noise mode, internal 500-Ω CW feedback resistor, 14-bit ADC resolution, ADC_CLKP and ADC_CLKM = 50-MHz differential, LVDS mode to capture ADC data, input signal frequency fIN = 5 MHz, and output amplitude VOUT = –1 dBFS, unless otherwise noted. Minimum and maximum values are specified across the full temperature range. PARAMETER TEST CONDITION MIN TYP MAX UNIT CW SUMMING AMPLIFIER Output common-mode voltage Internally provided 1.5 Summing amplifier output Input-referred voltage noise V 4 At 100 Hz 1.6 At 1 kHz 0.9 At 2 kHz to 100 MHz 0.8 VPP nV/√Hz Input-referred current noise 3.75 Unity-gain bandwidth 150 MHz 50 mAPP Maximum output current pA/√Hz ADC SPECIFICATIONS (Clock Input) Sample rate 14-bit rate 5 65 12-bit rate 5 80 Input clock amplitude differential (ADC_CLKP – ADC_CLKM) Sine-wave, ac-coupled LVDS, ac-coupled 0.3 Input clock CMOS amplitude single-ended (ADC_CLKP) High-level input voltage (VIH) 1.5 MSPS 1.5 LVPECL, ac-coupled 1.6 Low-level input voltage (VIL) VPP 0.3 Input clock duty cycle 35% 50% V 65% ADC SPECIFICATIONS (Signal-to-Noise Ratio) 14-bit ratio SNR Signal-to-noise ratio 12-bit ratio Without signal 75 With full-scale signal 72.5 Without signal dBFS 72 With full-scale signal 69.5 ADC SPECIFICATIONS (Analog Input) ADC input full-scale range 2 LVDS rate VPP 1000 Mbps POWER DISSIPATION AVDD_1P8 voltage 1.7 1.8 1.9 V AVDD_3P3 voltage 3.15 3.3 3.6 V AVDD_5V voltage 4.75 5 5.25 V DVDD_1P2 voltage 1.15 1.2 1.25 V DVDD_1P8 voltage 1.7 1.8 1.9 V Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 17 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com Electrical Characteristics (continued) At TA = 25°C, AVDD_1P8 = 1.8 V, AVDD_3P3 = 3.3 V, AVDD_5V = 5 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, accoupled with a 0.1-µF capacitor at INP, 15-nF capacitor to ground at INM, no active termination, VCNTLP = VCNTLM = 0 V, LNA = 18 dB, PGA = 24 dB, LPF filter = 15 MHz, low-noise mode, internal 500-Ω CW feedback resistor, 14-bit ADC resolution, ADC_CLKP and ADC_CLKM = 50-MHz differential, LVDS mode to capture ADC data, input signal frequency fIN = 5 MHz, and output amplitude VOUT = –1 dBFS, unless otherwise noted. Minimum and maximum values are specified across the full temperature range. PARAMETER TEST CONDITION MIN TYP MAX ADC in 12-bit resolution, 80 MSPS 143 170 ADC in 14-bit resolution, 65 MSPS 140 ADC in 14-bit resolution, 50 MSPS 136 ADC in 14-bit resolution, 40 MSPS 134 UNIT POWER DISSIPATION (continued) TGC low-noise mode, no signal TGC mode (Total power dissipation per channel) TGC low-noise mode, 500-mVPP input,1% duty cycle 139.5 TGC medium-power mode 104.4 TGC medium-power mode, 500-mVPP input, 1% duty cycle 107.4 TGC low-power mode 93.5 TGC low-power, 500-mVPP input, 1% duty cycle CW mode (Total power dissipation per channel with ADC and PGA in power-down state) CW mode, no signal, ADC shutdown CW mode 96 16X clock = 32 MHz 80 16X clock = 80 MHz 95 CW mode, 16X clock = 80 MHz, CW summing amplifier external feedback resistance = 33 Ω, 500-mVPP input to all 16 channels, ADC shutdown 203 TGC low-noise mode, no signal 414 TGC medium-power mode, no signal 260 TGC low-power mode, no signal AVDD_3P3 current CW mode, no signal 285 16X clock = 80 MHz 285 430 TGC medium-power mode, 500-mVPP input, 1% duty cycle 274 TGC low-power mode, 500-mVPP input, 1% duty cycle 219 CW mode, 16X clock = 80 MHz, 500-mVPP input to all 16 channels 740 TGC low-noise, medium-power, or low-power mode, no signal CW mode, no signal 64 16X clock = 80 MHz 115 CW mode, 16X clock = 80 MHz, 500-mVPP input to all 16 channels AVDD_1P8 current 14-bit mode 12-bit mode DVDD_1P2 current 14-bit mode 12-bit mode DVDD_1P8 current 14-bit mode 18 57 16X clock = 32 MHz TGC, low-noise, medium-power, or low-power mode, 500-mVPP input, 1% duty cycle 12-bit mode 112 mW/Ch 467 207 16X clock = 32 MHz TGC low-noise mode, 500-mVPP input, 1% duty cycle AVDD_5V current mW/Ch mA 80 136 mA 57 160 80 MSPS 170 20 MSPS 120 65 MSPS 160 20 MSPS 120 80 MSPS 110 20 MSPS 50 65 MSPS 95 20 MSPS 52 80 MSPS 100 20 MSPS 85 65 MSPS 95 20 MSPS 85 Submit Documentation Feedback 337 197 mA 160 mA 132 mA Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 Electrical Characteristics (continued) At TA = 25°C, AVDD_1P8 = 1.8 V, AVDD_3P3 = 3.3 V, AVDD_5V = 5 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, accoupled with a 0.1-µF capacitor at INP, 15-nF capacitor to ground at INM, no active termination, VCNTLP = VCNTLM = 0 V, LNA = 18 dB, PGA = 24 dB, LPF filter = 15 MHz, low-noise mode, internal 500-Ω CW feedback resistor, 14-bit ADC resolution, ADC_CLKP and ADC_CLKM = 50-MHz differential, LVDS mode to capture ADC data, input signal frequency fIN = 5 MHz, and output amplitude VOUT = –1 dBFS, unless otherwise noted. Minimum and maximum values are specified across the full temperature range. PARAMETER TEST CONDITION MIN TYP MAX UNIT POWER-DOWN Power dissipation in power-down mode Partial power-down when PDN_FAST = high (1.8 V) 28 Complete power-down when PDN_GBL = high (1.8 V) 2.2 Power-down response time Power-up response time Partial power-down when PDN_FAST= high (1.8 V) and the device in partial power-down time for < 500 µs Complete power-down when PDN_GBL = high (1.8 V) 1 µs 3 µs 2.7 ms PSMR Power-supply modulation fIN = 5 MHz, supply tone of 100 mVPP at ratio 1-kHz frequency AVDD_3P3 AVDD_5V –63 PSRR Power-supply rejection ratio (3) AVDD_3P3 –70 AVDD_5V –70 (3) Supply tone of 100 mVPP at 1-kHz frequency mW/Ch –65 dBc dBc The PSRR value in dBc is measured with respect to the supply tone amplitude applied at the device supply (that is, 100 mVPP). 8.6 Digital Characteristics The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. Typical values are at TA = 25°C, minimum and maximum values are across the full temperature range of TMIN = -40°C to TMAX = 85°C, AVDD_1P8 = 1.8 V, AVDD_3P3 = 3.3 V, AVDD_5V = 5 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, external differential load resistance between the LVDS output pair, and RLOAD = 100 Ω, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOAD RESISTANCE External differential load resistance Between LVDS output pair Ω 100 CMOS DIGITAL INPUTS (PDN_GBL, PDN_FAST, RESET, SCLK, SDIN, SEN) VIH High-level input voltage 1.4 2.1 VIL Low-level input voltage 0 0.3 V IIH High-level input current 100 µA IIL Low-level input current 100 µA Ci Input capacitance 4 pF 420 mV 1.03 V V LVDS DIGITAL OUTPUTS (DOUTPx, DOUTMx) (1) |VOD| Output differential voltage VOS Output offset voltage Common-mode voltage of DOUTPx and DOUTMx CMOS DIGITAL OUTPUT (SDOUT) VOH High-level output voltage 1.4 DVDD_1P8 VOL Low-level output voltage DVSS 0.3 zo Output impedance (1) 50 V V Ω All LVDS specifications are characterized but are not tested at production. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 19 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 8.7 Output Interface Timing Typical values are at TA = 25°C, AVDD_1P8 = 1.8 V, AVDD_3P3 = 3.3 V, AVDD_5V = 5 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, differential ADC clock, LVDS load CLOAD = 5 pF, RLOAD = 100 Ω, 14-bit ADC resolution, and sample rate = 65 MSPS, unless otherwise noted. Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = 85°C. MIN TYP MAX UNIT GENERAL tAP Aperture delay (1) δtAP Aperture delay variation from device to device (at same temperature and supply) tAPJ Aperture jitter with LVPECL clock as input clock 1.6 ns ±0.5 ns 0.5 ps 15 Cycles 1 ms Time to valid data after stopping and restarting the input clock 100 µs Default after reset (1) 8.5 Low-latency mode 4.5 Time to valid data after exiting standby mode (units are in number of ADC_CLKP, ADC_CLKM cycles) Wake-up time Time to valid data after exiting PDN_GBL mode ADC TIMING Cd ADC latency ADC clocks LVDS TIMING (2) fF Frame clock frequency (1) DFRAME Frame clock duty cycle NSER Number of bits serialization of each ADC word fCLKIN MHz 50% 12 16 1X output data rate mode NSER × fCLKIN 1000 2X output data rate mode 2 × NSER × fCLKIN 1000 500 fD Output rate of serialized data fB Bit clock frequency fD / 2 DBIT Bit clock duty cycle 50% tD Data bit duration (1) tPDI Clock propagation delay (1) δtPROP 1 Bits Mbps MHz 1000 / fD ns 6 × tD+ 5 ns Clock propagation delay variation from device to device (at same temperature and supply) ±2 ns tORF DOUT, DCLK, FCLK rise and fall time, transition time between –100 mV and +100 mV 0.2 ns tOSU Minimum serial data, serial clock setup time (1) tD / 2 – 0.4 ns tOH Minimum serial data, serial clock hold time (1) tD / 2 – 0.4 ns tDV Minimum data valid window (3) (1) tD – 0.65 ns TX_TRIG TIMING tTX_TRIG_DEL Delay between TX_TRIG and TX_TRIGD (4) tSU_TX_TRIGD Setup time related to latching TX_TRIGD relative to the rising edge of the system clock 0.6 ns tH_TX_TRIGD Hold time related to latching TX_TRIGD relative to the rising edge of the system clock 0.4 ns (1) (2) (3) (4) (5) 20 0.4 × tCLKIN (5) 0.5 ns See Figure 1. All LVDS specifications are characterized but are not tested at production. The specification for the minimum data valid window is larger than the sum of the minimum setup and hold times because there can be a skew between the ideal transitions of the serial output data with respect to the transition of the bit clock. This skew can vary across channels and across devices. A mechanism to correct this skew can therefore improve the setup and hold timing margins. For example, the LVDS_DCLK_DELAY_PROG control can be used to shift the relative timing of the bit clock with respect to the data. TX_TRIGD is the internally delayed version of TX_TRIG that gets latched on the rising edge of the ADC clock. tCLKIN is the ADC clock period in nanoseconds (ns). Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com 8.8 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 Serial Interface Timing Characteristics Typical values are at TA = 25°C, AVDD_1P8 = 1.8 V, AVDD_3P3 = 3.3 V, AVDD_5V = 5 V, DVDD_1P2 = 1.2 V, and DVDD_1P8 = 1.8 V, unless otherwise noted. Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = 85°C. MIN TYP MAX UNIT tSCLK SCLK period 50 ns tSCLK_H SCLK high time 20 ns tSCLK_L SCLK low time 20 ns tDSU Data setup time 5 ns tDHO Data hold time 5 ns tSEN_SU SEN falling edge to SCLK rising edge 8 ns tSEN_HO Time between last SCLK rising edge to SEN rising edge 8 tOUT_DV SDOUT delay ns 12 20 28 ns Sample N Input Signal TAP Cd Clock Cycles Latency Input Clock (CLKIN) Frequency = fCLKIN TF tPDI Frame Clock (FCLK) Frequency = fCLKIN Bit Clock (DCLK) Frequency = 7 x fCLKIN Output Data (CHn OUT) Data Rate = 14 x fCLKIN 1 (12) 0 (13) 13 (0) 12 (1) 11 (2) 10 (3) 9 (4) 8 (5) 7 (6) 6 (7) 5 (8) 4 (9) 3 (10) 2 (11) 1 (12) 0 (13) 13 (0) 12 (1) 11 (2) 10 (3) 9 (4) 8 (5) 7 (6) 6 (7) 5 (8) 4 (9) 3 (10) 2 (11) 1 (12) 0 (13) 13 (0) 13 (0) 12 (1) 11 (2) 10 (3) 9 (4) 8 (5) 7 (6) 6 (7) 5 (8) 4 (9) 3 (10) 2 (11) 1 (12) 0 (13) 13 (0) 12 (1) Sample N Sample N-1 Data Bit in MSB-First Mode Data Bit in LSB-First Mode D0 DOUT1 D2 D1 D3 D4 Bit Clock (DCLK) tD tD tOH tOSU tB Bit Clock (DCLK) tDV tDV Figure 1. Output Timing Specification Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 21 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 8.9 Typical Characteristics At TA = 25°C, AVDD_1P8 = 1.8 V, AVDD_3P3 = 3.3 V, AVDD_5V = 5 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, accoupled with a 0.1-µF capacitor at INP, 15-nF capacitor to ground at INM, no active termination, VCNTLP = VCNTLM = 0 V, LNA = 18 dB, PGA = 24 dB, LPF filter = 15 MHz, low-noise mode, internal 500-Ω CW feedback resistor, 14-bit ADC resolution, ADC_CLKP and ADC_CLKM = 50-MHz differential, LVDS mode to capture ADC data, input signal frequency fIN = 5 MHz, and output amplitude VOUT = –1 dBFS, unless otherwise noted. Minimum and maximum values are specified across the full temperature range. 45 45 Low Noise Low Power Medium Power 40 35 35 30 30 Gain (dB) 25 20 25 20 15 15 10 10 5 5 0 0 1.1 1.2 1.3 1.4 1.5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VCNTL (V) D002 Across power modes Figure 2. Gain vs VCNTL 4000 4000 3500 D004 Gain Matching (dB) D005 Gain Matching (dB) VCNTL = 0.3 V 0.9 0.8 0.7 0.6 0.5 0.4 -0.8 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 0.1 0 -0.1 0 -0.2 500 -0.3 500 -0.4 1000 -0.5 1000 0.3 1500 0.2 1500 2000 0 2000 2500 0.1 2500 -0.6 D003 3000 -0.5 3000 -0.6 3500 -0.7 Number of Occurrences 4500 4500 -0.7 1.1 1.2 Figure 3. Gain vs VCNTL 5000 -0.8 Number of Occurrences 1 Across temperature -0.1 1 VCNTL (V) -0.2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 -0.3 0 -0.4 Gain (dB) -40qC 25qC 85qC 40 VCNTL = 0.6 V Figure 4. Gain Matching Histogram (17472 Channels) Figure 5. Gain Matching Histogram (17472 Channels) 4000 2500 Number of Occurrences Number of Occurrences 3500 3000 2500 2000 1500 1000 2000 1500 1000 500 500 Gain Matching (dB) D006 85 75 65 55 45 35 25 15 5 -5 -15 -25 -35 -45 -55 -65 ADC Output VCNTL = 0.9 V D007 VCNTL = 0 V Figure 6. Gain Matching Histogram (17472 Channels) 22 -75 -85 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 0 -0.8 0 Figure 7. Output Offset Histogram (17472 Channels) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 Typical Characteristics (continued) At TA = 25°C, AVDD_1P8 = 1.8 V, AVDD_3P3 = 3.3 V, AVDD_5V = 5 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, accoupled with a 0.1-µF capacitor at INP, 15-nF capacitor to ground at INM, no active termination, VCNTLP = VCNTLM = 0 V, LNA = 18 dB, PGA = 24 dB, LPF filter = 15 MHz, low-noise mode, internal 500-Ω CW feedback resistor, 14-bit ADC resolution, ADC_CLKP and ADC_CLKM = 50-MHz differential, LVDS mode to capture ADC data, input signal frequency fIN = 5 MHz, and output amplitude VOUT = –1 dBFS, unless otherwise noted. Minimum and maximum values are specified across the full temperature range. 12000 10 Open 10000 -10 -20 8000 Phase (q) Impedance (:) Open 0 6000 4000 -30 -40 -50 -60 -70 2000 -80 0 0.5 4.5 8.5 12.5 Frequency (MHz) 16.5 -90 0.5 20.5 4.5 D008 Without active termination 16.5 20.5 D009 Without active termination Figure 8. Input Impedance Magnitude vs Frequency Figure 9. Input Impedance Phase vs Frequency 550 10 50 : 100 : 200 : 400 : 500 450 400 0 -10 -20 350 Phase (q) Impedance (:) 8.5 12.5 Frequency (MHz) 300 250 200 -30 -40 -50 -60 150 100 -70 50 -80 0 0 5 10 15 Frequency (MHz) 20 -90 0.5 25 50 : 100 : 200 : 400 : 4.5 D010 Across active termination 8.5 12.5 Frequency (MHz) 16.5 20.5 D011 Across active termination Figure 10. Input Impedance Magnitude vs Frequency Figure 11. Input Impedance Phase vs Frequency 5 3 0 0 -3 -5 Amplitude (dB) Amplitude (dB) -6 -10 -15 -20 10 MHz 15 MHz 20 MHz 30 MHz 35 MHz 50 MHz -25 -30 -35 10 20 -15 -18 Register 203[3:2], 205[8] = 01, 1 Register 203[3:2], 205[8] = 01, 0 Register 203[3:2], 205[8] = 00, 0 Register 203[3:2], 205[8] = 11, 0 Register 203[3:2], 205[8] = 10, 0 -21 -24 -27 -40 0 -9 -12 30 40 50 60 Frequency (MHz) 70 80 90 -30 10 D012 Across LPF corner settings 20 30 40 50 70 100 Frequency (kHz) 200 300 500 D013 Across LNA_HPF_PROG (register 203, bits 3-2) and RED_LNA_HPF_3X (register 205, bit 8) Figure 12. Full-Channel Amplitude Response vs Frequency Figure 13. LNA High-Pass Filter Amplitude Response vs Frequency Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 23 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com Typical Characteristics (continued) At TA = 25°C, AVDD_1P8 = 1.8 V, AVDD_3P3 = 3.3 V, AVDD_5V = 5 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, accoupled with a 0.1-µF capacitor at INP, 15-nF capacitor to ground at INM, no active termination, VCNTLP = VCNTLM = 0 V, LNA = 18 dB, PGA = 24 dB, LPF filter = 15 MHz, low-noise mode, internal 500-Ω CW feedback resistor, 14-bit ADC resolution, ADC_CLKP and ADC_CLKM = 50-MHz differential, LVDS mode to capture ADC data, input signal frequency fIN = 5 MHz, and output amplitude VOUT = –1 dBFS, unless otherwise noted. Minimum and maximum values are specified across the full temperature range. 5 5 PGA Integrator Enable PGA Integrator Disable 0 -5 0 Amplitude (dB) Amplitude (dB) -10 -15 -20 -25 -5 -30 -10 -35 -40 -45 10 -15 100 Frequency (kHz) 500 0 100 200 300 D014 400 500 600 700 Frequency (kHz) 800 900 1000 D015 With INM capacitor = 1 μF -144 -146 -148 -150 -152 -154 -156 -158 -160 -162 -164 -166 -168 -170 100 Figure 15. Full-Channel Low Frequency Amplitude Response vs Frequency 16X Clock Mode 8X Clock Mode 4X Clock Mode Phase Noise (dBc/Hz) Phase Noise (dBc/Hz) Figure 14. Full-Channel High-Pass Filter Amplitude Response vs Frequency 1k 10k Offset Frequency (Hz) 50k -144 -146 -148 -150 -152 -154 -156 -158 -160 -162 -164 -166 -168 -170 100 D017 Figure 17. CW Phase Noise vs Offset Frequency 45 16X Clock Mode 8X Clock Mode 4X Clock Mode LNA 12 dB LNA 18 dB LNA 24 dB 40 Input-Referred Noise (nV—Hz) Phase Noise (dBc/Hz) 50k fIN = 2 MHz, across one channel and 16 channels Figure 16. CW Phase Noise vs Offset Frequency 35 30 25 20 15 10 5 0 1k 10k Offset Frequency (Hz) 50k 0 D018 fIN = 2 MHz, 16 channels across CW clock modes Figure 18. CW Phase Noise vs Offset Frequency 24 1k 10k Offset Frequency (Hz) D016 fIN = 2 MHz, one channel across CW clock modes -144 -146 -148 -150 -152 -154 -156 -158 -160 -162 -164 -166 -168 -170 100 Phase Noise 1 Channel Phase Noise 16 Channels Submit Documentation Feedback 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VCNTL (V) 1 1.1 1.2 D019 Across LNA gain for low-noise mode Figure 19. Input-Referred Noise vs VCNTL Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 Typical Characteristics (continued) At TA = 25°C, AVDD_1P8 = 1.8 V, AVDD_3P3 = 3.3 V, AVDD_5V = 5 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, accoupled with a 0.1-µF capacitor at INP, 15-nF capacitor to ground at INM, no active termination, VCNTLP = VCNTLM = 0 V, LNA = 18 dB, PGA = 24 dB, LPF filter = 15 MHz, low-noise mode, internal 500-Ω CW feedback resistor, 14-bit ADC resolution, ADC_CLKP and ADC_CLKM = 50-MHz differential, LVDS mode to capture ADC data, input signal frequency fIN = 5 MHz, and output amplitude VOUT = –1 dBFS, unless otherwise noted. Minimum and maximum values are specified across the full temperature range. 50 LNA 12 dB LNA 18 dB LNA 24 dB 3 LNA 12 dB LNA 18 dB LNA 24 dB 45 Input-Referred Noise (nV—Hz) Input-Referred Noise (nV—Hz) 3.5 2.5 2 1.5 1 0.5 40 35 30 25 20 15 10 5 0 0 0 0.1 0.2 VCNTL (V) 0.3 0 0.4 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VCNTL (V) D020 Across LNA gain for low-noise mode D021 Figure 21. Input-Referred Noise vs VCNTL 70 3 LNA 12 dB LNA 18 dB LNA 24 dB 2.5 Input-Referred Noise (nV—Hz) Input-Referred Noise (nV—Hz) 1.1 1.2 Across LNA gain for medium-power mode Figure 20. Input-Referred Noise vs VCNTL (Zoomed) 2 1.5 1 LNA 12 dB LNA 18 dB LNA 24 dB 60 50 40 30 20 10 0 0.5 0 0.1 0.2 VCNTL (V) 0.3 0 0.4 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VCNTL (V) D022 Across LNA gain for medium-power mode 1 1.1 1.2 D023 Across LNA gain for low-power mode Figure 22. Input-Referred Noise vs VCNTL (Zoomed) Figure 23. Input-Referred Noise vs VCNTL 230 3.5 LNA 12 dB LNA 18 dB LNA 24 dB 3 LNA 12 dB LNA 18 dB LNA 24 dB 210 Output-Referred Noise (nV—Hz) Input-Referred Noise (nV—Hz) 1 2.5 2 1.5 1 190 170 150 130 110 90 70 50 30 0.5 0 0.1 0.2 VCNTL (V) 0.3 0.4 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VCNTL (V) D024 Across LNA gain for low-power mode 1 1.1 1.2 D025 Across LNA gain for low-noise mode Figure 24. Input-Referred Noise vs VCNTL (Zoomed) Figure 25. Output-Referred Noise vs VCNTL Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 25 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com Typical Characteristics (continued) At TA = 25°C, AVDD_1P8 = 1.8 V, AVDD_3P3 = 3.3 V, AVDD_5V = 5 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, accoupled with a 0.1-µF capacitor at INP, 15-nF capacitor to ground at INM, no active termination, VCNTLP = VCNTLM = 0 V, LNA = 18 dB, PGA = 24 dB, LPF filter = 15 MHz, low-noise mode, internal 500-Ω CW feedback resistor, 14-bit ADC resolution, ADC_CLKP and ADC_CLKM = 50-MHz differential, LVDS mode to capture ADC data, input signal frequency fIN = 5 MHz, and output amplitude VOUT = –1 dBFS, unless otherwise noted. Minimum and maximum values are specified across the full temperature range. LNA 12 dB LNA 18 dB LNA 24 dB 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VCNTL (V) 1 360 340 320 300 280 260 240 220 200 180 160 140 120 100 80 60 40 Output-Referred Noise (nV—Hz) Output-Referred Noise (nV—Hz) 300 280 260 240 220 200 180 160 140 120 100 80 60 40 1.1 1.2 LNA 12 dB LNA 18 dB LNA 24 dB 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VCNTL (V) D026 Across LNA gain for medium-power mode 1.1 1.2 D027 Across LNA gain for low-power mode Figure 26. Output-Referred Noise vs VCNTL Figure 27. Output-Referred Noise vs VCNTL 250 250 Regsiter 203[3:2], 205[8] = 01, 1 Regsiter 203[3:2], 205[8] = 01, 0 Regsiter 203[3:2], 205[8] = 00, 0 Regsiter 203[3:2], 205[8] = 11, 0 Regsiter 203[3:2], 205[8] = 10, 0 225 200 Output-Referred Noise (nV/—Hz) Output-Referred Noise (nV/—Hz) 1 175 150 125 100 75 0 200 400 600 800 1000 Frequency (kHz) 1200 1400 1600 225 200 175 150 125 100 75 50 250 450 650 850 1050 Frequency (kHz) D028 Across LNA_HPF_PROG (register 203, bits 3-2) and RED_LNA_HPF_3X (register 205, bit 8) 1250 1450 1650 D029 INMx capacitor = 1 µF, PGA_HPF_DIS (register 195, bit 4) = 1 Figure 28. Low-Frequency Output-Referred Noise vs Frequency Figure 29. Low-Frequency Output-Referred Noise vs Frequency 180 1.5 Output-Referred Noise (nV/—Hz) Input-Referred Noise (nV/—Hz) 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 160 140 120 100 80 60 0.4 40 0.3 1 2 3 4 5 6 7 8 Frequency (MHz) 9 10 11 12 Figure 30. Input-Referred Noise vs Frequency 26 1 D030 2 3 4 5 6 7 8 Frequency (MHz) 9 10 11 12 D031 Figure 31. Output-Referred Noise vs Frequency Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 Typical Characteristics (continued) 75 75 70 70 SNR (dBFS) SNR (dBFS) At TA = 25°C, AVDD_1P8 = 1.8 V, AVDD_3P3 = 3.3 V, AVDD_5V = 5 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, accoupled with a 0.1-µF capacitor at INP, 15-nF capacitor to ground at INM, no active termination, VCNTLP = VCNTLM = 0 V, LNA = 18 dB, PGA = 24 dB, LPF filter = 15 MHz, low-noise mode, internal 500-Ω CW feedback resistor, 14-bit ADC resolution, ADC_CLKP and ADC_CLKM = 50-MHz differential, LVDS mode to capture ADC data, input signal frequency fIN = 5 MHz, and output amplitude VOUT = –1 dBFS, unless otherwise noted. Minimum and maximum values are specified across the full temperature range. 65 60 55 65 60 55 24-dB PGA Gain 30-dB PGA Gain 24-dB PGA Gain 30-dB PGA Gain 50 50 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VCNTL (V) 1 1.1 1.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VCNTL (V) D032 Low-noise mode across PGA gain Figure 32. Signal-to-Noise Ratio vs VCNTL D033 Figure 33. Signal-to-Noise Ratio vs VCNTL 12 Low Noise Low Power 71 100 : 200 : 400 : Without Termination 11 10 69 9 Noise Figure (dB) SNR (dBFS) 1.1 1.2 Low-power mode across PGA gain 73 67 65 63 61 8 7 6 5 4 3 2 59 1 57 0 3 6 9 0 50 12 15 18 21 24 27 30 33 36 39 42 Gain (dB) D034 Across power modes 100 150 200 250 300 Source Impedence (:) 350 400 D035 LNA = 12 dB, low-noise mode across active termination Figure 34. Signal-to-Noise Ratio vs Gain Figure 35. Noise Figure vs Source Impedance 10 12 50 : 100 : 200 : 400 : Without Termination 10 9 8 50 : 100 : 200 : 400 : Without Termination 9 8 Noise Figure (dB) 11 Noise Figure (dB) 1 7 6 5 4 7 6 5 4 3 3 2 2 1 1 0 50 100 150 200 250 300 Source Impedence (:) 350 400 0 50 100 D036 LNA = 18 dB, low-noise mode across active termination Figure 36. Noise Figure vs Source Impedance 150 200 250 300 Source Impedence (:) 350 400 D037 LNA = 24 dB, low-noise mode across active termination Figure 37. Noise Figure vs Source Impedance Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 27 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com Typical Characteristics (continued) At TA = 25°C, AVDD_1P8 = 1.8 V, AVDD_3P3 = 3.3 V, AVDD_5V = 5 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, accoupled with a 0.1-µF capacitor at INP, 15-nF capacitor to ground at INM, no active termination, VCNTLP = VCNTLM = 0 V, LNA = 18 dB, PGA = 24 dB, LPF filter = 15 MHz, low-noise mode, internal 500-Ω CW feedback resistor, 14-bit ADC resolution, ADC_CLKP and ADC_CLKM = 50-MHz differential, LVDS mode to capture ADC data, input signal frequency fIN = 5 MHz, and output amplitude VOUT = –1 dBFS, unless otherwise noted. Minimum and maximum values are specified across the full temperature range. 4.5 4.5 Low Noise Low Power Medium Power Low Noise Figure 3.5 Noise Figure (dB) Noise Figure (dB) Low Noise Low Power Medium Power Low Noise Figure 3.5 2.5 2.5 1.5 1.5 50 100 150 200 250 300 Source Impedence (:) 350 0.5 50 400 Active termination = 400-Ω across power modes 150 200 250 300 Source Impedence (:) 350 400 D039 Without active termination across power modes Figure 38. Noise Figure vs Source Impedance Figure 39. Noise Figure vs Source Impedance -50 -45 -55 -50 -60 -55 HD3 (dBc) HD2 (dBc) 100 D038 -65 -70 Low Noise Low Power Medium Power -60 -65 Low Noise Low Power Medium Power -75 -70 -80 -75 1 2 3 4 5 6 7 Frequency (MHz) 8 9 10 1 2 3 D040 VIN = 500 mVPP, VOUT = –1 dBFS across power modes Figure 40. Second-Order Harmonic Distortion vs Frequency 4 5 6 7 Frequency (MHz) 8 9 10 D041 VIN = 500 mVPP, VOUT = –1 dBFS across power modes Figure 41. Third-Order Harmonic Distortion vs Frequency -30 -40 Low Noise Low Power Medium Power -45 -50 Low Noise Low Power Medium Power -40 -60 HD3 (dBc) HD2 (dBc) -55 -65 -70 -50 -60 -75 -80 -70 -85 -90 -80 6 12 18 24 Gain (dB) 30 36 LNA = 12 dB, VOUT = –1 dBFS across power modes Figure 42. Second-Order Harmonic Distortion vs Gain 28 6 12 18 24 Gain (dB) D042 30 36 D043 LNA = 12 dB, VOUT = –1 dBFS across power modes Figure 43. Third-Order Harmonic Distortion vs Gain Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 Typical Characteristics (continued) At TA = 25°C, AVDD_1P8 = 1.8 V, AVDD_3P3 = 3.3 V, AVDD_5V = 5 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, accoupled with a 0.1-µF capacitor at INP, 15-nF capacitor to ground at INM, no active termination, VCNTLP = VCNTLM = 0 V, LNA = 18 dB, PGA = 24 dB, LPF filter = 15 MHz, low-noise mode, internal 500-Ω CW feedback resistor, 14-bit ADC resolution, ADC_CLKP and ADC_CLKM = 50-MHz differential, LVDS mode to capture ADC data, input signal frequency fIN = 5 MHz, and output amplitude VOUT = –1 dBFS, unless otherwise noted. Minimum and maximum values are specified across the full temperature range. -40 -30 Low Noise Low Power Medium Power -60 -40 HD3 (dBc) HD2 (dBc) -50 -70 Low Noise Low Power Medium Power -80 -50 -60 -70 -90 12 18 24 30 36 -80 12 42 18 24 Gain (dB) 30 36 42 Gain (dB) LNA = 18 dB, VOUT = –1 dBFS across power modes D045 LNA = 18 dB, VOUT = –1 dBFS, across power modes Figure 44. Second-Order Harmonic Distortion vs Gain Figure 45. Third-Order Harmonic Distortion vs Gain -30 -40 Low Noise Low Power Medium Power -45 -50 Low Noise Low Power Medium Power -40 -60 HD3 (dBc) HD2 (dBc) -55 -65 -70 -50 -60 -75 -80 -70 -85 -90 18 24 30 36 42 -80 18 48 Gain (dB) 24 30 LNA = 24 dB, VOUT = –1 dBFS across power modes 48 D047 Figure 47. Third-Order Harmonic Distortion vs Gain -54 -54 fIN1 = 2 MHz, fIN2 = 2.01 MHz fIN1 = 5 MHz, fIN2 = 5.01 MHz fIN1 = 2 MHz, fIN2 = 2.01 MHz fIN1 = 5 MHz, fIN2 = 5.01 MHz -58 IMD3 (dBFS) -58 IMD3 (dBFS) 42 LNA = 24 dB, VOUT = –1 dBFS across power modes Figure 46. Second-Order Harmonic Distortion vs Gain -62 -66 -70 -74 14 36 Gain (dB) D046 -62 -66 -70 18 22 26 30 Gain (dB) 34 38 42 -74 14 D048 fOUT1 = –1 dBFS, fOUT2 = –21 dBFS 18 22 26 30 Gain (dB) 34 38 42 D049 fOUT1 = –7 dBFS, fOUT2 = –7 dBFS Figure 48. IMD3 vs Gain Figure 49. IMD3 vs Gain Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 29 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com Typical Characteristics (continued) At TA = 25°C, AVDD_1P8 = 1.8 V, AVDD_3P3 = 3.3 V, AVDD_5V = 5 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, accoupled with a 0.1-µF capacitor at INP, 15-nF capacitor to ground at INM, no active termination, VCNTLP = VCNTLM = 0 V, LNA = 18 dB, PGA = 24 dB, LPF filter = 15 MHz, low-noise mode, internal 500-Ω CW feedback resistor, 14-bit ADC resolution, ADC_CLKP and ADC_CLKM = 50-MHz differential, LVDS mode to capture ADC data, input signal frequency fIN = 5 MHz, and output amplitude VOUT = –1 dBFS, unless otherwise noted. Minimum and maximum values are specified across the full temperature range. -60 -50 VCNTL = 0 V VCNTL = 0.3 V VCNTL = 0.6 V VCNTL = 0.9 V -55 -65 PSMR (dBc) PSMR (dBc) VCNTL = 0 V VCNTL = 0.3 V VCNTL = 0.6 V VCNTL = 0.9 V -60 -65 -70 -70 -75 -75 5 10 100 Supply Frequency (kHz) 1k 2k 5 10 100 Supply Frequency (kHz) D050 Across VCNTL -10 VCNTL = 0 V VCNTL = 0.3 V VCNTL = 0.6 V VCNTL = 0.9 V -40 VCNTL = 0 V VCNTL = 0.3 V VCNTL = 0.6 V VCNTL = 0.9 V -20 PSRR wrt Supply Tone (dB) -30 -50 -60 -70 -80 -30 -40 -50 -60 -70 -80 -90 -90 5 10 100 Supply Frequency (kHz) 1k 2k 5 10 D052 100 Supply Frequency (kHz) Across VCNTL 1k 2k D053 Across VCNTL Figure 52. AVDD Power-Supply Rejection Ratio vs 100-mVPP Supply Noise Frequencies 1.35 18000 1.2 16000 1.05 16000 1.05 14000 0.9 14000 0.9 12000 0.75 12000 0.75 10000 0.6 8000 0.45 6000 0.3 4000 0.15 4000 2000 0 2000 0 -0.15 0 0.5 1 1.5 Time (Ps) 2 2.5 3 Output Code (LSB) 1.35 Output Code 1.2 VCNTL 20000 18000 VCNTL (V) 20000 Figure 53. AVDD_5V Power-Supply Rejection Ratio vs 100-mVPP Supply Noise Frequencies 10000 0.6 8000 0.45 6000 0.3 VCNTL (V) PSRR wrt Supply Tone (dB) D051 Figure 51. AVDD_5V Power-Supply Modulation Ratio vs 100-mVPP Supply Noise Frequencies -20 Output Code (LSB) 2k Across VCNTL Figure 50. AVDD Power-Supply Modulation Ratio vs 100-mVPP Supply Noise Frequencies 0.15 0 0 0.2 0.4 0.6 0.8 D054 Figure 54. VCNTL Response vs Time 30 1k Submit Documentation Feedback 1 1.2 1.4 1.6 1.8 Time (Ps) Output Code 0 VCNTL -0.15 2 2.2 2.4 2.6 D055 Figure 55. VCNTL Response vs Time Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 Typical Characteristics (continued) 1.2 1.2 0.6 0.6 Input (V) Input (V) At TA = 25°C, AVDD_1P8 = 1.8 V, AVDD_3P3 = 3.3 V, AVDD_5V = 5 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, accoupled with a 0.1-µF capacitor at INP, 15-nF capacitor to ground at INM, no active termination, VCNTLP = VCNTLM = 0 V, LNA = 18 dB, PGA = 24 dB, LPF filter = 15 MHz, low-noise mode, internal 500-Ω CW feedback resistor, 14-bit ADC resolution, ADC_CLKP and ADC_CLKM = 50-MHz differential, LVDS mode to capture ADC data, input signal frequency fIN = 5 MHz, and output amplitude VOUT = –1 dBFS, unless otherwise noted. Minimum and maximum values are specified across the full temperature range. 0 -0.6 -0.6 -1.2 -1.2 0 0.5 1 1.5 Time (Ps) 2 2.5 3 0 Figure 56. Pulse Inversion Asymmetrical Positive Input 0.5 1 1.5 Time (Ps) 2 2.5 3 Figure 57. Pulse Inversion Asymmetrical Negative Input 600 10000 Positive Overload Negative Overload Average 8000 Positive Overload Negative Overload Average 400 Output Code (LSB) 6000 Output Code (LSB) 0 4000 2000 0 -2000 -4000 -6000 200 0 -200 -400 -8000 -600 -10000 0 1 2 3 4 5 6 Time (Ps) 7 8 9 0 10 D058 3 4 5 6 Time (Ps) 7 8 9 10 11 D059 Figure 59. Device Pulse Inversion Output vs Time (Zoomed) 2000 10000 47 nF 15 nF 8000 47 nF 15 nF 1600 6000 1200 4000 800 Output Code (LSB) Output Code (LSB) 2 VIN = 2 VPP, PRF = 1 kHz, gain = 21 dB VIN = 2 VPP, PRF = 1 kHz, gain = 21 dB, across pulse inversion asymmetrical positive and negative input Figure 58. Device Pulse Inversion Output vs Time 1 2000 0 -2000 -4000 400 0 -400 -800 -6000 -1200 -8000 -1600 -2000 -10000 0 0.5 1 1.5 2 2.5 3 Time (Ps) 3.5 4 4.5 5 1 D060 VIN = large amplitude (50 mVPP) followed by small amplitude (500 µVPP), across INM capacitor Figure 60. Overload Recovery Output vs Time 1.5 2 2.5 3 3.5 Time (Ps) 4 4.5 5 D061 VIN = large amplitude (50 mVPP) followed by small amplitude (500 µVPP), across INM capacitor Figure 61. Overload Recovery Output vs Time (Zoomed) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 31 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com Typical Characteristics (continued) At TA = 25°C, AVDD_1P8 = 1.8 V, AVDD_3P3 = 3.3 V, AVDD_5V = 5 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, accoupled with a 0.1-µF capacitor at INP, 15-nF capacitor to ground at INM, no active termination, VCNTLP = VCNTLM = 0 V, LNA = 18 dB, PGA = 24 dB, LPF filter = 15 MHz, low-noise mode, internal 500-Ω CW feedback resistor, 14-bit ADC resolution, ADC_CLKP and ADC_CLKM = 50-MHz differential, LVDS mode to capture ADC data, input signal frequency fIN = 5 MHz, and output amplitude VOUT = –1 dBFS, unless otherwise noted. Minimum and maximum values are specified across the full temperature range. 10 0 Gain (dB) -10 Normalized K = 0 Normalized K = 1 HPF_CORNER_CHxy = 2 HPF_CORNER_CHxy = 3 HPF_CORNER_CHxy = 4 HPF_CORNER_CHxy = 5 HPF_CORNER_CHxy = 6 HPF_CORNER_CHxy = 7 HPF_CORNER_CHxy = 8 HPF_CORNER_CHxy = 9 HPF_CORNER_CHxy = 10 -20 -30 -40 -50 -60 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Frequency (MHz) 1.6 1.8 2 D062 Across various HPF corner settings Figure 62. Digital High-Pass Filter Gain Response vs Frequency 32 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 9 Detailed Description 9.1 Overview The AFE5818 is a highly-integrated, analog front-end (AFE) solution specifically designed for ultrasound systems in which high performance and higher integration are required. The device integrates a complete time-gaincontrol (TGC) imaging path and a continuous wave Doppler (CWD) path. The device also enables users to select from a variety of power and noise combinations to optimize system performance. The device contains 16 dedicated channels, each comprising a low-noise amplifier (LNA), voltage-controlled attenuator (VCAT), programmable gain amplifier (PGA), low-pass filter (LPF), and either a 14-bit or 12-bit analog-to-digital converter (ADC). At the output of the 16 ADCs is a low-voltage differential signaling (LVDS) serializer to transfer digital data. In addition, the device also contains a continuous wave (CW) mixer. Multiple features in the device are suitable for ultrasound applications (such as active termination, individual channel control, fast power-up and power-down response, programmable clamp voltage control, fast and consistent overload recovery, and digital processing). Therefore, this device brings premium image quality to ultra-portable, handheld systems all the way up to high-end ultrasound systems. In addition, the signal chain of the device can handle signal frequencies as low as 10 kHz and as high as 50 MHz. This broad analog frequency range enables the device to be used in both sonar and medical applications. See the Functional Block Diagram section for a simplified function block diagram. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 33 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com DVDD_1P8 DVDD_1P2 AVDD_1P8 AVDD_5V AVDD_3P3 9.2 Functional Block Diagram VCM CM_BYP1 Reference Voltage, Current Generator CM_BYP2 VHIGH1 VHIGH2 Programmable Active Termination ACT1 INP1 VCAT 0 dB to -40 dB LNA INM1 LPF 10, 15, 20, 30, 35, and 50 MHz PGA 24 dB, 30 dB ADC 1 VNCTL CW Mixer LVDS CW_CH1 DOUTP1 DOUTM1 16x16 CrossPoint SW CW_CLOCK DOUTP2 Programmable Active Termination DOUTM2 INM2 LPF 10, 15, 20, 30, 35, and 50 MHz PGA 24 dB, 30 dB ADC 2 VCNTL CW_CH2 CW Mixer 16x16 CrossPoint SW CW_CLOCK LVDS Outputs VCAT 0 dB to -40 dB LNA LVDS Serializer Analog Inputs INP2 Digital Processing (Optional) ACT2 DOUTP16 DOUTM16 FCLKP FCLKM DCLKP DCLKM Programmable Active Termination ACT16 INP16 VCAT 0 dB to -40 dB LNA INM16 LPF 10, 15, 20, 30, 35, and 50 MHz PGA 24 dB, 30 dB ADC 16 VCNTL CW Mixer CW_CH16 Conversion Clock 16x16 CrossPoint SW CW_CLOCK VCNTL CW_CLOCK CW Clock CLKM_16x Clock Generator CW_CH15 CW_CH16 CW_CH1 CW_CH2 VCNTRL Block CLKP_16x Serial Interface SYNC Generator SDOUT 16 Phase Generator CLKP_1x CLKM_1x SEN SDIN SCLK RESET PDN_GBL PDN_FAST TX_TRIG ADC_CLKP ADC_CLKM VCNTLM VCNTLP DVSS AVSS Summing Amplifier CW_IP_OUTP, CW_IP_OUTM, CW_QP_OUTP, CW_QP_OUTM, ADC Clock or System Clock 34 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 9.3 Feature Description 9.3.1 Low-Noise Amplifier In many high-gain systems, a low-noise amplifier is critical to achieve overall performance. The device uses new proprietary architecture and a bipolar junction transistor (BJT) input transistor to achieve exceptional low-noise performance when operating on a low-quiescent current. 9.3.1.1 Input Signal Support The LNA takes a single-ended input signal and converts it to a differential output signal that is configurable for programmable gains of 24 dB, 18 dB, and 12 dB. The differential output signal has an input-referred noise of 0.63 nV/√Hz, 0.70 nV/√Hz, and 0.9 nV/√Hz, respectively, across the different gain modes. The LNA supports a maximum linear differential output swing of 4 VPP across all gain settings. Therefore, depending on the LNA gain, the maximum linear input swing support changes from 250 mVPP, 500 mVPP, and 1 VPP, for LNA gains of 24 dB, 18 dB, and 12 dB, respectively. 9.3.1.2 Input Circuit The LNA input pin (INPx) is internally biased at approximately 2.2 V. AC couple the input signal to the INPx pin with an adequately-sized capacitor, CIN. TI recommends using a 0.1-μF capacitor for CIN. Similarly, the active termination pin is internally biased at 1.5 V. TI recommends connecting a 1-µF capacitor (CACT) from the active termination pin (ACTx) to the INP capacitor, as shown in Figure 63. AFE CLAMP CACT ACTx CIN INPx CBYPASS INMx Input LNAx Optional Diodes DC Offset Correction S0498-01 Figure 63. Device Input Circuit 9.3.1.3 LNA High-Pass Filter To reject an unwanted low-frequency leakage signal from the transducer and to achieve low dc offset drift from the device, the AFE5818 incorporates a dc offset correction circuit for each amplifier stage; see Figure 63. This circuit extracts the low-frequency component from the LNA output, which is then fed back to the LNA complementary input for low-frequency signal rejection. Afterwards, this feedback circuit functions as a high-pass filter (HPF). The effective corner frequency of the HPF is determined by the CBYPASS capacitor connected at the INMx pin of the device. The corner frequency is lower with larger CBYPASS capacitors. A large capacitor (such as 1 μF) can be used for setting the low corner frequency (< 2 kHz) of the LNA dc offset correction circuit. For stable operation, the minimum value of the CBYPASS capacitor that is supported by device is 15 nF. To disable this HPF, set the LNA_HPF_DIS register bit to 1. Note that disabling this HPF results in a large dc offset at the device output. Also, for a given INMx capacitor, the corner frequency of the HPF can be programmed using the LNA_HPF_PROG bit. Table 1 lists the HPF corner frequency for any arbitrary CBYPASS capacitor connected at the INMx pin across various LNA_HPF_PROG bit settings. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 35 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com Feature Description (continued) Table 1. LNA HPF Corner Frequency LNA_HPF_PROG (Register 203, Bits 3-2) HPF CORNER WITH 15-nF CAPACITOR CONNECTED AT INMx PIN HPF CORNER WITH CBYPASS CAPACITOR CONNECTED AT INMx PIN 00 100 kHz 100 kHz × (15 nF / CBYPASS) 01 50 kHz 50 kHz × (15 nF / CBYPASS) 10 200 kHz 200 kHz × (15 nF / CBYPASS) 11 150 kHz 150 kHz × (15 nF / CBYPASS) The LNA HPF corner frequency can be reduced by 3X by setting the RED_LNA_HPF_3X (register 205, bit 8) bit to 1. For instance, if the INMx capacitor is 15 nF, the LNA_HPF_PROG bits are set to 01, and RED_LNA_HPF_3X is set to 1, then the LNA HPF corner frequency is given by 50 kHz / 3 = 16.6 kHz. Figure 28 and Figure 29 illustrate the low-frequency noise for various LNA_HPF_PROG, RED_LNA_HPF_3X, and INM capacitor combinations. 9.3.1.4 LNA Input Impedance In ultrasound applications, signal reflection exists as a result of long cables between the transducer and system. This reflection results in extra ringing added to echo signals in PW mode. This ringing effect can degrade the axial resolution, which depends on the echo signal length. Therefore, either passive termination or active termination is preferred if good axial resolution is desired. Figure 64 shows three termination configurations: no termination, active termination, and passive termination. Rs LNA (a) No Termination Rf Rs LNA (b) Active Termination Rs Rt LNA (c) Passive Termination S0499-01 Figure 64. Termination Configurations 36 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 Under the no termination configuration, the input impedance of the device is approximately 6 kΩ (8 KΩ // 20 pF) at 1 MHz. Passive termination requires an external termination resistor (Rt), which contributes to additional thermal noise. The LNA supports active termination with programmable values, as shown in Figure 65. 450Ω 900Ω 1800Ω ACTx 3600Ω 4500Ω INPx Input INMx LNAx AFE S0500-01 Figure 65. Active Termination Implementation The device has four pre-settings: 50 Ω, 100 Ω, 200 Ω, and 400 Ω, which are configurable through the registers. Other termination values can be realized by setting the termination switches shown in Figure 65. The ACT_TERM_IND_RES register (register 196, bits 4-0) is used to enable these switches. The input impedance of the LNA under the active termination configuration approximately follows Equation 1: ZIN = Rf / /CIN / /RIN AnLNA 1+ 2 where: • RIN (8 kΩ) and CIN (20 pF) are the input resistance and capacitance of the LNA, respectively. (1) Table 75 lists the LNA RINs under different LNA gains. System designers can achieve fine tuning for different probes. Therefore, ZIN is frequency dependent and decreases as frequency increases; see Figure 9. This rollingoff effect does not greatly affect system performance because 2 MHz to 10 MHz is the most commonly-used frequency range in medical ultrasound applications. Active termination can be applied to both CW and TGC modes; however, resulting from NF concerns, CW mode can use no termination mode. The flexibility of the impedance configuration is of great benefit because each ultrasound system includes multiple transducers with different impedances. Figure 36, Figure 37, Figure 38, Figure 39, and Figure 40 illustrate the noise frequency (NF) under different termination configurations. All these NF plots indicate that no termination achieves the best noise figure. However, active termination adds less noise than passive termination. Thus, termination topology must be carefully selected based on each scenario in an ultrasound application. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 37 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 9.3.1.5 LNA Gain Switch Response The LNA gain is programmable through the LNA_GAIN_GBL (register 196, bits 14-13) SPI registers. The gain switching time depends on the SPI speed as well as the LNA gain response time. During switching, glitches can occur and sometimes appear as artifacts in images. In addition, the signal chain requires approximately 14 µs to settle after the LNA gain change. Thus, the LNA gain switching may not be preferred when switching time or settling time for the signal chain is limited. Note that a gain switch also changes the voltage level of clamping diodes; therefore, the setting time of the clamp circuit must be considered. 9.3.1.6 LNA Noise Contribution The noise specification is critical for the LNA and determines the dynamic range of the entire system. The device LNA achieves low power, an exceptionally low-noise voltage of 0.63 nV/√Hz, and a low-current noise of 2.7 pA/√Hz. Typical ultrasonic transducer impedance (Rs) varies from tens of ohms to several hundreds of ohms. Voltage noise is the dominant noise in most cases; however, the LNA current noise flowing through the source impedance (Rs) generates additional voltage noise. Total LNA noise can be computed with Equation 2. 2 2 LNA _ Noise total = VLNAnoise + R2s ´ ILNAnoise (2) The device achieves a low noise figure (NF) over a wide range of source resistances; see Figure 36, Figure 37, Figure 38, Figure 39, and Figure 40. 9.3.1.7 LNA Overload Recovery To avoid any image artifacts in an ultrasound system, the device must offer consistent and fast overload recovery response. In order to achieve this response, a clamping circuit is used on the active termination path; see Figure 63 to create a low-impedance path when an overload signal is detected by the device. The clamp circuit limits large input signals at the LNA inputs and improves the overload recovery performance. The clamp level can be automatically set to 350 mVPP, 600 mVPP, or 1.15 VPP, depending on the LNA gain settings when the INPUT_CLAMP_LVL register (register 196, bits 10-9) is set to 00. Other clamp voltages (such as 1.15 VPP, 0.6 VPP, and 1.5 VPP) are also achievable by setting different combinations of the INPUT_CLAMP_LVL bits. This clamping circuit is also designed to obtain good pulse inversion performance and reduce the affect of asymmetrical inputs. For very large overload signals (> 6 dB of the linear input signal range), TI recommends using back-to-back Schottky clamping diodes at the input to limit the amplitude of the input signal. 9.3.2 Voltage-Controlled Attenuator The voltage-controlled attenuator is designed to have a linear-in-dB attenuation characteristic (that is, the average attenuation in dB; see Figure 3) that is constant for each equal increment of the control voltage (VCNTL = VCNTLP – VCNTLM). In the device, a differential control structure is used to reduce common-mode noise. However, a single-ended control voltage is also supported. A simplified attenuator structure is illustrated in Figure 66 and Figure 67 for analog and digital structures, respectively. A1 - A7 Attenuator Stages Attenuator Input RS Attenuator Output Q1 VB A1 Q2 A1 C1 V1 Q3 A1 C2 V2 Q4 A1 C3 V3 Q5 A1 C4 V4 Q6 A1 C5 V5 Q7 A1 C6 V6 C7 V7 VCNTL Control Input C1 - C8 Clipping Amplifiers Figure 66. Simplified Voltage-Controlled Attenuator (Analog Structure) 38 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 RS Attenuator Input Attenuator Output Q1 Q2 Q3 Q4 Q5 SW5 SW6 Q6 Q7 VB SW1 SW2 SW3 SW4 SW7 VHIGH Figure 67. Simplified Voltage-Controlled Attenuator (Digital Structure) The attenuator is essentially a variable voltage divider that consists of the series input resistor (RS) and seven shunt field-effect transistors (FETs) placed in parallel and controlled by sequentially activated clipping amplifiers (A1 through A7). VCNTL is the effective difference between VCNTLP and VCNTLM. Each clipping amplifier can be understood as a specialized voltage comparator with a soft transfer characteristic and well-controlled output limit voltage. Reference voltages V1 through V7 are equally spaced over the 0-V to 1.5-V control voltage range. As control voltage increases through the input range of each clipping amplifier, the amplifier output rises from a voltage where the FET is nearly off to VHIGH where the FET is completely on. As each FET approaches its onstate and the control voltage continues to rise, the next clipping amplifier and FET combination takes over for the next portion of the piecewise linear attenuation characteristic. Thus, low control voltages have most of the FETs turned off, producing minimum signal attenuation. Similarly, high control voltages turn the FETs on, leading to a maximum signal attenuation. Therefore, each FET functions to decrease the shunt resistance of the voltage divider formed by RS and the parallel FET network. Even though splitting the control voltage into seven segments achieves the full attenuation through different setoff transistors, the gain curve across the VCNTL voltage slightly deviates from the ideal dB-linear curve. The typical ripple is in the order of ±0.5 dB. The typical gain range for this VCAT is approximately 40 dB, and this gain range is independent of the LNA and PGA gain settings. The TGC gain curve is inversely proportional to the voltage difference between VCNTLP and VCNTLM. The maximum attenuation (minimum channel gain) of the TGC gain curve appears at VCNTLP – VCNTLM = 1.5 V, and minimum attenuation (maximum channel gain) of the TGC gain curve occurs at VCNTLP – VCNTLM = 0 V. The total channel gain for an 18-dB LNA gain and a 24-dB PGA gain setting, for different VCNTL values, is illustrated in Figure 2. When the device operates in CW mode, the attenuator stage remains connected to the LNA outputs. Therefore, powering down the VCA is recommended using the PDWN_VCA_PGA (register 197, bit 12) register bit. In this case, the VCNTLP and VCNTLM voltage does not matter. 9.3.2.1 Digital TGC Additionally, a digitally-controlled TGC mode is implemented to achieve better phase-noise performance in the device. The attenuator can be controlled digitally instead of by the analog control voltage, VCNTL. This mode can be set by the EN_DIG_TGC (register 203, bit 7) register bit. The variable voltage divider is implemented as a fixed series resistance and a FET is implemented as the shunt resistance. Each FET can be turned on by connecting the SW[7:1] switches. Turning on each of these switches provides approximately 6 dB of attenuation. This attenuation can be controlled by the DIG_TGC_ATTENUATION (register 203, bits 6-4) register bits. This digital control feature can eliminate the noise from the VCNTL circuit and provide better SNR and phase noise for the TGC path. This digital TGC can be used for PW Doppler or color Doppler modes to achieve better performance than analog TGC. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 39 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 9.3.2.2 Control Voltage Input As previously mentioned, VCNTLP and VCNTLM can be driven by either a differential or a single-ended signal. For single-ended operation, VCNTLM can be grounded and VCNTLP can be swept from 0 V to 1.5 V. The TGC gain profile for the single-ended VCNTL is as shown in Figure 68a. For differentially driving VCNTL, VCNTLP must always be kept higher than VCNTLM with a typical common-mode of 0.75 V, as shown in Figure 68b. 1.5 V VCNTLP VCNTLM = 0 V X + 40 dB TGC Gain X dB (a) Single-Ended Input at VCNTLP 1.5 V VCNTLP 0.75 V VCNTLM 0V X + 40 dB TGC Gain X dB (b) Differential Inputs at VCNTLP and VCNTLM Figure 68. VCNTLP and VCNTLM Configurations The VCNTL pins are high-impedance pins, and the VCNTL pins of multiple devices can be connected in parallel with no significant loading effect. When the voltage level (VCNTLP, VCNTLM) is above 1.5 V or below 0 V, the attenuator continues to operate at its maximum attenuation level or minimum attenuation level, respectively. Limiting the voltage from –0.3 V to 2 V is recommended. The VCNTL inputs have an approximate bandwidth of 800 kHz. This wide bandwidth, although useful in many applications (such as fast VCNTL response), can also allow high-frequency noise to modulate the gain control input and finally affect the Doppler performance. In practice, this modulation can be avoided by additional external filtering (RVCNTL and CVCNTL) at the VCNTLM and VCNTLP, pins as Figure 104 illustrates. However, the external filter cutoff frequency cannot be kept too low, which results in a low gain response time. Without an external filter on the VCNTLP, VCNTLM pins, the gain control response time typically requires less than 1 μs, as indicated in Figure 54. 40 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 Noise at the VCNTL pins must be low enough to obtain good system performance because this noise is correlated across channels. Figure 69 shows the allowed noise on the VCNTL pins for different channel systems. 10 16 Channels 32 Channels 64 Channels 128 Channels 192 Channels 9 Noise (nV/—Hz) 8 7 6 5 4 3 2 1 0 1 2 3 4 5 7 10 20 30 50 100 200 Frequency (kHz) 500 1000 5000 D063 Figure 69. Allowed Noise on the VCNTL Signal Across Frequency and Different Channels Typical VCNTLM and VCNTLP signals are generated by an 8-bit to 12-bit, 10-MSPS, digital-to-analog converter (DAC) and a differential operation amplifier. TI’s DACs, such as the TLV5626, DAC7821. Differential amplifiers with output common-mode voltage control (that is, the THS4130 and OPA1632) can connect the DAC to the VCNTLM and VCNTLP pins. The buffer amplifier can also be configured as an active filter to suppress low frequency noise. The VCNTLM and VCNTLP circuit achieve low noise in order to prevent the VCNTLM and VCNTLP noise from being modulated to RF signals. VCNTLM and VCNTLP noise is recommended to be below 25 nV/√Hz at 1 kHz and 5 nV/√Hz at 50 kHz. For more information, see the THS413x data sheet and application report Design for a Wideband Differential Transimpedance DAC Output (SBAA150). 9.3.2.3 Voltage Attenuator Noise The voltage-controlled attenuator noise follows a monotonic relationship to the attenuation coefficient. At higher attenuation the input-referred noise is higher, and vice-versa. The attenuator noise is then amplified by the PGA and becomes the noise floor at the ADC input. In the high attenuation operating range of the attenuator (that is, when VCNTL is high), the attenuator input noise can exceed the LNA output noise. The attenuator then becomes the dominant noise source for the following PGA stage and ADC. Therefore, minimize the attenuator noise compared to the LNA output noise. The device attenuator is designed for achieving very low noise even at high attenuation (low channel gain) and realizing better SNR of near-field imaging in ultrasound systems. The inputreferred noise for different attenuations are listed in Table 2. Table 2. Voltage-Controlled Attenuator Noise vs Attenuation ATTENUATION (dB) ATTENUATOR INPUT-REFERRED NOISE (nV/√Hz) –40 10.5 –36 10 –30 9 –24 8.5 –18 6 –12 4 –6 3 0 2 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 41 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 9.3.3 Programmable Gain Amplifier (PGA) After the voltage-controlled attenuator, a programmable gain amplifier can be configured as 24 dB or 30 dB with a constant input-referred noise of 1.75 nV/√Hz. The PGA structure consists of a differential voltage-to-current (V2I) converter with programmable gain, clamping circuits, a transimpedance amplifier (I2V) with a programmable third-order low-pass filter, and a dc offset correction circuit. The simplified PGA block diagram is shown in Figure 70. Voltage Clamp Current Clamp To ADC From Attenuator I2V LPF V2I Voltage Clamp Current Clamp DC Offset Correction Loop Figure 70. Simplified Block Diagram of the PGA 9.3.3.1 PGA Clamp The PGA consists of two clamp circuits, positioned as shown in Figure 70. These clamps limit the amplitude of the overloaded signal and therefore provide better overload recovery performance. An input-to-voltage (I2V) block in the PGA supports a maximum output swing of 2 VPP, which means that the maximum allowed signal amplitude supported at the voltage-to-input (V2I) block input is 125 mVPP (for a PGA gain = 24 dB) or 62.5 mVPP (for a PGA gain = 30 dB). If the input signal amplitude of the V2I bock is much higher than the allowable range, then the V2I input can be clamped using a voltage clamp as shown in Figure 70. This voltage clamp is disabled by default and can be enabled by using the V2I_CLAMP (register 205, bit 13) register bit. A current clamp is at the output of the V2I block, as shown in Figure 70, to further limit the overload signal amplitude. This current clamp can be programmed through the PGA_CLAMP_DIS (register 195, bit 7) and PGA_CLAMP_LVL (register 195, bit 6) register bits. Note that in low-power and medium-power modes, the current clamp is disabled for power savings if PGA_CLAMP_DIS (register 195, bit 7) = 0. This current clamp helps obtain a better overload recovery response. Without enabling this current clamp, at a 0.5-V VCNTL, the device shows a standard deviation of 4 LSBs at the output signal immediately after the overload. However, with the current clamp enabled, the standard deviation approaches 3.2 LSBs, meaning that the device requires less time to reach stable output. Also note that when the PGA output levels are greater than –2 dBFS and the current clamp is enabled, there is a degradation of approximately 3 dB to 5 dB in HD3 performance. If the V2I block input is massively overloaded, the output of the I2V block can become saturated even if the voltage and current clamp described previously is enabled. When the I2V block becomes saturated, higher-order harmonics are generated that are aliased back to signal bandwidth after sampling. To avoid this undesirable V2I output saturation, a current clamp can be programmed to –6 dBFs, using the PGA_CLAMP_HALF bit (register 205, bit 15). 42 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 9.3.3.2 Low-Pass Filter (LPF) The current from the V2I is fed to a programmable transimpedance amplifier, which also functions as a low-pass filter (LPF). The LPF is designed as a differential, active, third-order filter with Butterworth characteristics and a typical 18-dB per octave roll-off. Programmable through the serial interface, the –1-dB frequency corner can be set to 10 MHz, 15 MHz, 20 MHz, 30 MHz, 35 MHz, or 50 MHz. The filter bandwidth is set for all channels simultaneously. When very low bandwidth is desired (usually when suppressing higher order harmonics to a very low value), a 5-MHz filtering mode can be enabled using the SUPRESS_HIGHER_HARMONICS (register 205, bit 14) bit. However, enabling this mode can cause higher gain variation across devices when compared to other filter corner modes. 9.3.3.3 High-Pass Filter (HPF) A selectable dc offset correction circuit is implemented in the PGA as well. This correction circuit is similar to the one used in the LNA. This circuit extracts the dc component of the PGA outputs, which are fed back to the PGA complimentary inputs for dc offset correction. This dc offset correction circuit also has a high-pass response with a cutoff frequency of 80 kHz. This HPF is enabled by default and can be disabled by using the PGA_HPF_DIS (register 195, bit 4) bit. 9.3.3.4 Noise Low input noise is always preferred in a PGA and its noise contribution must not degrade the ADC SNR too much after the attenuator. The PGA is designed as a 24-dB or 30-dB gain with a constant input-referred noise of 1.75 nV/√Hz. The LNA noise dominates at minimum attenuation (used for small input signals), and the PGA and ADC noise dominate at maximum attenuation (large input signals). Thus, a 24-dB PGA gain achieves better SNR as long as the amplified signals can exceed the noise floor of the ADC. 9.3.4 Analog-to-Digital Converter (ADC) The device supports a high-performance, 14-bit ADC that achieves 72-dBFS SNR. This ADC ensures excellent SNR at low-chain gain. The ADC can operate at maximum speeds of 65 MSPS and 80 MSPS, providing a 14-bit and a 12-bit output, respectively. The low-voltage differential signaling (LVDS) outputs of the ADC enable a flexible system integration that is desirable for miniaturized systems. In the following sections, full description of all inputs and outputs of the ADC with different configurations are provided along with suitable examples. 9.3.4.1 System Clock Input The 16 channels on the device operate from a single clock input. To ensure that the aperture delay and jitter are the same for all channels, the device uses a clock tree network to generate individual sampling clocks for each channel. The clock lines for all channels are matched from the source point to the sampling circuit for each of the 16 internal ADCs. The delay variation is described by the aperture delay parameter of the Output Interface Timing Characteristics table. Variation over time is described by the aperture jitter parameter of the Output Interface Timing Characteristics table. This system clock input can be driven differentially (sine wave, LVPECL, or LVDS) or single-ended (LVCMOS). The device clock input has an internal buffer and clock amplifier (see Figure 71) which is enabled or disabled automatically, depending on the type of clock provided (auto-detect feature). Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 43 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com AVDD_1P8 0.7 V VCM 100 pF 5 kQ 5 kQ CLKP 6 pF 6 pF CLKM Figure 71. Internal Clock Buffer for Differential Clock Mode If the preferred clocking scheme for the device is single-ended, connect the CLKM pin to ground (in other words, short CLKM directly to AVSS, as shown in Figure 72). In this case, the auto-detect feature shuts down the internal clock buffer and the device automatically goes into a single-ended clock input. Connect the single-ended clock source directly (without decoupling) to the CLKP pin, which is the only device clock input available because CLKM is connected to ground. Therefore, TI recommends using low-jitter, square signals (LVCMOS levels, 1.8-V amplitude) to drive the ADC (see technical brief, Clocking High-Speed Data Converters, SLYT075 for further details). CMOS Clock Input CLKP CLKM Figure 72. Single-Ended Clock Driving Circuit 44 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 For single-ended sinusoidal clocks, or for differential clocks (such as differential sine wave, LVPECL, LVDS, and so forth), enable the clock amplifier with the connection scheme shown in Figure 73. The 10-nF capacitor used to couple the clock input is as shown in Figure 73. This same scheme applies when the clock is single-ended but the clock amplitude is either small or its edges are not sharp (for instance, with a sinusoidal single-ended clock). In this case, the input clock signal can be connected with a capacitor to CLKP (as in Figure 73) and connect CLKM to ground through a capacitor (that is, ac-coupled to AVSS). If a transformer is used with the secondary coil floating (for instance, to convert from single-ended to differential), the transformer can be connected directly to the clock inputs without requiring the 10-nF series capacitors. 10 nF CLKP Differential Sine Wave or PECL or LVDS Clock Signal CLKM 10 nF Figure 73. Differential Clock Driving Circuit Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 45 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 9.3.4.2 System Clock Configuration for Multiple Devices To ensure that the aperture delay and jitter are the same for all channels, the device uses a clock tree network to generate individual sampling clocks for each channel. For all channels, the clock is matched from the source point to the sampling circuit of each of the eight internal devices. The variation on this delay is described in the Aperture Delay parameter of the Output Interface Timing Characteristics table. Variation is described by the aperture jitter parameter of the Output Interface Timing Characteristics table. The system clock input can be driven by differential clocks (sine wave, LVPECL, or LVDS) or single-ended clocks (LVCMOS). In the single-ended case, TI recommends the use of low-jitter square signals (LVCMOS levels, 1.8-V amplitude). See technical brief, Clocking High-Speed Data Converters, SLYT075 for further details on the theory. The jitter cleaners CDCM7005, CDCE72010, or LMK048X series are suitable to generate the system clock and ensure high performance for the 14-bit device resolution. Figure 74 shows a clock distribution network. FPGA Clock, Noisy Clock n × (5 MHz to 100 MHz) TI Jitter Cleaner LMK048X CDCE72010 CDCM7005 5-MHz to 100-MHz ADC CLK CDCLVP1208 LMK0030X LMK01000 The CDCE72010 has 10 outputs DUT DUT DUT DUT DUT DUT DUT DUT 8 Synchronized DUT System CLKs Figure 74. System Clock Distribution Network 46 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 9.3.4.3 LVDS Interface The device supports an LVDS output interface in order to transfer device digital data serially to an FPGA. The device has a total of 18 LVDS output lines. One of these pairs is a serial data clock, another pair is a data framing clock, and the remaining 16 pairs are dedicated for data transfer. A graphical representation of the LVDS output is shown in Figure 75. LVDS Buffer DOUTP1 DOUTM1 DOUTP2 DOUTM2 Digital Output DOUTP16 DOUTM16 DCLKP DCLKM Serial Clock FCLKP FCLKM Frame Clock Figure 75. LVDS Output Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 47 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 9.3.4.3.1 LVDS Buffer The equivalent circuit of each LVDS output buffer is shown in Figure 76. The buffer is designed for an output impedance of 100 Ω (ROUT). The differential outputs can be terminated at the receiver end by a 100-Ω termination. The buffer output impedance functions like a source-side series termination. By absorbing reflections from the receiver end, the buffer output impedance helps improve signal integrity. Note that this internal termination can neither be disabled nor its value changed. Low +0.4 V High Device OUTP 0.4 V High 1.03 V Low External 100- Load ROUT OUTM Switch impedance is nominally 50 (r10%). Figure 76. LVDS Output Circuit 48 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 9.3.4.3.2 LVDS Data Rate Modes The LVDS interface supports two data rate modes, as described in this section. Figure 77 shows the Nomenclatures used in LVDS timing diagrams DCLKP Bit Clock DCLKM t t su h t t su h CH1 out DN + 1 Dn Output Data Pair Figure 77. LVDS Timing Nomenclature 9.3.4.3.2.1 1X Data Rate Mode In 1X data rate mode, each LVDS output carries data from a single ADC. Figure 78 and Figure 79 show the output data, serial clock, and frame clock LVDS lines for the 14-bit and 12-bit 1X mode, respectively. Input Signal Sample N Sample N+Cd+1 Sample N+Cd TA TA Cd Clock Cycles Latency Input Clock (CLKIN) Frequency = fCLKIN T tPDI Frame Clock (FCLK) Frequency = fCLKIN Bit Clock (DCLK) Frequency = 7 x fCLKIN Output Data (CHn OUT) Data Rate = 14 x fCLKIN 1 (12) 0 (13) 13 (0) 12 (1) 11 (2) 10 (3) 9 (4) 8 (5) 7 (6) 6 (7) 5 (8) 4 (9) 3 (10) 2 (11) 1 (12) 0 (13) 13 (0) 12 (1) 11 (2) 10 (3) 9 (4) Sample N-Cd 8 (5) 7 (6) 6 (7) 5 (8) 4 (9) 3 (10) 2 (11) 1 (12) 0 (13) 13 (0) 12 (1) 11 (2) 10 (3) 9 (4) 8 (5) Sample N-1 7 (6) 6 (7) 5 (8) 4 (9) 3 (10) 2 (11) 1 (12) 0 (13) 13 (0) 1 (1 Sample N Data Bit in MSB-First Mode 13 (0) Data Bit in LSB-First Mode (1) K = ADC resolution. Figure 78. 14-Bit, 1X Data Rate Output Timing Specification Sample N Input Signal TA Sample N+Cd+1 Cd Clock Cycles Latency Input Clock (CLKIN) Frequency = fCLKIN tPDI T Frame Clock (FCLK) Frequency = fCLKIN Bit Clock (DCLK) Frequency = 6 x fCLKIN Output Data (CHn OUT) Data Rate = 12 x fCLKIN 1 (10) 0 (11) 11 (0) 10 (1) 9 (2) 8 (3) 7 (4) 6 (5) 5 (6) 4 (7) Sample N-Cd 1 (10) 3 (8) 2 (9) 1 (10) 0 (11) 11 (0) 10 (1) 9 (2) 8 (3) 7 (4) 6 (5) 5 (6) 4 (7) 3 (8) 2 (9) 1 (10) 0 (11) 11 (0) 10 (1) 9 (2) 8 (3) 7 (4) Sample N-1 6 (5) 5 (6) 4 (7) 3 (8) 2 (9) 1 (10) 0 (11) Sample N 11 (0) 10 (1) Sample N+1 Data Bit in MSB-First Mode Data Bit in LSB-First Mode Figure 79. 12-Bit, 1X Data Rate Output Timing Specification Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 49 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 9.3.4.3.2.2 2X Data Rate Mode In 2X data rate mode, only half of the LVDS lines are used to transfer data. Thus, this mode is useful for saving power when lower sampling frequency ranges permit. This mode is enabled with the LVDS_RATE_2X register bit (register 1, bit 14). After enabling this mode, the digital data from two ADCs are transmitted with a single LVDS lane. When compared to the 1X data rate mode, the 2X data rate mode serial clock frequency is doubled, but the frame clock frequency remains the same (for the same serialization factor and ADC resolution). When the frame clock is high, data on DOUT1 corresponds to channel 1, DOUT2 corresponds to channel 3, and so forth. When the frame clock is low, DOUT1 transmits channel 2 data, DOUT2 transmits channel 4 data, and so forth. Figure 80 and Figure 81 show a timing diagram for the 14-bit and 12-bit 2X mode, respectively. Channel and LVDS data line mapping for this mode are listed in Table 3. Note that idle LVDS lines are not powered down by default. To save power, these lines can be powered down using the corresponding power-down bits (PDN_LVDSx). Sample N+Cd Input Signal Sample N+Cd+1 TA tPDI Input Clock (CLKIN) Frequency = fCLKIN T Frame Clock (FCLK) Frequency = fCLKIN Bit Clock (DCLK) Frequency = 14 x fCLKIN utput Data (CHn OUT) Data Rate = 28 x fCLKIN 4 (8) 3 (9) 2 (10) 1 (12) 0 (13) 13 (0) 12 (1) 11 (2) 10 (3) 9 (4) 8 (5) 7 (6) 6 (7) 5 (8) 4 (9) 3 (10) 2 (11) 1 (12) 0 (13) 13 (0) 12 (1) 11 (2) 10 (3) 9 (4) 8 (5) 7 (6) 6 (7) 5 (8) 4 (9) 3 (10) 2 (11) 1 (12) 0 (13) 13 (0) 12 (1) 11 (2) 10 (3) 8 (5) 7 (6) 6 (7) 5 (8) 4 (9) 3 (10) 2 (11) (1 ADC first channel, Sample N+1 ADC second channel, Sample N ADC first channel, Sample N 9 (4) Data Bit in MSB-First Mode 13 (0) Data Bit in LSB-First Mode Figure 80. 14-Bit, 2X Data Rate Output Timing Specification Sample N+Cd Input Signal Sample N+Cd+1 TA tPDI Input Clock (CLKIN) Frequency = fCLKIN T Frame Clock (FCLK) Frequency = fCLKIN Bit Clock (DCLK) Frequency = 12 x fCLKIN Output Data (CHn OUT) Data Rate = 24 x fCLKIN 4 (7) 3 (8) 2 (9) 1 (10) 0 (11) 11 (0) 10 (1) 9 (2) 8 (3) 7 (4) 6 (5) 5 (6) 4 (7) 3 (8) ADC first channel, Sample N 1 (10) 2 (9) 1 (10) 0 (11) 11 (0) 10 (1) 9 (2) 8 (3) 7 (4) 6 (5) 5 (6) 4 (7) 3 (8) ADC second channel, Sample N 2 (9) 1 (10) 0 (11) 11 (0) 10 (1) 9 (2) 8 (3) 7 (4) 7 (4) 6 (5) 5 (6) 4 (7) 3 (8) 2 (9) 1 (10) 0 (11) 11 (0) 10 (1) ADC first channel, Sample N+1 Data Bit in MSB-First Mode Data Bit in LSB-First Mode Figure 81. 12-Bit, 2X Data Rate Output Timing Specification 50 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 Table 3. Channel and ADC Data Line Mapping (2X Rate) CHANNELS MAPPING DOUT1 ADC data for channels 1 and 2 DOUT2 ADC data for channels 3 and 4 DOUT3 ADC data for channels 5 and 6 DOUT4 ADC data for channels 7 and 8 DOUT5 Idle DOUT6 Idle DOUT7 Idle DOUT8 Idle DOUT9 ADC data for channels 9 and 10 DOUT10 ADC data for channels 11 and 12 DOUT11 ADC data for channels 13 and 14 DOUT12 ADC data for channels 15 and 16 DOUT13 Idle DOUT14 Idle DOUT15 Idle DOUT16 Idle Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 51 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 9.3.4.4 ADC Register, Digital Processing Description The ADC has extensive digital processing functionalities that can be used to enhance ADC output performance. The digital processing blocks are arranged as shown in Figure 82. ADC 2 Output Digital Test Patterns 12b, 14b Final Digital Output MUX ADC1 Output Digital Average Default = No Digital Gain Default = 0 Digital HPF Default = No 12b, 14b Digital Offset Default = No Figure 82. ADC Digital Block Diagram 9.3.4.4.1 Digital Offset Digital functionality provides for channel offset correction. Setting the DIG_OFFSET_EN bit to 1 enables the subtraction of the offset value from the ADC output. There are two offset correction modes, as shown in Figure 83. DIG_OFFSET_EN 0 Analog Inputs ADCx Bits 13-0 (0s appended as LSBs when in 12-bit resolutions.) OFFSET_REMOVAL_START_SEL (Register 4, Bit 14) OFFSET_REMOVAL_ START_MANUAL (Register 4, Bit 13) TX_TRIG Pin 0 Start MUX + AUTO_OFFSET_REMOVAL_ ACC_CYCLES (Register 4, Bits 12-9) Accumulator Bits 29-0 MUX 1 Bits 9-0 OFFSET_CHx - Data Output, Bits 13-0 1 OFFSET_REMOVAL_SELF (Register 4, Bit 15) Truncation and Rounding Data Bits Extending Sign Bit to 14 Bits Bits 13-0 1 MUX 0 Bits 13-0 Figure 83. Digital Offset Correction Block Diagram 9.3.4.4.1.1 Manual Offset Correction If the channel offset is known, the appropriate value can be written in the OFFSET_CHx register (bits 13-0, offset for channel x). The offset value programmed in the OFFSET_CHx register (bits 13-0) subtracts out from the ADC output. The offset of each of the 16 ADC output channels can be independently programmed. The same offset value must be programmed into two adjacent offset registers. For instance, when programming the channel 1 offset value 0000011101, write the same offset value of 0000011101 in registers 13 (bits 9-0) and 14 (bits 9-0). 52 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 9.3.4.4.1.2 Auto Offset Correction Mode (Offset Correction using a Built-In Offset Calculation Function) The auto offset calculation module can be used to calculate the channel offset that is then subtracted from the ADC output. To enable the auto offset correction mode, set the OFFSET_REMOVAL_SELF bit to 1. In auto offset correction mode the dc component of the ADC output (assumed to be the channel offset) is estimated using a digital accumulator. The ADC output sample set used by the accumulator is determined by a start time or first sample and number of samples to be used. Figure 83 illustrates the options available to determine the accumulator sample set. A high pulse on the TX_TRIG pin or setting the OFFSET_REMOVAL_START_MANUAL register can be used to determine the accumulator first sample. To set the number of samples, the AUTO_OFFSET_REMOVAL_ACC_CYCLES register (bits 12-9) must be programmed according to Table 4. If a pulse on the TX_TRIG pin is used to set the first sample, additional flexibility in setting the first sample is provided. A programmable delay between the TX_TRIG pulse and first sample can be set by writing to the OFFSET_CORR_DELAY_FROM_TX_TRIG register. The determined offset value can be read out channel wise. Set the channel number in the AUTO_OFFSET_REMOVAL_VAL_RD_CH_SEL register and read the offset value for the corresponding channel in the AUTO_OFFSET_REMOVAL_VAL_RD register. Table 4. Auto Offset Removal Accumulator Cycles AUTO_OFFSET_REMOVAL_ACC_CYCLES (Bits 3-0) NUMBER OF SAMPLES USED FOR OFFSET VALUE EVALUATION 0 2047 1 127 2 255 3 511 4 1023 5 2045 6 4095 7 8191 8 16383 9 32767 10 to 15 65535 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 53 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 9.3.4.4.2 Digital Average The signal-to-noise ratio (SNR) of the signal chain can be further improved by averaging two channels with the AVG_EN register bit (register 2, bit 11). The way data are transmitted on the digital output lines in this mode is described in Table 5. Table 5. Channel and ADC Data Line Mapping (Averaging Enabled) CHANNELS MAPPING DOUT1 Average of channels 1 and 2 DOUT2 Average of channels 3 and 4 DOUT3 Average of channels 5 and 6 DOUT4 Average of channels 7 and 8 DOUT5 Idle DOUT6 Idle DOUT7 Idle DOUT8 Idle DOUT9 Average of channels 9 and 10 DOUT10 Average of channels 11 and 12 DOUT11 Average of channels 13 and 14 DOUT12 Average of channels 15 and 16 DOUT13 Idle DOUT14 Idle DOUT15 Idle DOUT16 Idle NOTE Idle LVDS lines are not powered down by default. To save power, these lines can be powered down using corresponding power-down bits (PDN_LVDSx). The serialization factor must be greater than the ADC resolution to obtain SNR improvement after averaging in 12b resolution. 9.3.4.4.3 Digital Gain To enable the digital gain block, set DIG_GAIN_EN (register 3, bit 12) to 1. When enabled, the gain value for channel x (where x is from 1 to 16) can be set with the register bits for the corresponding channel (GAIN_CHx, bits 15-11). Gain is given as [0 dB + 0.2 dB × GAIN CHx (bits 15-11)]. For instance, if GAIN_CH5 (bits 15-11) = 3, then channel 5 is increased by 0.6-dB gain. GAIN_CHx (bits 15-11) = 31 produces the same effect as GAIN_CHx (bits 15-11) = 30, which sets the gain of channel x to 6 dB. 54 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 9.3.4.4.4 Digital HPF To enable the digital high-pass filter (HPF) of channel 1 to 8 and 9 to 16, set the DIG_HPF_EN_CH1-8 (register 21, bit 0) and DIG_HPF_EN_CH9-16 (register 45, bit 0) register bits to 1, respectively. The HPF_CORNER_CHxy register bits (where xy are 1-4, 5-8, 9-12, or 13-16) control the characteristics of a digital high-pass transfer function applied to the output data, based on Equation 3. These bits correspond to bits 4-1 in registers 21, 33, 45, and 57, respectively (these register settings describe the value of K). The valid values of K are 2 to 10. The digital HPF can be used to suppress low-frequency noise. Table 6 shows the cutoff frequency versus K. 2k Y(n) = [x(n) - x(n - 1) + y(n - 1)] 2k + 1 (3) Table 6. Digital HPF, –1-dB Corner Frequency versus K and fS CORNER FREQUENCY (kHz) CORNER FREQUENCY (k) (HPF_CORNER_CHxy Register) fS = 40 MSPS fS = 50 MSPS fS = 65 MSPS 2 2780 3480 4520 3 1490 1860 2420 4 738 230 1200 5 369 461 600 6 185 230 300 7 111 138 180 8 49 61 80 9 25 30 40 10 12. 15 20 HPF output is mapped to ADC resolution bits either by truncation or a round-off operation. By default, the HPF output is truncated to map to the ADC resolution. To enable the rounding operation to map the HPF output to the ADC resolution, set the HPF_ROUND_ENABLE register bit (register 21, bit 5) to 1. 9.3.5 LVDS Synchronization Operation Different test patterns can be synchronized on the LVDS serialized output lines to help set and program the FPGA timing that receives the LVDS serial output. Of these test patterns, the ramp, toggle, and pseudo-random sequence (PRBS) test patterns can be reset or synchronized by providing a synchronization pulse on the TX_TRIG pin or by setting and resetting a specific register bit. The synchronization pulse on the TX_TRIG pin must meet the setup and hold time constraints with respect to the system clock, as shown in Figure 84. t_setup = 3.6 ns t_hold = 1 ns System Clock TX_TRIG Figure 84. Setup and Hold Time Constraint for the TX_TRIG Signal The PRBS_SYNC register bit (register 4, bit 7) can be used to synchronize the PRBS sequence. SCLK must be synchronous with the system clock and must meet the setup and hold time constraints with respect to the system clock, as shown in Figure 85. t_setup = 2.5 ns t_hold = 5 ns System Clock SCLK Figure 85. Setup and Hold Time Constraints on SCLK for Using Software, SOFTWARE_RESET, and RESET Functions Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 55 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 9.3.6 Continuous-Wave (CW) Beamformer The continuous-wave Doppler is a key function in mid-end to high-end ultrasound systems. Compared to the TGC mode, the CW path must handle high dynamic range along with strict phase noise performance. CW beamforming is often implemented in the analog domain because of the strict requirements. Multiple beamforming methods are implemented in ultrasound systems, including a passive delay line, active mixer, and passive mixer. Among these approaches, the passive mixer achieves optimized power and noise. This mixer satisfies the CW processing requirements (such as wide dynamic range, low phase noise, and accurate gain and phase matching). A simplified CW path block diagram and an in-phase or quadrature (I/Q) channel block diagram are illustrated in Figure 86 and Figure 87, respectively. Each CW channel includes an LNA, a voltage-to-current converter, a switch-based mixer, a shared summing amplifier with a low-pass filter, and clocking circuits. NOTE The local oscillator inputs of the passive mixer are cos (ωt) for the I channel and sin (ωt) for the Q channel, respectively. Depending on the application-specific CW Doppler complex FFT processing, swapping the I and Q channels in either the field-programmable gate array (FPGA) or digital signal processor (DSP) can be required in order to obtain correct blood flow direction. All blocks include well-matched, in-phase, quadrature channels to achieve good image frequency rejection as well as beamforming accuracy. As a result, the image rejection ratio from an I/Q channel is better than –46 dBc, which is desired in ultrasound systems. 56 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 I-CLK LNA1 I-Channel Voltage-to-Current Converter Q-Channel Q-CLK Sum Amp with LPF 1 × fcw CLK I-Channel Clock Distribution Circuits Q-Channel N × fcw CLK Sum Amp with LPF I-CLK LNA16 Voltage-to-Current Converter I-Channel Q-Channel Q-CLK Figure 86. Simplified Block Diagram of the CW Path Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 57 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com ACT1 Mixer Clock 1 500 IN1 LNA1 Input 1 INM1 Cext 500 ACT2 Mixer Clock 2 Rint, Rext 500 CW_OUTP IN2 LNA2 Input 2 CW_AMPINM 10 Ÿ 10 Ÿ INM2 CW_AMPINP I2V Sum Amp CW_OUTM 500 Rint, Rext Cext ACT16 Mixer Clock 16 500 IN16 CW I- or Q- Channel Structure LNA16 Input 16 INM16 500 NOTE: The 10-Ω to 15-Ω resistors at CW_AMPINM and CW_AMPINP result from the internal device routing and can create slight attenuation. Figure 87. A Complete In-Phase or Quadrature-Phase Channel The CW mixer in the device is passive and switch based; the passive mixer adds less noise than active mixers. The CW mixer achieves good performance at low power. Figure 88 and the calculations of Equation 4 describe the principles of the mixer operation. The LO(t) is square-wave based and includes odd harmonic components. Vi(t) Vo(t) LO(t) Figure 88. Mixer Operation Block Diagram where: • 58 Vi(t), Vo(t), and LO(t) are the input, output, and local oscillator (LO) signals for a mixer, respectively. Submit Documentation Feedback (4) Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 From Equation 4, the third- and fifth-order harmonics from the LO can interface with the third- and fifth-order harmonic signals in the Vi(t) or the noise around the third- and fifth-order harmonics in the Vi(t). Therefore. the mixer performance is degraded. In order to eliminate this side effect resulting from the square-wave demodulation, a proprietary harmonic suppression circuit is implemented in the device. The third- and fifth-order harmonic components from the LO can be suppressed by over 12 dB. Thus, the LNA output noise around the third- and fifth-order harmonic bands are not down-converted to base band. Hence, a better noise figure is achieved. The conversion loss of the mixer is approximately –4 dB, which is derived from 20log10 2 / π. The mixed current outputs of the 16 channels are summed together internally. An internal low-noise operational amplifier is used to convert the summed current to a voltage output. The internal summing amplifier is designed to accomplish low power consumption, low noise, and ease of use. CW outputs from multiple devices can be further combined on the system board to implement a CW beamformer with more than 16 channels. Multiple clock options are supported in the device CW path. Two CW clock inputs are required: an N × ƒcw clock and a 1 × ƒcw clock, where ƒcw is the CW transmitting frequency and N can be 16, 8, 4, or 1. The most convenient system clock solution can be selected for the device. In the 16 × ƒcw and 8 × ƒcw modes, the thirdand fifth-order harmonic suppression feature can be supported. Thus, the 16 × ƒcw and 8 × ƒcw modes achieve better performance than the 4 × ƒcw and 1 × ƒcw modes. 9.3.6.1 16 × ƒcw Mode The 16 × ƒcw mode achieves the best phase accuracy compared to other modes. This mode is the default mode for CW operation. In this mode, 16 × ƒcw and 1 × ƒcw clocks are required. 16 × fcw generates LO signals with 16 accurate phases. Multiple devices can be synchronized by the 1 × ƒcw (that is, LO signals in multiple AFEs can have the same starting phase). The phase noise spec is critical only for 16X clock. 1X clock is for synchronization only and doesn’t require low phase noise. Please see the phase noise requirement in the section of application information. The top-level clock distribution diagram is shown in Figure 89. Each mixer clock is distributed through a 16 × 16 cross-point switch. The inputs of the cross-point switch are 16 different phases of the 1X clock. TI recommends aligning the 1 × ƒcw and 16 × ƒcw clocks; see Figure 90. fIN 16X Clock INV D Q fIN 1X Clock Fin 1X Clock 16-Phase Generator 1X Clock Phase 0º 1X Clock Phase 22.5º SPI 1X Clock Phase 292.5º 1X Clock Phase 315º 1X Clock Phase 337.5º 16:8 Crosspoint Switch Mixer 1 1X Clock Mixer 2 1X Clock Mixer 3 1X Clock Mixer 14 1X Clock Mixer 15 1X Clock Mixer 16 1X Clock Figure 89. CW Clock Distribution Scheme Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 59 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com Figure 90. 1X and 16X CW Clock Timing Diagram The cross-point switch distributes the clocks with an appropriate phase delay to each mixer. For example, Vi(t) is a received signal with a delay of (1 / 16) T. Apply a delayed LO(t) to the mixer in order to compensate for the (1 / 16) T delay. Thus, a 22.5⁰ delayed clock, that is 2π / 16 is selected for this channel. The mathematic calculation is expressed in Equation 5. é æ ù 1 ö Vi(t) = sin êw0 ç t + ÷ + wd t ú = sin [w0 t + 22.5° + wd t ] ëê è 16 f0 ø ûú LO(t) = é æ 4 1 öù 4 sin êw0 ç t + ÷ ú = sin [w0 t + 22.5°] 16 p f0 ø ûú p ëê è Vo(t) = 2 cos (wd t ) + f (wn t ) p (5) Vo(t) represents the demodulated Doppler signal of each channel. When the Doppler signals from N channels are summed, the signal-to-noise ratio improves. ωd is the Doppler frequency, ωo is the local oscillator frequency, and ωn represents the high-frequency components that are filtered out. 60 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 9.3.6.2 8 × ƒcw and 4 × ƒcw Modes The 8 × ƒcw and 4 × ƒcw modes are alternative modes when a higher frequency clock solution (that is, a 16 × ƒcw clock) is not available in the system. The block diagram of these two modes is shown in Figure 91. INV 4X, 8X Clock I/Q CLK Generator D Q 1X Clock LNA2 to 16 In-Phase CLK Weight Summed In-Phase Quadrature CLK I/V Weight LNA1 I/V Weight Summed Quadrature Weight Figure 91. 8 × ƒcw and 4 × ƒcw Block Diagram Good phase accuracy and matching are also maintained. The quadrature clock generator is used to create inphase and quadrature clocks with exactly a 90° phase difference. The only difference between the 8 × ƒcw and 4 × ƒcw modes is the accessibility of the third- and fifth-order harmonic suppression filter. In the 8 × ƒcw mode, the suppression filter can be supported. In both modes, a (1 / 16) T phase delay resolution is achieved by weighting the in-phase and quadrature paths correspondingly. For example, if a delay of (1 / 16) T or 22.5° is targeted, the weighting coefficients must follow Equation 6, assuming Iin and Qin are sin (ω0t) and cos (ω0t), respectively. æ 1 ö æ 2p ö æ 2p ö Idelayed (t) = Iin cos ç ÷ + Qin sin ç ÷ = Iin ç t + ÷ 16 16 16 f0 ø è ø è ø è æ 1 ö æ 2p ö æ 2p ö Qdelayed (t) = Qin cos ç ÷ - Iin sin ç ÷ = Qin ç t + ÷ è 16 ø è 16 ø è 16 f0 ø (6) Therefore, after the I/Q mixers, phase delay in the received signals is compensated. The mixer outputs from all channels are aligned and added linearly to improve the signal-to-noise ratio. TI recommends meeting the timing between the 1 × fcw clock and 4 × fcw or 8 × fcw clock; see Figure 92. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 61 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com Figure 92. 8 × ƒcw and 4 × ƒcw Timing Diagram 9.3.6.3 1 × ƒcw Mode The 1 × ƒcw mode requires in-phase and quadrature clocks with low phase noise specifications. A block diagram for this mode is shown in Figure 93. The (1 / 16) T phase delay resolution is also achieved by weighting the inphase and quadrature signals, as described in the 8 × ƒcw and 4 × ƒcw Modes section. Synchronized I/Q Clocks LNA2 to 16 In-Phase CLK Weight Quadrature CLK Summed In-Phase I/V Weight LNA1 Weight Weight I/V Summed Quadrature Figure 93. 1 × ƒcw Mode Block Diagram 62 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 9.3.6.4 CW High-Pass Filter The summing amplifier is implemented in the device to sum and convert 16-channel mixer current outputs to a differential voltage output. This summing amplifier has five internal gain adjustment resistors that can provide 32 different gain settings; see Table 80. System designers can easily adjust the CW path gain, depending on signal strength and transducer sensitivity. For any other gain values an external resistor option is supported. The gain of the summation amplifier is determined by the ratio between the 2000 Ω resistors after the LNA and internal or external resistor network (Rs). Thus, the matching between these resistors plays a more important role than the absolute resistor values. Better than 1% matching is achieved on-chip. The absolute resistor tolerance can be higher, depending on the process variation. If external resistors are used, the gain error between the I/Q channels or among multiple AFEs can increase. TI recommends using internal resistors to set the gain in order to achieve better gain matching (across channels and multiple AFEs). The device provides an extra feature to suppress undesired low-frequency signal presents at the CW output, which is achieved by implementing an HPF at the CW output using the scheme shown in Figure 94. ACT1 Mixer Clock 1 500 IN1 Input 1 Rh LNA1 INM1 Ch CW_DC_INP Cs 500 CW_DC_OUTM ACT2 Mixer Clock 2 Rs 500 IN2 Input 2 10 Ÿ 10 Ÿ LNA2 INM2 CW_AMPINM CW_AMPINP I2V Sum Amp 500 Rs CW_OUTP CW_OUTM + 2000 2000 HPF Amp _ CW Output CW_DC_INM CW_DC_OUTP Ch ACT16 Cs Mixer Clock 16 500 IN16 LNA16 Input 16 Rh CW I- or Q-Channel Structure INM16 500 Figure 94. CW Summing Amplifier and High-Pass Filter Implementation Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 63 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com When this feature is enabled, the overall transfer function of the CW summing amplifier across frequency is as shown in Figure 95. 0 -3 Fc_HPF Fc_LPF -6 Gain (dB) -9 -12 -15 -18 -21 -24 -27 100 1k 10k Frequency (Hz) 100k 1M D066 Figure 95. CW Summing Amplifier Transfer Function The high-pass corner and low-pass corner shown in Figure 95 is given by Equation 7 and Equation 8, respectively: Fc_hpf = Rs / (2 × π × Rh × Ch × 2000 Ω) Fc_lpf = 1 / (2 × π × Rs × Cs) (7) (8) The following rules can be used to calculate the value of different components: 1. Rs is the resistor value determined by how much signal gain is needed. 2. Cs is selected depending upon the value of Fc_lpf. 3. Rh is determined by the amplitude of the undesired low-frequency signal required to be rejected. For instance, suppose that without enabling the CW HPF feature, the peak-to-peak amplitude of the lowfrequency signal at the CW summing amplifier output is given by Vopp. Then the value of Rh has the relationship shown in Equation 9. The previous constraint occurs because the CW HPF amplifier output can only swing up to 4 Vpp. Rh < 4 × Rs / Vopp (9) NOTE Higher resistance values of Rh provide better noise performance. 4. Ch is the selected value of this capacitor depending upon the value of Fc_hpf. 64 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 An alternative current-summing circuit is shown in Figure 96. However, this circuit only achieves good performance when a lower noise operational amplifier is available compared to the device internal summing differential amplifier. This current output mode requires the internal summing amplifier to be powered down (register 198, bit 9) and Rs set to 0 Ω. AFE No.X CW_AMPINP AFE No.2 ACT1 500 Mixer 1 Clock CW_AMPINM Preferably, use an ultra-low noise, fully-differential amplifier with a high output driving current. AFE No.1 IN1 Input 1 INM1 LNA1 CM_BYP 500 ACT2 500 Mixer 1 Clock IN2 Input 2 INM2 CW_AMPINP LNA2 CW_AMPINM 500 - + CM_BYP CW I or Q Channel Structure + - ACT16 500 IN16 Input 16 INM16 Mixer 1 Clock LNA16 Ultra-low noise, single-ended amplifiers are an option as well. 500 Figure 96. CW Circuit With Multiple Devices (Current Output Mode, CM_BYP = 1.5 V) The CW I/Q channels are well matched internally to suppress image frequency components in the Doppler spectrum. Use low tolerance components and precise operational amplifiers for achieving good matching in the external circuits as well. NOTE The local oscillator inputs of the passive mixer are cos (ωt) for the I channel and sin (ωt) for the Q channel, respectively. Depending on the application-specific CW Doppler complex FFT processing, swapping I/Q channels in the FPGA or DSP may be needed in order to obtain correct blood flow directions. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 65 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 9.3.6.5 CW Clock Selection The device can accept differential LVDS, LVPECL, and other differential clock inputs as well as a single-ended CMOS clock. An internally-generated VCM of 2.5 V is applied to CW clock inputs (that is, CLKP_16X, CLKM_16X and CLKP_1X, CLKM_1X). Because this 2.5-V VCM is different from the one used in standard LVDS or LVPECL clocks, ac coupling is required between clock drivers and the device CW clock inputs. When the CMOS clock is used, tie CLKM_1X and CLKM_16X to ground. Common clock configurations are shown in Figure 97. Appropriate termination is recommended to achieve good signal integrity. NOTE The configurations shown in Figure 97 can also be used as a reference for the ADC clock input. 3.3 V 130 : 3.3 V 0.1 PF 83 : LMK048x, CDCM7005, CDCE7010 AFE Clocks 0.1 PF 130 : LVPECL (a) LVPECL Configuration 100 : CDCE72010 0.1 PF 0.1 PF AFE Clocks LVDS (b) LVDS Configuration C1 100 nF Clock Source 0.1 PF R1 50 : L1 1 m: 0.1 PF AFE Clocks 0.1 PF (c) Transformer-Based Configuration CMOS CLK Driver AFE CMOS CLK CMOS (d) CMOS Configuration Figure 97. Clock Configurations 66 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 The combination of the clock noise and the CW path noise can degrade CW performance. The internal clocking circuit is designed for achieving excellent phase noise required by CW operation. The phase noise of the device CW path is better than 160 dBc/Hz at a 1-kHz offset. Consequently, the phase noise of the mixer clock inputs must be better than 160 dBc/Hz. In the 16, 8, and 4 × ƒcw operations modes, a low-phase noise clock is required for the 16, 8, and 4 × ƒcw clocks (that is, the CLKP_16X and CLKM_16X pins) in order to maintain good CW phase noise performance. The 1 × ƒcw clock (that is, the CLKP_1X and CLKM_1X pins) is only used to synchronize the multiple device chips and is not used for demodulation. Thus, the 1 × ƒcw clock phase noise is not a concern. However, in the 1 × ƒcw operation mode, low-phase noise clocks are required for both the CLKP_16X, CLKM_16X and CLKP_1X, CLKM_1X pins because both are used for mixer demodulation. In general, a higher slew rate clock has lower phase noise. Thus, clocks with high amplitude and fast slew rate are preferred in CW operation. In the CMOS clock mode, a 5-V CMOS clock can achieve the highest slew rate. Clock phase noise can be improved by a divider as long as the divider phase noise is lower than the target phase noise. The phase noise of a divided clock can be improved approximately by a factor of 20logN dB, where N is the dividing factor of 16, 8, or 4. If the target phase noise of the mixer LO clock 1 × fcw is 160 dBc/Hz at a 1kHz off the carrier, the 16 × fcw clock phase noise must be better than 160 – 20log16 = 136 dBc/Hz. TI’s jitter cleaners LMK048x, CDCM7005, and CDCE72010 exceed this requirement and can be selected to work with the device. In the 4X and 1X modes, higher quality input clocks are expected to achieve the same performance because N is smaller. Thus, the 16X mode is a preferred mode because this mode reduces the phase noise requirement for the system clock design. In addition, the phase delay accuracy is specified by the internal clock divider and distribution circuit. Note that in the 16X operation mode, the CW operation range is limited to 8 MHz as a result of the 16X clock. The maximum clock frequency for the 16X clock is 128 MHz. In the 8X, 4X, and 1X modes, higher CW signal frequencies up to 15 MHz can be supported with a small degradation in performance. For example, the phase noise is degraded by 9 dB at 15 MHz, compared to 2 MHz. As the channel number in a system increases, clock distribution becomes more complex. Using one clock driver output is not preferred to drive multiple AFEs because the clock buffer load capacitance increases by a factor of N. The section can be used as a reference for the system clock configuration. When clock phase noise is not a concern (for example, the 1 × ƒcw clock in the 16, 8, and 4 × ƒcw operation modes), one clock driver output can excite more than one device. Nevertheless, special considerations must be applied for such a clock distribution network design. Preferably, all clocks are generated from the same clock source in typical ultrasound systems (such as 16 × ƒcw , 1 × ƒcw clocks, audio ADC clocks, RF ADC clock, pulse repetition frequency signal, frame clock, and so on). By using the same clock source, interference resulting from clock asynchronization can be minimized. 9.3.6.6 CW Supporting Circuits As a general practice in the CW circuit design, in-phase and quadrature channels must be strictly symmetrical by using well-matched layout and high-accuracy components. In systems, additional high-pass wall filters (20 Hz to 500 Hz) and low-pass audio filters (10 kHz to 100 kHz) with multiple poles are usually needed. Because the CW Doppler signal ranges from 20 Hz to 20 kHz, noise under this range is critical. Consequently, low-noise audio operational amplifiers are suitable to build these active filters for CW post-processing (that is, the OPA1632, OPA2211, or THS4131). More filter design techniques can be found at www.ti.com. The TI active filter design tool is the WEBENCH® Filter Designer. The filtered audio CW I/Q signals are sampled by audio ADCs and processed by the DSP or PC. Although CW signal frequency is from 20 Hz to 20 KHz, higher sampling rate ADCs are still preferred for further decimation and SNR enhancement. Because of the large dynamic range of CW signals, high-resolution ADCs (≥ 16 bits) are required [such as the ADS8413 (2 MSPS, 16 bits, 92-dBFS SNR) and the ADS8472 (1 MSPS, 16 bits, 95-dBFS SNR)]. ADCs for in-phase and quadrature-phase channels must be strictly matched, not only for amplitude matching but also for phase matching in order to achieve the best I/Q matching. In addition, the in-phase and quadrature ADC channels must be sampled simultaneously. 9.3.6.7 Power Management Power management plays a critical role to extend battery life and to ensure a long operation time. The device has a fast and flexible power-up and power-down control that can maximize battery life. The device can be powered down or up through external pins or internal registers. This section describes the functionality of different power-down pins and register bits available in the device. The device can be divided in two major blocks, the VCA and ADC; see Figure 98 and Figure 99. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 67 AFE5818 www.ti.com AVDD_5V AVDD_3P3 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 CM_BYP1 CM_BYP2 Reference Voltage, Current Generator VHIGH1 Band-Gap Circuit VHIGH2 One Channel Block ACT1 INP1 VCAT 0 to -40 dB LNA LPF 10, 15, 20, 30, 35 and 50 MHz PGA 24, 30 dB INM1 To ADC Channel 1 VCNTL CW Mixer CW_CH1 16X16 Cross Point SW CW_CLOCK ACT2 INP2 VCAT 0 to -40 dB LNA PGA 24, 30 dB INM2 LPF 10, 15, 20, 30, 35 and 50 MHz To ADC Channel 2 LPF 10, 15, 20, 30, 35 and 50 MHz To ADC Channel 16 VCNTL Analog Inputs CW Mixer CW_CH2 16X16 Cross Point SW CW_CLOCK ACT16 INP16 VCAT 0 to -40 dB LNA PGA 24, 30 dB INM16 VCNTL CW Mixer CW_CLOCK CW_CH16 16X16 Cross Point SW VCNTL CLKP_16x CLKM_16x CW_CH15 CW_CH16 CW_CH1 CW_CH2 CW_CLOCK VCNTRL Block Serial Interface SDOUT 16-Phase Generator CW Clock CLKP_1x CLKM_1x SCLK SEN RESET SDIN PDN_GBL PDN_FAST VCNTLM AVSS VCNTLP Summing Amplifier CW_IP_OUTP, CW_IP_OUTM, CW_QP_OUTP, CW_QP_OUTM Figure 98. VCA Block Diagram 68 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 Reference Voltage, Current Generator VCM DVDD_1P8 DVDD_1P2 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 AVDD_1P8 www.ti.com Band-Gap Circuit ADC1 ADC Analog ADC Digital LVDS Data Serializer and Buffer DOUTP1 DOUTM1 ADC Analog ADC Digital LVDS Data Serializer and Buffer DOUTP2 DOUTM2 LVDS Data Serializer and Buffer DOUTP16 DOUTM16 ADC2 VCA Output ADC16 LVDS Outputs ADC Analog ADC Digital FCLKP FCLKM LVDS Frame, Clock Serializer, and Buffer DCLKP DCLKM PLL Serial Interface SDOUT SCLK SEN PDN_FAST PDN_GBL RESET SDIN ADC_CLKP ADC Clock ADC_CLKM ADC Clock Buffer Figure 99. ADC Block Diagram Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 69 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 9.3.6.7.1 VCA The VCA consists of the following blocks: • Band-gap circuit, • Serial interface, • Reference voltage and current generator, • A total of 16 channel blocks (each channel block includes an LNA, VCAT, PGA, LPF, CW mixer, and a 16X16 cross-point switch), • VCNTRL block, • Phase generator for CW mode, and • CW summing amplifier. Of these VCA blocks, only the band gap and serial interface block cannot be powered down by using powerdown pins or bits. Table 7 lists all the VCA blocks that are powered down using various pin and bit settings. Table 7. VCA Power-Down Mode Descriptions NAME TYPE (Pin or Register) LNA VCAT + PGA + LPF CW MIXER 16X16 CROSS-POINT SWITCH REFERE NCE VCNTRL BLOCK CW SUMMING AMPLIFIER + PHASE GENERATOR CHANNEL PDN_GBL Pin Yes (1) Yes Yes Yes Yes Yes Yes All (2) GBL_PDWN Register 197, bit 15 Yes Yes Yes Yes Yes Yes Yes All PDN_FAST Pin Yes Yes Yes Yes No No Yes All FAST_PDWN Register 197, bit 14 Yes Yes Yes Yes No No Yes All PDNCHxx Register 197, bits 7-0, register 213, bits 7-0 Yes Yes Yes Yes No No No Individual PDWN_LNA Register 197, bit 13 Yes No No No No No No All PDWN_VCA_PGA Register 197, bit 12 No Yes No No No No No All (1) (2) Yes = powered down. No = active. All = all channels are powered down. Individual = only a single channel is powered down, depending upon the corresponding bit. If more than one bit is simultaneously enabled, then all blocks listed as Yes for each bit setting is powered down. 70 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 9.3.6.7.2 ADC The ADC consists of the following blocks: • Band-gap circuit, • Serial interface, • Reference voltage and current generator, • ADC analog block that performs a sampling and conversion, • ADC digital block that includes all the digital post processing blocks (such as the offset, gain, digital HPF, and so forth), • LVDS data serializer and buffer that converts the ADC parallel data to a serial stream. • LVDS frame and clock serializer and buffer, • PLL (phase-locked loop) that generates a high-frequency clock for both the ADC and serializer. Of all these blocks, only the band gap and serial interface block cannot be power down using power-down pins or bits. Table 8 lists which blocks in the ADC are powered down using different pins and bits. Table 8. Power-Down Modes Description for the ADC NAME TYPE (Pin or Register) ADC ANALOG ADC DIGITAL LVDS DATA SERIALIZER, BUFFER LVDS FRAME AND CLOCK SERIALIZER, BUFFER REFERENCE + ADC CLOCK BUFFER PLL CHANNEL PDN_GBL Pin Yes (1) Yes Yes Yes Yes Yes All (2) GLOBAL_PDN Register 1, bit 0 Yes Yes Yes Yes Yes Yes All PDN_FAST Pin Yes Yes Yes No No No All DIS_LVDS Register 1, bit 5 No No Yes Yes No No All PDN_ANA_CHx Registers 24 (bits 7-4), 36 (bits 7-4), 48 (bits 7-4), and 60 (bits 7-4) Yes No No No No No Individual PDN_DIG_CHx Registers 4 (bits 15-12), 36 (bits 15-12), 48 (bits 15-12), and 60 (bits 15-12) No Yes No No No No Individual PDN_LVDSx Register 24 (bits 11-8), 36 (bits 11-8), 48 (bits 11-8), and 60 (bits 11-8) No No Yes No No No Individual (1) (2) Yes = powered down. No = active. All = all channels are powered down. Individual = only a single channel is powered down, depending upon the corresponding bit. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 71 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 9.4 Device Functional Modes 9.4.1 ADC Test Pattern Mode 9.4.1.1 Test Patterns 9.4.1.1.1 LVDS Test Pattern Mode The ADC data coming out of the LVDS outputs can be replaced by different kinds of test patterns. The different test patterns are described in Table 9. Table 9. Description of LVDS Test Patterns TEST PATTERN MODE PROGRAMMING THE MODE THE SAME PATTERN MUST BE COMMON TO ALL DATA LINES (DOUT) THE PATTERN IS SELECTIVELY REQUIRED ON ONE OR MORE DATA LINE (DOUT) TEST PATTERNS REPLACE (1) All 0s Set the mode using PAT_MODES[2:0] Set PAT_SELECT_IND = 1. To output the pattern on the DOUTx line, select PAT_LVDSx[2:0]. Zeros in all bits (00000000000000) All 1s Set the mode using PAT_MODES[2:0] Set PAT_SELECT_IND = 1. To output the pattern on the DOUTx line, select PAT_LVDSx[2:0]. Ones in all bits (11111111111111) Deskew Set the mode using PAT_MODES[2:0] Set PAT_SELECT_IND = 1. To output the pattern on the DOUTx line, select PAT_LVDSx[2:0]. The ADC data are replaced by alternate 0s and 1s (01010101010101) Sync Set the mode using PAT_MODES[2:0] Set PAT_SELECT_IND = 1. To output the pattern on the DOUTx line, select PAT_LVDSx[2:0]. ADC data are replaced by half 1s and half 0s (11111110000000) Set PAT_SELECT_IND = 1. To output the pattern on the DOUTx line, select PAT_LVDSx[2:0]. The word written in the CUSTOM_PATTERN control (taken from the MSB side) replaces ADC data. (For instance, CUSTOM_PATTERN = 1100101101011100 and ADC data = 11001011010111 when the serialization factor is 14.) Set PAT_SELECT_IND = 1. To output the pattern on the DOUTx line, select PAT_LVDSx[2:0]. The ADC data are replaced by a word that increments by 1 LSB every conversion clock starting at negative full-scale, increments until positive fullscale, and wraps back to negative full-scale. The step size of the ramp pattern is function of ADC resolution (N) and serialization factor (S) and is given by 2(S-N). Custom Ramp Set the mode using PAT_MODES[2:0]. Set the desired custom pattern using the CUSTOM_PATTERN register control. Set the mode using PAT_MODES[2:0] Toggle Set the mode using PAT_MODES[2:0] Set PAT_SELECT_IND = 1. To output the pattern on the DOUTx line, select PAT_LVDSx[2:0]. The ADC data alternate between two words that are all 1s and all 0s. At each setting of the toggle pattern, the start word can either be all 0s or all 1s. (Alternate between 11111111111111 and 00000000000000.) PRBS Set SEL_PRBS_PAT_GBL = 1. Select either custom or ramp pattern with PAT_MODES[2:0]. Enable PRBS mode using PRBS_EN. Select the desired PRBS mode using PRBS_MODE. Reset the PRBS generator with PRBS_SYNC. Set PAT_SELECT_IND = 1. Select either custom or ramp pattern with PAT_LVDSx[2:0]. Enable PRBS mode on DOUTx with the PAT_PRBS_LVDSx control. Select the desired PRBS mode using PRBS_MODE. Reset the PRBS generator with PRBS_SYNC. A 16-bit pattern is generated by a 23-bit (or 9-bit) PRBS pattern generator (taken from the MSB side) and replaces the ADC data. (1) Shown for a serialization factor of 14. 72 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 All patterns listed in Table 9 (except the PRBS pattern) can also be forced on the frame clock output line by using PAT_MODES_FCLK[2:0]. To force a PRBS pattern on the frame clock, use the SEL_PRBS_PAT_FCLK, PRBS_EN, and PAT_MODES_FCLK register controls. The ramp, toggle, and pseudo-random sequence (PRBS) test patterns can be reset or synchronized by providing a synchronization pulse on the TX_TRIG pin or by setting and resetting a specific register bit. Figure 100 depicts a block diagram representation of this scheme. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 73 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com PAT_MODES[2:0] PAT_MODES[2:0] Global Pattern ADC1 0 1 PAT_SELECT_IND 0 Serializer DOUTP1, DOUTM1 Serializer DOUTP16, DOUTM16 1 0 Individual Pattern for LVDS1 1 PAT_LVDS1[2:0] ADC16 0 1 PAT_SELECT_IND 0 1 0 Individual Pattern for LVDS16 1 PAT_LVDS16[2:0] Figure 100. Test Pattern Block Diagram 74 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 9.4.2 Partial Power-Up and Power-Down Mode The partial power-up and power-down mode is also called fast power-up and power-down mode. The VCA can be programmed in partial power-down mode either by setting the PDN_FAST pin high or setting the FAST_PDWN (register 197, bit 14) register bit to 1. Similarly, the ADC can be programmed in this mode by setting the PDN_FAST pin high. In this mode, most amplifiers in the signal path are powered down and the internal reference circuits remain active as well as all the data and frame and clock LVDS serializer and buffer. The partial power-down function allows the device to quickly wake-up from a low-power state. This configuration ensures that the external capacitors are discharged slowly; thus, a minimum wake-up time is required as long as the charges on these capacitors are restored. The VCA wake-up response is typically approximately 2 μs or 1% of the power-down duration, whichever is larger. The longest wake-up time depends on the capacitors connected at INP and INM, because the wake-up time is the time required to recharge the capacitors to the desired operating voltages. For instance, 0.1 μF at INP and 15 nF at INM provides a wake-up time of 2.5 ms. For larger capacitors, this time is longer. The ADC wake-up time is approximately 1 μs. Thus, the device wake-up time is more dependent on the VCA wake-up time with the assumption that the ADC clock is running for at least 50 μs before the normal operating mode resumes. The power-down time is instantaneous, less than 1 μs. This fast wake-up response is desired for portable ultrasound applications in which power savings is critical. The pulse repetition frequency of an ultrasound system can vary from 50 kHz to 500 Hz, and the imaging depth (that is, the active period for a receive path) varies from tens of µs to hundreds of μs. The power savings can be quite significant when a system PRF is low. In some cases, only the VCA is powered down when the ADC runs normally to ensure minimal interference to the FPGAs; see the Electrical Characteristics table to determine device power dissipation in partial power-down mode. 9.4.3 Global Power-Down Mode To achieve the lowest power dissipation, the device can be placed into a complete power-down mode. This mode is controlled through the GBL_PDWN (for the VCA) or GLOBAL_PDN (for the ADC) registers or the PDN_GBL pin (for both the VCA and ADC). In complete power-down mode, all circuits (including reference circuits within the device) are powered down and the capacitors connected to the device are discharged. The wake-up time depends on the time that the device spends in shutdown mode. 0.1 μF at INP and 15 nF at INM provide a wake-up time of approximately 2.5 ms. 9.4.4 TGC Configuration By default, after reset the VCA is configured in TGC mode. Depending upon the system requirements, the device can be programmed in a suitable power mode using the POW_MODES (register 197, bits 11-10) register bits. 9.4.5 CW Configuration To configure the device in CW mode, set the CW_TGC_SEL (register 198, bit 9) register bit to 1. To save power, the voltage-controlled attenuator and programmable gain amplifier in the TGC path can be disabled by setting the PDWN_VCA_PGA bit (register 197, bit 12) to 1. Also, the ADC can be powered down completely using the GLOBAL_PDN bit (register 1, bit 0). Usually only half the number of channels in a system are active in the CW mode. Thus, the individual channel control can power-down unused channels and save power; see Table 7 and Table 8. 9.4.6 TGC + CW Mode In systems that require fast switching between the TGC and CW modes, both TGC and CW mode can remain active simply by setting the CW_TGC_SEL (register 198, bit 9) register bit to 1. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 75 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 9.5 Programming 9.5.1 Serial Peripheral Interface (SPI) Operation Several different device modes can be programmed with the serial peripheral interface (SPI). This interface is formed by the SEN (serial interface enable), SCLK (serial interface clock), SDIN (serial interface data), and RESET pins. Inside the device, the SCLK and SDIN pins have a 16-kΩ, pulldown resistor to ground and the SEN pin has a 16-kΩ, pullup resistor to the DVDD_1P8 supply. Serially shifting bits into the device is enabled when SEN is low. SDIN serial data are latched at every SCLK rising edge when SEN is active (low). SDIN serial data are loaded into the register at every 24th SCLK rising edge when SEN is low. If the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of 24-bit words within a single active SEN pulse (an internal counter counts the number of 24 clock groups after the SEN falling edge). The interface can function with SCLK frequencies from 20 MHz down to low speeds (of a few hertz) and also with a non-50% SCLK duty cycle. Data are divided into two main portions: the register address (8 bits) and data (16 bits). These portions are loaded on the addressed register. When writing to a register with unused bits, set these bits to 0. Figure 101 shows this process. SEN tSEN_SU tSCLK_H Data Latched On SCLK Rising Edge tSCLK tSEN_HO SCLK tSCLK_L tDH tDSU SDIN A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RESET Figure 101. Serial Interface Timing Diagram 76 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 Programming (continued) 9.5.1.1 Register Readout The device includes an option where the contents of the internal registers can be read back. This readback feature can be useful as a diagnostic test to verify the serial interface communication between the external controller and the AFE. First, the REG_READ_EN bit (register 0, bit 1) must be set to 1. Then, initiate a serial interface cycle specifying the address of the register (A[7:0]) whose content must be read. The data bits are don’t care. The device outputs the contents (bits 15-0) of the selected register on the SDOUT pin. SDOUT has a typical 20-ns delay (tOUT_DV) from the SCLK falling edge. For lower-speed SCLKs, SDOUT can be latched on the SCLK rising edge. For higher-speed SCLKs (for example, if the SCLK period is less than 60 ns), latching SDOUT at the next SCLK falling edge is preferable. The read operation timing diagram is shown in Figure 102 (see the Serial Interface Timing Characteristics table). In readout mode, the REG_READ_EN bit can be accessed with SDIN, SCLK, and SEN. To enable serial register writes, set the REG_READ_EN bit back to 0. The device SDOUT buffer is 3-stated and is only enabled when the REG_READ_EN bit (register 0, bit 1) is enabled. SDOUT pins from multiple devices can be tied together without any pullup resistors. The SN74AUP1T04 level shifter can be used to convert 1.8-V logic to 2.5-V or 3.3-V logic, if necessary. SEN SCLK tOUT_DV SDOUT SDIN A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X X X X X X X X X Figure 102. Serial Interface Register, Read Operation Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 77 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information The device supports a wide-frequency bandwidth signal in the range of several kHz to several MHz. The device is a highly-integrated solution that includes a low-noise amplifier (LNA), a voltage-controlled attenuator (VCAT), a programmable gain amplifier (PGA), an antialiasing filter, an analog-to-digital converter (ADC), and a continuous wave (CW) mixer. As a result of the device functionality, the device can be used in various applications (such as in medical ultrasound imaging systems, sonar imaging equipment, radar, and other systems that require a very large dynamic range). 10.2 Typical Application Transmitter 1 1 uF ACT1 SPI Control 0.1 uF Channel 1 INP1 T/R Switch Clamping Diode Transmitter 16 AFE 1 LVDS Receiver LVDS lines 1 uF ACT16 0.1 uF Channel 16 INP16 T/R Switch 64 Channels Transducer Array FPGA Data Processing And Storage Clamping Diode AFE 4 Transmitter 64 LVDS lines LVDS Receiver 1 uF ACT16 0.1 uF Channel 64 INP16 Clock Generator T/R Switch Clamping Diode Figure 103. Simplified Schematic 78 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 Typical Application (continued) 5 VA 10 PF N(1) x AVSS 0.1 PF N(1) x AVSS 0.1 PF 1.2 VD 10 PF N(1) x AVSS 0.1 PF 1 PF 0.1 PF 1.8 VD 10 PF N(1) x DVSS 0.1 PF N(1) x DVSS 0.1 PF DVDD_1P8 DVDD_1P2 AVDD_3P3 AVDD_1P8 INP1 AVDD_5V 0.1 PF IN CH2 3.3 VA 10 PF ACT1 1 PF IN CH1 1.8 VA 10 PF DOUTP1 DOUTM1 ACT2 DOUTP2 INP2 DOUTM2 10 nF ADC_CLKP ADC_CLKM 10 nF CLKP_16X DOUTP3, DOUTM3 to DOUTP14, DOUTM14 ACT3, INP3 to ACT14, INP14 AFE5818 Clock Inputs CLKM_16X 10 nF DOUTP15 ACT15 1 PF CLKP_1X CLKM_1X DOUTM15 10 nF DOUTP16 0.1 PF IN CH15 INP15 DOUTM16 SDOUT SDIN DCLKP ACT16 1 PF SCLK 0.1 PF IN CH16 DCLKM INP16 TX_TRIG FCLKP SEN •15 nF INM1 •15 nF INM2 AFE5818 Analog Inputs, Analog Outputs, REF and BIAS Decoupling, LVDS Outputs INM16 •15 nF AFE5818 Digital Inputs FCLKM Other AFE5818 Outputs RESET RSUM CW_IP_AMPINP REXT (optional) CW_IP_OUTM CS CW_IP_AMPINM REXT (optional) RSUM CS RSUM PDN_FAST PDN_GBL CW_IP_OUTP To Summing Amplifier CW_DC_INM_IP CH CW_DC_OUTP_IP •1 PF CM_BYP1 Other AFE5818 Outputs RSUM CW_DC_INP_IP •1 PF CM_BYP2 •1 PF VHIGH1 •1 PF VHIGH2 CH CW_DC_OUTM_IP Other AFE5818 Outputs RSUM CW_QP_AMPINP CW_QP_OUTM CW_QP_AMPINM CW_QP_OUTP CS REXT (optional) RSUM CS RSUM To Summing Amplifier REXT (optional) RVCNTL 200 Ÿ CW_DC_INM_QP CVCNTL 470 pF VCNTLP CW_DC_OUTP_QP CH VCNTLP VCNTLM VCNTLM RVCNTL 200 Ÿ Other AFE5818 Outputs RSUM CW_DC_INP_QP CVCNTL 470 pF CW_DC_OUTM_QP CH NCs AVSS (1) DVSS N represents the number of capacitors connected to the supply. Placing at least one capacitor for every three supply pins is recommended. Figure 104. Application Circuit Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 79 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com Typical Application (continued) 10.2.0.2 Design Requirements Typical requirements for a medical ultrasound imaging system are listed in Table 10. Table 10. Design Parameters DESIGN PARAMETER EXAMPLE VALUES Signal center frequency 5 MHz Signal bandwidth 2 MHz Maximum overloaded signal 1 VPP Maximum input signal amplitude 100 mVPP Transducer noise level 1 nV/√Hz Dynamic range 151 dBc/Hz Time gain compensation range 40 dB Total harmonic distortion 40 dBc 10.2.0.3 Detailed Design Procedure Medical ultrasound imaging is a widely-used diagnostic technique that enables visualization of internal organs, their size, structure, and blood flow estimation. An ultrasound system uses a focal imaging technique that involves time shifting, scaling, and intelligently summing the echo energy using an array of transducers to achieve high imaging performance. The concept of focal imaging provides the ability to focus on a single point in the scan region. By subsequently focusing at different points, an image is assembled. See Figure 103 for a simplified schematic of a 64-channel ultrasound imaging system. When initiating an imaging, a pulse is generated and transmitted from each of the 64 transducer elements. The pulse, now in the form of mechanical energy, propagates through the body as sound waves, typically in the frequency range of 1 MHz to 15 MHz. The sound waves weaken rapidly as they travel through the objects being imaged, falling off as the square of the distance traveled. As the signal travels, portions of the wave front energy are reflected. Signals that are reflected immediately after transmission are very strong because they are from reflections close to the surface; reflections that occur long after the transmit pulse are very weak because they are reflecting from deep in the body. As a result of the limitations on the amount of energy that can be put into the imaging object, the industry developed extremely sensitive receive electronics. Receive echoes from focal points close to the surface require little, if any, amplification. This region is referred to as the near field. However, receive echoes from focal points deep in the body are extremely weak and must be amplified by a factor of 100 or more. This region is referred to as the far field. In the high-gain (far field) mode, the limit of performance is the sum of all noise sources in the receive chain. In high-gain (far field) mode, system performance is defined by its overall noise level, which is limited by the noise level of the transducer assembly and the receive low-noise amplifier (LNA). However in the low-gain (near field) mode, system performance is defined by the maximum amplitude of the input signal that the system can handle. The ratio between noise levels in high-gain mode and the signal amplitude level in low-gain mode is defined as the dynamic range of the system. The high integration and high dynamic range of the device make it ideally suited for ultrasound imaging applications. The device includes an integrated LNA and VCAT (which use the gain that can be changed with enough time to handle both near- and far-field systems), a low-pass antialiasing filter to limit the noise bandwidth, an ADC with high SNR performance, and a CW mixer. Figure 104 illustrates an application circuit of the device. 80 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 Use the following steps to design medical ultrasound imaging systems: 1. Use the signal center frequency and signal bandwidth to select an appropriate ADC sampling frequency. 2. Use the time gain compensation range to select the range of the VCNTL signal. 3. Use the transducer noise level and maximum input signal amplitude to select the appropriate LNA gain. The device input-referred noise level reduces with higher LNA gain. However, higher LNA gain leads to lower input signal swing support. 4. See Figure 104 to select different passive components for different device pins. 5. See the LNA Input Impedance section to select the appropriate input termination configuration. 6. See the CW Clock Selection section to select the clock configuration for the ADC and CW clocks. 10.2.0.4 Application Curves 0 0 -20 -20 Magnitude (dBFS) Magnitude (dBFS) Figure 105 and Figure 106 show the FFT of a device output for VCNTL = 0 V and VCNTL = 0.9 V, respectively, with an input signal at 5 MHz captured at a sample rate of 50 MHz. Figure 105 shows the spectrum for a far field imaging scenario with the full Nyquist band, default device settings, and VCNTL = 0 V.Figure 106 shows the spectrum for a near field imaging scenario for the full Nyquist band with default device settings and VCNTL = 0.9 V. -40 -60 -80 -40 -60 -80 -100 -100 -120 -120 0 2.5 5 7.5 10 12.5 15 17.5 Frequency (MHz) 20 22.5 25 0 D064 Figure 105. FFT for VCNTL = 0 V 2.5 5 7.5 10 12.5 15 17.5 Frequency (MHz) 20 22.5 Product Folder Links: AFE5818 D065 Figure 106. FFT for VCNTL = 0.9 V Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated 25 81 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 10.3 Do's and Don'ts Driving the inputs (analog or digital) beyond the power-supply rails. For device reliability, an input must not go more than 300 mV below the ground pins or 300 mV above the supply pins as suggested in the Absolute Maximum Ratings table. Exceeding these limits, even on a transient basis, can cause faulty or erratic operation and can impair device reliability. Driving the device signal input with an excessively high level signal. The device offers consistent and fast overload recovery with a 6-dB overloaded signal. For very large overload signals (> 6 dB of the linear input signal range), TI recommends back-to-back Schottky clamping diodes at the input to limit the amplitude of the input signal; see the LNA Overload Recovery section for more details. Driving the VCNTL signal with an excessive noise source. Noise on the VCNTL signal gets directly modulated with the input signal and causes higher output noise and reduction in SNR performance. Maintain a noise level for the VCNTL signal as discussed in the Control Voltage Input section. Using a clock source with excessive jitter, an excessively long input clock signal trace, or having other signals coupled to the ADC or CW clock signal trace. These situations cause the sampling interval to vary, causing an excessive output noise and a reduction in SNR performance. For a system with multiple devices, the clock tree scheme must be used to apply an ADC or CW clock; see the CW Clock Selection section for clock mismatch between devices, which can lead to latency mismatch and reduction in SNR performance. LVDS routing length mismatch. The routing length of all LVDS lines routing to the FPGA must be matched to avoid any timing related issue. For systems with multiple devices, the LVDS serialized data clock (DCLKP, DCLKM) and the frame clock (FCLKP, FCLKM) of each individual device must be used to deserialize the corresponding LDVS serialized data (DOUTP, DOUTM). Failure to provide adequate heat removal. Use the appropriate thermal parameter listed in the Thermal Information table and an ambient, board, or case temperature in order to calculate device junction temperature. A suitable heat removal technique must be used to keep the device junction temperature below the maximum limit of 105°C. Incorrect register programming. After resetting the device, write register 1, bit 2 = 1 and register 1, bit 4 = 1. If these bits are not set as specified, the device will not function properly. Furthermore, ADD_OFFSET (register 0, bit 2) must be used carefully; see the VCA Register Map section. 10.4 Initialization Set Up After bringing up all the supplies, use the following steps to initialize the device: 1. Apply a hardware reset pulse on the RESET pin with a minimum pulse duration of 100 ns. Note that after powering up the device, a hardware reset is required. 2. After applying a hardware reset pulse, wait for a minimum time of 100 ns. 3. Set register 1, bits 2 and 4 to 1 using SPI signals. 4. Write any other register settings as required. 82 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 11 Power Supply Recommendations The device requires a total of five supplies in order to operate properly. These supplies are: AVDD_5V, AVDD_3P3, AVDD_1P8, DVDD_1P8, and DVDD_1P2. For detailed information regarding the operating voltage minimum and maximum specifications of different supplies, see the Recommended Operating Conditions table. 11.1 Power Sequencing and Initialization 11.1.1 Power Sequencing Figure 107 shows the suggested power-up sequencing and reset timing for the device. Note that the DVDD_1P2 supply must rise before the AVDD_1P8 supply. If the AVDD_1P8 supply rises before the DVDD_1P2 supply, the AVDD_1P8 supply current is eight to 12 times larger than the normal current until the DVDD_1P2 supply reaches a 1.2-V level. t1 t2 DVDD_1P2 DVDD_1P8, AVDD_1P8, AVDD_3P3, AVDD_5V t3 t4 t7 t5 RESET t6 Device ready for register write Device ready for data conversion Start of clock SEN t8 NOTE: 10 µs < t1 < 50 ms, 10 µs < t2 < 50 ms, t3 > t1, t4 > 10 ms, t5 > 100 ns, t6 > 100 ns, t7 > 4 ADC clock cycles, and t8 > 100 µs. Figure 107. Recommended Power-Up Sequencing and Reset Timing Diagram Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 83 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 12 Layout 12.1 Layout Guidelines 12.1.1 Power Supply, Grounding, and Bypassing In a mixed-signal system design, the power-supply and grounding design plays a significant role. The device distinguishes between two different grounds: AVSS (analog ground) and DVSS (digital ground). In most cases laying out the printed circuit board (PCB) to use a single ground plane is adequate, but in high-frequency or highperformance systems, care must be taken so that this ground plane is properly partitioned between various sections within the system to minimize interactions between analog and digital circuitry. Alternatively, the digital supply set consisting of the DVDD_1P8, DVDD_1P2, and DVSS pins can be placed on separate power and ground planes. For this configuration, tie the AVSS and DVSS grounds together at the power connector in a star layout. In addition, optical or digital isolators (such as the ISO7240) can completely separate the analog portion from the digital portion. Consequently, such isolators prevent digital noise from contaminating the analog portion. Table 11 lists the related circuit blocks for each power supply. Table 11. Supply versus Circuit Blocks (1) POWER SUPPLY GROUND CIRCUIT BLOCKS (1) AVDD_5V AVSS Reference voltage and current generator, LNA, VCNTRL block, CW mixer, CW clock buffer, 16x16 cross-point switch, 16-phase generator AVDD_3P3 AVSS Band-gap circuit, reference voltage and current generator, LNA, VCAT, PGA, LPF, CW summing amplifier, VCA SPI AVDD_1P8 AVSS ADC analog, reference voltage and current generator, band-gap circuit, ADC clock buffer DVDD_1P8 DVSS LVDS serializer and buffer, PLL DVDD_1P2 DVSS ADC digital, serial interface See Figure 98 and Figure 99 for further details. Reference all bypassing and power supplies for the device to their corresponding ground planes. Bypass all supply pins with 0.1-μF ceramic chip capacitors (size 0603 or smaller). In order to minimize the lead and trace inductance, the capacitors must be located as close to the supply pins as possible. Where double-sided component mounting is allowed, these capacitors are best placed directly under the package. In addition, larger bipolar decoupling capacitors (2.2 µF to 10 μF, effective at lower frequencies) can also be used on the main supply pins. These components can be placed on the PCB in close proximity (< 0.5 inch or 12.7 mm) to the device itself. The device has a number of reference supplies that must be bypassed, such as CM_BYP1, CM_BYP2 and VHIGH1, VHIGH2. Bypass these pins with at least a 1-μF capacitor; higher value capacitors can be used for better low-frequency noise suppression. For best results, choose low-inductance ceramic chip capacitors (size 0402, > 1 μF) and placed as close as possible to the device pins. 12.1.2 Board Layout High-speed, mixed-signal devices are sensitive to various types of noise coupling. One primary source of noise is the switching noise from the serializer and the output buffer and drivers. For the device, care must be taken to ensure that the interaction between the analog and digital supplies within the device is kept to a minimal amount. The extent of noise coupled and transmitted from the digital and analog sections depends on the effective inductances of each of the supply and ground connections. Smaller effective inductances of the supply and ground pins result in better noise suppression. For this reason, multiple pins are used to connect each supply and ground sets. Low inductance properties must be maintained throughout the design of the PCB layout by use of proper planes and layer thickness. To avoid noise coupling through supply pins, TI recommends to keep sensitive input pins (such as INM, INP, and ACT pins) away from the AVDD_3P3 and AVDD_5V planes. For example, do not route the traces or vias connected to these pins across the AVDD_3P3 and AVDD_5V planes. That is, avoid the power planes under the INM, INP, and ACT pins. 84 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 In order to maintain proper LVDS timing, all LVDS traces must follow a controlled impedance design. In addition, all LVDS trace lengths must be equal and symmetrical; TI recommends keeping trace length variations less than 150 mil (0.150 inch or 3.81 mm). In addition, appropriate delay matching must be considered for the CW clock path, especially in systems with a high channel count. For example, if the clock delay is half of the 16X clock period, a phase error of 22.5°C can exist. Thus, the timing delay difference among channels contributes to the beamformer accuracy. Additional details on the NFBGA PCB layout techniques can be found in the Texas Instruments application report, MicroStar BGA Packaging Reference Guide (SSYZ015), which can be downloaded from www.ti.com. 12.2 Layout Example Figure 108 and Figure 109 illustrate example layouts for the top and bottom layers, respectively. CM_BYP1, CM_BYP2, VHIGH1, VHIGH2 decapacitors placed near the device. INPx, INMx and ACTx Routing Differential Clock Input Differential CW Output Differential ADC Clock LVDS Differential Routing Figure 108. Top Layer Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 85 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com Layout Example (continued) CM_BYP1, CM_BYP2, VHIGH1, VHIGH2 decapacitors placed near the device. INMx capacitor placed near the device. Different supply decapacitors placed near the device pins. Figure 109. Bottom Layer 86 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 Layout Example (continued) Figure 110 shows a routing example for the ground planes. Analog Ground (AVSS) Plane The INPx, INMx, and ACTx pin area is isolated from the ground plane. ADC Digital Ground (DVSS) Plane Figure 110. Ground Plane Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 87 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com Layout Example (continued) Figure 111, Figure 112, and Figure 113 illustrate routing examples for different power planes. The AVDD_1P8 power plane is routed in the same area as that of analog ground plane. The INPx, INMx, and ACTx pin area is isolated from the ground plane. ADC Digital Ground (DVSS) Plane Figure 111. AVDD_1P8 Power Plane 88 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 Layout Example (continued) Analog Ground (AVSS) Plane The INPx, INMx, and ACTx pin area is isolated from the ground plane. The AVDD_3P3 power plane is routed in the same area as that of the analog ground plane. ADC Digital Ground (DVSS) Plane The DVDD_1P8 power plane is routed in the same area as that of the digital ground plane. Figure 112. AVDD_3P3, DVDD_1P8 Power Planes Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 89 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com Layout Example (continued) The AVDD_5V power plane is routed in the same area as that of the analog ground plane. The INPx, INMx, and ACTx pin area is isolated from the ground plane. The DVDD_1P2 power plane is routed in the same area as that of the digital ground plane. Figure 113. AVDD_5V, DVDD_1P2 Power Planes 90 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 13 Register Maps 13.1 Serial Register Map The device has two voltage-controlled amplifier (VCA) dies and one analog-to-digital converter (ADC) die, as shown in Figure 114. Figure 114 also describes the channel mapping of VCA dies to the input pins. All dies share the same SPI control signals (SCLK, SDIN, and SEN). The address space of the programmable registers for the ADC die is from register 1 to register 60. By default, the address space of the programmable registers for the VCA dies are shared (that is, both VCA dies have an address space from register 192 to register 205). Therefore, the ADC and VCA dies can be programmed independently. Because the VCA dies share the same address space, these dies are programmed together. To program VCA die 1 and VCA die 2 independently, the address space for these dies must be separated by enabling the ADD_OFFSET bit (register 0, bit 2). All programmable bits and addresses are listed in this section. ADC VCA Die 1 IN2 VCA_IN1 VCA_OUT1 ADC_IN2 DOUT2 IN4 VCA_IN2 VCA_OUT2 ADC_IN4 DOUT4 IN6 VCA_IN3 VCA_OUT3 ADC_IN6 DOUT6 IN8 VCA_IN4 VCA_OUT4 ADC_IN8 DOUT8 IN10 VCA_IN5 VCA_OUT5 ADC_IN10 DOUT10 IN12 VCA_IN6 VCA_OUT6 ADC_IN12 DOUT12 IN14 VCA_IN7 VCA_OUT7 ADC_IN14 DOUT14 IN16 VCA_IN8 VCA_OUT8 ADC_IN16 DOUT16 VCA Die 2 IN1 VCA_IN1 VCA_OUT1 ADC_IN1 DOUT1 IN3 VCA_IN2 VCA_OUT2 ADC_IN3 DOUT3 IN5 VCA_IN3 VCA_OUT3 ADC_IN5 DOUT5 IN7 VCA_IN4 VCA_OUT4 ADC_IN7 DOUT7 IN9 VCA_IN5 VCA_OUT5 ADC_IN9 DOUT9 IN11 VCA_IN6 VCA_OUT6 ADC_IN11 DOUT11 IN13 VCA_IN7 VCA_OUT7 ADC_IN13 DOUT13 VCA_IN8 VCA_OUT8 ADC_IN15 DOUT15 IN15 Device Figure 114. Channel Mapping: VCA Dies A reset process is required at the device initialization stage. NOTE Initialization can be accomplished with a hardware reset by applying a positive pulse to the RESET pin. After reset, all ADC and VCA registers are set to 0 (default). Note that during register programming, all unlisted register bits must be set to 0. The Global Register is comprised of register 0 and controls both the VCA and ADC die. The ADC Registers include registers that control the ADC die. The VCA Registers include registers that control the VCA dies (that is, VCA die 1 and VCA die 2). Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 91 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com Serial Register Map (continued) 13.1.1 Global Register Map This section discusses the global register. A register map is available in Table 12. Table 12. Global Register Map REGISTER ADDRESS REGISTER DATA (1) DECIMAL HEX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD_ OFFSET REG_READ_ EN SOFTWARE_ RESET (1) The default value of all registers is 0. 13.1.1.1 Description of Global Register 13.1.1.1.1 Register 0 (address = 0h) Figure 115. Register 0 15 0 W-0h 14 0 W-0h 13 0 W-0h 12 0 W-0h 11 0 W-0h 10 0 W-0h 9 0 W-0h 8 0 W-0h 7 6 5 4 3 2 0 0 0 0 0 ADD_OFFSET W-0h W-0h W-0h W-0h W-0h W-0h 1 REG_READ_ EN W-0h 0 SOFTWARE_ RESET W-0h LEGEND: W = Write only; -n = value Table 13. Register 0 Field Descriptions Bit Field Type Reset Description 0 W 0h Must write 0 2 ADD_OFFSET W 0h 0 = Normal operation 1 = Separates the SPI address space of the VCA die 1 and VCA die 2. Set this bit to 1 to write register addresses 213, 215, 216, and 217. Otherwise set this bit to 0. 1 REG_READ_EN W 0h 0 = Register readout mode disabled 1 = Register readout mode enabled; see the Register Readout section for further details 0 SOFTWARE_RESET W 0h 0 = Disabled 1 = Enabled (this setting returns the device to a reset state). This bit is a self-clearing register bit. 15-3 92 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 13.1.2 ADC Register Map This section discusses the ADC and LVDS registers. A register map is available in Table 14. Table 14. ADC Register Map REGISTER DATA (1) REGISTER ADDRESS DECIMAL HEX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 LVDS_ RATE_2X 0 0 0 0 0 0 0 0 DIS_LVDS 1 0 1 0 GLOBAL_ PDN 2 2 PAT_MODES_FCLK[2:0] LOW_ LATENCY_ EN AVG_EN SEL_PRBS _PAT_ FCLK 3 3 SER_DATA_RATE DIG_GAIN _EN 0 4 4 5 5 7 7 8 8 11 B 13 D 14 15 OFFSET_ REMOVAL _START_ SEL OFFEST_ REMOVAL _START_ MANUAL OFFSET_CORR_DELAY _FROM_TX_TRIG[7:6] AUTO_OFFSET_REMOVAL_ACC_CYCLES[3:0] OFFSET_CORR_DELAY_FROM_TX_TRIG[5:0] DIG_ OFFSET_ EN 0 0 0 0 0 0 PAT_ SELECT_ IND PRBS_ SYNC PRBS_ MODE PRBS_EN MSB_ FIRST 0 0 0 0 0 0 0 0 CHOPPER _EN 0 0 0 0 0 0 0 ADC_RES CUSTOM_PATTERN[15:0] AUTO_OFFSET_REMOVAL_VAL_RD_CH_SEL[4:0] 0 0 0 0 0 0 0 AUTO_OFFSET_REMOVAL_VAL_RD[13:0] 0 0 0 EN_DITHE R 0 0 0 0 0 0 GAIN_CH1 0 OFFSET_CH1 E 0 0 OFFSET_CH1 F GAIN_CH2 0 OFFSET_CH2 16 10 0 0 OFFSET_CH2 17 11 GAIN_CH3 0 OFFSET_CH3 18 12 0 0 OFFSET_CH3 19 13 GAIN_CH4 0 OFFSET_CH4 20 14 0 0 21 15 23 17 0 0 0 0 0 0 0 0 18 PDN_DIG_ CH4 PDN_DIG_ CH3 PDN_DIG_ CH2 PDN_DIG_ CH1 PDN_ LVDS4 PDN_ LVDS3 PDN_ LVDS2 PDN_ LVDS1 24 (1) OFFSET_ REMOVAL _SELF SEL_PRBS _PAT_GBL PAT_MODES[2:0] PAT_PRBS _LVDS1 PAT_PRBS _LVDS2 PAT_PRBS _LVDS3 PAT_PRBS _LVDS4 OFFSET_CH4 PAT_LVDS1[2:0] HPF_ROU ND_EN PAT_LVDS2[2:0] PAT_LVDS3[2:0] PDN_ANA_ CH4 PDN_ANA_ CH3 PAT_LVDS4[2:0] PDN_ANA_ CH2 DIG_HPF_ EN_CH1-4 HPF_CORNER_CH1-4[3:0] PDN_ANA_ CH1 25 19 GAIN_CH5 0 OFFSET_CH5 26 1A 0 0 OFFSET_CH5 27 1B GAIN_CH6 0 OFFSET_CH6 28 1C 0 0 OFFSET_CH6 29 1D GAIN_CH7 0 OFFSET_CH7 30 1E 0 0 OFFSET_CH7 31 1F GAIN_CH8 0 OFFSET_CH8 32 20 0 0 OFFSET_CH8 INVERT_ LVDS4 INVERT_ LVDS3 0 0 INVERT_ LVDS2 INVERT_ LVDS1 Default value of all registers is 0. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 93 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com Table 14. ADC Register Map (continued) REGISTER DATA (1) REGISTER ADDRESS DECIMAL HEX 15 14 13 12 33 21 PAT_PRBS _LVDS5 PAT_PRBS _LVDS6 PAT_PRBS _LVDS7 PAT_PRBS _LVDS8 35 23 0 0 0 0 0 0 0 0 36 24 PDN_DIG_ CH8 PDN_DIG_ CH7 PDN_DIG_ CH6 PDN_DIG_ CH5 PDN_ LVDS8 PDN_ LVDS7 PDN_ LVDS6 PDN_ LVDS5 37 25 GAIN_CH9 0 38 26 0 0 OFFSET_CH9 39 27 GAIN_CH10 0 OFFSET_CH10 40 28 0 0 OFFSET_CH10 41 29 GAIN_CH11 0 OFFSET_CH11 42 2A 0 0 OFFSET_CH11 43 2B GAIN_CH12 0 OFFSET_CH12 44 2C 0 0 OFFSET_CH12 45 2D 47 2F 0 0 0 0 0 0 0 0 48 30 PDN_DIG_ CH12 PDN_DIG_ CH11 PDN_DIG_ CH10 PDN_DIG_ CH9 PDN_ LVDS12 PDN_ LVDS11 PDN_ LVDS10 PDN_ LVDS9 49 31 GAIN_CH13 0 OFFSET_CH13 50 32 0 0 OFFSET_CH13 51 33 GAIN_CH14 0 OFFSET_CH14 52 34 0 0 OFFSET_CH14 53 35 GAIN_CH15 0 OFFSET_CH15 54 36 0 0 OFFSET_CH15 55 37 GAIN_CH16 0 OFFSET_CH16 56 38 0 0 OFFSET_CH16 57 39 59 3B 0 0 0 0 0 0 0 0 60 3C PDN_DIG_ CH16 PDN_DIG_ CH15 PDN_DIG_ CH14 PDN_DIG_ CH13 PDN_ LVDS16 PDN_ LVDS15 PDN_ LVDS14 PDN_ LVDS13 PDN_ANA_ CH16 PDN_ANA_ CH15 PDN_ANA_ CH14 67 43 0 0 0 0 0 0 0 0 0 0 0 94 PAT_PRBS _LVDS9 PAT_PRBS _LVDS13 PAT_PRBS _LVDS10 PAT_PRBS _LVDS14 PAT_PRBS _LVDS11 PAT_PRBS _LVDS15 11 10 9 8 PAT_LVDS5[2:0] PAT_PRBS _LVDS12 6 5 4 PDN_ANA_ CH7 2 1 PAT_LVDS8[2:0] PDN_ANA_ CH6 PDN_ANA_ CH5 INVERT_ CH8 INVERT_ CH7 0 DIG_HPF_ EN_CH5-8 HPF_CORNER_CH5-8[3:0] PAT_LVDS7[2:0] PDN_ANA_ CH8 3 0 0 0 INVERT_ CH6 INVERT_ CH5 OFFSET_CH9 PAT_LVDS9[2:0] PAT_PRBS _LVDS16 7 PAT_LVDS6[2:0] PAT_LVDS10[2:0] PAT_LVDS13[2:0] 0 PAT_LVDS11[2:0] PDN_ANA_ CH12 PDN_ANA_ CH11 PAT_LVDS12[2:0] PDN_ANA_ CH10 PAT_LVDS14[2:0] PDN_ANA_ CH9 0 PIN_PAT_LVDS15[2:0] Submit Documentation Feedback DIG_HPF_ EN_ CH9-12 HPF_CORNER_CH9-12[3:0] INVERT_ CH12 INVERT_ CH11 0 0 INVERT_ CH10 INVERT_ CH9 DIG_HPF_ EN_ CH13-16 HPF_CORNER_CH13-16[3:0] PAT_LVDS16[2:0] PDN_ANA_ CH13 INVERT_ CH16 INVERT_ CH15 0 0 INVERT_ CH14 INVERT_ CH13 LVDS_DCLK_DELAY_PROG[3:0] 0 Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 13.1.2.1 Description of ADC Registers 13.1.2.1.1 Register 1 (address = 1h) Figure 116. Register 1 15 R/W-0h 14 LVDS_RATE_ 2X R/W-0h 7 0 R/W-0h 6 0 R/W-0h 0 13 12 11 10 9 8 0 0 0 0 0 0 R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 5 DIS_LVDS R/W-0h 4 1 W-1h 3 0 R/W-0h 2 1 W-1h 1 0 R/W-0h 0 GLOBAL_PDN R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 15. Register 1 Field Descriptions Bit Field Type Reset Description 15 0 R/W 0h Must write 0 14 LVDS_RATE_2X R/W 0h 0 = 1x rate; normal operation (default) 1 = 2x rate. This setting combines the data of two LVDS pairs into a single LVDS pair. This feature can be used when the ADC clock rate is low; see the LVDS Interface section for further details. 0 R/W 0h Must write 0 5 DIS_LVDS R/W 0h 0 = LVDS interface is enabled (default) 1 = LVDS interface is disabled 4 1 R/W 0h Must write 1 3 0 R/W 0h Must write 0 2 1 R/W 0h Must write 1 1 0 R/W 0h Must write 0 0 GLOBAL_PDN R/W 0h 0 = Device operates in normal mode (default) 1 = ADC enters in complete power-down mode 13-6 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 95 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 13.1.2.1.2 Register 2 (address = 2h) Figure 117. Register 2 15 14 13 PAT_MODES_FCLK[2:0] R/W-0h 7 PAT_ MODES[2:0] R/W-0h 6 SEL_PRBS_ PAT_GBL R/W-0h 12 LOW_ LATENCY_EN R/W-0h AVG_EN 4 5 11 9 R/W-0h 10 SEL_PRBS_ PAT_FCLK R/W-0h 3 2 1 8 PAT_MODES[2:0] R/W-0h 0 OFFSET_CORR_DELAY_FROM_TX_TRIG[5:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 16. Register 2 Field Descriptions Bit Field Type Reset Description PAT_MODES_FCLK[2:0] R/W 0h These bits enable different test patterns on the frame clock line; see Table 17 for bit descriptions and to the Test Patterns section for further details. 12 LOW_LATENCY_EN R/W 0h 0 = Default latency with digital features supported 1 = Low-latency with digital features bypassed 11 AVG_EN R/W 0h 0 = No averaging 1 = Enables averaging of two channels to improve signal-tonoise ratio (SNR); see the LVDS Interface section for further details. 10 SEL_PRBS_PAT_FCLK R/W 0h 0 = Normal operation 1 = Enables the PRBS pattern to be generated on fCLK; see the Test Patterns section for further details. 9-7 PAT_MODES[2:0] R/W 0h These bits enable different test patterns on the LVDS data lines; see Table 17 for bit descriptions and to the Test Patterns section for further details. SEL_PRBS_PAT_GBL R/W 0h 0 = Normal operation 1 = Enables the PRBS pattern to be generated; see the Test Patterns section for further details. OFFSET_CORR_DELAY_FROM_ TX_TRIG[5:0] R/W 0h 8-bit register to initiate offset correction after the TX_TRIG input pulse (each step is equivalent to one sample delay); the remaining two MSB bits are the OFFSET_CORR_DELAY_FROM_TX_TRIG[7:6] bits (bits 10-9) in register 3. 15-13 6 5-0 Table 17. Pattern Mode Bit Description PAT_MODES[2:0] 96 DESCRIPTION 000 Normal operation 001 Sync (half frame 0, half frame 1) 010 Alternate 0s and 1s 011 Custom pattern 100 All 1s 101 Toggle mode 110 All 0s 111 Ramp pattern Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 13.1.2.1.3 Register 3 (address = 3h) Figure 118. Register 3 15 14 12 11 SER_DATA_RATE DIG_GAIN_EN 0 R/W-0h R/W-0h R/W-0h 4 0 R/W-0h 3 0 R/W-0h 7 0 R/W-0h 6 0 R/W-0h 13 5 0 R/W-0h 10 9 OFFSET_CORR_DELAY_FROM _TX_TRIG[7:6] R/W-0h 2 0 R/W-0h 1 0 R/W-0h 8 DIG_ OFFSET_EN R/W-0h 0 0 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 18. Register 3 Field Descriptions Bit Field Type Reset Description SER_DATA_RATE R/W 0h These bits control the LVDS serialization rate. 000 = 12x 001 = 14x 100 = 16x 101, 110, 111, 010, 011 = Unused 12 DIG_GAIN_EN R/W 0h 0 = Digital gain disabled 1 = Digital gain enabled 11 0 R/W 0h Must write 0 OFFSET_CORR_DELAY_FROM_ TX_TRIG[7:6] R/W 0h 8-bit register to initiate offset correction after the TX_TRIG input pulse (each step is equivalent to one sample delay); the remaining six LSB bits are the OFFSET_CORR_DELAY_FROM_TX_TRIG[5:0] bits (bits 5-0) in register 2. DIG_OFFSET_EN R/W 0h 0 = Digital offset subtraction disabled 1 = Digital offset subtraction enabled 0 R/W 0h Must write 0 15-13 10-9 8 7-0 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 97 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 13.1.2.1.4 Register 4 (address = 4h) Figure 119. Register 4 15 OFFSET_ REMOVAL_ SELF R/W-0h 7 PRBS_ SYNC R/W-0h 14 13 12 11 10 9 8 0 0 0 0 0 0 PAT_ SELECT_IND R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 6 PRBS_ MODE R/W-0h 5 4 3 2 1 0 PRBS_EN MSB_FIRST 0 0 ADC_RES R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 19. Register 4 Field Descriptions Bit Field Type Reset Description 15 OFFSET_REMOVAL_SELF R/W 0h Auto offset removal mode is enabled when this bit is set to 1 14 OFFSET_REMOVAL_START_SEL R/W 0h Enable this bit to initiate offset correction with a pulse at the TX_TRIG pin, otherwise offset correction is initiated when the OFFSET_REMOVAL_START_MANUAL bit (bit 13) in register 4 is enabled. 13 OFFSET_REMOVAL_START_ MANUAL R/W 0h This bit initiates offset correction manually instead of with a TX_TRIG pulse AUTO_OFFSET_REMOVAL_ACC_ CYCLES R/W 0h These bits define the number of samples required to generate an offset in auto offset correction mode 8 PAT_SELECT_IND R/W 0h 0 = All LVDS output lines have the same pattern, as determined by the PAT_MODES[2:0] bits (register 2, bits 9-7) 1 = Different test patterns can be sent on different LVDS lines, depending upon the channel and register; see the Test Patterns section for further details. 7 PRBS_SYNC R/W 0h 0 = Normal operation 1 = PRBS generator is in a reset state 6 PRBS_MODE R/W 0h 0 = 23-bit PRBS generator 1 = 9-bit PRBS generator 5 PRBS_EN R/W 0h 0 = PRBS sequence generation block disabled 1 = PRBS sequence generation block enabled; see the Test Patterns section for further details. 4 MSB_FIRST R/W 0h 0 = The LSB is transmitted first on serialized output data 1 = The MSB is transmitted first on serialized output data 3 0 R/W 0h Must write 0 2 0 R/W 0h Must write 0 ADC_RES R/W 0h These bits control the ADC resolution. 00 = 12-bit resolution 01 = 14-bit resolution 10, 11 = Unused 12-9 1-0 98 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 13.1.2.1.5 Register 5 (address = 5h) Figure 120. Register 5 15 14 13 12 11 CUSTOM_PATTERN[15:0] R/W-0h 10 9 8 7 6 5 4 3 CUSTOM_PATTERN[15:0] R/W-0h 2 1 0 LEGEND: R/W = Read/Write; -n = value after reset Table 20. Register 5 Field Descriptions Bit 15-0 Field Type Reset Description CUSTOM_PATTERN[15:0] R/W 0h If the pattern mode is programmed to a custom pattern mode, then the custom pattern value can be provided by programming these bits; see the Test Patterns section for further details. 13.1.2.1.6 Register 7 (address = 7h) Figure 121. Register 7 15 14 13 12 AUTO_OFFSET_REMOVAL_VAL_RD_CH_SEL R/W-0h 7 0 R/W-0h 6 0 R/W-0h 5 0 R/W-0h 4 0 R/W-0h 11 10 0 R/W-0h 9 0 R/W-0h 8 0 R/W-0h 3 0 R/W-0h 2 0 R/W-0h 1 0 R/W-0h 0 CHOPPER_EN R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 21. Register 7 Field Descriptions Field Type Reset Description 15-11 Bit AUTO_OFFSET_REMOVAL_VAL_ RD_CH_SEL R/W 0h Write the channel number to read the offset value in auto offset correction mode for a corresponding channel number (read the offset value in register 8, bits 13-0) 10-1 0 R/W 0h Must write 0 CHOPPER_EN R/W 0h The chopper can be used to move low-frequency, 1 / f noise to an fS / 2 frequency. 0 = Chopper disabled 1 = Chopper enabled 0 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 99 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 13.1.2.1.7 Register 8 (address = 8h) Figure 122. Register 8 15 0 R/W-0h 14 0 R/W-0h 13 7 6 5 12 11 10 AUTO_OFFSET_REMOVAL_VAL_RD[13:0] R/W-0h 4 3 AUTO_OFFSET_REMOVAL_VAL_RD[13:0] R/W-0h 2 9 8 1 0 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 22. Register 8 Field Descriptions Bit Field Type Reset Description 15-14 0 R/W 0h Must write 0 13-0 AUTO_OFFSET_REMOVAL_VAL_ RD R/W 0h Read the offset value applied in auto offset correction mode for a specific channel number as defined in register 7, bits 15-11 13.1.2.1.8 Register 11 (address = Bh) Figure 123. Register 11 15 0 R/W-0h 14 0 R/W-0h 13 0 R/W-0h 12 0 R/W-0h 11 EN_DITHER R/W-0h 10 0 R/W-0h 9 0 R/W-0h 8 0 R/W-0h 7 0 R/W-0h 6 0 R/W-0h 5 0 R/W-0h 4 0 R/W-0h 3 0 R/W-0h 2 0 R/W-0h 1 0 R/W-0h 0 0 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 23. Register 11 Field Descriptions Bit 15-12 11 10-0 100 Field Type Reset Description 0 R/W 0h Must write 0 EN_DITHER R/W 0h Dither can be used to remove higher-order harmonics. 0 = Dither disabled 1 = Dither enable Note: Enabling the dither converts higher-order harmonics power in noise. Thus, enabling this mode removes harmonics but degrades SNR. 0 R/W 0h Must write 0 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 13.1.2.1.9 Register 13 (address = Dh) Figure 124. Register 13 15 14 7 6 13 GAIN_CH1 R/W-0h 12 5 4 11 3 10 0 R/W-0h 9 2 1 8 OFFSET_CH1 R/W-0h 0 OFFSET_CH1 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 24. Register 13 Field Descriptions Bit Field Type Reset Description GAIN_CH1 R/W 0h When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, then the digital gain value for channel 1 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, set the digital gain to N × 0.2 dB. 10 0 R/W 0h Must write 0 9-0 OFFSET_CH1 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 1 can be obtained with this 10bit register. The offset value is in twos complement format. Write the same offset value in register 14, bits 9-0. 15-11 13.1.2.1.10 Register 14 (address = Eh) Figure 125. Register 14 15 0 R/W-0h 14 0 R/W-0h 13 0 R/W-0h 12 0 R/W-0h 11 0 R/W-0h 10 0 R/W-0h 9 7 6 5 4 3 2 1 8 OFFSET_CH1 R/W-0h 0 OFFSET_CH1 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 25. Register 14 Field Descriptions Bit 15-10 9-0 Field Type Reset Description 0 R/W 0h Must write 0 OFFSET_CH1 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 1 can be obtained with this 10bit register. The offset value is in twos complement format. Write the same offset value in register 13, bits 9-0. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 101 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 13.1.2.1.11 Register 15 (address = Fh) Figure 126. Register 15 15 14 7 13 GAIN_CH2 R/W-0h 12 5 4 6 11 3 10 0 R/W-0h 9 2 1 8 OFFSET_CH2 R/W-0h 0 OFFSET_CH2 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 26. Register 15 Field Descriptions Bit Field Type Reset Description GAIN_CH2 R/W 0h When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, then the digital gain value for channel 2 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, set the digital gain to N × 0.2 dB. 10 0 R/W 0h Must write 0 9-0 OFFSET_CH2 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 2 can be obtained with this 10bit register. The offset value is in twos complement format. Write the same offset value in register 16, bits 9-0. 15-11 13.1.2.1.12 Register 16 (address = 10h) Figure 127. Register 16 15 0 R/W-0h 14 0 R/W-0h 13 0 R/W-0h 12 0 R/W-0h 11 0 R/W-0h 10 0 R/W-0h 9 7 6 5 4 3 2 1 8 OFFSET_CH2 R/W-0h 0 OFFSET_CH2 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 27. Register 16 Field Descriptions Bit 15-10 9-0 102 Field Type Reset Description 0 R/W 0h Must write 0 OFFSET_CH2 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 2 can be obtained with this 10bit register. The offset value is in twos complement format. Write the same offset value in register 15, bits 9-0. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 13.1.2.1.13 Register 17 (address = 11h) Figure 128. Register 17 15 14 7 6 13 GAIN_CH3 R/W-0h 12 5 4 11 3 10 0 R/W-0h 9 2 1 8 OFFSET_CH3 R/W-0h 0 OFFSET_CH3 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 28. Register 17 Field Descriptions Bit Field Type Reset Description GAIN_CH3 R/W 0h When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, then the digital gain value for channel 3 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, set the digital gain to N × 0.2 dB. 10 0 R/W 0h Must write 0 9-0 OFFSET_CH3 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 3 can be obtained with this 10bit register. The offset value is in twos complement format. Write the same offset value in register 18, bits 9-0. 15-11 13.1.2.1.14 Register 18 (address = 12h) Figure 129. Register 18 15 0 R/W-0h 14 0 R/W-0h 13 0 R/W-0h 12 0 R/W-0h 11 0 R/W-0h 10 0 R/W-0h 9 7 6 5 4 3 2 1 8 OFFSET_CH3 R/W-0h 0 OFFSET_CH3 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 29. Register 18 Field Descriptions Bit 15-10 9-0 Field Type Reset Description 0 R/W 0h Must write 0 OFFSET_CH3 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 3 can be obtained with this 10bit register. The offset value is in twos complement format. Write the same offset value in register 19, bits 9-0. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 103 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 13.1.2.1.15 Register 19 (address = 13h) Figure 130. Register 19 15 14 7 13 GAIN_CH4 R/W-0h 12 5 4 6 11 3 10 0 R/W-0h 9 2 1 8 OFFSET_CH4 R/W-0h 0 OFFSET_CH4 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 30. Register 19 Field Descriptions Bit Field Type Reset Description GAIN_CH4 R/W 0h When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, then the digital gain value for channel 4 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, set the digital gain to N × 0.2 dB. 10 0 R/W 0h Must write 0 9-0 OFFSET_CH4 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 4 can be obtained with this 10bit register. The offset value is in twos complement format. Write the same offset value in register 20, bits 9-0. 15-11 13.1.2.1.16 Register 20 (address = 14h) Figure 131. Register 20 15 0 R/W-0h 14 0 R/W-0h 13 0 R/W-0h 12 0 R/W-0h 11 0 R/W-0h 10 0 R/W-0h 9 7 6 5 4 3 2 1 8 OFFSET_CH4 R/W-0h 0 OFFSET_CH4 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 31. Register 20 Field Descriptions Bit 15-10 9-0 104 Field Type Reset Description 0 R/W 0h Must write 0 OFFSET_CH4 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 4 can be obtained with this 10bit register. The offset value is in twos complement format. Write the same offset value in register 19, bits 9-0. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 13.1.2.1.17 Register 21 (address = 15h) Figure 132. Register 21 15 PAT_PRBS_ LVDS1 R/W-0h 14 PAT_PRBS_ LVDS2 R/W-0h 13 PAT_PRBS_ LVDS3 R/W-0h 12 PAT_PRBS_ LVDS4 R/W-0h 11 7 6 5 HPF_ROUND_ EN R/W-0h 4 3 PAT_LVDS2[2:0] R/W-0h 10 9 8 PAT_ LVDS2[2:0] R/W-0h 1 0 DIG_HPF_EN_ CH1-4 R/W-0h PAT_LVDS1[2:0] R/W-0h 2 HPF_CORNER_CH1-4[3:0] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 32. Register 21 Field Descriptions Bit Field Type Reset Description 15 PAT_PRBS_LVDS1 R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the PRBS pattern on LVDS output 1 can be enabled with this bit; see the Test Patterns section for further details. 14 PAT_PRBS_LVDS2 R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the PRBS pattern on LVDS output 2 can be enabled with this bit; see the Test Patterns section for further details. 13 PAT_PRBS_LVDS3 R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the PRBS pattern on LVDS output 3 can be enabled with this bit; see the Test Patterns section for further details. 12 PAT_PRBS_LVDS4 R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the PRBS pattern on LVDS output 4 can be enabled with this bit; see the Test Patterns section for further details. 11-9 PAT_LVDS1[2:0] R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the different pattern on LVDS output 1 can be programmed with these bits; see Table 33 for bit descriptions. 8-6 PAT_LVDS2[2:0] R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the different pattern on LVDS output 2 can be programmed with these bits; see Table 33 for bit descriptions. 5 HPF_ROUND_EN R/W 0h 0 = Rounding in the ADC HPF is disabled. HPF output is truncated to be mapped to the ADC resolution bits. 1 = HPF output is mapped to the ADC resolution bits by the round-off operation. HPF_CORNER_CH1-4[3:0] R/W 0h When the DIG_HPF_EN_CH1-4 bit is set to 1, then the digital HPF characteristic for the corresponding channels can be programmed by setting the value of k with these bits. Characteristics of a digital high-pass transfer function applied to the output data for a given value of k is defined by: 4-1 Y(n) = 2k 2k + 1 [x(n) - x(n - 1) + y(n - 1)] Note that the value of k can be from 2 to 10 (0010b to 1010b); see the Digital HPF section for further details. 0 DIG_HPF_EN_CH1-4 R/W 0h 0 = Digital HPF disabled for channels 1 to 4 (default) 1 = Enables digital HPF for channels 1 to 4 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 105 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com Table 33. Pattern Mode Bit Description PAT_MODES[2:0] DESCRIPTION 000 Normal operation 001 Sync (half frame 0, half frame 1) 010 Alternate 0s and 1s 011 Custom pattern 100 All 1s 101 Toggle mode 110 All 0s 111 Ramp pattern 13.1.2.1.18 Register 23 (address = 17h) Figure 133. Register 23 15 0 R/W-0h 14 0 R/W-0h 13 0 R/W-0h 12 0 R/W-0h 11 0 R/W-0h 10 0 R/W-0h 9 0 R/W-0h 8 0 R/W-0h 7 6 PAT_LVDS3[2:0] R/W-0h 5 4 3 PAT_LVDS4[2:0] R/W-0h 2 1 0 R/W-0h 0 0 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 34. Register 23 Field Descriptions Bit 106 Field Type Reset Description 15-8 0 R/W 0h Must write 0 7-5 PAT_LVDS3[2:0] R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the different pattern on LVDS output 3 can be programmed with these bits; see Table 33 for bit descriptions. 4-2 PAT_LVDS4[2:0] R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the different pattern on LVDS output 4 can be programmed with these bits; see Table 33 for bit descriptions. 1-0 0 R/W 0h Must write 0 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 13.1.2.1.19 Register 24 (address = 18h) Figure 134. Register 24 15 PDN_DIG_ CH4 R/W-0h 14 PDN_DIG_ CH3 R/W-0h 13 PDN_DIG_ CH2 R/W-0h 12 PDN_DIG_ CH1 R/W-0h 11 10 9 8 PDN_LVDS4 PDN_LVDS3 PDN_LVDS2 PDN_LVDS1 R/W-0h R/W-0h R/W-0h R/W-0h 7 PDN_ANA_ CH4 R/W-0h 6 PDN_ANA_ CH3 R/W-0h 5 PDN_ANA_ CH2 R/W-0h 4 PDN_ANA_ CH1 R/W-0h 3 INVERT_ LVDS4 R/W-0h 2 INVERT_ LVDS3 R/W-0h 1 INVERT_ LVDS2 R/W-0h 0 INVERT_ LVDS1 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 35. Register 24 Field Descriptions Bit Field Type Reset Description 15 PDN_DIG_CH4 R/W 0h 0 = Normal operation (default) 1 = Powers down the digital block for channel 4 14 PDN_DIG_CH3 R/W 0h 0 = Normal operation (default) 1 = Powers down the digital block for channel 3 13 PDN_DIG_CH2 R/W 0h 0 = Normal operation (default) 1 = Powers down the digital block for channel2 12 PDN_DIG_CH1 R/W 0h 0 = Normal operation (default) 1 = Powers down the digital block for channel 1 11 PDN_LVDS4 R/W 0h 0 = Normal operation (default) 1 = Powers down LVDS output line 4 10 PDN_LVDS3 R/W 0h 0 = Normal operation (default) 1 = Powers down LVDS output line 3 9 PDN_LVDS2 R/W 0h 0 = Normal operation (default) 1 = Powers down LVDS output line 2 8 PDN_LVDS1 R/W 0h 0 = Normal operation (default) 1 = Powers down LVDS output line 1 7 PDN_ANA_CH4 R/W 0h 0 = Normal operation (default) 1 = Powers down the analog block for channel 4 6 PDN_ANA_CH3 R/W 0h 0 = Normal operation (default) 1 = Powers down the analog block for channel 3 5 PDN_ANA_CH2 R/W 0h 0 = Normal operation (default) 1 = Powers down the analog block for channel 2 4 PDN_ANA_CH1 R/W 0h 0 = Normal operation (default) 1 = Powers down the analog block for channel 1 3 INVERT_LVDS4 R/W 0h 0 = Normal operation (default) 1 = Inverts digital output data sent on LVDS output line 4 2 INVERT_LVDS3 R/W 0h 0 = Normal operation (default) 1 = Inverts digital output data sent on LVDS output line 3 1 INVERT_LVDS2 R/W 0h 0 = Normal operation (default) 1 = Inverts digital output data sent on LVDS output line 2 0 INVERT_LVDS1 R/W 0h 0 = Normal operation (default) 1 = Inverts digital output data sent on LVDS output line 1 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 107 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 13.1.2.1.20 Register 25 (address = 19h) Figure 135. Register 25 15 14 7 13 GAIN_CH5 R/W-0h 12 5 4 6 11 3 10 0 R/W-0h 9 2 1 8 OFFSET_CH5 R/W-0h 0 OFFSET_CH5 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 36. Register 25 Field Descriptions Bit Field Type Reset Description GAIN_CH5 R/W 0h When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, then the digital gain value for channel 5 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, set the digital gain to N × 0.2 dB. 10 0 R/W 0h Must write 0 9-0 OFFSET_CH5 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 5 can be obtained with this 10bit register. The offset value is in twos complement format. Write the same offset value in register 26, bits 9-0. 15-11 13.1.2.1.21 Register 26 (address = 1Ah) Figure 136. Register 26 15 0 R/W-0h 14 0 R/W-0h 13 0 R/W-0h 12 0 R/W-0h 11 0 R/W-0h 10 0 R/W-0h 9 7 6 5 4 3 2 1 8 OFFSET_CH5 R/W-0h 0 OFFSET_CH5 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 37. Register 26 Field Descriptions Bit 15-10 9-0 108 Field Type Reset Description 0 R/W 0h Must write 0 OFFSET_CH5 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 5 can be obtained with this 10bit register. The offset value is in twos complement format. Write the same offset value in register 25, bits 9-0. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 13.1.2.1.22 Register 27 (address = 1Bh) Figure 137. Register 27 15 14 7 6 13 GAIN_CH6 R/W-0h 12 5 4 11 3 10 0 R/W-0h 9 2 1 8 OFFSET_CH6 R/W-0h 0 OFFSET_CH6 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 38. Register 27 Field Descriptions Bit Field Type Reset Description GAIN_CH6 R/W 0h When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, then the digital gain value for channel 6 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, set the digital gain to N × 0.2 dB. 10 0 R/W 0h Must write 0 9-0 OFFSET_CH6 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 6 can be obtained with this 10bit register. The offset value is in twos complement format. Write the same offset value in register 28, bits 9-0. 15-11 13.1.2.1.23 Register 28 (address = 1Ch) Figure 138. Register 28 15 0 R/W-0h 14 0 R/W-0h 13 0 R/W-0h 12 0 R/W-0h 11 0 R/W-0h 10 0 R/W-0h 9 7 6 5 4 3 2 1 8 OFFSET_CH6 R/W-0h 0 OFFSET_CH6 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 39. Register 28 Field Descriptions Bit 15-10 9-0 Field Type Reset Description 0 R/W 0h Must write 0 OFFSET_CH6 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 6 can be obtained with this 10bit register. The offset value is in twos complement format. Write the same offset value in register 27, bits 9-0. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 109 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 13.1.2.1.24 Register 29 (address = 1Dh) Figure 139. Register 29 15 14 7 13 GAIN_CH7 R/W-0h 12 5 4 6 11 3 10 0 R/W-0h 9 2 1 8 OFFSET_CH7 R/W-0h 0 OFFSET_CH7 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 40. Register 29 Field Descriptions Bit Field Type Reset Description GAIN_CH7 R/W 0h When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, then the digital gain value for channel 7 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, set the digital gain to N × 0.2 dB. 10 0 R/W 0h Must write 0 9-0 OFFSET_CH7 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 7 can be obtained with this 10bit register. The offset value is in twos complement format. Write the same offset value in register 30, bits 9-0. 15-11 13.1.2.1.25 Register 30 (address = 1Eh) Figure 140. Register 30 15 0 R/W-0h 14 0 R/W-0h 13 0 R/W-0h 12 0 R/W-0h 11 0 R/W-0h 10 0 R/W-0h 9 7 6 5 4 3 2 1 8 OFFSET_CH7 R/W-0h 0 OFFSET_CH7 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 41. Register 30 Field Descriptions Bit 15-10 9-0 110 Field Type Reset Description 0 R/W 0h Must write 0 OFFSET_CH7 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 7 can be obtained with this 10bit register. The offset value is in twos complement format. Write the same offset value in register 29, bits 9-0. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 13.1.2.1.26 Register 31 (address = 1Fh) Figure 141. Register 31 15 14 7 6 13 GAIN_CH8 R/W-0h 12 5 4 11 3 10 0 R/W-0h 9 2 1 8 OFFSET_CH8 R/W-0h 0 OFFSET_CH8 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 42. Register 31 Field Descriptions Bit Field Type Reset Description GAIN_CH8 R/W 0h When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, then the digital gain value for channel 8 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, set the digital gain to N × 0.2 dB. 10 0 R/W 0h Must write 0 9-0 OFFSET_CH8 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 8 can be obtained with this 10bit register. The offset value is in twos complement format. Write the same offset value in register 32, bits 9-0. 15-11 13.1.2.1.27 Register 32 (address = 20h) Figure 142. Register 32 15 0 R/W-0h 14 0 R/W-0h 13 0 R/W-0h 12 0 R/W-0h 11 0 R/W-0h 10 0 R/W-0h 9 7 6 5 4 3 2 1 8 OFFSET_CH8 R/W-0h 0 OFFSET_CH8 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 43. Register 32 Field Descriptions Bit 15-10 9-0 Field Type Reset Description 0 R/W 0h Must write 0 OFFSET_CH8 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 16 can be obtained with this 10-bit register. The offset value is in twos complement format. Write the same offset value in register 31, bits 9-0. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 111 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 13.1.2.1.28 Register 33 (address = 21h) Figure 143. Register 33 15 PAT_PRBS_ LVDS5 R/W-0h 14 PAT_PRBS_ LVDS6 R/W-0h 13 PAT_PRBS_ LVDS7 R/W-0h 12 PAT_PRBS_ LVDS8 R/W-0h 11 7 6 5 4 3 10 9 8 PAT_ LVDS6[2:0] R/W-0h 1 0 DIG_HPF_EN_ CH5-8 R/W-0h PAT_LVDS5[2:0] R/W-0h 2 PAT_LVDS6[2:0] 0 HPF_CORNER_CH5-8[3:0] R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 44. Register 33 Field Descriptions Bit Field Type Reset Description 15 PAT_PRBS_LVDS5 R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the PRBS pattern on LVDS output 5 can be enabled with this bit; see the Test Patterns section for further details. 14 PAT_PRBS_LVDS6 R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the PRBS pattern on LVDS output 6 can be enabled with this bit; see the Test Patterns section for further details. 13 PAT_PRBS_LVDS7 R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the PRBS pattern on LVDS output 7 can be enabled with this bit; see the Test Patterns section for further details. 12 PAT_PRBS_LVDS8 R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the PRBS pattern on LVDS output 8 can be enabled with this bit; see the Test Patterns section for further details. 11-9 PAT_LVDS5[2:0] R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the different pattern on LVDS output 5 can be programmed with these bits; see Table 33 for bit descriptions. 8-6 PAT_LVDS6[2:0] R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the different pattern on LVDS output 6 can be programmed with these bits; see Table 33 for bit descriptions. 0 R/W 0h Must write 0 HPF_CORNER_CH5-8[3:0] R/W 0h When the DIG_HPF_EN_CH5-8 bit is set to 1, then the digital HPF characteristic for the corresponding channels can be programmed by setting the value of k with these bits. Characteristics of a digital high-pass transfer function applied to the output data for a given value of k is defined by: 5 4-1 Y(n) = 2k 2k + 1 [x(n) - x(n - 1) + y(n - 1)] Note that the value of k can be from 2 to 10 (0010b to 1010b); see the Digital HPF section for further details. 0 112 DIG_HPF_EN_CH5-8 R/W 0h 0 = Digital HPF disabled for channels 5 to 8 (default) 1 = Enables digital HPF for channels 5 to 8 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 13.1.2.1.29 Register 35 (address = 23h) Figure 144. Register 35 15 0 R/W-0h 14 0 R/W-0h 13 0 R/W-0h 12 0 R/W-0h 11 0 R/W-0h 10 0 R/W-0h 9 0 R/W-0h 8 0 R/W-0h 7 6 PAT_LVDS7[2:0] R/W-0h 5 4 3 PAT_LVDS8[2:0] R/W-0h 2 1 0 R/W-0h 0 0 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 45. Register 35 Field Descriptions Bit Field Type Reset Description 15-8 0 R/W 0h Must write 0 7-5 PAT_LVDS7[2:0] R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the different pattern on LVDS output 7 can be programmed with these bits; see Table 33 for bit descriptions. 4-2 PAT_LVDS8[2:0] R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the different pattern on LVDS output 8 can be programmed with these bits; see Table 33 for bit descriptions. 1-0 0 R/W 0h Must write 0 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 113 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 13.1.2.1.30 Register 36 (address = 24h) Figure 145. Register 36 15 PDN_DIG_ CH8 R/W-0h 14 PDN_DIG_ CH7 R/W-0h 13 PDN_DIG_ CH6 R/W-0h 12 PDN_DIG_ CH5 R/W-0h 11 10 9 8 PDN_LVDS8 PDN_LVDS7 PDN_LVDS6 PDN_LVDS5 R/W-0h R/W-0h R/W-0h R/W-0h 7 PDN_ANA_ CH8 R/W-0h 6 PDN_ANA_ CH7 R/W-0h 5 PDN_ANA_ CH6 R/W-0h 4 PDN_ANA_ CH5 R/W-0h 3 INVERT_ CH8 R/W-0h 2 INVERT_ CH7 R/W-0h 1 INVERT_ CH6 R/W-0h 0 INVERT_ CH5 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 46. Register 36 Field Descriptions 114 Bit Field Type Reset Description 15 PDN_DIG_CH8 R/W 0h 0 = Normal operation (default) 1 = Powers down the digital block for channel 8 14 PDN_DIG_CH7 R/W 0h 0 = Normal operation (default) 1 = Powers down the digital block for channel 7 13 PDN_DIG_CH6 R/W 0h 0 = Normal operation (default) 1 = Powers down the digital block for channel 6 12 PDN_DIG_CH5 R/W 0h 0 = Normal operation (default) 1 = Powers down the digital block for channel 5 11 PDN_LVDS8 R/W 0h 0 = Normal operation (default) 1 = Powers down LVDS output line 8 10 PDN_LVDS7 R/W 0h 0 = Normal operation (default) 1 = Powers down LVDS output line 7 9 PDN_LVDS6 R/W 0h 0 = Normal operation (default) 1 = Powers down LVDS output line 6 8 PDN_LVDS5 R/W 0h 0 = Normal operation (default) 1 = Powers down LVDS output line 5 7 PDN_ANA_CH8 R/W 0h 0 = Normal operation (default) 1 = Powers down the analog block for channel 8 6 PDN_ANA_CH7 R/W 0h 0 = Normal operation (default) 1 = Powers down the analog block for channel 7 5 PDN_ANA_CH6 R/W 0h 0 = Normal operation (default) 1 = Powers down the analog block for channel 6 4 PDN_ANA_CH5 R/W 0h 0 = Normal operation (default) 1 = Powers down the analog block for channel 5 3 INVERT_CH8 R/W 0h 0 = Normal operation (default) 1 = Inverts digital output data sent on LVDS output line 8 2 INVERT_CH7 R/W 0h 0 = Normal operation (default) 1 = Inverts digital output data sent on LVDS output line 7 1 INVERT_CH6 R/W 0h 0 = Normal operation (default) 1 = Inverts digital output data sent on LVDS output line 6 0 INVERT_CH5 R/W 0h 0 = Normal operation (default) 1 = Inverts digital output data sent on LVDS output line 5 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 13.1.2.1.31 Register 37 (address = 25h) Figure 146. Register 37 15 14 7 6 13 GAIN_CH9 R/W-0h 12 5 4 11 3 10 0 R/W-0h 9 2 1 8 OFFSET_CH9 R/W-0h 0 OFFSET_CH9 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 47. Register 37 Field Descriptions Bit Field Type Reset Description GAIN_CH9 R/W 0h When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, then the digital gain value for channel 9 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, set the digital gain to N × 0.2 dB. 10 0 R/W 0h Must write 0 9-0 OFFSET_CH9 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 9 can be obtained with this 10bit register. The offset value is in twos complement format. Write the same offset value in register 38, bits 9-0. 15-11 13.1.2.1.32 Register 38 (address = 26h) Figure 147. Register 38 15 0 R/W-0h 14 0 R/W-0h 13 0 R/W-0h 12 0 R/W-0h 11 0 R/W-0h 10 0 R/W-0h 9 7 6 5 4 3 2 1 8 OFFSET_CH9 R/W-0h 0 OFFSET_CH9 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 48. Register 38 Field Descriptions Bit 15-10 9-0 Field Type Reset Description 0 R/W 0h Must write 0 OFFSET_CH9 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 9 can be obtained with this 10bit register. The offset value is in twos complement format. Write the same offset value in register 37, bits 9-0. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 115 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 13.1.2.1.33 Register 39 (address = 27h) Figure 148. Register 39 15 14 7 13 GAIN_CH10 R/W-0h 12 5 4 6 11 3 10 0 R/W-0h 9 2 1 8 OFFSET_CH10 R/W-0h 0 OFFSET_CH10 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 49. Register 39 Field Descriptions Bit Field Type Reset Description GAIN_CH10 R/W 0h When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, then the digital gain value for channel 10 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, set the digital gain to N × 0.2 dB. 10 0 R/W 0h Must write 0 9-0 OFFSET_CH10 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 10 can be obtained with this 10-bit register. The offset value is in twos complement format. Write the same offset value in register 40, bits 9-0. 15-11 13.1.2.1.34 Register 40 (address = 28h) Figure 149. Register 40 15 0 R/W-0h 14 0 R/W-0h 13 0 R/W-0h 12 0 R/W-0h 11 0 R/W-0h 10 0 R/W-0h 9 7 6 5 4 3 2 1 8 OFFSET_CH10 R/W-0h 0 OFFSET_CH10 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 50. Register 40 Field Descriptions Bit 15-10 9-0 116 Field Type Reset Description 0 R/W 0h Must write 0 OFFSET_CH10 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 10 can be obtained with this 10-bit register. The offset value is in twos complement format. Write the same offset value in register 39, bits 9-0. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 13.1.2.1.35 Register 41 (address = 29h) Figure 150. Register 41 15 14 7 6 13 GAIN_CH11 R/W-0h 12 5 4 11 3 10 0 R/W-0h 9 2 1 8 OFFSET_CH11 R/W-0h 0 OFFSET_CH11 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 51. Register 41 Field Descriptions Bit Field Type Reset Description GAIN_CH11 R/W 0h When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, then the digital gain value for channel 11 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, set the digital gain to N × 0.2 dB. 10 0 R/W 0h Must write 0 9-0 OFFSET_CH11 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 11 can be obtained with this 10-bit register. The offset value is in twos complement format. Write the same offset value in register 42, bits 9-0. 15-11 13.1.2.1.36 Register 42 (address = 2Ah) Figure 151. Register 42 15 0 R/W-0h 14 0 R/W-0h 13 0 R/W-0h 12 0 R/W-0h 11 0 R/W-0h 10 0 R/W-0h 9 7 6 5 4 3 2 1 8 OFFSET_CH11 R/W-0h 0 OFFSET_CH11 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 52. Register 42 Field Descriptions Bit 15-10 9-0 Field Type Reset Description 0 R/W 0h Must write 0 OFFSET_CH11 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 11 can be obtained with this 10-bit register. The offset value is in twos complement format. Write the same offset value in register 41, bits 9-0. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 117 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 13.1.2.1.37 Register 43 (address = 2Bh) Figure 152. Register 43 15 14 7 13 GAIN_CH12 R/W-0h 12 5 4 6 11 3 10 0 R/W-0h 9 2 1 8 OFFSET_CH12 R/W-0h 0 OFFSET_CH12 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 53. Register 43 Field Descriptions Bit Field Type Reset Description GAIN_CH12 R/W 0h When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, then the digital gain value for channel 12 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, set the digital gain to N × 0.2 dB. 10 0 R/W 0h Must write 0 9-0 OFFSET_CH12 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 12 can be obtained with this 10-bit register. The offset value is in twos complement format. Write the same offset value in register 44, bits 9-0. 15-11 13.1.2.1.38 Register 44 (address = 2Ch) Figure 153. Register 44 15 0 R/W-0h 14 0 R/W-0h 13 0 R/W-0h 12 0 R/W-0h 11 0 R/W-0h 10 0 R/W-0h 9 7 6 5 4 3 2 1 8 OFFSET_CH12 R/W-0h 0 OFFSET_CH12 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 54. Register 44 Field Descriptions Bit 15-10 9-0 118 Field Type Reset Description 0 R/W 0h Must write 0 OFFSET_CH12 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 12 can be obtained with this 10-bit register. The offset value is in twos complement format. Write the same offset value in register 43, bits 9-0. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 13.1.2.1.39 Register 45 (address = 2Dh) Figure 154. Register 45 15 PAT_PRBS_ LVDS9 R/W-0h 14 PAT_PRBS_ LVDS10 R/W-0h 13 PAT_PRBS_ LVDS11 R/W-0h 12 PAT_PRBS_ LVDS12 R/W-0h 11 10 7 6 5 4 3 PAT_LVDS10[2:0] 0 HPF_CORNER_CH9-12[3:0] R/W-0h R/W-0h R/W-0h 9 8 PAT_ LVDS10[2:0] R/W-0h 1 0 DIG_HPF_EN_ CH9-12 R/W-0h PAT_LVDS9[2:0] R/W-0h 2 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 55. Register 45 Field Descriptions Bit Field Type Reset Description 15 PAT_PRBS_LVDS9 R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the PRBS pattern on LVDS output 9 can be enabled with this bit; see the Test Patterns section for further details. 14 PAT_PRBS_LVDS10 R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the PRBS pattern on LVDS output 10 can be enabled with this bit; see the Test Patterns section for further details. 13 PAT_PRBS_LVDS11 R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the PRBS pattern on LVDS output 11 can be enabled with this bit; see the Test Patterns section for further details. 12 PAT_PRBS_LVDS12 R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the PRBS pattern on LVDS output 12 can be enabled with this bit; see the Test Patterns section for further details. 11-9 PAT_LVDS9[2:0] R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the different pattern on LVDS output 9 can be programmed with these bits; see Table 33 for bit descriptions. 8-6 PAT_LVDS10[2:0] R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the different pattern on LVDS output 10 can be programmed with these bits; see Table 33 for bit descriptions. 0 R/W 0h Must write 0 HPF_CORNER_CH9-12[3:0] R/W 0h When the DIG_HPF_EN_CH9-12 bit is set to 1, then the digital HPF characteristic for the corresponding channels can be programmed by setting the value of k with these bits. Characteristics of a digital high-pass transfer function applied to the output data for a given value of k is defined by: 5 4-1 Y(n) = 2k 2k + 1 [x(n) - x(n - 1) + y(n - 1)] Note that the value of k can be from 2 to 10 (0010b to 1010b); see the Digital HPF section for further details. 0 DIG_HPF_EN_CH9-12 R/W 0h 0 = Digital HPF disabled for channels 9 to 12 (default) 1 = Enables digital HPF for channels 9 to 12 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 119 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 13.1.2.1.40 Register 47 (address = 2Fh) Figure 155. Register 47 15 0 R/W-0h 14 0 R/W-0h 13 0 R/W-0h 12 0 R/W-0h 11 0 R/W-0h 10 0 R/W-0h 9 0 R/W-0h 8 0 R/W-0h 7 6 PAT_LVDS11[2:0] R/W-0h 5 4 3 PAT_LVDS12[2:0] R/W-0h 2 1 0 R/W-0h 0 0 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 56. Register 47 Field Descriptions Bit 15-18 120 Field Type Reset Description 0 R/W 0h Must write 0 7-5 PAT_LVDS11[2:0] R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the different pattern on LVDS output 11 can be programmed with these bits; see Table 33 for bit descriptions. 4-2 PAT_LVDS12[2:0] R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the different pattern on LVDS output 12 can be programmed with these bits; see Table 33 for bit descriptions. 1-0 0 R/W 0h Must write 0 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 13.1.2.1.41 Register 48 (address = 30h) Figure 156. Register 48 15 PDN_DIG_ CH12 R/W-0h 14 PDN_DIG_ CH11 R/W-0h 13 PDN_DIG_ CH10 R/W-0h 12 PDN_DIG_ CH9 R/W-0h 11 10 9 8 PDN_LVDS12 PDN_LVDS11 PDN_LVDS10 PDN_LVDS9 R/W-0h R/W-0h R/W-0h R/W-0h 7 PDN_ANA_ CH12 R/W-0h 6 PDN_ANA_ CH11 R/W-0h 5 PDN_ANA_ CH10 R/W-0h 4 PDN_ANA_ CH9 R/W-0h 3 INVERT_ CH12 R/W-0h 2 INVERT_ CH11 R/W-0h 1 INVERT_ CH10 R/W-0h 0 INVERT_ CH9 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 57. Register 48 Field Descriptions Bit Field Type Reset Description 15 PDN_DIG_CH12 R/W 0h 0 = Normal operation (default) 1 = Powers down the digital block for channel 12 14 PDN_DIG_CH11 R/W 0h 0 = Normal operation (default) 1 = Powers down the digital block for channel 11 13 PDN_DIG_CH10 R/W 0h 0 = Normal operation (default) 1 = Powers down the digital block for channel 10 12 PDN_DIG_CH9 R/W 0h 0 = Normal operation (default) 1 = Powers down the digital block for channel 9 11 PDN_LVDS12 R/W 0h 0 = Normal operation (default) 1 = Powers down LVDS output line 12 10 PDN_LVDS11 R/W 0h 0 = Normal operation (default) 1 = Powers down LVDS output line 11 9 PDN_LVDS10 R/W 0h 0 = Normal operation (default) 1 = Powers down LVDS output line 10 8 PDN_LVDS9 R/W 0h 0 = Normal operation (default) 1 = Powers down LVDS output line 9 7 PDN_ANA_CH12 R/W 0h 0 = Normal operation (default) 1 = Powers down the analog block for channel 12 6 PDN_ANA_CH11 R/W 0h 0 = Normal operation (default) 1 = Powers down the analog block for channel 11 5 PDN_ANA_CH10 R/W 0h 0 = Normal operation (default) 1 = Powers down the analog block for channel 10 4 PDN_ANA_CH9 R/W 0h 0 = Normal operation (default) 1 = Powers down the analog block for channel 9 3 INVERT_CH12 R/W 0h 0 = Normal operation (default) 1 = Inverts digital output data sent on LVDS output line 12 2 INVERT_CH11 R/W 0h 0 = Normal operation (default) 1 = Inverts digital output data sent on LVDS output line 11 1 INVERT_CH10 R/W 0h 0 = Normal operation (default) 1 = Inverts digital output data sent on LVDS output line 10 0 INVERT_CH9 R/W 0h 0 = Normal operation (default) 1 = Inverts digital output data sent on LVDS output line 9 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 121 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 13.1.2.1.42 Register 49 (address = 31h) Figure 157. Register 49 15 14 7 13 GAIN_CH13 R/W-0h 12 5 4 6 11 3 10 0 R/W-0h 9 2 1 8 OFFSET_CH13 R/W-0h 0 OFFSET_CH13 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 58. Register 49 Field Descriptions Bit Field Type Reset Description GAIN_CH13 R/W 0h When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, then the digital gain value for channel 13 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, set the digital gain to N × 0.2 dB. 10 0 R/W 0h Must write 0 9-0 OFFSET_CH13 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 13 can be obtained with this 10-bit register. The offset value is in twos complement format. Write the same offset value in register 50, bits 9-0. 15-11 13.1.2.1.43 Register 50 (address = 32h) Figure 158. Register 50 15 0 R/W-0h 14 0 R/W-0h 13 0 R/W-0h 12 0 R/W-0h 11 0 R/W-0h 10 0 R/W-0h 9 7 6 5 4 3 2 1 8 OFFSET_CH13 R/W-0h 0 OFFSET_CH13 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 59. Register 50 Field Descriptions Bit 15-10 9-0 122 Field Type Reset Description 0 R/W 0h Must write 0 OFFSET_CH13 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 13 can be obtained with this 10-bit register. The offset value is in twos complement format. Write the same offset value in register 49, bits 9-0. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 13.1.2.1.44 Register 51 (address = 33h) Figure 159. Register 51 15 14 7 6 13 GAIN_CH14 R/W-0h 12 5 4 11 3 10 0 R/W-0h 9 2 1 8 OFFSET_CH14 R/W-0h 0 OFFSET_CH14 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 60. Register 51 Field Descriptions Bit Field Type Reset Description GAIN_CH14 R/W 0h When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, then the digital gain value for channel 14 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, set the digital gain to N × 0.2 dB. 10 0 R/W 0h Must write 0 9-0 OFFSET_CH14 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 14 can be obtained with this 10-bit register. The offset value is in twos complement format. Write the same offset value in register 52, bits 9-0. 15-11 13.1.2.1.45 Register 52 (address = 34h) Figure 160. Register 52 15 0 R/W-0h 14 0 R/W-0h 13 0 R/W-0h 12 0 R/W-0h 11 0 R/W-0h 10 0 R/W-0h 9 7 6 5 4 3 2 1 8 OFFSET_CH14 R/W-0h 0 OFFSET_CH14 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 61. Register 52 Field Descriptions Bit 15-10 9-0 Field Type Reset Description 0 R/W 0h Must write 0 OFFSET_CH14 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 14 can be obtained with this 10-bit register. The offset value is in twos complement format. Write the same offset value in register 51, bits 9-0. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 123 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 13.1.2.1.46 Register 53 (address = 35h) Figure 161. Register 53 15 14 7 13 GAIN_CH15 R/W-0h 12 5 4 6 11 3 10 0 R/W-0h 9 2 1 8 OFFSET_CH15 R/W-0h 0 OFFSET_CH15 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 62. Register 53 Field Descriptions Bit Field Type Reset Description GAIN_CH15 R/W 0h When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, then the digital gain value for channel 15 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, set the digital gain to N × 0.2 dB. 10 0 R/W 0h Must write 0 9-0 OFFSET_CH15 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 15 can be obtained with this 10-bit register. the offset value is in twos complement format. Write the same offset value in register 54, bits 9-0. 15-11 13.1.2.1.47 Register 54 (address = 36h) Figure 162. Register 54 15 0 R/W-0h 14 0 R/W-0h 13 0 R/W-0h 12 0 R/W-0h 11 0 R/W-0h 10 0 R/W-0h 9 7 6 5 4 3 2 1 8 OFFSET_CH15 R/W-0h 0 OFFSET_CH15 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 63. Register 54 Field Descriptions Bit 15-10 9-0 124 Field Type Reset Description 0 R/W 0h Must write 0 OFFSET_CH15 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 15 can be obtained with this 10-bit register. the offset value is in twos complement format. Write the same offset value in register 53, bits 9-0. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 13.1.2.1.48 Register 55 (address = 37h) Figure 163. Register 55 15 14 7 6 13 GAIN_CH16 R/W-0h 12 5 4 11 3 10 0 R/W-0h 9 2 1 8 OFFSET_CH16 R/W-0h 0 OFFSET_CH16 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 64. Register 55 Field Descriptions Bit Field Type Reset Description GAIN_CH16 R/W 0h When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, then the digital gain value for channel 16 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, set the digital gain to N × 0.2 dB. 10 0 R/W 0h Must write 0 9-0 OFFSET_CH16 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 16 can be obtained with this 10-bit register. the offset value is in twos complement format. Write the same offset value in register 56, bits 9-0. 15-11 13.1.2.1.49 Register 56 (address = 38h) Figure 164. Register 56 15 0 R/W-0h 14 0 R/W-0h 13 0 R/W-0h 12 0 R/W-0h 11 0 R/W-0h 10 0 R/W-0h 9 7 6 5 4 3 2 1 8 OFFSET_CH16 R/W-0h 0 OFFSET_CH16 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 65. Register 56 Field Descriptions Bit 15-10 9-0 Field Type Reset Description 0 R/W 0h Must write 0 OFFSET_CH16 R/W 0h When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, then the offset value for channel 16 can be obtained with this 10-bit register. the offset value is in twos complement format. Write the same offset value in register 55, bits 9-0. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 125 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 13.1.2.1.50 Register 57 (address = 39h) Figure 165. Register 57 15 PAT_PRBS_ LVDS13 R/W-0h 14 PAT_PRBS_ LVDS14 R/W-0h 13 PAT_PRBS_ LVDS15 R/W-0h 12 PAT_PRBS_ LVDS16 R/W-0h 11 10 7 6 5 4 3 PAT_LVDS14[2:0] 0 HPF_CORNER_CH25-32[3:0] R/W-0h R/W-0h R/W-0h 9 8 PAT_ LVDS14[2:0] R/W-0h 1 0 DIG_HPF_EN_ CH25-32 R/W-0h PAT_LVDS13[2:0] R/W-0h 2 LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 66. Register 57 Field Descriptions Bit Field Type Reset Description 15 PAT_PRBS_LVDS13 R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the PRBS pattern on LVDS output 13 can be enabled with this bit; see the Test Patterns section for further details. 14 PAT_PRBS_LVDS14 R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the PRBS pattern on LVDS output 14 can be enabled with this bit; see the Test Patterns section for further details. 13 PAT_PRBS_LVDS15 R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the PRBS pattern on LVDS output 15 can be enabled with this bit; see the Test Patterns section for further details. 12 PAT_PRBS_LVDS16 R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the PRBS pattern on LVDS output 16 can be enabled with this bit; see the Test Patterns section for further details. 11-9 PAT_LVDS13[2:0] R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the different pattern on LVDS output 13 can be programmed with these bits; see Table 33 for bit descriptions. 8-6 PAT_LVDS14[2:0] R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the different pattern on LVDS output 14 can be programmed with these bits; see Table 33 for bit descriptions. 0 R/W 0h Must write 0 HPF_CORNER_CH13-16[3:0] R/W 0h When the DIG_HPF_EN_CH13-16 bit is set to 1, then the digital HPF characteristic for the corresponding channels can be programmed by setting the value of k with these bits. Characteristics of a digital high-pass transfer function applied to the output data for a given value of k is defined by: 5 4-1 Y(n) = 2k 2k + 1 [x(n) - x(n - 1) + y(n - 1)] Note that the value of k can be from 2 to 10 (0010b to 1010b); see the Digital HPF section for further details. 0 126 DIG_HPF_EN_CH13-16 R/W 0h 0 = Digital HPF disabled for channels 13 to 16 (default) 1 = Enables digital HPF for channels 13 to 16 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 13.1.2.1.51 Register 59 (address = 3Bh) Figure 166. Register 59 15 0 R/W-0h 14 0 R/W-0h 13 0 R/W-0h 12 0 R/W-0h 11 0 R/W-0h 10 0 R/W-0h 9 0 R/W-0h 8 0 R/W-0h 7 6 PIN_PAT_LVDS15[2:0] R/W-0h 5 4 3 PAT_LVDS16[2:0] R/W-0h 2 1 0 R/W-0h 0 0 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 67. Register 59 Field Descriptions Bit Field Type Reset Description 15-8 0 R/W 0h Must write 0 7-5 PAT_LVDS15[2:0] R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the differentpattern on LVDS output 15 can be programmed with these bits; see Table 33 for bit descriptions. 4-2 PAT_LVDS16[2:0] R/W 0h When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, then the different pattern on LVDS output 16 can be programmed with these bits; see Table 33 for bit descriptions. 1-0 0 R/W 0h Must write 0 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 127 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 13.1.2.1.52 Register 60 (address = 3Ch) Figure 167. Register 60 15 PDN_DIG_ CH16 R/W-0h 14 PDN_DIG_ CH15 R/W-0h 13 PDN_DIG_ CH14 R/W-0h 12 PDN_DIG_ CH13 R/W-0h 11 10 9 8 PDN_LVDS16 PDN_LVDS15 PDN_LVDS14 PDN_LVDS13 R/W-0h R/W-0h R/W-0h R/W-0h 7 PDN_ANA_ CH16 R/W-0h 6 PDN_ANA_ CH15 R/W-0h 5 PDN_ANA_ CH14 R/W-0h 4 PDN_ANA_ CH13 R/W-0h 3 INVERT_ CH16 R/W-0h 2 INVERT_ CH15 R/W-0h 1 INVERT_ CH14 R/W-0h 0 INVERT_ CH13 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 68. Register 60 Field Descriptions 128 Bit Field Type Reset Description 15 PDN_DIG_CH16 R/W 0h 0 = Normal operation (default) 1 = Powers down the digital block for channel 16 14 PDN_DIG_CH15 R/W 0h 0 = Normal operation (default) 1 = Powers down the digital block for channel 15 13 PDN_DIG_CH14 R/W 0h 0 = Normal operation (default) 1 = Powers down the digital block for channel 14 12 PDN_DIG_CH13 R/W 0h 0 = Normal operation (default) 1 = Powers down the digital block for channel 13 11 PDN_LVDS16 R/W 0h 0 = Normal operation (default) 1 = Powers down LVDS output line 16 10 PDN_LVDS15 R/W 0h 0 = Normal operation (default) 1 = Powers down LVDS output line 15 9 PDN_LVDS14 R/W 0h 0 = Normal operation (default) 1 = Powers down LVDS output line 14 8 PDN_LVDS13 R/W 0h 0 = Normal operation (default) 1 = Powers down LVDS output line 13 7 PDN_ANA_CH16 R/W 0h 0 = Normal operation (default) 1 = Powers down the analog block for channel 16 6 PDN_ANA_CH15 R/W 0h 0 = Normal operation (default) 1 = Powers down the analog block for channel 15 5 PDN_ANA_CH14 R/W 0h 0 = Normal operation (default) 1 = Powers down the analog block for channel 14 4 PDN_ANA_CH13 R/W 0h 0 = Normal operation (default) 1 = Powers down the analog block for channel 13 3 INVERT_CH15 R/W 0h 0 = Normal operation (default) 1 = Inverts digital output data sent on LVDS output line 16 2 INVERT_CH16 R/W 0h 0 = Normal operation (default) 1 = Inverts digital output data sent on LVDS output line 15 1 INVERT_CH14 R/W 0h 0 = Normal operation (default) 1 = Inverts digital output data sent on LVDS output line 14 0 INVERT_CH13 R/W 0h 0 = Normal operation (default) 1 = Inverts digital output data sent on LVDS output line 13 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 13.1.2.1.53 Register 67 (address = 43h) Figure 168. Register 67 15 0 R/W-0h 14 0 R/W-0h 13 0 R/W-0h 12 0 R/W-0h 7 0 R/W-0h 6 0 R/W-0h 5 0 R/W-0h 4 11 0 R/W-0h 10 0 R/W-0h 3 2 LVDS_DCLK_DELAY_PROG[3:0] R/W-0h 9 0 R/W-0h 8 0 R/W-0h 1 0 0 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 69. Register 67 Field Descriptions Bit Field Type Reset Description 15-5 0 R/W 0h Must write 0 4-1 LVDS_DCLK_DELAY_PROG[3:0] R/W 0h The LVDS DCLK output delay is programmable with 110-ps steps. Delay values are in twos complement format. Increasing the positive delay increases setup time and reduces hold time, and vice-versa for the negative delay. 0000 = No delay 0001 = 110 ps 0010 = 220 ps … 1110 = –220 ps 1111 = –110ps … 0 R/W 0h Must write 0 0 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 129 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 13.1.3 VCA Register Map This section discusses the VCA registers. A register map is available in Table 70. Table 70. VCA Register Map REGISTER DATA (1) REGISTER ADDRESS DECIMAL 130 15 14 PGA_GAIN 12 11 0 6 0 PGA_ CLAMP_ LVL 5 4 0 PGA_HPF_ DIS 3 2 1 0 PDCH3/4 PDCH1/2 LNA_GAIN _IND_EN 197 C5 GBL_ PDWN FAST_ PDWN 198 C6 0 CW_HPF_ EN 199 C7 CW_MIX_PH_CH7/8 CW_MIX_PH_CH5/6 CW_MIX_PH_CH3/4 CW_MIX_PH_CH1/2 200 C8 CW_MIX_PH_CH15/16 CW_MIX_PH_CH13/14 CW_MIX_PH_CH11/12 CW_MIX_PH_CH9/10 201 C9 PDWN_ VCA_ PGA CW_HPF_FB_RES LNA_GAIN_CH13/14 0 7 PGA_ CLAMP_ DIS C4 LNA_GAIN_CH15/16 LNA_HPF_ DIS 0 8 196 PDWN_ LNA 0 9 0 LNA_GAIN_GBL 0 10 C3 CB 0 13 195 203 (1) HEX INPUT_CLAMP_LVL ACT_ TERM_ EN GBL_ACTIVE_TERM ACT_ TERM_ IND_RES_ EN POW_MODES LOW_NF 0 PDCH 15/16 PDCH 13/14 PDCH 11/12 CW_CLK_MODE DIS_CW_ AMP CW_TGC_ SEL 0 1X_CLK_ BUF_ MODE 16X_CLK_ BUF_ MODE LNA_GAIN_CH11/12 LNA_GAIN_CH9/10 LNA_GAIN_CH7/8 LPF_PROG ACT_TERM_IND_RES PDCH9/10 PDCH7/8 CW_SUM_AMP_GAIN LNA_GAIN_CH5/6 LNA_GAIN_CH3/4 0 0 0 0 0 0 0 0 EN_DIG_ TGC V2I_ CLAMP 0 0 0 0 RED_LNA_ HPF_3X 0 0 0 0 0 PDWN_ LNA_ DIE2 PDWN_ VCA_ PGA_DIE2 LOW_NF_ DIE2 0 PDCH15 PDCH13 PDCH11 PDCH9 PDCH7 DIG_TGC_ATTENUATION 205 CD PGA_ CLAMP_ HALF SUPRESS _HIGHER_ HAR MONICS 213 D5 GBL_ PDWN_ DIE2 FAST_ PDWN_ DIE2 215 D7 CW_MIX_PH_CH7 CW_MIX_PH_CH5 CW_MIX_PH_CH3 216 D8 CW_MIX_PH_CH15 CW_MIX_PH_CH13 CW_MIX_PH_CH11 217 D9 LNA_GAIN_CH15 LNA_GAIN_CH13 POW_MODES_DIE2 LNA_GAIN_CH11 LNA_GAIN_CH9 LNA_GAIN_CH7 PDCH5/6 LNA_HPF_PROG LNA_GAIN_CH5 LNA_GAIN_CH1/2 0 0 0 0 0 PDCH5 PDCH3 PDCH1 CW_MIX_PH_CH1 CW_MIX_PH_CH9 LNA_GAIN_CH3 LNA_GAIN_CH1 The default value of all registers is 0. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 13.1.3.1 Description of VCA Registers 13.1.3.1.1 Register 195 (address = C3h) Table 71. Register 195 15 0 R/W-0h 14 0 R/W-0h 13 PGA_GAIN R/W-0h 12 0 R/W-0h 11 0 R/W-0h 10 0 R/W-0h 9 0 R/W-0h 8 0 R/W-0h 7 PGA_CLAMP_ DIS R/W-0h 6 PGA_CLAMP_ LVL R/W-0h 5 4 3 2 1 0 0 PGA_HPF_DIS LPF_PROG R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 72. Register 195 Field Descriptions Bit 15-14 13 12-8 Field Type Reset Description 0 R/W 0h Must write 0 PGA_GAIN R/W 0h 0 = PGA gain set to 24 dB 1 = PGA gain set to 30 dB 0 R/W 0h Must write 0 7 PGA_CLAMP_DIS R/W 0h When POW_MODES (register 197, bits 11-10) is 01 or 10: 0 = Disables the PGA current clamp circuit 1 = Enables the PGA current clamp circuit before the PGA outputs When POW_MODES (register 197, bits 11-10) is 00: 0 = Enables the PGA current clamp circuit 1 = Disables the PGA current clamp circuit before the PGA outputs PGA_CLAMP_LVL (register 195, bit 6) determines the current clamp level. 6 PGA_CLAMP_LVL R/W 0h 0 = –2 dBFS 1 = 0 dBFS Note that the current clamp circuit ensures that the PGA output is in the linear range. For example, at a 0-dBFS setting, the PGA output HD3 worsens by 3 dB at a –2-dBFS ADC input. In normal operation, the current clamp function can be set as 0 dBFS. 5 0 R/W 0h Must write 0 4 PGA_HPF_DIS R/W 0h 0 = PGA high-pass filter enabled 1 = PGA high-pass filter disabled LPF_PROG R/W 0h These bits program the cutoff frequency of the antialiasing lowpass filter. 0000 = 15 MHz 0100 = 20 MHz 0101 = 35 MHz 0110 = 30 MHz 0111 = 50 MHz 1000 = 10 MHz All other bit combinations are not applicable 3-0 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 131 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 13.1.3.1.2 Register 196 (address = C4h) Table 73. Register 196 15 LNA_GAIN_ IND_EN R/W-0h 14 7 6 13 12 11 10 LNA_GAIN_GBL LNA_HPF_DIS 0 INPUT_CLAMP_LVL R/W-0h R/W-0h R/W-0h 4 3 GBL_ACTIVE_TERM R/W-0h 5 ACT_TERM_ IND_RES_EN R/W-0h 9 R/W-0h 2 1 8 ACT_TERM_ EN R/W-0h 0 ACT_TERM_IND_RES R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value Table 74. Register 196 Field Descriptions Bit Field Type Reset Description 15 LNA_GAIN_IND_EN R/W 0h 0 = Disabled 1 = LNA individual channel control enabled See register 201 and register 217 for details. LNA_GAIN_GBL R/W 0h 00 01 10 11 12 LNA_HPF_DIS R/W 0h 0 = LNA high-pass filter enabled 1 = LNA high-pass filter disabled 11 0 R/W 0h Must write 0 INPUT_CLAMP_LVL R/W 0h 00 01 10 11 ACT_TERM_EN R/W 0h 0 = Active termination disabled 1 = Active termination enabled GBL_ACTIVE_TERM R/W 0h 00 = 50 Ω 01 = 100 Ω 10 = 200 Ω 11 = 400 Ω Note that the device adjusts resistor mapping (register 196, bits 4-0) automatically. 50-Ω active termination is not supported in the 12-dB LNA setting. Instead, 00 represents high-impedance mode when LNA gain is 12 dB. ACT_TERM_IND_RES_EN R/W 0h 0 = Disabled 1 = Internal active termination individual resistor control enabled ACT_TERM_IND_RES R/W 0h To enable this bit, ensure that ACT_TERM_IND_RES_EN (register 196, bit 5) is 1. For further details, see Table 75. 14-13 10-9 8 7-6 5 4-0 132 = 18 dB = 24 dB = 12 dB = Reserved = Auto setting = 1.5 VPP = 1.15 VPP = 0.6 VPP Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 Table 75. ACT_TERM_IND_RES (1) (Register 196, Bits 4-0) versus LNA Input Impedances ACT_TERM_IND_RES (Register 196, Bits 4-0) (1) BIT SETTINGS LNA = 12 dB LNA = 18 dB LNA = 24 dB 00000 High-Z High-Z High-Z 00001 150 Ω 90 Ω 50 Ω 00010 300 Ω 180 Ω 100 Ω 00011 100 Ω 60 Ω 33 Ω 00100 600 Ω 360 Ω 200 Ω 00101 120 Ω 72 Ω 40 Ω 00110 200 Ω 120 Ω 66.67 Ω 00111 86 Ω 51 Ω 29 Ω 01000 1200 Ω 720 Ω 400 Ω 01001 133 Ω 80 Ω 44 Ω 01010 240 Ω 144 Ω 80 Ω 01011 92 Ω 55 Ω 31 Ω 01100 400 Ω 240 Ω 133 Ω 01101 109 Ω 65 Ω 36 Ω 01110 171 Ω 103 Ω 57 Ω 01111 80 Ω 48 Ω 27 Ω 10000 1500 Ω 900 Ω 500 Ω 10001 136 Ω 82 Ω 45 Ω 10010 250 Ω 150 Ω 83 Ω 10011 94 Ω 56 Ω 31 Ω 10100 429 Ω 257 Ω 143 Ω 10101 111 Ω 67 Ω 37 Ω 10110 176 Ω 106 Ω 59 Ω 10111 81 Ω 49 Ω 27 Ω 11000 667 Ω 400 Ω 222 Ω 11001 122 Ω 73 Ω 41 Ω 11010 207 Ω 124 Ω 69 Ω 11011 87 Ω 52 Ω 29 Ω 11100 316 Ω 189 Ω 105 Ω 11101 102 Ω 61 Ω 34 Ω 11110 154 Ω 92 Ω 51 Ω 11111 76 Ω 46 Ω 25 Ω Total device input impedance is given by the parallel combination of the mentioned active termination resistance and a passive resistance of 15 kΩ. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 133 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 13.1.3.1.3 Register 197 (address = C5h) Table 76. Register 197 15 14 13 11 R/W-0h 12 PDWN_VCA_ PGA R/W-0h GBL_PDWN FAST_PDWN PDWN_LNA R/W-0h R/W-0h 7 PDCH15/16 R/W-0h 6 PDCH13/14 R/W-0h 10 9 8 POW_MODES LOW_NF 0 5 PDCH11/12 R/W-0h 4 PDCH9/10 R/W-0h 3 PDCH7/8 R/W-0h R/W-0h R/W-0h R/W-0h 1 PDCH3/4 R/W-0h 0 PDCH1/2 R/W-0h 2 PDCH5/6 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value Table 77. Register 197 Field Descriptions Bit Field Type Reset Description 15 GBL_PDWN R/W 0h 0 = Normal operation 1 = When ADD_OFFSET is set to 0, the LNA, VCAT, and PGA are completely powered down (slow wake response) for both VCA dies 1 and 2 When ADD_OFFSET is set to 1, the LNA, VCAT, and PGA are completely powered down (slow wake response) for only VCA die 1. This bit can overwrite FAST PDWN (register 197, bit 14). Note that enabling this bit does not power-down the ADC. This bit only powers down the VCA dies. 14 FAST_PDWN R/W 0h 0 = Normal operation 1 = When ADD_OFFSET set to 0, the LNA, VCAT, and PGA are partially powered down (fast wake response) for both VCA dies 1 and 2 When ADD_OFFSET set to 1, the LNA, VCAT, and PGA are partially powered down (fast wake response) for only VCA die 1. Note that enabling this bit does not power-down the ADC. This bit only powers down the VCA dies. 13 PDWN_LNA R/W 0h 0 = Normal operation 1 = When ADD_OFFSET is set to 0, only the LNA is powered down for both VCA dies 1 and 2 When ADD_OFFSET is set to 1, only the LNA is powered down for VCA die 1. 12 PDWN_VCA_PGA R/W 0h 0 = Normal operation 1 = When ADD_OFFSET is set to 0, the VCAT and PGA are powered down for both VCA dies 1 and 2 When ADD_OFFSET set to 1, the VCAT and PGA are powered down for only VCA die 1. POW_MODES R/W 0h 00 = Low-noise mode 01 = Set to low-power mode; at 30-dB PGA the total chain gain can slightly change 10 = Set to medium-power mode; at 30-dB PGA the total chain gain can slightly change 11 = Reserved When ADD_OFFSET is set to 0, the device performs an operation as this POW_MODES section describes on both VCA dies 1 and 2. When ADD_OFFSET is set to 1, the device performs an operation as this POW_MODES section describes only on VCA die 1. 9 LOW_NF R/W 0h This mode can be used to improve the noise figure for high-impedance probes. To write to this register, ensure that POW MODES (register 197, bits 11-10) = 00. 0 = Disable low-noise figure mode 1 = When ADD_OFFSET is set to 0, the low-noise figure mode is enabled on both VCA dies 1 and 2 When ADD_OFFSET set to 1, the low-noise figure mode is enabled only on VCA die 1. 8 0 R/W 0h Must write 0 7 PDCH15/16 R/W 0h 0 = Default 1 = When ADD_OFFSET is 0, channels 15 and 16 are powered down; when ADD_OFFSET is 1, only channel 16 is powered down This bit only powers down the channel of the VCA die (that is, LNA + VCA + PGA). This bit does not affect the ADC channel. 11-10 134 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 Table 77. Register 197 Field Descriptions (continued) Bit Field Type Reset Description 6 PDCH13/14 R/W 0h 0 = Default 1 = When ADD_OFFSET is 0, channels 13 and 14 are powered down; when ADD_OFFSET is 1, only channel 14 is powered down This bit only powers down the channel of the VCA die (that is, LNA + VCA + PGA). This bit does not affect the ADC channel. 5 PDCH11/12 R/W 0h 0 = Default 1 = When ADD_OFFSET is 0, channels 11 and 12 are powered down; when ADD_OFFSET is 1, only channel 12 is powered down This bit only powers down the channel of the VCA die (that is, LNA + VCA + PGA). This bit does not affect the ADC channel. 4 PDCH9/10 R/W 0h 0 = Default 1 = When ADD_OFFSET is 0, channels 9 and 10 are powered down; when ADD_OFFSET is 1, only channel 10 is powered down This bit only powers down the channel of the VCA die (that is, LNA + VCA + PGA). This bit does not affect the ADC channel. 3 PDCH7/8 R/W 0h 0 = Default 1 = When ADD_OFFSET is 0, channels 7 and 8 are powered down; when ADD_OFFSET is 1, only channel 8 is powered down This bit only powers down the channel of the VCA die (that is, LNA + VCA + PGA). This bit doesn’t have any impact on ADC channel. 2 PDCH5/6 R/W 0h 0 = Default 1 = When ADD_OFFSET is 0, channels 5 and 6 are powered down; when ADD_OFFSET is 1, only channel 6 is powered down This bit only powers down the channel of the VCA die (that is, LNA + VCA + PGA). This bit does not affect the ADC channel. 1 PDCH3/4 R/W 0h 0 = Default 1 = When ADD_OFFSET is 0, channels 3 and 4 are powered down; when ADD_OFFSET is 1, only channel 4 is powered down This bit only powers down the channel of the VCA die (that is, LNA + VCA + PGA). This bit does not affect the ADC channel. 0 PDCH1/2 R/W 0h 0 = Default 1 = When ADD_OFFSET is 0, channels 1 and 2 are powered down; when ADD_OFFSET is 1, only channel 2 is powered down This bit only powers down the channel of the VCA die (that is, LNA + VCA + PGA). This bit does not affect the ADC channel. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 135 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 13.1.3.1.4 Register 198 (address = C6h) Table 78. Register 198 15 0 R/W-0h 14 CW_HPF_EN R/W-0h 7 0 6 1X_CLK_BUF_ MODE R/W-0h R/W-0h 13 12 CW_HPF_FB_RES R/W-0h 5 16X_CLK_BUF _MODE R/W-0h 4 11 10 CW_CLK_MODE R/W-0h 3 9 DIS_CW_AMP R/W-0h 8 CW_TGC_SEL R/W-0h 1 0 2 CW_SUM_AMP_GAIN R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value Table 79. Register 198 Field Descriptions Bit Field Type Reset Description 15 0 R/W 0h Must write 0 14 CW_HPF_EN R/W 0h 0 = Normal operation 1 = Enables CW output high-pass filter 13-12 CW_HPF_FB_RES R/W 0h If CW_HPF_EN = 1 then the value of the CW high-pass filter feedback resistor is given by: 00 = 400 Ω 01 = 133 Ω 10 = 80 Ω 11 = 57 Ω If CW_HPF_EN = 0 then these bits are ignored and the feedback path remains open. 11-10 CW_CLK_MODE R/W 0h 00 = 16X mode 01 = 8X mode 10 = 4X mode 11 = 1X mode 9 DIS_CW_AMP R/W 0h 0 = CW summing amplifier enabled 1 = CW summing amplifier disabled Note that this bit is only effective in CW mode. 8 CW_TGC_SEL R/W 0h 0 = TGC mode 1 = CW mode Note that the VCAT and PGA still function in CW mode. Power-down the VCAT and PGA separately with PDWN_VCA_PGA (register 197, bit 12). 7 0 R/W 0h Must write 0 6 1X_CLK_BUF_MODE R/W 0h 0 = Accepts CMOS clock 1 = Accepts differential clock 5 16X_CLK_BUF_MODE R/W 0h 0 = Accepts differential clock 1 = Accepts CMOS clock 4-0 CW_SUM_AMP_GAIN R/W 0h These bits select the feedback resistor for the CW amplifier, as per Table 75. Table 80. CW Summing Amplifier Feedback Resistor 136 REGISTER 198 (Bits 4-0) FEEDBACK RESISTOR REGISTER 198 (Bits 4-0) FEEDBACK RESISTOR REGISTER 198 (Bits 4-0) FEEDBACK RESISTOR 00000 Open 01011 111 Ω 10110 153 Ω 00001 250 Ω 01100 333 Ω 10111 95 Ω 00010 250 Ω 01101 142 Ω 11000 666 Ω 00011 125 Ω 01110 142 Ω 11001 181 Ω 00100 500 Ω 01111 90 Ω 11010 181 Ω 00101 166 Ω 10000 2000 Ω 11011 105 Ω 00110 166 Ω 10001 222 Ω 11100 285 Ω 00111 100 Ω 10010 222 Ω 11101 133 Ω 01000 1000 Ω 10011 117 Ω 11110 133 Ω 01001 200 Ω 10100 400 Ω 11111 87 Ω 01010 200 Ω 10101 153 Ω Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 13.1.3.1.5 Register 199 (address = C7h) Table 81. Register 199 15 14 13 CW_MIX_PH_CH[7/8] R/W-0h 12 11 10 9 CW_MIX_PH_CH[5/6] R/W-0h 8 7 6 5 CW_MIX_PH_CH[3/4] R/W-0h 4 3 2 1 CW_MIX_PH_CH[1/2] R/W-0h 0 LEGEND: R/W = Read/Write; W = Write only; -n = value Table 82. Register 199 Field Descriptions Bit Field Type Reset Description 15-12 CW_MIX_PH_CH[7/8] R/W 0h These bits control the CW mixer phase. Writing N to these bits sets the corresponding channel phase to N × 22.5°. Where, N = 0 to 15; see Table 83 for further details. The functionality of these bits depends upon the value of the ADD_OFFSET bit. When the ADD_OFFSET bit is set to 0, setting bits 15-12 programs the CW phase of channels 7 and 8. When the ADD_OFFSET bit is set to 1, setting bits 15-12 programs the CW phase of only channel 8. 11-8 CW_MIX_PH_CH[5/6] R/W 0h These bits control the CW mixer phase. Writing N to these bits sets the corresponding channel phase to N × 22.5°. Where, N = 0 to 15; see Table 83 for further details. The functionality of these bits depends upon the value of the ADD_OFFSET bit. When the ADD_OFFSET bit is set to 0, setting bits 11-8 programs the CW phase of channels 5 and 6. When the ADD_OFFSET bit is set to 1, setting bits 11-8 programs the CW phase of only channel 6. 7-4 CW_MIX_PH_CH[3/4] R/W 0h These bits control the CW mixer phase. Writing N to these bits sets the corresponding channel phase to N × 22.5°. Where, N = 0 to 15; see Table 83 for further details. The functionality of these bits depends upon the value of the ADD_OFFSET bit. When the ADD_OFFSET bit is set to 0, setting bits 7-4 programs the CW phase of channels 3 and 4. When the ADD_OFFSET bit is set to 1, setting bits 7-4 programs the CW phase of only channel 4. 3-0 CW_MIX_PH_CH[1/2] R/W 0h These bits control the CW mixer phase. Writing N to these bits sets the corresponding channel phase to N × 22.5°. Where, N = 0 to 15; see Table 83 for further details. The functionality of these bits depends upon the value of the ADD_OFFSET bit. When the ADD_OFFSET bit is set to 0, setting bits 3-0 programs the CW phase of channels 1 and 2. When the ADD_OFFSET bit is set to 1, setting bits 3-0 programs the CW phase of only channel 2. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 137 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com Table 83. CW Mixer Phase Delay versus Register Settings 138 BIT SETTINGS CW_MIX_PH_CHX, CW_MIX_PH_CHY PHASE SHIFT 0000 0 0001 22.5° 0010 45° 0011 67.5° 0100 90° 0101 112.5° 0110 135° 0111 157.5° 1000 180° 1001 202.5° 1010 225° 1011 247.5° 1100 270° 1101 292.5° 1110 315° 1111 337.5° Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 13.1.3.1.6 Register 200 (address = C8h) Table 84. Register 200 15 14 13 CW_MIX_PH_CH[15/16] R/W-0h 12 11 10 9 CW_MIX_PH_CH[13/14] R/W-0h 8 7 6 5 CW_MIX_PH_CH[11/12] R/W-0h 4 3 2 1 CW_MIX_PH_CH[9/10] R/W-0h 0 LEGEND: R/W = Read/Write; W = Write only; -n = value Table 85. Register 200 Field Descriptions Bit Field Type Reset Description 15-12 CW_MIX_PH_CH[15/16] R/W 0h These bits control the CW mixer phase. Writing N to these bits sets the corresponding channel phase to N × 22.5°. Where, N = 0 to 15; see Table 83 for further details. The functionality of these bits depends upon the value of the ADD_OFFSET bit. When the ADD_OFFSET bit is set to 0, setting bits 15-12 programs the CW phase of channels 15 and 16. When the ADD_OFFSET bit is set to 1, setting bits 15-12 programs the CW phase of only channel 16. 11-8 CW_MIX_PH_CH[13/14] R/W 0h These bits control the CW mixer phase. Writing N to these bits sets the corresponding channel phase to N × 22.5°. Where, N = 0 to 15; see Table 83 for further details. The functionality of these bits depends upon the value of the ADD_OFFSET bit. When the ADD_OFFSET bit is set to 0, setting bits 11-8 programs the CW phase of channels 13 and 14. When the ADD_OFFSET bit is set to 1, setting bits 11-8 programs the CW phase of only channel 14. 7-4 CW_MIX_PH_CH[11/12] R/W 0h These bits control the CW mixer phase. Writing N to these bits sets the corresponding channel phase to N × 22.5°. Where, N = 0 to 15; see Table 83 for further details. The functionality of these bits depends upon the value of the ADD_OFFSET bit. When the ADD_OFFSET bit is set to 0, setting bits 7-4 programs the CW phase of channels 11 and 12. When the ADD_OFFSET bit is set to 1, setting bits 7-4 programs the CW phase of only channel 12. 3-0 CW_MIX_PH_CH[9/10] R/W 0h These bits control the CW mixer phase. Writing N to these bits sets the corresponding channel phase to N × 22.5°. Where, N = 0 to 15; see Table 83 for further details. The functionality of these bits depends upon the value of the ADD_OFFSET bit. When the ADD_OFFSET bit is set to 0, setting bits 3-0 programs the CW phase of channels 9 and 10. When the ADD_OFFSET bit is set to 1, setting bits 3-0 programs the CW phase of only channel 10. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 139 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 13.1.3.1.7 Register 201 (address = C9h) Table 86. Register 201 15 14 LNA_GAIN_CH[15/16] R/W-0h 13 12 LNA_GAIN_CH[13/14] R/W-0h 11 10 LNA_GAIN_CH[11/12] R/W-0h 9 8 LNA_GAIN_CH[9/10] R/W-0h 7 6 LNA_GAIN_CH[7/8] R/W-0h 5 4 LNA_GAIN_CH[5/6] R/W-0h 3 2 LNA_GAIN_CH[3/4] R/W-0h 1 0 LNA_GAIN_CH[1/2] R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value Table 87. Register 201 Field Descriptions Bit Field Type Reset Description 15-14 LNA_GAIN_CH[15/16] R/W 0h To enable this bit, ensure that LNA_GAIN_IND_EN (register 196, bit 15) is 1. 00 = 18 dB 01 = 24 dB 10 = 12 dB 11 = Do not use The functionality of this bit depends on the ADD_OFFSET bit. When ADD_OFFSET is 0, the gain of channels 15 and 16 are programmed; when ADD_OFFSET is 1, only the gain of channel 16 is programmed. 13-12 LNA_GAIN_CH[13/14] R/W 0h To enable this bit, ensure that LNA_GAIN_IND_EN (register 196, bit 15) is 1. 00 = 18 dB 01 = 24 dB 10 = 12 dB 11 = Do not use The functionality of this bit depends on the ADD_OFFSET bit. When ADD_OFFSET is 0, the gain of channels 13 and 14 are programmed; when ADD_OFFSET is 1, only the gain of channel 14 is programmed. 11-10 LNA_GAIN_CH[11/12] R/W 0h To enable this bit, ensure that LNA_GAIN_IND_EN (register 196, bit 15) is 1. 00 = 18 dB 01 = 24 dB 10 = 12 dB 11 = Do not use The functionality of this bit depends on the ADD_OFFSET bit. When ADD_OFFSET is 0, the gain of channels 11 and 12 are programmed; when ADD_OFFSET is 1, only the gain of channel 12 is programmed. 9-8 LNA_GAIN_CH[9/10] R/W 0h To enable this bit, ensure that LNA_GAIN_IND_EN (register 196, bit 15) is 1. 00 = 18 dB 01 = 24 dB 10 = 12 dB 11 = Do not use The functionality of this bit depends on the ADD_OFFSET bit. When ADD_OFFSET is 0, the gain of channels 9 and 10 are programmed; when ADD_OFFSET is 1, only the gain of channel 10 is programmed. 140 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 Table 87. Register 201 Field Descriptions (continued) Bit Field Type Reset Description 7-6 LNA_GAIN_CH[7/8] R/W 0h To enable this bit, ensure that LNA_GAIN_IND_EN (register 196, bit 15) is 1. 00 = 18 dB 01 = 24 dB 10 = 12 dB 11 = Do not use The functionality of this bit depends on the ADD_OFFSET bit. When ADD_OFFSET is 0, the gain of channels 7 and 8 are programmed; when ADD_OFFSET is 1, only the gain of channel 8 is programmed. 5-4 LNA_GAIN_CH[5/6] R/W 0h To enable this bit, ensure that LNA_GAIN_IND_EN (register 196, bit 15) is 1. 00 = 18 dB 01 = 24 dB 10 = 12 dB 11 = Do not use The functionality of this bit depends on the ADD_OFFSET bit. When ADD_OFFSET is 0, the gain of channels 5 and 6 are programmed; when ADD_OFFSET is 1, only the gain of channel 6 is programmed. 3-2 LNA_GAIN_CH[3/4] R/W 0h To enable this bit, ensure that LNA_GAIN_IND_EN (register 196, bit 15) is 1. 00 = 18 dB 01 = 24 dB 10 = 12 dB 11 = Do not use The functionality of this bit depends on the ADD_OFFSET bit. When ADD_OFFSET is 0, the gain of channels 3 and 4 are programmed; when ADD_OFFSET is 1, only the gain of channel 4 is programmed. 1-0 LNA_GAIN_CH[1/2] R/W 0h To enable this bit, ensure that LNA_GAIN_IND_EN (register 196, bit 15) is 1. 00 = 18 dB 01 = 24 dB 10 = 12 dB 11 = Do not use The functionality of this bit depends on the ADD_OFFSET bit. When ADD_OFFSET is 0, the gain of channels 1 and 2 are programmed; when ADD_OFFSET is 1, only the gain of channel 2 is programmed. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 141 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 13.1.3.1.8 Register 203 (address = CBh) Table 88. Register 203 15 0 R/W-0h 14 0 R/W-0h 13 0 R/W-0h 12 0 R/W-0h 7 EN_DIG_TGC R/W-0h 6 5 DIG_TGC_ATTENUATION R/W-0h 4 11 0 R/W-0h 10 0 R/W-0h 3 2 LNA_HPF_PROG R/W-0h 9 0 R/W-0h 8 0 R/W-0h 1 0 R/W-0h 0 0 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value Table 89. Register 203 Field Descriptions Bit Field Type Reset Description 0 R/W 0h Must write 0 EN_DIG_TGC R/W 0h 0 = Disable digital TGC attenuator 1 = Enable digital TGC attenuator 6-4 DIG_TGC_ATTENUATION R/W 0h When EN_DIG_TGC (register 203, bit 7) is set to 1, then the digital attenuation in the TGC path is programmed as follows: 000 = 0-dB attenuation 001 = 6-dB attenuation 010 = 12-dB attenuation 011 = 18-dB attenuation 100 = 24-dB attenuation. 101 = 30-dB attenuation 110 = 36-dB attenuation 111 = 42-dB attenuation 3-2 LNA_HPF_PROG R/W 0h 00 01 10 11 1-0 0 R/W 0h Must write 0 15-8 7 142 = 100 kHz = 50 kHz = 200 kHz = 150 kHz with 0.015 µF on INMx Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 13.1.3.1.9 Register 205 (address = CDh) Table 90. Register 205 15 13 12 11 10 9 8 V2I_CLAMP 0 0 0 0 RED_LNA_ HPF_3X R/W-0h 14 SUPRESS_ HIGHER_ HARMONICS R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 0 R/W-0h 6 0 R/W-0h 5 0 R/W-0h 4 0 R/W-0h 3 0 R/W-0h 2 0 R/W-0h 1 0 R/W-0h 0 0 R/W-0h PGA_CLAMP_ HALF LEGEND: R/W = Read/Write; W = Write only; -n = value Table 91. Register 205 Field Descriptions Bit Field Type Reset Description 15 PGA_CLAMP_HALF R/W 0h 0 = Disables –6-dB PGA clamp 1 = Enables a –6-dB PGA clamp setting (that is, the PGA output HD3 worsens by 3 dB at a –6-dBFS ADC input). The actual PGA output is reduced to approximately 1.5 VPP. As a result, the device low-pass filter (LPF) is not saturated and can suppress harmonic signals better at the PGA output. Resulting from the reduction of the PGA output, the ADC output dynamic range is affected. 14 SUPRESS_HIGHER_HARMONICS R/W 0h 0 = Disables a 1st-order, 5-MHz LPF filter 1 = Enables a 1st-order, 5-MHz LPF filter to suppress signals > 5 MHz or high-order harmonics 13 V2I_CLAMP R/W 0h 0 = Disables V2I clamp in the PGA 1 = Enables V2I clamp in the PGA 0 R/W 0h Must write 0 RED_LNA_HPF_3X R/W 0h 0 = The LNA HPF corner frequency is given as per the LNA_HPF_PROG bit description 1 = The LNA HPF corner frequency reduces by 3x as per the LNA_HPF_PROG bit description. For example, if LNA_HPF_PROG = 01 and RED_LNA_HPF_3X = 1, then the LNA HPF corner is given by the equation 50 kHz / 3 = 16.6 kHz. 0 R/W 0h Must write 0 12-9 8 7-0 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 143 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 13.1.3.1.10 Register 213 (address = D5h) Table 92. Register 213 15 GBL_PDWN_ DIE2 R/W-0h 14 FAST_PDWN_ DIE2 R/W-0h 13 PDWN_LNA_ DIE2 R/W-0h 12 PDWN_VCA_ PGA_DIE2 R/W-0h 7 PDCH15 R/W-0h 6 PDCH13 R/W-0h 5 PDCH11 R/W-0h 4 PDCH9 R/W-0h 11 10 POW_MODES_DIE2 R/W-0h 3 PDCH7 R/W-0h 2 PDCH5 R/W-0h 9 LOW_NF_ DIE2 R/W-0h 8 R/W-0h 1 PDCH3 R/W-0h 0 PDCH1 R/W-0h 0 LEGEND: R/W = Read/Write; W = Write only; -n = value Table 93. Register 213 Field Descriptions Bit Field Type Reset Description 15 GBL_PDWN_DIE2 R/W 0h 0 = Normal operation 1 = When ADD_OFFSET is set to 1, the LNA, VCAT, and PGA are completely powered down (slow wake response) for only VCA die 2. Note that enabling this bit does not power-down the ADC. This bit only powers down VCA dies. 14 FAST_PDWN_DIE2 R/W 0h 0 = Normal operation 1 = When ADD_OFFSET set to 1, the LNA, VCAT, and PGA partially powered down (fast wake response) for only VCA die 2. Note that enabling this bit does not power-down the ADC. This bit only powers down VCA dies. 13 PDWN_LNA_DIE2 R/W 0h 0 = Normal operation 1 = When ADD_OFFSET is set to 1, only the LNA is powered down for VCA die 2. 12 PDWN_VCA_PGA_DIE2 R/W 0h 0 = Normal operation 1 = When ADD_OFFSET set to 1, the VCAT and PGA are powered down for only VCA die 2. POW_MODES_DIE2 R/W 0h 00 = Low-noise mode 01 = Set to low-power mode. At 30-dB PGA, the total chain gain may slightly change. 10 = Set to medium-power mode. At 30-dB PGA, the total chain gain may slightly change. 11 = Reserved When ADD_OFFSET set to 1, the device performs an operation as described in this POW_MODES_DIE2 section only on die 2. 9 LOW_NF_DIE2 R/W 0h This mode can be used to improve the noise figure for highimpedance probes. To write to this register, set POW MODES_DIE2 (register 213, bits 11-10) = 00. 0 = Disable the low-noise figure mode 1 = When ADD_OFFSET set to 1, the low-noise figure mode is enabled on only on VCA die 2. 8 0 R/W 0h Must write 0 7 PDNCH15 R/W 0h 0 = Default 1 = When ADD_OFFSET is 1, channel 15 is powered down This bit powers down the channel of the VCA die only (that is, LNA + VCA + PGA). This bit does not affect the ADC channel. 6 PDNCH13 R/W 0h 0 = Default 1 = When ADD_OFFSET is 1, channel 13 is powered down This bit powers down the channel of the VCA die only (that is, LNA + VCA + PGA). This bit does not affect the ADC channel. 5 PDNCH11 R/W 0h 0 = Default 1 = When ADD_OFFSET is 1, channel 11 is powered down This bit powers down the channel of the VCA die only (that is, LNA + VCA + PGA). This bit does not affect the ADC channel. 4 PDNCH9 R/W 0h 0 = Default 1 = When ADD_OFFSET is 1, channel 9 is powered down This bit powers down the channel of the VCA die only (that is, LNA + VCA + PGA). This bit does not affect the ADC channel. 11-10 144 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 Table 93. Register 213 Field Descriptions (continued) Bit Field Type Reset Description 3 PDNCH7 R/W 0h 0 = Default 1 = When ADD_OFFSET is 1, channel 7 is powered down This bit powers down the channel of the VCA die only (that is, LNA + VCA + PGA). This bit does not affect the ADC channel. 2 PDNCH5 R/W 0h 0 = Default 1 = When ADD_OFFSET is 1, channel 5 is powered down This bit powers down the channel of the VCA die only (that is, LNA + VCA + PGA). This bit does not affect the ADC channel. 1 PDNCH3 R/W 0h 0 = Default 1 = When ADD_OFFSET is 1, channel 3 is powered down This bit powers down the channel of the VCA die only (that is, LNA + VCA + PGA). This bit does not affect the ADC channel. 0 PDNCH1 R/W 0h 0 = Default 1 = When ADD_OFFSET is 1, channel 1 is powered down This bit powers down the channel of the VCA die only (that is, LNA + VCA + PGA). This bit does not affect the ADC channel. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 145 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 13.1.3.1.11 Register 215 (address = D7h) Table 94. Register 215 15 14 13 CW_MIX_PH_CH7 R/W-0h 12 11 10 9 CW_MIX_PH_CH5 R/W-0h 8 7 6 5 CW_MIX_PH_CH3 R/W-0h 4 3 2 1 CW_MIX_PH_CH1 R/W-0h 0 LEGEND: R/W = Read/Write; W = Write only; -n = value Table 95. Register 215 Field Descriptions Bit Field Type Reset Description 15-12 CW_MIX_PH_CH[7] R/W 0h These bits control the CW mixer phase. Writing N to these bits sets the corresponding channel phase to N × 22.5°. Where, N = 0 to 15; see Table 83 for further details. When the ADD_OFFSET bit is set to 1, setting bits 15-12 programs the CW phase of channel 7. 11-8 CW_MIX_PH_CH[5] R/W 0h These bits control the CW mixer phase. Writing N to these bits sets the corresponding channel phase to N × 22.5°. Where, N = 0 to 15; see Table 83 for further details. When the ADD_OFFSET bit is set to 1, setting bits 11-8 programs the CW phase of channel 5. 7-4 CW_MIX_PH_CH[3] R/W 0h These bits control the CW mixer phase. Writing N to these bits sets the corresponding channel phase to N × 22.5°. Where, N = 0 to 15; see Table 83 for further details. When the ADD_OFFSET bit is set to 1, setting bits 7-4 programs the CW phase of channel 3. 3-0 CW_MIX_PH_CH[1] R/W 0h These bits control the CW mixer phase. Writing N to these bits sets the corresponding channel phase to N × 22.5°. Where, N = 0 to 15; see Table 83 for further details. When the ADD_OFFSET bit is set to 1, setting bits 3-0 programs the CW phase of channel 1. 146 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 13.1.3.1.12 Register 216 (address = D8h) Table 96. Register 216 15 14 13 CW_MIX_PH_CH15 R/W-0h 12 11 10 9 CW_MIX_PH_CH13 R/W-0h 8 7 6 5 CW_MIX_PH_CH11 R/W-0h 4 3 2 1 CW_MIX_PH_CH9 R/W-0h 0 LEGEND: R/W = Read/Write; W = Write only; -n = value Table 97. Register 216 Field Descriptions Bit Field Type Reset Description 15-12 CW_MIX_PH_CH[15] R/W 0h These bits control the CW mixer phase. Writing N to these bits sets the corresponding channel phase to N × 22.5°. Where, N = 0 to 15; see Table 83 for further details. When the ADD_OFFSET bit is set to 1, setting bits 15-12 programs the CW phase of channel 15. 11-8 CW_MIX_PH_CH[13] R/W 0h These bits control the CW mixer phase. Writing N to these bits sets the corresponding channel phase to N × 22.5°. Where, N = 0 to 15; see Table 83 for further details. When the ADD_OFFSET bit is set to 1, setting bits 11-8 programs the CW phase of channel 13. 7-4 CW_MIX_PH_CH[11] R/W 0h These bits control the CW mixer phase. Writing N to these bits sets the corresponding channel phase to N × 22.5°. Where, N = 0 to 15; see Table 83 for further details. When the ADD_OFFSET bit is set to 1, setting bits 7-4 programs the CW phase of channel 11. 3-0 CW_MIX_PH_CH[9] R/W 0h These bits control the CW mixer phase. Writing N to these bits sets the corresponding channel phase to N × 22.5°. Where, N = 0 to 15; see Table 83 for further details. When the ADD_OFFSET bit is set to 1, setting bits 3-0 programs the CW phase of channel 9. 13.1.3.1.13 Register 217 (address = D9h) Table 98. Register 217 15 14 LNA_GAIN_CH15 R/W-0h 13 12 LNA_GAIN_CH13 R/W-0h 11 10 LNA_GAIN_CH11 R/W-0h 9 8 LNA_GAIN_CH9 R/W-0h 7 6 LNA_GAIN_CH7 R/W-0h 5 4 LNA_GAIN_CH5 R/W-0h 3 2 LNA_GAIN_CH3 R/W-0h 1 0 LNA_GAIN_CH1 R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 147 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com Table 99. Register 217 Field Descriptions Field Type Reset Description 15-14 Bit LNA_GAIN_CH[15] R/W 0h To enable this bit, set LNA_GAIN_IND_EN (register 196, bit D15) to 1. 00 = 18 dB 01 = 24 dB 10 = 12 dB 11 = Do not use When ADD_OFFSET is 1, the gain of channel 15 is programmed. 13-12 LNA_GAIN_CH[13] R/W 0h To enable this bit, set LNA_GAIN_IND_EN (register 196, bit D15) to 1. 00 = 18 dB 01 = 24 dB 10 = 12 dB 11 = Do not use When ADD_OFFSET is 1, the gain of channel 13 is programmed. 11-10 LNA_GAIN_CH[11] R/W 0h To enable this bit, set LNA_GAIN_IND_EN (register 196, bit D15) to 1. 00 = 18 dB 01 = 24 dB 10 = 12 dB 11 = Do not use When ADD_OFFSET is 1, the gain of channel 11 is programmed. 9-8 LNA_GAIN_CH[9] R/W 0h To enable this bit, set LNA_GAIN_IND_EN (register 196, bit D15) to 1. 00 = 18 dB 01 = 24 dB 10 = 12 dB 11 = Do not use When ADD_OFFSET is 1, the gain of channel 9 is programmed. 7-6 LNA_GAIN_CH[7] R/W 0h To enable this bit, set LNA_GAIN_IND_EN (register 196, bit D15) to 1. 00 = 18 dB 01 = 24 dB 10 = 12 dB 11 = Do not use When ADD_OFFSET is 1, the gain of channel 7 is programmed. 5-4 LNA_GAIN_CH[5] R/W 0h To enable this bit, set LNA_GAIN_IND_EN (register 196, bit D15) to 1. 00 = 18 dB 01 = 24 dB 10 = 12 dB 11 = Do not use When ADD_OFFSET is 1, the gain of channel 5 is programmed. 3-2 LNA_GAIN_CH[3] R/W 0h To enable this bit, set LNA_GAIN_IND_EN (register 196, bit D15) to 1. 00 = 18 dB 01 = 24 dB 10 = 12 dB 11 = Do not use When ADD_OFFSET is 1, the gain of channel 3 is programmed. 1-0 LNA_GAIN_CH[1] R/W 0h To enable this bit, set LNA_GAIN_IND_EN (register 196, bit D15) to 1. 00 = 18 dB 01 = 24 dB 10 = 12 dB 11 = Do not use When ADD_OFFSET is 1, the gain of channel 1 is programmed. 148 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 14 Device and Documentation Support 14.1 Documentation Support 14.1.1 Related Documentation AFE5816 Data Sheet, SBAS688 MicroStar BGA Packaging Reference Guide, SSYZ015 Clocking High-Speed Data Converters, SLYT075 Design for a Wideband Differential Transimpedance DAC Output, SBAA150 TI Active Filter Design Tool, WEBENCH® Filter Designer CDCM7005 Data Sheet, SCAS793 CDCE72010 Data Sheet, SCAS858 TLV5626 Data Sheet, SLAS236 DAC7821 Data Sheet, SBAS365 THS413x Data Sheet, SLOS318 OPA1632 Data Sheet, SBOS286 LMK048x Data Sheet, SNAS489 OPA2211 Data Sheet, SBOS377 ADS8413 Data Sheet, SLAS490 ADS8472 Data Sheet, SLAS514 ADS8881 Data Sheet, SBAS547 SN74AUP1T04 Data Sheet, SCES800 UCC28250 Data Sheet,SLUSA29 ISO7240 Data Sheet, SLLS868 14.2 Trademarks All trademarks are the property of their respective owners. 14.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 14.4 Export Control Notice Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled product restricted by other applicable national regulations, received from disclosing party under nondisclosure obligations (if any), or any direct product of such technology, to any destination to which such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S. Department of Commerce and other competent Government authorities to the extent required by those laws. 14.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 149 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com 15 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 150 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 AFE5818 www.ti.com SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 15.1 Tray Information Figure 169. Tray Diagram, Section 1 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 151 AFE5818 SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015 www.ti.com Tray Information (continued) Figure 170. Tray Diagram, Section 2 152 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE5818 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) AFE5818ZBV ACTIVE NFBGA ZBV 289 126 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 AFE5818 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of