AFE8201PFBT

AFE8201 SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005 IF Analog-to-Digital Converter with Digital Downconverter FEATURES D D 12-BIT, 80MSPS ADC INTEGRATED DIGITAL DOWNCONVERTER (DDC): DESCRIPTION The AFE8201 consists of a general-purpose, 80MSPS, 12-bit analog-to-digital converter (ADC), a digital downconverter (DDC), and user-programmable digital filters. It is designed to sample narrowband (2.5MHz or less) IF signals and digitally mix, filter, and decimate the signals to baseband. The DDC consists of a digital quadrature mixer followed by a CIC decimation filter and FIR filters. The mixer frequency and initial phase are independently programmed by 32-bit control words. D D D D D Quadrature Mixer/NCO CIC Decimation Filter FIR Filters MIXER: 32-BIT FREQUENCY AND PHASE DECIMATION RATIO: 32 to 4096 USER PROGRAMMABLE FIR FILTERS WITH 16-BIT COEFFICIENTS 12-BIT AUXILIARY DAC DATA INTERFACE COMPATIBLE WITH TI C5x/C6x DSP BUFFERED SERIAL PORT (McBSP): D D D D D D D D Code Composer Module for Easy Software Generation SPI CONTROL INTERFACE 3.3V ANALOG, 1.8V DIGITAL SUPPLY 1.8V to 3.3V I/O SUPPLY TQFP-48 APPLICATIONS SOFTWARE RADIOS IF RECEIVE CHANNEL DIGITAL RADIO RECEIVERS NARROWBAND RECEIVERS Following the first FIR filter are two parallel FIR filters that can be used to provide two output streams or interleaved to form one extended filter with up to 262 taps. The AFE8201 also contains a 12-bit general-purpose auxiliary digital-to-analog converter (DAC) for applications such as AGC amplifier control. Control register data as well as decimation filter coefficients are written to the AFE8201 through the industry-standard SPI control interface. The baseband output signals are transported through a generalpurpose, high-speed serial interface that is compatible with TI C5x/C6x DSP family buffered serial ports (McBSP). IFP IFM 12− Bit Pipeline ADC DOUT0 Quadrature Mixer CIC Filter N FIR Filter 1 2 FIR Filter 2A 2 Data Interface DOUT1 DFSO DCLK DIN NCO FIR Filter 2B 2 AUX Auxiliary DAC DFSI Voltage Reference Clock Interface Timing Generator SPI Control Interface REFM VCM REFP VGB MCLK MCLKB PWD SYNC RST_N SCK MOSI MISO CS_N Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright  2003−2005, Texas Instruments Incorporated www.ti.com PRODUCT PREVIEW After the CIC filter, the internal I and Q signals are passed on to the first FIR filter, which can implement even, odd, halfband, and arbitrary impulse responses with up to 62 taps using 16-bit coefficients. AFE8201 www.ti.com SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005 ORDERING INFORMATION(1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PFB SPECIFIED TEMPERATURE RANGE −40°C to +85°C PACKAGE MARKING AFE8201 ORDERING NUMBER AFE8201PFBT AFE8201PFBR TRANSPORT MEDIA, QUANTITY Tape and Reel, 250 Tape and Reel, 2000 AFE8201 TQFP-48 (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) Supply Voltage Range: AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5V to 4V DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5V to 2.3V IOVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5V to 3.6V Voltage Between AGND and DGND . . . . . . . . . . . . . −0.3V to 0.5V Voltage Between AVDD to DVDD . . . . . . . . . . . . . . . −3.3V to 3.3V Digital Inputs(2) . . . . . . . . . . . . . . . . . . . . . . . −0.3V to DVDD + 0.3V Digital Output Data . . . . . . . . . . . . . . . . . . . . −0.3V to DVDD + 0.3V Operating Free-Air Temperature Range. TA . . . . . . −40°C to 85°C Storage Temperature Range . . . . . . . . . . . . . . . . . −55°C to +125°C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions beyond those indicated under the Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Measured with respect to DGND. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PRODUCT PREVIEW RECOMMENDED OPERATING CONDITIONS MIN Supplies and References Operating Free-Air Temperature, TA Analog Supply Voltage, AVDD Digital Supply Voltage, DVDD Output Driver Supply Voltage, IOVDD Input Common-Mode Voltage Differential Input Voltage Range Clock Inputs: MCLK and MCLKB Sample Rate, fS Differential Input Mode Voltage Input Swing Differential Input Common-Mode Voltage Single-Ended Mode High-Level Input Voltage, VIHC Single-Ended Mode Low-Level Input Voltage, VILC Clock Pulse Width High, tW(H) Clock Pulse Width Low, tW(L) Digital Inputs High-Level Input Voltage, VIH Low-Level Input Voltage, VIL 0.7 × IOVDD 0.25 × IOVDD V V 5.625 5.625 6.25 6.25 2 0.8 5 0.4 1.65 80 3.3 MHz V V V V ns ns −40 3.15 1.6 1.6 VCM 2 3.3 1.8 85 3.45 2.0 3.6 °C V V V V VPP TYP MAX UNITS 2 AFE8201 www.ti.com SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005 AUXILIARY DAC CHARACTERISTICS All specifications at +25°C, AVDD = +3.3V, and DVDD = +1.8V, unless otherwise noted. PARAMETER Resolution Input code 0x000 Output voltage range Output impedance Settling time Offset Gain error DC performance Differential nonlinearity, DNL Integral nonlinearity, INL Power-supply rejection ratio, PSRR Ensured monotonic After correcting for gain and offset errors Input code 0x400, AVDD = 3.15VDC to 3.45VDC to 0.1% FSR ±1 ±5 ±0.5 ±2 60 Input code 0xFFF CONDITIONS MIN TYP 12 0.0 2.75 1 10 MAX UNIT bits V V kΩ µs % of FSR % of FSR LSB LSB dB RECEIVE CHANNEL CHARACTERISTICS All specifications at +25°C, fS = 80MSPS, AVDD = +3.3V, DVDD = +1.8V, IOVDD = +3.3V, Gain = 1, Decimation Ratio = 80, Internal Digital Filter Bandwidth = 264kHz, and Input Signal = 10.7MHz, unless otherwise noted. PARAMETER DC Accuracy Input impedance Differential nonlinearity, DNL Integral nonlinearity, INL Offset error Gain error Gain = 1 Gain = 1.14 Gain = 1.33 Full-scale input level (peak differential) Gain = 1.6 Gain = 2.0 Gain = 2.67 Gain = 4.0 Gain change settling time Power-supply rejection ratio, PSRR References Negative reference, VREFN Positive reference, VREFP Common-mode voltage, VCM AC Performance Input 455kHz, −1dBFS Spurious-free dynamic range, SFDR 2nd-order harmonic, HD2 Input 10.7MHz, −1dBFS Input 10.7MHz, −1dBFS Input 455kHz, −1dBFS Signal-to-noise ratio, SNR Aperture delay Aperture uncertainty Power Supply Analog supply voltage, AVDD Digital supply voltage, DVDD Output driver supply voltage, IOVDD Normal operation Power dissipation Digital I/O supply current Digital supply current Analog supply current Power-down 3.15 1.71 3.15 3.3 1.8 3.3 490 20 7 72 103 3.45 1.89 3.45 570 V V V mW mW mA mA mA Input 10.7MHz, −1dBFS In 3kHz bandwidth, −1dBFS, 10.7MHz, 20kHz from fundamental 70 76 76 86 80 75 74 102 2 0.2 dBc dBc dBc dB dB dB ns ps 1.1 2.1 1.25 2.25 1.8 1.4 2.4 V V V Number of samples to achieve rated accuracy AVDD = 3.15VDC to 3.45VDC −0.0244 −0.0244 6.25 ±0.0122 ±0.012 3 1 1.0 0.875 0.75 0.625 0.5 0.375 0.25 2 70 +0.0244 +0.0244 kΩ %FSR %FSR mV %FS V V V V V V V Samples dB CONDITIONS MIN TYP MAX UNIT 3 PRODUCT PREVIEW AFE8201 www.ti.com SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005 DIGITAL INTERFACE SPECIFICATIONS PARAMETER High Level Input Current, IIH Low-Level Input Current, IIL High-Level Output Voltage, VOH Low-Level Output Voltage, VOL All specifications at +25°C, AVDD = 3.3V, DVDD = 1.8V, and VDDS = 3.3V, unless otherwise noted. CONDITIONS VIH = 1.6V to 3.6V VIL = 0V to 0.4V IOH = −50µA IOL = 50µA MIN −10 −10 0.8 × IOVDD 0.2 × IOVDD TYP MAX 10 10 UNITS µA µA V V DATA INTERFACE TIMING DCLKO DFSO DOUT0 IA[15] IA[14] IA[13] IA[12] DOUT1 IB[15] td1 td2 t d3 IB[14] IB[13] IB[12] PRODUCT PREVIEW Figure 1. Data Interface Timing 1 PARAMETER DCLKO to DFSO Delay, td1 DCLKO to DOUT0 Delay, td2 DCLKO to DOUT1 Delay, td3 CONDITIONS MIN −0.4 −0.2 −0.2 TYP MAX 3.2 2.5 2.5 UNITS ns ns ns DCLKO DFSI DIN tsu1 t h1 tsu2 D[15] D[14] D[13] D[12] th2 Figure 2. Data Interface Timing 2 PARAMETER DFSI to DCLKO Setup Time, tsu1 DFSI to DCLKO Hold Time, th1 DIN to DCLKO Setup Time, tsu2 DIN to DCLKO Hold Time, th2 CONDITIONS MIN 1.2 0.4 1.0 0.4 TYP MAX UNITS ns ns ns ns 4 AFE8201 www.ti.com SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005 CONTROL INTERFACE TIMING SCK CS_N MOSI MISO tL t su3 th3 td4 tT tI Figure 3. Control Interface Timing PARAMETER Maximum SCK Frequency CS_N Leading Time, tL CS_N Trailing Time, tT CS_N Idle Time, tL MOSI to SCK Setup Time, tsu3 MOSI to SCK Hold Time, th3 SCK to MISO Delay Time, td4 Leading CS_N to Trailing CS_N Trailing CS_N to Leading SCK Trailing SCK to Leading CS_N 5.0 5.0 5.0 5.0 1.0 1.0 8.0 CONDITIONS MIN TYP MAX 1 UNITS MHz ns ns ns ns ns 5 PRODUCT PREVIEW ns AFE8201 www.ti.com SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005 PIN ASSIGNMENTS IOGND IOGND 38 IOVDD DGND AGND AGND AGND DVDD AVDD AVDD AVDD PWD 37 36 SYNC 35 RST_N 34 DOUT1 33 DOUT0 32 DCLK 31 DFSO 30 DIN 29 DFSI 28 SCK 27 MISO 26 MOSI 25 CS_N 13 AVDD 14 AUX 15 AGND 16 NC 17 AGND 18 MCLK 19 MCLKB 20 AVDD 21 DGND 22 DVDD 23 IOGND 24 IOVDD 48 AVDD 1 AGND 2 IFP 3 IFM 4 AGND 5 VCM 6 AVDD 7 VREFM 8 VREFP 9 AVDD 10 AGND 11 47 46 45 44 43 42 41 40 39 AFE8201 PRODUCT PREVIEW VBG 12 NAME IFP IFM VCM REFM REFP VGB AUX MCLK MCLKB CS_N MOSI MISO SCK DFSI DIN DFSO DCLK DOUT0 DOUT1 RESET SYNC PWD AVDD AGND DVDD DGND IOVDD IOGND PIN 3 4 6 8 9 12 14 18 19 25 26 27 28 29 30 31 32 33 34 35 36 37 1, 7, 10, 13, 20, 45, 46, 48 2, 5, 11, 15, 17, 43, 44, 47 22, 41 21, 42 24, 39 23, 38, 40 TYPE Input Input Output Output Output Output Output Input Input Input Input Output Input Input Input Output Output Output Output Input Input Input Supply Ground Supply Ground Supply Ground FUNCTION Positive IF Input Negative IF Input Common-Mode Voltage Output Negative Reference Voltage Output Positive Reference Voltage Output Bandgap Voltage Output Auxiliary DAC Output Master Clock Input Complementary Master Clock Input SPI Chip Select (active low) SPI Serial Input SPI Serial Output SPI Serial Clock Data Interface Input Frame Sync Data Interface Input Data Data Interface Output Frame Sync Data Interface Clock Output Data Interface Filter 0 Output Data Data Interface Filter 1 Output Data Global Reset External Sync ‘1’ = power down; ‘0’ = normal operation Analog Supply (3.3V) Analog Ground Digital Supply (1.5V to 1.8V) Digital Ground Digital I/O Supply (1.5V to 3.3V) Digital I/O Ground 6 AFE8201 www.ti.com SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005 DETAILED DESCRIPTION The AFE8201 consists of a general-purpose, 80MSPS, 12-bit analog-to-digital converter (ADC) with programmable input range, Digital Downconverter (DDC), and user programmable digital filters with 16-bit coefficients. It is designed to sample narrowband (up to 2.5MHz) IF signals and digitally mix, filter, and decimate the signals to baseband. The ADC integrates a programmable gain sample-and-hold amplifier that is variable over gains of 1x to 4x to change the full-scale input voltage range of the device from 1.0V peak to 0.25V peak. When the gain is changed, two sample periods may be needed for the output of the ADC to settle to the correct value. The DDC consists of a digital quadrature mixer followed by a CIC decimation filter and FIR filters (FIR1 and FIR2). The mixer frequency and initial phase are independently programmed by 32-bit control words. The quadrature mixer generates I and Q signals, each of which are decimated by the CIC filter. The CIC is a 5th-order Comb filter with a decimation factor that is programmable over a range of 8 to 1024. Each of the FIR filters adds an additional deciamtion factor of 2, for a total range of 32 to 4096. The I and Q signals generated by the quadrature mixer are then passed on to the first FIR filter (FIR1). This decimate-by-two FIR filter can implement even, odd, halfband, and arbitrary impulse responses. The length of the filter response is dependent on the decimation factor of the CIC filter and the FIR filter response type, up to a maximum of 62 taps. Coefficients for multiple filter responses may be stored in the coefficient memory (up to 64 unique coefficients may be stored); responses can be changed by changing a control register to point the filter to a different section of coefficient memory. Following the first FIR filter are two parallel decimate-by-two FIR filters (FIR2a and FIR2b). These filters are similar to the first FIR filter, but have twice the data and coefficient memory and can therefore realize longer filter responses. The responses of the two filters can be different from each other (with some limitations). In addition, the two filters can be optionally interleaved to form a single extra-long FIR filter which can realize up to 250 taps. Control register information, as well as decimation filter coefficients, are written to the AFE8201 through the industry-standard SPI control interface. The baseband output signals are transported through a high-speed serial interface that is compatible with the TI C5x/C6x DSP buffered serial ports (McBSP). The AFE8201 also contains a 12-bit auxiliary digital-to-analog converter (DAC) which can be used for a number of purposes, including tuner automatic gain control or frequency control. Input data for the DAC may be sent either from the DSP through the serial data port or from a microcontroller through the SPI control interface. CONTROL INTERFACE The AFE8201 uses an SPI slave interface to read and write control data. Control data consists of eleven 16-bit control registers, as shown in Table 1, and three memory banks (see Table 2). The control registers are used to program all chip parameters. The memory banks store 16-bit FIR filter coefficient data. To read and write to control registers and memory banks, data is transferred by a 16-bit instruction followed by 16 bits of data. Memory bank read and write operations also support block transfer. Memory bank block transfer consists of a 16-bit instruction followed by multiple 16 bit data words. Table 1. Control Registers Register Address 0 1 2 3 4 5 6 7 8 9 10 11 12 Description Data interface parameters DIV, MODE NCO frequency (bits 0−15) NCO frequency (bits 16−31) NCO Initial Phase (bits 0−15) NCO Initial Phase (bits 16−31) CIC Filter Decimation Rate: DEC_RATE CIC Filter Parameters: SCALE, SHIFT First FIR Filter Parameters: BASE_ADDR, NCOEFF, MODE Second FIR A Filter Parameters: BASE_ADDR, NCOEFF, MODE Second FIR B Filter Parameters: BASE_ADDR, NCOEFF, MODE Setup for the Second FIR Auxiliary DAC: DAC_DATA ADC Parameters: GAIN, PWD 7 PRODUCT PREVIEW AFE8201 www.ti.com SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005 Table 2. Memory Banks Memory Bank Address 0 1 2 Description FIR Filter 1 Coefficients FIR Filter 2A Coefficients FIR Filter 2B Coefficients Size 64 Coefficients 128 Coefficients 128 Coefficients Data Memory 62 Samples 126 Samples 126 Samples The SPI interface consists of four signals: a serial clock (SCK), an active-low chip select (CS_N), a serial data input (MOSI—M aster Out, Slave In), and a serial data output (MISO—Master In, Slave Out). Data is transferred in groups of 32 bits. The first 16 bits are the instruction, which indicate: (1) if data is to be written or to be read; (2) if the data target is a control register or a memory bank; and (3) the address of the data target. The second 16 bits is the data transfer, which is input on MOSI for a write cycle or output on MISO for a read cycle. PRODUCT PREVIEW A single data word write cycle is shown in Figure 4. The cycle is initiated by the high-to-low transition of the CS_N line. 32 SCK pulses clock the instruction and the data into the MOSI line. Instructions and data are clocked in MSB first. The first 16 bits are the instruction; the second 16 bits are the data word. There are two possible single data word write cycle instructions: register write and memory write. The formats for these instructions are shown in Figure 5 and Figure 6. SCK CS_N MSB MOSI LSB MISO Instruction Data Figure 4. Single Data Word Control Interface Write Cycle for Registers or Memory 1 15 0 14 0 13 12 11 REG_ADDR 10 9 8 7 6 5 Don’t Care 4 3 2 1 0 Figure 5. Register Write Instruction Format 1 15 0 14 1 13 12 Don’t Care 11 10 9 MEM 8 7 6 5 MEM_ADDR 4 3 2 1 0 Figure 6. Memory Write Instruction Format The only information required for a register write is the 5-bit register address (REG_ADDR). For a memory write, the 2-bit memory select (MEM) and the 8-bit memory address (MEM_ADDR) are required. Following the 16-bit instruction, the 16-bit data word is clocked in, again MSB first. At the end of the write cycle this data word is written to the appropriate register or memory location in the AFE. 8 AFE8201 www.ti.com SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005 The read cycle is illustrated in Figure 7. It is similar to the write cycle, except that instead of the data word being clocked into MOSI during the second half of the cycle, the data word is clocked out of MISO. The two data read instructions are similar to the corresponding data write instructions and are shown in Figure 8 and Figure 9. SCK CS_N MSB MOSI MSB MISO Instruction Data LSB LSB Figure 7. Single Data Word Control Interface Read Cycle for Registers or Memory 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 8. Register Read Instruction Format 0 15 1 14 1 13 12 Don’t Care 11 10 9 MEM 8 7 6 5 MEM_ADDR 4 3 2 1 0 Figure 9. Memory Read Instruction Format Block transfers are supported for memory reading and writing. Multiple data words are transmitted following the memory read or write instruction for a block transfer. The data words are sequentially read from or written to RAM sequentially starting at the address contained in the instruction. The sequential RAM access terminates when the CS_N line goes high. Figure 10 shows a memory block read cycle. In the illustration, three successive memory locations are read starting at address N. The memory block write cycle is similar, except of course data is clocked into MOSI. SCK CS_N MSB LSB MSB MISO Instruction Data (N) Data (N + 1) Data (N + 2) LSB Figure 10. Block Memory Read Cycle Control Interface In all cases, the control interface is reset when CS_N goes high. If the final SCK is not received before CS_N goes high, then the cycle will end prematurely. For a read cycle, transfer of data will terminate; for a write cycle, no data will be written to register or memory. 9 PRODUCT PREVIEW 0 1 0 REG_ADDR Don’t Care AFE8201 www.ti.com SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005 DATA INTERFACE The data interface consists of six signals: 1. serial data clock DCLKO; 2. output frame sync DFSO; 3. output data line DOUT0; 4. output data line DOUT1; 5. input frame sync DFSI; and 6. input data line DIN. The decimation filter outputs from the DDC (either IA and QA, or IA, QA, IB, and QB) are multiplexed onto the data outputs. The control DAC data is shifted into the data input. Control Register 0 programs the functionality of the data interface, as seen in Figure 11. 0 0 0 0 0 15 14 13 12 11 10 Don’t Care 9 8 7 6 5 4 3 2 DIV 1 MODE 0 Register Address Figure 11. Data Interface Control Register PRODUCT PREVIEW Two parameters, DIV and MODE, control the data interface and are programmed by register 0. The first parameter is DIV. The serial data clock, DCLKO, is derived from MCLK in a manner controlled by DIV such that the frequency of DCLKO is: f f DCLKO + MCLK 2 DIV (1) where DIV ranges from 0 to 3. As an example, if MCLK is 80MHz, DCLK0 can be either 80MHz, 40MHz, 20MHz, or 10MHz. DCLK0, of course, must be fast enough to clock out the I and Q data words generated by the on-chip DDC and filters. The second parameter is MODE. When MODE is 0, all four DDC outputs are time multiplexed onto DOUT0, as shown in Figure 12. When MODE is 1, IA and QA outputs are multiplexed onto DOUT0 while IB and QB outputs are multiplexed onto DOUT1, see Figure 13. If only one set of I/Q outputs is used, MODE 1 is recommended so that data is output through DOUT0. DCLKO DFSO MSB DOUT0 IA LSB QA IB QB DOUT1 DFSI MSB DIN DAC LSB Figure 12. Data Interface Timing for MODE = 0 10 AFE8201 www.ti.com SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005 DCLKO DFSO MSB DOUT0 MSB DOUT1 IB QB IA QA LSB LSB DFSI MSB DIN DAC LSB Figure 13. Data Interface Timing for MODE = 1 When the data interface receives new outputs from the decimation filters, an output cycle is started by asserting DFSO for one DCLKO period. On successive leading edges of DCLKO, the filter output data is shifted out MSB first on DOUT0 (and DOUT1 for MODE = 1), as shown in the timing diagrams. The spacing of the DFSO pulses depends on two settings: the overall decimation ratio R of the DDC and the factor DIV. The number of bits which need to be transmitted in one frame, NBITS, is 64 for MODE = 0 and 32 for MODE = 1. In order to have enough DCLKO cycles between DFSO pulses, the following relationship must be true: R w NBITS 2 DIV or (2) DIV v log 2 R NBITS (3) For example, assume the overall decimation ratio, R, for the DDC is 80. For MODE = 0, the largest allowable value for DIV is 0. In other words, if MCLK is 80MHz, for R = 80, DCLKO must be 80MHz so that all of the 64 data bits may be clocked out before the next I and Q data words must be clocked out. For MODE = 1, since only 32 bits need to be clocked out during one cycle, DCLKO can be reduced to 40MHz (which means that DIV may be increased to 1, cutting the frequency of DCLKO in half). DFSI and DIN are used to send control DAC data to the AFE8201. DCLKO supplied by the AFE8201 is used as the serial clock. An input cycle is initiated by holding DFSI high through one rising edge of DCLKO. On the successive 16 leading edges of DCLKO the input data word is read in serially, MSB first. The lower 12 bits of the data word are sent to the DAC as the unsigned DAC input. Note that the input data does not need to bear any timing relationship to the output data, except that both data streams are synchronous with DCLKO. QUADRATURE MIXER/NCO The NCO frequency and initial phase are set by the 32-bit unsigned variables FREQ and PHASE. Each of these variables is set via a pair of control registers; see Figure 14. The I and Q outputs of the mixer are given by: I + ADC Q + ADC sin(2pft ) f) and (4) (5) cos(2pft ) f) FREQ 232 where ADC is the output of the IF A/D converter, f is the NCO frequency given by: f + f MCLK and φ is the NCO phase offset (in radians) given by: (6) f + 2p PHASE 232 (7) 11 PRODUCT PREVIEW AFE8201 www.ti.com SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005 MSB 0 0 0 0 1 15 14 13 12 11 10 9 FREQ[15:0] 8 7 6 5 4 3 2 1 LSB Register Address 0 0 0 0 1 0 15 14 13 12 11 10 9 FREQ[31:16] 8 7 6 5 4 3 2 1 0 Register Address 0 0 0 1 1 15 14 13 12 11 10 9 PHASE[15:0] 8 7 6 5 4 3 2 1 0 Register Address 0 0 1 0 0 15 14 13 12 11 10 9 PHASE[31:16] 8 7 6 5 4 3 2 1 0 Register Address Figure 14. Mixer Control Registers PRODUCT PREVIEW The SYNC pin can be used to externally control the phase of mixer. While the SYNC pin is high, the phase accumulator is held to a constant value PHASE, essentially holding t to zero in the I and Q equations. When the SYNC pin is brought low, the phase accumulator is incremented by the value FREQ once per MCLK cycle. Note that the mixer can be bypassed by setting FREQ and PHASE to 0 and using only the Q (real) output. CIC FILTER The first stage of decimation filtering is provided by a 5th-order CIC filter. The operation of the CIC filter is controlled by the unsigned variable DEC_RATE, SCALE, and SHIFT which are mapped into control registers as illustrated in Figure 15. The valid range for DEC_RATE is from 8 to 1024. 0 0 1 0 1 15 14 Don’t Care 13 12 11 10 9 8 7 6 DEC_RATE 5 4 3 2 1 0 Register Address 0 0 1 1 0 15 Don’t Care 14 13 12 11 10 SCALE 9 8 7 6 5 4 3 SHIFT 2 1 0 Register Address Figure 15. CIC Filter Control Registers The inherent dc gain of the CIC filter is DEC_RATE5. The control variables SHIFT and SCALE are used to reduce this very high gain before the signal is output to the next stage of decimation filter. The combined effect of DEC_RATE, SHIFT, and SCALE produces an overall dc gain for the CIC filter of: Gain + DEC_RATE 5 Scale 32 2 shift (8) In general, SHIFT and SCALE should be chosen to make GAIN as close to 1 as possible. For example, if DEC_RATE is 20, setting SHIFT to 22 and scale to 41 will result in a GAIN of 0.9775. 12 AFE8201 www.ti.com SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005 FIRST FIR FILTER The block following the CIC filter is a decimate-by-two FIR filter with programmable coefficients. MODE sets the type of filter response—ODD (MODE = 00: symmetric impulse response, odd number of taps), EVEN (MODE = 01: symmetric impulse response, even number of taps), HALFBAND (MODE = 10), and ARBITRARY (MODE = 11: non-symmetric impulse response). The 16-bit wide filter coefficients are stored in memory bank 0. Up to 64 coefficients can be stored in this memory. Depending on the types of filters desired and the number of taps, coefficients for multiple filter responses may be stored in the memory bank. The filter response may be changed simply by updating the control register with new values for MODE, NCOEFF, and BASE_ADDR, as shown in Figure 16. 0 0 1 1 1 Don’t Care 15 14 13 12 BASE_ADDR 11 10 9 8 7 6 NCOEFF 5 4 3 2 1 MODE 0 Register Address Figure 16. First FIR Filter Control Register NCOEFF defines the number of unique filter coefficients which make up the filter response. BASE_ADDR defines the memory location where the first filter coefficient is stored. The actual filter length is a function of MODE and NCOEFF: Filter length = 2(NCOEFF − 1) + 1 for ODD Filter length = 2NCOEFF for EVEN Filter length = 4(NCOEFF − 1) + 1 for HALFBAND Filter length = NCOEFF for ARBITRARY The maximum filter length which can be realized is limited by two factors. First, the number of clock cycles between successive filter outputs limits the number of coefficients which can be processed to: NCOEFF v 2 DEC_RATE * 4 (9) where DEC_RATE is the decimation ration of the CIC filter. Second, the size of the data memory (which stores incoming data samples) limits filter length to 62 taps. A filter response is defined by a set of NCOEFF 16-bit filter coefficients stored in memory bank 0 (MEM = 0) starting at address BASE_ADDR. MODE determines how the coefficients are applied to the samples stored in data memory. Figure 17 is an example illustrating how the filter coefficients are applied to stored input samples in the various filter modes with NCOEFF = 6. Because NCOEFF = 6 in this example, six computation cycles are required to calculate the filter output regardless of the filter mode. The leftmost grouping in Figure 17 represents the six filter coefficients stored at ascending memory address in the coefficient memory starting at BASE_ADDR. At each computation cycle, the coefficient being applied to the input data is highlighted. The leftmost grouping in Figure 17 represents the six filter coefficients stored at ascending memory address in the coefficient memory starting at BASE_ADDR. At each computation cycle, the coefficient being applied to the input data is highlighted. The four groupings on the right in Figure 17 represent the four filter modes: EVEN, ODD, HALFBAND, and ARBITRARY. In each column, the locations in data memory that are operated on at each computation cycle is shown. The leftmost data sample in each group is the newest sample, the rightmost sample is the oldest. The chart illustrates the order in which computation on data occurs. To use the chart, select the filter mode of interest, then move down the chart through the six computation cycles to understand the sequence of calculations. 13 PRODUCT PREVIEW PRODUCT PREVIEW 14 COMPUTATION CYCLE 5 4 3 2 BA SE _A D DR BAS E _AD DR +1 BAS E _AD DR +2 BAS E _AD DR +3 BAS E _AD DR +4 BAS E _AD DR +5 B ASE _ ADD R+5 BA SE_ A DD R+5 BAS E_ AD DR +5 BA S E_A DD R+ 5 B ASE _ ADD R+4 BA SE_ A DD R+4 BAS E_ AD DR +4 BA S E_A DD R+ 4 B ASE _ ADD R+2 B ASE _ ADD R+3 BA SE_ A DD R+2 BA SE_ A DD R+3 BAS E_ AD DR +2 BAS E_ AD DR +3 BA S E_A DD R+ 2 BA S E_A DD R+ 3 B ASE _ ADD R+1 BA SE_ A DD R+1 BAS E_ AD DR +1 BA S E_A DD R+ 1 B ASE _ AD DR B ASE _ ADD R BA SE _AD DR B A SE_ A DD R AFE8201 6 1 BA SE _A D DR BAS E_ AD DR +1 BAS E_ AD DR +2 BAS E_ AD DR +3 BAS E_ AD DR +4 COEFFICIENT BANK BAS E_ AD DR +5 N N +1 N +2 N +3 N +4 N +5 N +6 N +7 N +8 N +9 N+ 10 N+ 11 N +11 N +11 N+11 N +10 N +10 N+10 N+9 N+9 N +9 N+8 N+8 N +8 N+7 N+7 N +7 N+6 N+6 N +6 N+5 N+5 N +5 N+5 N+6 N+7 N+8 N+9 N +10 N +11 N+3 N+4 N+3 N+4 N +3 N +4 N+3 N+4 N+2 N+2 N +2 N+2 N N +1 N N+1 N N+1 N N +1 N N+1 N +2 N +3 N +4 N +5 EVEN N +6 SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005 N +7 N +8 N +9 N+10 N+11 N N +1 N +2 N +3 N +4 N +5 N +6 N +7 N +8 N +9 N+ 10 N +10 N +10 N+9 N+9 N+8 N+8 N+7 N+7 N+5 N+6 N+5 N+6 N+4 N+4 N +4 N +5 N +6 N +7 N +8 N +9 N+10 N+2 N+3 N+2 N+3 N +2 N +3 N+1 N+1 N +1 N N N N N N +1 N +2 N +3 N +1 N +2 N +3 ODD N +4 N +4 N +5 N +6 N +7 N +8 N +9 N +1 0 N +5 N +6 N +7 N +8 N +9 N+ 10 N N +1 N +2 N +3 N +4 N +5 N +6 N +7 N +8 N +9 N+10 N+11 N+12 N+13 N+14 N+15 N+16 N+17 N+18 N +1 7 N +1 8 N +1 5 N +1 6 N +1 4 N +1 2 N +1 3 N +1 1 N+9 N +1 0 N+8 N+7 N+5 N+6 N+4 N+4 N+5 N+6 N+7 N+8 N+9 N +1 0 N +1 1 N +1 2 N +1 3 N +1 4 N +1 5 N +1 6 N +1 7 N +1 8 N+2 N+3 N+2 N+3 N N +1 N N+1 N N+1 N N +1 N +2 N +3 N +4 N +5 N +6 N +7 N +8 N +9 N+1 0 N+1 1 N+1 2 N+1 3 N+1 4 N+1 5 N+1 6 N+1 7 N+1 8 N N +1 N +2 N +3 N +4 N +5 N +6 N +7 N +8 N +9 N+1 0 N+1 1 N+1 2 N+1 3 N+1 4 N+1 5 N+1 6 N+1 7 N+1 8 FILTER PROCESSING N +2 N +3 N +4 N +5 N +6 N +7 N +8 N +9 N+1 0 HALFBAND N+1 1 N+1 2 N+1 3 N+1 4 Figure 17. Application of Filter Coefficients in Different Filter Modes N N +1 N +2 N +3 N +4 N +5 N N +1 N +2 N +3 N +4 N +5 N N+ 1 N+ 2 N+ 3 N+ 4 N+ 5 N N+1 N+2 N+3 N+4 N+5 N N+1 N+2 N+3 N+4 N+5 N+1 5 N+1 6 N+1 7 N+1 8 N N +1 N +2 N +3 N +4 ARBITRARY www.ti.com N +5 AFE8201 www.ti.com SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005 For example, using the ODD mode in the first cycle of MCLK, the filter coefficient at BASE_ADDR is applied to two values in data memory, the most recent at address N and the oldest at address N+10. In the next cycle of MCLK the coefficient at BASE_ADDR+1 is applied to the data values at N+1 and N+9, and so on until the last coefficient at BASE_ADDR+5 is reached. Because this is an odd filter, the final coefficient is applied only to the data value at address N+5. The full cycle is shown in Table 3. Table 3. ODD Mode Calculation Example with Six Filter Coefficients Cycle 1 2 3 4 5 6 Filter Coefficient Address BASE_ADDR BASE_ADDR+1 BASE_ADDR+2 BASE_ADDR+3 BASE_ADDR+4 BASE_ADDR+5 Applied to Data Address N and N+10 N+1 and N+9 N+2 and N+8 N+3 and N+7 N+4 and N+6 N+5 Figure 17 clearly illustrates that the overall filter length is different in different filter mode even if NCOEFF is unchanged. For NCOEFF = 6, filter length ranges from 6 taps for ARBITRARY mode to 19 taps for HALFBAND mode. The dc gain of the FIR filter depends on the coefficient values and the filter mode. NCOEFF * 1 GAIN + h NCOEFF ) n+1 S 2hn 2 15 * 1 (10) where hn is the nth of NCOEFF filter coefficients stored in memory. For EVEN mode the dc gain is: NCOEFF GAIN + n+1 S 2h n 215 * 1 (11) while for ARBITRARY mode the gain is: NCOEFF GAIN + n+1 S hn 215 * 1 (12) 15 PRODUCT PREVIEW For ODD mode and for HALFBAND mode, the dc gain is given by: AFE8201 www.ti.com SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005 SECOND FIR FILTER The second FIR filter, shown in Figure 18, is similar to the first FIR filter with three notable exceptions. First, the depth of the coefficient and data memories are doubled to 128. This allows for filters up to 126 taps to be realized without running out of data memory. It also allows longer sets of filter coefficients to be stored in coefficient memory. Note that BASE_ADDR and NCOEFF are each one bit wider in the control register. 0 1 0 0 0 15 14 BASE_ADDR_A 13 12 11 10 9 8 7 6 NCOEFF_A 5 NCOEFF_B 10 9 8 M2X 7 6 5 4 3 2 4 3 2 MODE_A 1 0 Register Address 0 1 0 0 1 BASE_ADDR_B 15 14 13 12 Don’t Care 15 14 13 12 11 10 9 11 MODE_B 1 0 Register Address 0 1 0 1 0 SHIFT_B 7 6 5 4 3 SHIFT_A 2 1 0 Register Address 8 PRODUCT PREVIEW Figure 18. Second FIR Filter Control Register Second, because of the additional decimation by two from the first FIR filter, twice as many MCLK cycles are available to process coefficients, increasing the maximum allowable value of NCOEFF to: NCOEFF v 4 DEC_RATE * 4 (13) Finally, a second coefficient memory and computational unit is added to allow the simultaneous implementation of two filters with differing responses acting on the same input data stream. Coefficients for filter A are stored in memory bank 1 (MEM = 1) and coefficients for filter B are stored in memory bank 2 (MEM = 2). Note that while the coefficient values for filter A and filter B can be different, the two filters share the same values for MODE, NCOEFF, and BASE_ADDR. EXTENDED-LENGTH FILTER MODE If FIR2A or FIR2B cannot provide enough filter taps to achieve the desired frequency response, setting control bit M2X will put the two filters into an interleaved mode, which will double the length of filter which can be realized. The limitations are: 1. only odd symmetrical filters may be realized; 2. the filter length M must be such that (M + 1)/4 is an integer; and 3. only one filter can be realized (in M2X mode the A and B outputs are identical: IB = IA and QB = QA). In addition to setting the M2X bit, FIR2A must be set to EVEN mode and FIR2B must be set to ODD mode. NCOEFF_A and NCOEFF_B are both set to (M+1)/4. SHIFT_A and SHIFT_B should be identical. There are no restrictions on BASE_ADDR_A or BASE_ADDR_B. The M-tap filter will have (M+1)/2 unique coefficients. The first, third, fifth, etc. coefficients are loaded into the FIR2A coefficient memory; the second, fourth, sixth, etc. are loaded into the FIR2B memory. The center coefficient of the filter will end up as the last coefficient loaded into FIR2B. 16 AFE8201 www.ti.com SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005 AUXILIARY DAC In normal operation the auxiliary DAC values are sent over the data interface through input pin DIN and framed by DFSI. The auxiliary DAC control register, shown in Figure 19, allows the DAC value to be set through the control interface as an alternative. A new DAC value through either interface will cause the DAC output to change, regardless of which interface set the previous DAC value. Please note, however, that unpredictable results will occur if both interfaces write to the DAC at the same time. 0 1 0 1 1 15 Don’t Care 14 13 12 11 10 9 8 7 DAC_DATA 6 5 4 3 2 1 0 Register Address Figure 19. Auxiliary DAC Control Register PGA AND POWER-DOWN Table 4. PGA Gain Setting 3-Bit Code PGA Gain Range 1.00 1.14 1.33 1.60 2.00 2.67 4.00 (B4, B3, and B2) 000 100 010 110 001 101 011 Bit 0 PWD = 0 for normal operation. PWD = 1 for power-down. 0 1 1 0 0 15 14 13 12 11 Don’t Care 10 9 8 7 6 5 4 GAIN 3 2 Don’t Care 1 PWD 0 Register Address Figure 20. PGA and PWD Register 17 PRODUCT PREVIEW The gain of PGA and the power-down mode can be set in register 12. The gain setting of the PGA is shown in Table 4. PACKAGE OPTION ADDENDUM www.ti.com 31-Jan-2005 PACKAGING INFORMATION Orderable Device AFE8201PFBR AFE8201PFBT (1) Status (1) PREVIEW PREVIEW Package Type TQFP TQFP Package Drawing PFB PFB Pins Package Eco Plan (2) Qty 48 48 2000 250 None None Lead/Ball Finish Call TI Call TI MSL Peak Temp (3) Call TI Call TI The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,50 36 25 0,27 0,17 0,08 M 37 24 48 13 0,13 NOM 1 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 0,05 MIN 1,05 0,95 Seating Plane 0,75 0,45 Gage Plane 0,25 0°– 7° 12 1,20 MAX 0,08 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. 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