AMC1300B-Q1
SBASA40B – APRIL 2020 – REVISED JUNE 2022
AMC1300B-Q1 Automotive, Precision, ±250-mV Input, Reinforced Isolated Amplifier
1 Features
3 Description
•
The AMC1300B-Q1 is a precision, isolated amplifier
with an output separated from the input circuitry
by an isolation barrier that is highly resistant to
magnetic interference. This barrier is certified to
provide reinforced galvanic isolation of up to 5 kVRMS
according to DIN EN IEC 60747-17 (VDE 0884-17)
and UL1577, and supports a working voltage of up to
1.5 kVRMS.
•
•
•
•
•
•
•
•
•
AEC-Q100 qualified for automotive applications:
– Temperature grade 1: –40°C to 125°C, TA
Functional Safety-Capable
– Documentation available to aid functional safety
system design
±250-mV input voltage range optimized for current
measurements using shunt resistors
Fixed gain: 8.2 V/V
Low DC errors:
– Offset error: ±0.2 mV (max)
– Offset drift: ±0.9 μV/°C (max)
– Gain error: ±0.3% (max)
– Gain drift: ±30 ppm/°C (max)
– Nonlinearity: 0.03% (max)
3.3-V or 5-V operation on high-side and low-side
Fail-safe output
High CMTI: 100 kV/µs (min)
Low EMI, meets CISPR-11 and CISPR-25
standards
Safety-related certifications:
– 7071-VPK reinforced isolation per DIN EN IEC
60747-17 (VDE 0884-17)
– 5000-VRMS isolation for 1 minute per UL1577
2 Applications
•
The input of the AMC1300B-Q1 is optimized for direct
connection to a low-impedance shunt resistor or other
low-impedance voltage source with low signal levels.
The excellent DC accuracy and low temperature drift
supports accurate current control in PFC stages,
DC/DC converters, traction inverters, and OBCs over
the full automotive temperature range from –40°C to
+125°C.
The integrated missing-shunt and missing high-side
supply detection features simplify system-level design
and diagnostics.
Device Information(1)
Shunt-resistor-based current sensing in:
– HEV/EV charging piles
– HEV/EV onboard chargers (OBC)
– HEV/EV DC/DC converters
– HEV/EV traction inverters
PART NUMBER
AMC1300B-Q1
(1)
High-side supply
(3.3 V or 5 V)
VDD1
The isolation barrier separates parts of the system
that operate on different common-mode voltage levels
and protects the low-voltage side from hazardous
voltages and damage.
PACKAGE
SOIC (8)
BODY SIZE (NOM)
5.85 mm × 7.50 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Low-side supply
(3.3 V or 5 V)
AMC1300B-Q1
VDD2
RSHUNT
INP
+250 mV
0V
± 250 mV
INN
GND1
Reinforced Isolation
I
OUTP
VCMout
±2.05 V
ADC
OUTN
GND2
Typical Application
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AMC1300B-Q1
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SBASA40B – APRIL 2020 – REVISED JUNE 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Power Ratings.............................................................5
6.6 Insulation Specifications ............................................ 6
6.7 Safety-Related Certifications ..................................... 7
6.8 Safety Limiting Values.................................................7
6.9 Electrical Characteristics.............................................8
6.10 Switching Characteristics..........................................9
6.11 Timing Diagram......................................................... 9
6.12 Insulation Characteristics Curves........................... 10
6.13 Typical Characteristics............................................ 11
7 Detailed Description......................................................18
7.1 Overview................................................................... 18
7.2 Functional Block Diagram......................................... 18
7.3 Feature Description...................................................18
7.4 Device Functional Modes..........................................20
8 Application and Implementation.................................. 21
8.1 Application Information............................................. 21
8.2 Typical Application.................................................... 21
8.3 What to Do and What Not to Do............................... 24
9 Power Supply Recommendations................................24
10 Layout...........................................................................25
10.1 Layout Guidelines................................................... 25
10.2 Layout Example...................................................... 25
11 Device and Documentation Support..........................26
11.1 Documentation Support.......................................... 26
11.2 Receiving Notification of Documentation Updates.. 26
11.3 Support Resources................................................. 26
11.4 Trademarks............................................................. 26
11.5 Electrostatic Discharge Caution.............................. 26
11.6 Glossary.................................................................. 26
12 Mechanical, Packaging, and Orderable
Information.................................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (January 2021) to Revision B (June 2022)
Page
• Changed isolation standard from DIN VDE V 0884-11 (VDE V 0884-11) to DIN EN IEC 60747-17 (VDE
0884-17) and updated the Insulation Specifications and Safety-Related Certifications tables accordingly....... 1
• Added Functional Safety-Capable bullets to Features list.................................................................................. 1
• Changed external clearance (CLR) from ≥9 mm to ≥8.5 mm............................................................................. 6
• Changed CIO from ~1 pF to ~1.5 pF................................................................................................................... 6
Changes from Revision * (April 2020) to Revision A (January 2021)
Page
• Changed external clearance (CLR) from ≥8.5 mm to ≥9 mm............................................................................. 6
• Changed TCVOS from ±3 µV/°C to ±0.9 µV/°C................................................................................................... 8
• Changed TCEG from ±50 ppm/°C to ±30 ppm/°C...............................................................................................8
• Changed VDD1UV from 1.75 V (min) / 2.53 V (typ) / 2.7 V (max) to 2.4 V (min) / 2.6 V (typ) / 2.8 V (max)....... 8
2
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5 Pin Configuration and Functions
VDD1
1
8
VDD2
INP
2
7
OUTP
INN
3
6
OUTN
GND1
4
5
GND2
Not to scale
Figure 5-1. DWV Package, 8-Pin SOIC (Top View)
Table 5-1. Pin Functions
PIN
NO.
NAME
TYPE
DESCRIPTION
High-side power supply.(1)
1
VDD1
High-side power
2
INP
Analog input
Noninverting analog input. Either INP or INN must have a DC current path to GND1
to define the common-mode input voltage.(2)
3
INN
Analog input
Inverting analog input. Either INP or INN must have a DC current path to GND1 to
define the common-mode input voltage.(2)
4
GND1
High-side ground
High-side analog ground.
5
GND2
Low-side ground
Low-side analog ground.
6
OUTN
Analog output
Inverting analog output.
7
OUTP
Analog output
Noninverting analog output.
8
VDD2
Low-side power
(1)
(2)
Low-side power supply.(1)
See the Power Supply Recommendations section for power-supply decoupling recommendations.
See the Layout section for details.
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6 Specifications
6.1 Absolute Maximum Ratings
see(1)
Power-supply voltage
MIN
MAX
High-side VDD1 to GND1
–0.3
6.5
Low-side VDD2 to GND2
–0.3
6.5
GND1 – 6
VDD1 + 0.5
V
GND2 – 0.5
VDD2 + 0.5
V
Analog input voltage
INP, INN
Output voltage
OUTP, OUTN
Input current
Continuous, any pin except power-supply pins
Temperature
(1)
–10
10
Junction, TJ
150
Storage, Tstg
–65
150
UNIT
V
mA
°C
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002(1),
HBM ESD classification Level 2
±2000
Charged-device model (CDM), per AEC Q100-011,
CDM ESD classification Level C6
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
High-side power supply
VDD1 to GND1
3
5
5.5
V
Low-side power supply
VDD2 to GND2
3
3.3
5.5
V
ANALOG INPUT
VClipping
Differential input voltage before clipping output
VIN = VINP – VINN
±320
mV
VFSR
Specified linear differential full-scale voltage
VIN = VINP – VINN
–250
250
VCM
Operating common-mode input voltage
(VINP + VINN) / 2 to GND1
–0.16
VDD1 – 2.1
V
–40
125
°C
mV
TEMPERATURE RANGE
TA
4
Specified ambient temperature
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6.4 Thermal Information
AMC1300B-Q1
THERMAL
METRIC(1)
DWV (SOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
85.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
26.8
°C/W
RθJB
Junction-to-board thermal resistance
43.5
°C/W
ψJT
Junction-to-top characterization parameter
4.8
°C/W
ψJB
Junction-to-board characterization parameter
41.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
PD
Maximum power dissipation (both sides)
PD1
Maximum power dissipation (high-side)
PD2
Maximum power dissipation (low-side)
VALUE
UNIT
VDD1 = VDD2 = 5.5 V
TEST CONDITIONS
99
mW
VDD1 = 3.6 V
31
VDD1 = 5.5 V
54
VDD2 = 3.6 V
26
VDD2 = 5.5 V
45
mW
mW
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6.6 Insulation Specifications
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
CLR
External clearance(1)
Shortest pin-to-pin distance through air
≥ 8.5
mm
CPG
External creepage(1)
Shortest pin-to-pin distance across the package surface
≥ 8.5
mm
DTI
Distance through insulation
Minimum internal gap (internal clearance) of the double
insulation
≥ 0.021
mm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
≥ 600
V
Material group
According to IEC 60664-1
Overvoltage category
per IEC 60664-1
Rated mains voltage ≤ 600 VRMS
I-IV
Rated mains voltage ≤ 1000 VRMS
I-III
DIN EN IEC 60747-17 (VDE
I
0884-17)(2)
VIORM
Maximum repetitive peak
isolation voltage
VIOWM
At AC voltage
2120
VPK
Maximum-rated isolation
working voltage
At AC voltage (sine wave)
1500
VRMS
At DC voltage
2120
VDC
VIOTM
Maximum transient
isolation voltage
VTEST = VIOTM, t = 60 s (qualification test)
7000
VTEST = 1.2 × VIOTM, t = 1 s (100% production test)
8400
VIMP
Maximum impulse voltage(3)
Tested in air, 1.2/50-µs waveform per IEC 62368-1
9800
VPK
VIOSM
Maximum surge
isolation voltage(4)
Tested in oil (qualification test),
1.2/50-µs waveform per IEC 62368-1
12800
VPK
Apparent charge(5)
qpd
CIO
Barrier capacitance,
input to output(6)
RIO
Insulation resistance,
input to output(6)
Method a, after input/output safety test subgroups 2 and 3,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 × VIORM, tm = 10 s
≤5
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.6 × VIORM, tm = 10 s
≤5
Method b1, at routine test (100% production) and
preconditioning (type test), Vini = VIOTM, tini = 1 s, Vpd(m) = 1.875
× VIORM, tm = 1 s
≤5
VIO = 0.5 VPP at 1 MHz
~1.5
VIO = 500 V at TA = 25°C
> 1012
VIO = 500 V at 100°C ≤ TA ≤ 125°C
> 1011
VIO = 500 V at TS = 150°C
> 109
Pollution degree
2
Climatic category
55/125/21
VPK
pC
pF
Ω
UL1577
VISO
(1)
(2)
(3)
(4)
(5)
(6)
6
Withstand isolation voltage
VTEST = VISO = 5000 VRMS, t = 60 s (qualification),
VTEST = 1.2 × VISO = 6000 VRMS, t = 1 s (100% production test)
5000
VRMS
Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the
printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques
such as inserting grooves, ribs, or both on a PCB are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
Testing is carried out in air to determine the surge immunity of the package.
Testing is carried in oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier are tied together, creating a two-pin device.
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6.7 Safety-Related Certifications
VDE
UL
DIN EN IEC 60747-17 (VDE 0884-17),
EN IEC 60747-17,
DIN EN IEC 62368-1 (VDE 0868-1),
EN IEC 62368-1,
IEC 62368-1 Clause : 5.4.3 ; 5.4.4.4 ; 5.4.9
Recognized under 1577 component recognition
Reinforced insulation
Single protection
Certificate number: 40040142
File number: E181974
6.8 Safety Limiting Values
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A
failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to
over-heat the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
IS
Safety input, output, or supply current
RθJA = 85.4°C/W, VDDx = 5.5 V,
TJ = 150°C, TA = 25°C
IS
Safety input, output, or supply current
RθJA = 85.4°C/W, VDDx = 3.6 V,
TJ = 150°C, TA = 25°C
PS
Safety input, output, or total power
RθJA = 85.4°C/W, TJ = 150°C, TA = 25°C
TS
Maximum safety temperature
(1)
MIN
TYP
MAX
UNIT
266
mA
407
mA
1464
mW
150
°C
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These
limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature.
PS = IS × VDDmax, where VDDmax is the maximum supply voltage for high-side and low-side.
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6.9 Electrical Characteristics
minimum and maximum specifications apply from TA = –40°C to +125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, INP
= –250 mV to +250 mV, and INN = GND1; typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 3.3 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
VCMov
Common-mode overvoltage
detection level
(VINP + VINN) / 2 to GND1
VDD1 – 2
Hysteresis of common-mode
overvoltage detection level
Input offset voltage(1)
VOS
TCVOS
Input offset
V
60
Initial, at TA = 25°C, INP = INN = GND1
drift(1) (4)
–0.2
–0.9
fIN = 0 Hz, VCM min ≤ VCM ≤ VCM max
CMRR
Common-mode rejection ratio
RIN
Single-ended input resistance
RIND
Differential input resistance
IIB
Input bias current
INP = INN = GND1; IIB = (IIBP + IIBN) / 2
IIO
Input offset current
IIO = IIBP – IIBN; INP = INN = GND1
CIN
Single-ended input capacitance
CIND
Differential input capacitance
mV
±0.01
0.2
mV
±0.1
0.9
µV/°C
–100
fIN = 10 kHz, VCM min ≤ VCM ≤ VCM max
dB
–98
INN = GND1
–41
19
kΩ
22
kΩ
–30
–24
µA
±5
nA
INN = GND1, fIN = 275 kHz
2
pF
fIN = 275 kHz
1
pF
8.2
V/V
ANALOG OUTPUT
Nominal gain
error(1)
EG
Gain
TCEG
Gain drift(1) (5)
at TA = 25°C
Nonlinearity(1)
THD
SNR
–0.3%
±0.04%
–30
±5
–0.03%
±0.01%
–85
dB
Output noise
INP = INN = GND1, fIN = 0 Hz,
BW = 100 kHz brickwall filter
230
µVRMS
fIN = 1 kHz, BW = 10 kHz
81.5
fIN = 10 kHz, BW = 100 kHz
Power-supply rejection ratio(2)
–96
PSRR vs VDD2, at DC
Common-mode output voltage
VCLIPout
Clipping differential output voltage
VFailsafe
Failsafe differential output voltage
BW
Output bandwidth
ROUT
Output resistance
On OUTP or OUTN
Output short-circuit current
On OUTP or OUTN, sourcing or sinking,
INN = INP = GND1, outputs shorted to
either GND2 or VDD2
Common-mode transient immunity
|GND1 – GND2| = 1 kV
dB
–103
PSRR vs VDD1,
100-mV and 10-kHz ripple
VCMout
85
72
dB
–106
PSRR vs VDD2,
100-mV and 10-kHz ripple
8
0.03%
fIN = 10 kHz
PSRR vs VDD1, at DC
CMTI
30 ppm/°C
Total harmonic distortion(3)
Signal-to-noise ratio
PSRR
0.3%
–86
1.39
1.44
1.49
V
VOUT = (VOUTP – VOUTN);
|VIN| = |VINP – VINN| > |VClipping|
–2.52
±2.49
2.52
V
VCM ≥ VCMov, or VDD1 missing
–2.63
–2.57
–2.53
250
310
kHz
< 0.2
Ω
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100
V
14
mA
150
kV/µs
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6.9 Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, INP
= –250 mV to +250 mV, and INN = GND1; typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 3.3 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2.4
2.6
2.8
3.0 V ≤ VDD1 ≤ 3.6 V
6.3
8.5
4.5 V ≤ VDD1 ≤ 5.5 V
7.2
9.8
3.0 V ≤ VDD2 ≤ 3.6 V
5.3
7.2
4.5 V ≤ VDD2 ≤ 5.5 V
5.9
8.1
UNIT
POWER SUPPLY
VDD1UV
VDD1 undervoltage detection
threshold voltage
IDD1
High-side supply current
IDD2
Low-side supply current
(1)
(2)
(3)
(4)
(5)
VDD1 falling
V
mA
mA
The typical value includes one standard deviation (sigma) at nominal operating conditions.
This parameter is input referred.
THD is the ratio of the rms sum of the amplitues of first five higher harmonics to the amplitude of the fundamental.
Offset error temperature drift is calculated using the box method, as described by the following equation:
TCVOS = (VOS,MAX - VOS,MIN) / TempRange where VOS,MAX and VOS,MIN refer to the maximum and minimum VOS values measured
within the temperature range (–40 to 125℃).
Gain error temperature drift is calculated using the box method, as described by the following equation:
TCEG (ppm) = ((EG,MAX - EG,MIN) / TempRange) x 104 where EG,MAX and EG,MIN refer to the maximum and minimum EG values (in %)
measured within the temperature range (–40 to 125℃).
6.10 Switching Characteristics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
tr
Output signal rise time
tf
Output signal fall time
tAS
TEST CONDITIONS
MIN
TYP
MAX
1.3
UNIT
µs
1.3
µs
VINx to VOUTx signal delay (50% - 10%)
Unfiltered output
1
1.5
µs
VINx to VOUTx signal delay (50% - 50%)
Unfiltered output
1.6
2.1
µs
VINx to VOUTx signal delay (50% - 90%)
Unfiltered output
2.5
3
µs
Analog settling time
VDD1 step to 3.0 V with VDD2 ≥ 3.0 V, to
VOUTP, VOUTN valid, 0.1% settling
500
µs
6.11 Timing Diagram
250 mV
INP - INN
0
± 250 mV
tf
tr
OUTN
VCMout
OUTP
50% - 10%
50% - 50%
50% - 90%
Figure 6-1. Rise, Fall, and Delay Time Definition
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6.12 Insulation Characteristics Curves
500
1600
VDD1 = VDD2 = 3.6 V
VDD1 = VDD2 = 5.5 V
1400
1200
300
PS (mW)
IS (mA)
400
200
1000
800
600
400
100
200
0
0
0
25
50
75
TA (°C)
100
125
0
150
25
50
D069
75
TA (°C)
100
125
150
D070
Figure 6-3. Thermal Derating Curve for SafetyLimiting Power per VDE
Figure 6-2. Thermal Derating Curve for SafetyLimiting Current per VDE
1.E+11
87.5 %
1.E+10
254 Yrs
135 Yrs
1.E+09
Time to Fail (sec)
1.E+08
TDDB Line (< 1 ppm Fail Rate)
1.E+07
VDE Safety Margin Zone
1.E+06
Operating Zone
1.E+05
1.E+04
1.E+03
20 %
1.E+02
1.E+01
500
1500
2500
3500
4500
5500
6500
7500
Applied Voltage (VRMS)
TA up to 150°C, stress-voltage frequency = 60 Hz, isolation working voltage = 1500 VRMS, operating lifetime = 135 year
Figure 6-4. Reinforced Isolation Capacitor Lifetime Projection
10
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6.13 Typical Characteristics
at VDD1 = 5 V, VDD2 = 3.3 V, INP = –250 mV to 250 mV, INN = 0 V, and fIN = 10 kHz (unless otherwise noted)
3.8
3.3
3.4
3.25
3.2
VCMov (V)
VCMov (V)
3
2.6
2.2
1.8
3.15
3.1
3.05
3
1.4
2.95
2.9
-40
1
3
3.5
4
4.5
VDD1 (V)
5
5.5
-25
-10
5
20 35 50 65
Temperature (qC)
D001
Figure 6-5. Common-Mode Overvoltage Detection Level vs
High-Side Supply Voltage
80
95
110 125
D002
Figure 6-6. Common-Mode Overvoltage Detection Level vs
Temperature
50
200
VDD1
VDD2
150
40
30
VOS (PV)
Devices (%)
100
20
50
0
-50
-100
10
-150
-200
200
175
150
125
75
100
50
0
25
-25
-50
-75
-100
-125
-150
-175
-200
0
3
3.5
4
D023
VOS (PV)
4.5
VDDx (V)
5
5.5
D027
Figure 6-8. Input Offset Voltage vs Supply Voltage
Figure 6-7. Input Offset Voltage Histogram
50
200
Device 1
Device 2
Device 3
150
40
50
Devices (%)
VOS (PV)
100
0
-50
-100
30
20
10
-150
D026
Figure 6-9. Input Offset Voltage vs Temperature
TCVOS (PV/qC)
1
0.8
0.6
0.4
110 125
0.2
95
0
80
-0.2
20 35 50 65
Temperature (°C)
-0.4
5
-0.6
-10
-0.8
0
-25
-1
-200
-40
D024
Figure 6-10. Input Offset Drift Histogram
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, INP = –250 mV to 250 mV, INN = 0 V, and fIN = 10 kHz (unless otherwise noted)
-70
0
-75
-20
-80
CMRR (dB)
CMRR (dB)
-40
-60
-80
-85
-90
-95
-100
-100
-105
-120
0.001
0.01
0.1
1
fIN (kHz)
10
100
-110
-40
1000
-25
-10
5
D038
Figure 6-11. Common-Mode Rejection Ratio vs Input Frequency
20 35 50 65
Temperature (°C)
80
95
110 125
D039
Figure 6-12. Common-Mode Rejection Ratio vs Temperature
25
-23
-25
15
-27
-29
-5
IIB (PA)
IIB (PA)
5
-15
-31
-33
-35
-25
-37
-35
-39
-45
-0.5
-41
0
0.5
1
1.5
VCM (V)
2
2.5
3
3
3.5
4
D003
Figure 6-13. Input Bias Current vs Common-Mode Input Voltage
4.5
VDD1 (V)
5
5.5
D004
Figure 6-14. Input Bias Current vs High-Side Supply Voltage
-23
50
-25
40
-27
Devices (%)
IIB (PA)
-29
-31
-33
30
20
-35
10
-37
-39
D005
Figure 6-15. Input Bias Current vs Temperature
12
0.3
0.2
EG (%)
0.25
0.15
0
0.1
110 125
0.05
95
-0.05
80
-0.1
20 35 50 65
Temperature (°C)
-0.15
5
-0.2
-10
-0.25
0
-25
-0.3
-41
-40
D018
Figure 6-16. Gain Error Histogram
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6.13 Typical Characteristics (continued)
0.3
0.3
0.2
0.2
0.1
0.1
EG (%)
EG (%)
at VDD1 = 5 V, VDD2 = 3.3 V, INP = –250 mV to 250 mV, INN = 0 V, and fIN = 10 kHz (unless otherwise noted)
0
-0.1
Device 1
Device 2
Device 3
0
-0.1
-0.2
-0.2
VDD1
VDD1
-0.3
3
3.5
4
4.5
VDDx (V)
5
-0.3
-40
5.5
-25
-10
D020
Figure 6-17. Gain Error vs Supply Voltage
5
20 35 50 65
Temperature (°C)
80
95
110 125
D021
Figure 6-18. Gain Error vs Temperature
5
50
0
-5
Normalized Gain (dB)
Devices (%)
40
30
20
10
-10
-15
-20
-25
-30
-35
-40
30
25
20
15
5
10
0
-5
-10
-15
-20
-25
-30
0
1
10
100
1000
fIN (kHz)
D019
TCEG (ppm/qC)
Figure 6-19. Gain Error Drift Histogram
D007
Figure 6-20. Normalized Gain vs Input Frequency
0°
5
-45°
4.5
OUTN
OUTP
4
-90°
-135°
VOUT (V)
Output Phase
3.5
-180°
-225°
3
2.5
2
1.5
-270°
1
-315°
0.5
-360°
1
10
100
1000
fIN (kHz)
0
-350
-250
D008
Figure 6-21. Output Phase vs Input Frequency
-150
-50
50
150
Differential Input Voltage (mV)
250
350
D006
Figure 6-22. Output Voltage vs Input Voltage
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, INP = –250 mV to 250 mV, INN = 0 V, and fIN = 10 kHz (unless otherwise noted)
0.03
0.03
VDD1
VDD2
0.025
0.02
0.02
0.01
Nonlinearity (%)
Nonlinearity (%)
0.015
0.005
0
-0.005
-0.01
0.01
0
-0.01
-0.015
-0.02
-0.02
-0.025
-0.03
-250 -200 -150 -100 -50
0
50 100 150
Differential Input Voltage (mV)
200
-0.03
250
3
Figure 6-23. Nonlinearity vs Input Voltage
4
4.5
VDDx (V)
5
5.5
D029
Figure 6-24. Nonlinearity vs Supply Voltage
0.03
-70
Device 1
Device 2
Device 3
0.02
VDD1
VDD2
-75
0.01
-80
THD (dB)
Nonlinearity (%)
3.5
D028
0
-85
-0.01
-90
-0.02
-95
-0.03
-40
-100
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
3
3.5
4
D030
Figure 6-25. Nonlinearity vs Temperature
4.5
VDDx (V)
5
5.5
D056
Figure 6-26. Total Harmonic Distortion vs Supply Voltage
-70
10000
Noise Density (PV/—Hz)
-75
THD (dB)
-80
-85
-90
Device 1
Device 2
Device 3
-95
-100
-40
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
100
10
0.1
D059
Figure 6-27. Total Harmonic Distortion vs Temperature
14
1000
1
10
Frequency (kHz)
100
1000
D017
Figure 6-28. Input-Referred Noise Density vs Frequency
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6.13 Typical Characteristics (continued)
80
80
75
77.5
70
75
65
72.5
SNR (dB)
SNR (dB)
at VDD1 = 5 V, VDD2 = 3.3 V, INP = –250 mV to 250 mV, INN = 0 V, and fIN = 10 kHz (unless otherwise noted)
60
VDD1
VDD2
70
55
67.5
50
65
45
62.5
60
40
0
50
100
150
200
|VINP - VINN| (mV)
250
3
300
3.5
4
4.5
VDDx (V)
5
5.5
D034
D032
Figure 6-30. Signal-to-Noise Ratio vs Supply Voltage
Figure 6-29. Signal-to-Noise Ratio vs Input Voltage
80
0
77.5
-20
-40
72.5
PSRR (dB)
SNR (dB)
75
70
67.5
-60
-80
65
Device 1
Device 2
Device 3
62.5
60
-55 -40 -25 -10
5
20 35 50 65
Temperature (°C)
80
-100
-120
0.001
95 110 125
0.01
0.1
1
10
Ripple Frequency (kHz)
D035
Figure 6-31. Signal-to-Noise Ratio vs Temperature
100
1000
D041
Figure 6-32. Power-Supply Rejection Ratio vs Ripple Frequency
1.49
1.49
1.48
1.48
1.47
1.47
1.46
1.46
1.45
1.45
VCMout (V)
VCMout (V)
VDD2
VDD1
1.44
1.43
1.44
1.43
1.42
1.42
1.41
1.41
1.4
1.4
1.39
3
3.5
4
4.5
VDD2 (V)
5
5.5
1.39
-40
-25
D009
Figure 6-33. Output Common-Mode Voltage vs Low-Side Supply
Voltage
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
D010
Figure 6-34. Output Common-Mode Voltage vs Temperature
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6.13 Typical Characteristics (continued)
360
360
340
340
320
320
BW (kHz)
BW (kHz)
at VDD1 = 5 V, VDD2 = 3.3 V, INP = –250 mV to 250 mV, INN = 0 V, and fIN = 10 kHz (unless otherwise noted)
300
300
280
280
260
260
240
-40
240
3
3.5
4
4.5
VDD2 (V)
5
5.5
8
8
7.5
7.5
7
7
6.5
6.5
IDDx (mA)
IDDx (mA)
5
20 35 50 65
Temperature (°C)
80
95
110 125
D012
8.5
8.5
6
5.5
6
5.5
5
5
4.5
4.5
IDD1 vs VDD1
IDD2 vs VDD2
4
3
3.5
4
4.5
VDDx (V)
5
3.5
-40
5.5
3.5
3.5
3
3
2.5
2.5
tr/tf (Ps)
4
2
1.5
1
1
0.5
0.5
0
4.5
VDD2 (V)
5
5
20 35 50 65
Temperature (°C)
80
95
110 125
D044
2
1.5
4
-10
Figure 6-38. Supply Current vs Temperature
4
3.5
-25
D043
Figure 6-37. Supply Current vs Supply Voltage
3
IDD1
IDD2
4
3.5
tr / tf (Ps)
-10
Figure 6-36. Output Bandwidth vs Temperature
Figure 6-35. Output Bandwidth vs Low-Side Supply Voltage
5.5
0
-40
-25
D065
Figure 6-39. Output Rise and Fall Time vs Low-Side Supply
16
-25
D011
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
D066
Figure 6-40. Output Rise and Fall Time vs Temperature
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, INP = –250 mV to 250 mV, INN = 0 V, and fIN = 10 kHz (unless otherwise noted)
3.8
3.8
50% - 90%
50% - 50%
50% - 10%
3.4
3
Signal Delay (Ps)
Signal Delay (Ps)
3
50% - 90%
50% - 50%
50% - 10%
3.4
2.6
2.2
1.8
1.4
1
2.6
2.2
1.8
1.4
1
0.6
0.6
0.2
0.2
-40
3
3.5
4
4.5
VDD2 (V)
5
5.5
-25
D067
Figure 6-41. VIN to VOUT Signal Delay vs Low-Side Supply
Voltage
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
D068
Figure 6-42. VIN to VOUT Signal Delay vs Temperature
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7 Detailed Description
7.1 Overview
The AMC1300B-Q1 is a fully differential, precision, isolated amplifier. The input stage of the device consists
of a fully differential amplifier that drives a second-order, delta-sigma (ΔΣ) modulator. The modulator converts
the analog input signal into a digital bitstream that is transferred across the isolation barrier that separates the
high-side from the low-side. On the low-side, the received bitstream is processed by a fourth-order analog filter
that outputs a differential signal at the OUTP and OUTN pins that is proportional to the input signal.
The SiO2-based, capacitive isolation barrier supports a high level of magnetic field immunity, as described
in the ISO72x Digital Isolator Magnetic-Field Immunity application report. The digital modulation used in the
AMC1300B-Q1 to transmit data across the isolation barrier, and the isolation barrier characteristics itself, result
in high reliability and common-mode transient immunity.
7.2 Functional Block Diagram
AMC1300B-Q1
VDD2
Barrier
VDD1
Diagnostics
Analog Filter
GND1
TX / RX
INN
Isolation
û Modulator
RX / TX
INP
OUTP
OUTN
GND2
7.3 Feature Description
7.3.1 Analog Input
The differential amplifier input stage of the AMC1300B-Q1 feeds a second-order, switched-capacitor, feedforward ΔΣ modulator. The gain of the differential amplifier is set by internal precision resistors with a differential
input impedance of RIND. The modulator converts the analog input signal into a bitstream that is transferred
across the isolation barrier, as described in the Isolation Channel Signal Transmission section.
There are two restrictions on the analog input signals INP and INN. First, if the input voltages VINP or VINN
exceed the range specified in the Absolute Maximum Ratings table, the input currents must be limited to the
absolute maximum value, because the electrostatic discharge (ESD) protection turns on. In addition, the linearity
and parametric performance of the device are ensured only when the analog input voltage remains within
the linear full-scale range (VFSR) and within the common-mode input voltage range (VCM) as specified in the
Recommended Operating Conditions table.
18
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7.3.2 Isolation Channel Signal Transmission
The AMC1300B-Q1 uses an on-off keying (OOK) modulation scheme, as shown in Figure 7-1, to transmit
the modulator output bitstream across the SiO2-based isolation barrier. The transmit driver (TX) shown in the
Functional Block Diagram transmits an internally-generated, high-frequency carrier across the isolation barrier
to represent a digital one and does not send a signal to represent a digital zero. The nominal frequency of the
carrier used inside the AMC1300B-Q1 is 480 MHz.
The receiver (RX) on the other side of the isolation barrier recovers and demodulates the signal and provides
the input to the 4th-order analog filter. The AMC1300B-Q1 transmission channel is optimized to achieve the
highest level of common-mode transient immunity (CMTI) and lowest level of radiated emissions caused by the
high-frequency carrier and RX/TX buffer switching.
Internal Clock
Modulator Bitstream
on High-side
Signal Across Isolation Barrier
Recovered Sigal
on Low-side
Figure 7-1. OOK-Based Modulation Scheme
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7.3.3 Analog Output
The AMC1300B-Q1 offers a differential analog output comprised of the OUTP and OUTN pins. For differential
input voltages (VINP – VINN) in the range from –250 mV to 250 mV, the device provides a linear response with a
nominal gain of 8.2. For example, for a differential input voltage of 250 mV, the differential output voltage (VOUTP
– VOUTN) is 2.05 V. At zero input (INP shorted to INN), both pins output the same common-mode output voltage
VCMout, as specified in the Electrical Characteristics table. For absolute differential input voltages greater than
250 mV but less than 320 mV, the differential output voltage continues to increase in magnitude but with reduced
linearity performance. The outputs saturate at a differential output voltage of VCLIPout, as shown in Figure 7-2, if
the differential input voltage exceeds the VClipping value.
Maximum input range before clipping (VClipping)
Linear input range (VFSR)
VOUTN
VFAILSAFE
VCLIPout
VCMout
VOUTP
± 320 mV
± 250 mV
0
320 mV
250 mV
Differential Input Voltage (VINP ± VINN)
Figure 7-2. Output Behavior of the AMC1300B-Q1
The AMC1300B-Q1 offers a failsafe feature that simplifies diagnostics on system level. Figure 7-2 shows the
failsafe mode, in which the AMC1300B-Q1 outputs a negative differential output voltage that does not occur
under normal operating conditions. The failsafe output is active in two cases:
• When the high-side supply is missing or below the VDD1UV threshold
• When the common-mode input voltage, that is VCM = (VINP + VINN) / 2, exceeds the common-mode
overvoltage detection level VCMov
Use the maximum VFAILSAFE voltage specified in the Electrical Characteristics table as a reference value for
failsafe detection on system level.
7.4 Device Functional Modes
The AMC1300B-Q1 is operational when the power supplies VDD1 and VDD2 are applied, as specified in the
Recommended Operating Conditions table.
20
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The low analog input voltage range, excellent accuracy, and low temperature drift make the AMC1300B-Q1 a
high-performance solution for automotive applications where shunt-based current sensing in the presence of
high common-mode voltage levels is required.
8.2 Typical Application
The AMC1300B-Q1 is ideally suited for shunt-based current sensing applications where accurate current
monitoring is required in the presence of high common-mode voltages.
Figure 8-1 shows the AMC1300B-Q1 in a typical application. The load current flowing through an external
shunt resistor RSHUNT produces a voltage drop that is sensed by the AMC1300B-Q1. The AMC1300B-Q1
digitizes the analog input signal on the high-side, transfers the data across the isolation barrier to the low-side,
reconstructs the analog signal, and presents that signal as a differential voltage on the output pins.
The differential input, differential output, and the high common-mode transient immunity (CMTI) of the
AMC1300B-Q1 ensure reliable and accurate operation even in high-noise environments.
Floating Gate
Driver Supply
+ DC Link
Low-side supply
(3.3 V or 5 V)
1 uF
100 nF
AMC1300B-Q1
VDD1
VDD2
INP
OUTP
INN
OUTN
GND1
GND2
10 Ÿ 10 nF
1 uF
100 nF
10 Ÿ 10 nF
RSHUNT
ADC
Load
10 Ÿ
10 Ÿ
± DC Link
Figure 8-1. Using the AMC1300B-Q1 for Current Sensing in a Typical Application
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8.2.1 Design Requirements
Table 8-1 lists the parameters for this typical application.
Table 8-1. Design Requirements
PARAMETER
VALUE
High-side supply voltage
3.3 V or 5 V
Low-side supply voltage
3.3 V or 5 V
Voltage drop across RSHUNT for a linear response
±250 mV (maximum)
Signal delay (50% VIN to 90% OUTP, OUTN)
3 µs (maximum)
8.2.2 Detailed Design Procedure
In Figure 8-1, the high-side power supply (VDD1) for the AMC1300B-Q1 is derived from the floating power
supply of the upper gate driver.
The floating ground reference (GND1) is derived from the end of the shunt resistor that is connected to the
negative input of the AMC1300B-Q1 (INN). If a four-pin shunt is used, the inputs of the AMC1300B-Q1 are
connected to the inner leads and GND1 is connected to the outer lead on the INN-side of the shunt. To minimize
offset and improve accuracy, route the ground connection as a separate trace that connects directly to the shunt
resistor rather than shorting GND1 to INN directly at the input to the device. See the Layout section for more
details.
8.2.2.1 Shunt Resistor Sizing
Use Ohm's Law to calculate the voltage drop across the shunt resistor (VSHUNT) for the desired measured
current: VSHUNT = I × RSHUNT.
Consider the following two restrictions when selecting the value of the shunt resistor, RSHUNT:
•
•
The voltage drop caused by the nominal current range must not exceed the recommended differential input
voltage range for a linear response: |VSHUNT| ≤ |VFSR|
The voltage drop caused by the maximum allowed overcurrent must not exceed the input voltage that causes
a clipping output: |VSHUNT| ≤ |VClipping|
8.2.2.2 Input Filter Design
TI recommends placing an RC-filter in front of the isolated amplifier to improve signal-to-noise performance of
the signal path. Design the input filter such that:
•
•
•
The cutoff frequency of the filter is at least one order of magnitude lower than the sampling frequency (20
MHz) of the ΔΣ modulator
The input bias current does not generate significant voltage drop across the DC impedance of the input filter
The impedances measured from the analog inputs are equal
For most applications, the structure shown in Figure 8-2 achieves excellent performance.
RSHUNT
AMC1300B-Q1
10 Ÿ
VDD1
VDD2
INP
OUTP
INN
OUTN
GND1
GND2
10 nF
10 Ÿ
Figure 8-2. Differential Input Filter
22
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8.2.2.3 Differential to Single-Ended Output Conversion
Figure 8-3 shows an example of a TLVx313-Q1-based signal conversion and filter circuit for systems using
single-ended-input ADCs to convert the analog output voltage into digital. With R1 = R2 = R3 = R4, the output
voltage equals (VOUTP – VOUTN) + VREF. Tailor the bandwidth of this filter stage to the bandwidth requirement of
the system. For most applications, R1 = R2 = R3 = R4 = 3.3 kΩ and C1 = C2 = 330 pF yields good performance.
C1
AMC1300B-Q1
VDD1
VDD2
INP
OUTP
R2
R1
±
ADC
R3
INN
OUTN
GND1
GND2
To MCU
+
TLV313-Q1
C2
R4
VREF
Figure 8-3. Connecting the AMC1300B-Q1 Output to a Single-Ended Input ADC
For more information on the general procedure to design the filtering and driving stages of SAR ADCs, see
the 18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise and 18-Bit Data
Acquisition Block (DAQ) Optimized for Lowest Power reference guides, available for download at www.ti.com.
8.2.3 Application Curve
One important aspect of power-stage design is the effective detection of an overcurrent condition to protect the
switching devices and passive components from damage. To power off the system quickly in the event of an
overcurrent condition, a low delay caused by the isolated amplifier is required. Figure 8-4 shows the typical
full-scale step response of the AMC1300B-Q1.
VOUTP
VOUTN
VIN
Figure 8-4. Step Response of the AMC1300B-Q1
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8.3 What to Do and What Not to Do
Do not leave the inputs of the AMC1300B-Q1 unconnected (floating) when the device is powered up. If the
device inputs are left floating, the input bias current may drive the inputs to a positive value that exceeds the
operating common-mode input voltage and the device outputs the fail-safe voltage as described in the Analog
Output section.
Connect the high-side ground (GND1) to INN, either by a hard short or through a resistive path. A DC current
path between INN and GND1 is required to define the input common-mode voltage. Take care not to exceed
the input common-mode range as specified in the Recommended Operating Conditions table. For best accuracy,
route the ground connection as a separate trace that connects directly to the shunt resistor rather than shorting
GND1 to INN directly at the input to the device. See the Layout section for more details.
9 Power Supply Recommendations
The AMC1300B-Q1 does not require any specific power up sequencing. The high-side power-supply (VDD1) is
decoupled with a low-ESR 100-nF capacitor (C1) parallel to a low-ESR 1-µF capacitor (C2). The low-side power
supply (VDD2) is equally decoupled with a low-ESR 100-nF capacitor (C3) parallel to a low-ESR 1-µF capacitor
(C4). Place all four capacitors (C1, C2, C3, and C4) as close to the device as possible.
The ground reference for the high-side (GND1) is derived from the end of the shunt resistor, which is connected
to the negative input (INN) of the device. For best DC accuracy, use a separate trace (as shown in Figure 9-1)
to make this connection instead of shorting GND1 to INN directly at the device input. If a four-terminal shunt
is used, the device inputs are connected to the inner leads and GND1 is connected to the outer lead on the
INN-side of the shunt.
INP
VDD1
VDD2
C2 1 µF
C4 1 µF
AMC1300B-Q1
I
RSHUNT
C1 100 nF
C3 100 nF
R2 10 Ÿ
R1 10 Ÿ
C5
10 nF
VDD1
VDD2
INP
OUTP
to RC filter / ADC
INN
OUTN
to RC filter / ADC
GND1
GND2
Figure 9-1. Decoupling of the AMC1300B-Q1
Capacitors must provide adequate effective capacitance under the applicable DC bias conditions they
experience in the application. Multilayer ceramic capacitors (MLCCs) typically exhibit only a fraction of their
nominal capacitance under real-world conditions and this factor must be taken into consideration when selecting
these capacitors. This problem is especially acute in low-profile capacitors, in which the dielectric field strength is
higher than in taller components. Reputable capacitor manufacturers provide capacitance versus DC bias curves
that greatly simplify component selection.
24
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10 Layout
10.1 Layout Guidelines
Figure 10-1 shows a layout recommendation with the critical placement of the decoupling capacitors (as close as
possible to the AMC1300B-Q1 supply pins) and placement of the other components required by the device. For
best performance, place the shunt resistor close to the INP and INN inputs of the AMC1300B-Q1 and keep the
layout of both connections symmetrical.
Clearance area, to be
kept free of any
conductive materials.
C2
C4
INN
R2
R1
C5
RSHUNT
C1
INP
VDD2
VDD1
10.2 Layout Example
C3
AMC1300B-Q1
OUTP
to RC filter / ADC
OUTN
to RC filter / ADC
GND2
GND1
Top Metal
Inner or Bottom Layer Metal
Via
Figure 10-1. Recommended Layout of the AMC1300B-Q1
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
•
•
•
•
•
•
•
Texas Instruments, Isolation Glossary application report
Texas Instruments, Semiconductor and IC Package Thermal Metrics application report
Texas Instruments, ISO72x Digital Isolator Magnetic-Field Immunity application report
Texas Instruments, TLVx313-Q1 Low-Power, Rail-to-Rail In/Out, 750-µV Typical Offset, 1-MHz Operational
Amplifier for Cost-Sensitive Systems data sheet
Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise
reference guide
Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Power reference
guide
Texas Instruments, Isolated Amplifier Voltage Sensing Excel Calculator design tool
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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16-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
AMC1300BQDWVRQ1
ACTIVE
SOIC
DWV
8
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
MC1300BQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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