AMC1302DWVR

AMC1302 ZHCSIF3D – JUNE 2018 – REVISED JUNE 2021 AMC1302 精密、±50mV 输入、增强型隔离放大器 1 特性 3 说明 • ±50mV 输入电压范围，针对基于分流器的电流测量 进行了优化 • 固定增益：41 • 低直流误差： – 失调电压误差：±50µV（最大值） – 温漂：±0.8µV/°C（最大值） – 增益误差：±0.2%（最大值） – 增益漂移：±35ppm/°C（最大值） – 非线性度：0.03%（最大值） • 高侧和低侧以 3.3V 或 5V 电压运行 • 失效防护输出 • 高 CMTI：100kV/µs（最小值） • 低 EMI，符合 CISPR-11 和 CISPR-25 标准 • 安全相关认证： – 7071-VPK 增强型隔离，符合 DIN VDE V 0884-11：2017-01 – 符合 UL1577 标准且长达 1 分钟的 5000VRMS 隔离 • 可在工业级工作温度范围内正常工作：–40°C 至 +125°C AMC1302 是一款隔离式精密放大器，此放大器的输出 与输入电路由抗电磁干扰性能极强的隔离层隔开。该隔 离栅经认证可提供高达 5kVRMS 的增强型电隔离，符合 VDE V 0884-11 和 UL1577 标准，并且可支持最高 1.5kVRMS 的工作电压。 该隔离栅可将系统中以不同共模电压电平运行的各器件 隔开，并保护电压较低的器件免受高电压冲击。 AMC1302 的输入针对直接连接低阻抗分流电阻器或其 他具有低信号电平的低阻抗电压源的情况进行了优化。 出色的直流精度和低温漂支持在 –40°C 至 +125°C 的 工业级工作温度范围内，在 PFC 级、直流/直流转换 器、交流电机和伺服驱动器中进行精确的电流控制。 集成的无分流器和无高侧电源检测功能可简化系统级设 计和诊断。 器件信息(1) 器件型号 AMC1302 (1) 2 应用 封装 SOIC (8) 封装尺寸（标称值） 5.85mm × 7.50mm 如需了解所有可用封装，请参阅数据表末尾的可订购产品附 录。 • 可用于以下应用的隔离式电流感应： – 保护继电器 – 电机驱动器 – 电源 – 光电逆变器 High-side supply (3.3 V or 5 V) VDD1 Low-side supply (3.3 V or 5 V) AMC1302 VDD2 RSHUNT INP +50 mV 0V – mV INN Reinforced Isolation I GND1 OUTP VCMout ±2.05 V ADC OUTN GND2 典型应用 本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。 English Data Sheet: SBAS812 AMC1302 www.ti.com.cn ZHCSIF3D – JUNE 2018 – REVISED JUNE 2021 Table of Contents 1 特性................................................................................... 1 2 应用................................................................................... 1 3 说明................................................................................... 1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings ....................................... 4 6.2 ESD Ratings .............................................................. 4 6.3 Recommended Operating Conditions ........................4 6.4 Thermal Information ...................................................5 6.5 Power Ratings ............................................................5 6.6 Insulation Specification .............................................. 6 6.7 Safety-Related Certifications ..................................... 7 6.8 Safety Limiting Values ................................................7 6.9 Electrical Characteristics ............................................8 6.10 Switching Characteristics .........................................9 6.11 Timing Diagram......................................................... 9 6.12 Insulation Characteristics Curves........................... 10 6.13 Typical Characteristics............................................ 11 7 Detailed Description......................................................17 7.1 Overview................................................................... 17 7.2 Functional Block Diagram......................................... 17 7.3 Feature Description...................................................17 7.4 Device Functional Modes..........................................19 8 Application and Implementation.................................. 20 8.1 Application Information............................................. 20 8.2 Typical Application.................................................... 20 8.3 What to Do and What Not to Do............................... 22 9 Power Supply Recommendations................................23 10 Layout...........................................................................24 10.1 Layout Guidelines................................................... 24 10.2 Layout Example...................................................... 24 11 Device and Documentation Support..........................25 11.1 Documentation Support.......................................... 25 11.2 Trademarks............................................................. 25 11.3 Electrostatic Discharge Caution.............................. 25 11.4 术语表..................................................................... 25 12 Mechanical, Packaging, and Orderable Information.................................................................... 25 4 Revision History 注：以前版本的页码可能与当前版本的页码不同 Changes from Revision C (October 2019) to Revision D (June 2021) • • • • • • • • • Page 更新了整个文档中的表格、图和交叉参考的编号格式 ........................................................................................ 1 Changed CIO from ~1 pF to ~1.5 pF................................................................................................................... 6 Changed VOS from –100 µV / ±10 µV / 100 µV to –50 µV / ±2.5 µV / 50 µV (min / typ / max )....................... 8 Changed EG from –0.3% / ±0.05% / 0.3% to –0.2% / ±0.04% / 0.2% (min / typ / max) ................................ 8 Changed TCEG from –50 ppm/℃ / ±15 ppm/℃ / 50 ppm/℃ to –35 ppm/℃ / ±3 ppm/℃ / 35 ppm/℃ (min / typ / max) ........................................................................................................................................................... 8 Changed VFailsafe from –2.6 V / –2.5 V (typ / max) to –2.63 V / –2.57 V / –2.53 V (min / typ / max).......... 8 Changed CMTI from 55 kV/µs / 80 kV/µs to 100 kV/µs / 150 kV/µs (min / typ) ................................................. 8 Changed VDD1POR from 1.75 V / 2.15 V / 2.7 V to 2.4 V / 2.6 V / 2.8 V (min / typ / max)................................. 8 Changed Rise, Fall, and Delay Time Waveforms image.................................................................................... 9 Changes from Revision B (November 2018) to Revision C (October 2019) Page • 将安全相关认证 特性项目符号中的 VDE 认证从“DIN V VDE V 0884-11 (VDE V 0884-11)”更改为 DIN VDE V 0884-11 ...........................................................................................................................................................1 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC1302 AMC1302 www.ti.com.cn ZHCSIF3D – JUNE 2018 – REVISED JUNE 2021 5 Pin Configuration and Functions VDD1 1 8 VDD2 INP 2 7 OUTP INN 3 6 OUTN GND1 4 5 GND2 Not to scale 图 5-1. DWV Package, 8-Pin SOIC, Top View 表 5-1. Pin Functions PIN NO. NAME TYPE DESCRIPTION High-side power supply.(1) 1 VDD1 High-side power 2 INP Analog input Noninverting analog input. Either INP or INN must have a DC current path to GND1 to define the common-mode input voltage.(2) 3 INN Analog input Inverting analog input. Either INP or INN must have a DC current path to GND1 to define the common-mode input voltage.(2) 4 GND1 High-side ground High-side analog ground. 5 GND2 Low-side ground Low-side analog ground. 6 OUTN Analog output Inverting analog output. 7 OUTP Analog output Noninverting analog output. 8 VDD2 Low-side power (1) (2) Low-side power supply.(1) See the Power Supply Recommendations section for power-supply decoupling recommendations. See the Layout section for details. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC1302 3 AMC1302 www.ti.com.cn ZHCSIF3D – JUNE 2018 – REVISED JUNE 2021 6 Specifications 6.1 Absolute Maximum Ratings over operating ambient temperature range (unless otherwise noted)(1) Power-supply voltage High-side VDD1 to GND1 Low-side VDD2 to GND2 Analog input voltage INP, INN Output voltage OUTP, OUTN Input current Continuous, any pin except power-supply pins Temperature (1) MIN MAX –0.3 6.5 V –0.3 6.5 V GND1 – 6 VDD1 + 0.5 V GND2 – 0.5 VDD2 + 0.5 V 10 –10 Junction, TJ 150 Storage, Tstg UNIT 150 –65 mA °C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged device model (CDM), per JESD22-C101 (2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating ambient temperature range (unless otherwise noted) MIN NOM MAX UNIT POWER SUPPLY High-side power supply VDD1 to GND1 3 5 5.5 V Low-side power supply VDD2 to GND2 3 3.3 5.5 V ANALOG INPUT VClipping Differential input voltage before clipping output VIN = VINP – VINN VFSR Specified linear differential full-scale voltage VIN = VINP – VINN VCM Operating common-mode input voltage (VINP + VINN) / 2 to GND1 ±64 –50 –0.032 mV 50 VDD1 – 2.2 mV V TEMPERATURE RANGE TA 4 Specified ambient temperature –55 Submit Document Feedback 125 °C Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC1302 AMC1302 www.ti.com.cn ZHCSIF3D – JUNE 2018 – REVISED JUNE 2021 6.4 Thermal Information AMC1302 THERMAL METRIC(1) DWV (SOIC) UNIT 8 PINS RθJA Junction-to-ambient thermal resistance 85.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 26.8 °C/W RθJB Junction-to-board thermal resistance 43.5 °C/W ψJT Junction-to-top characterization parameter 4.8 °C/W ψJB Junction-to-board characterization parameter 41.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Power Ratings PARAMETER PD Maximum power dissipation (both sides) PD1 Maximum power dissipation (high-side) PD2 Maximum power dissipation (low-side) TEST CONDITIONS VALUE UNIT VDD1 = VDD2 = 5.5 V 99 mW VDD1 = 3.6 V 31 VDD1 = 5.5 V 54 VDD2 = 3.6 V 26 VDD2 = 5.5 V 45 mW mW Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC1302 5 AMC1302 www.ti.com.cn ZHCSIF3D – JUNE 2018 – REVISED JUNE 2021 6.6 Insulation Specification over operating ambient temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VALUE UNIT GENERAL External clearance(1) Shortest terminal-to-terminal distance through air ≥ 8.5 mm CPG External creepage(1) Shortest terminal-to-terminal distance across the package surface ≥ 8.5 mm DTI Distance through the insulation Minimum internal gap (internal clearance) of the double isolation (2 x 0.0105 mm) ≥ 0.021 mm CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 ≥ 600 V Material group According to IEC 60664-1 CLR Overvoltage category DIN V VDE 0884-11 (VDE V 0884-11): VIORM Maximum repetitive peak isolation voltage VIOWM I Rated mains voltage ≤ 600 VRMS I -IV Rated mains voltage ≤ 1000 VRMS I-III 2017-01(2) AC voltage 2121 VPK Maximum isolation working voltage AC voltage (sine wave) 1500 VRMS DC voltage 2121 VDC VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60 s (qualification test) 7071 VPK VTEST = VIOTM, t = 1 s (100% production test) 8485 VPK VIOSM Maximum surge isolation voltage(1) Test method per IEC 60065, 1.2/50 µs waveform, VTEST = 1.6 × VIOSM = 12800 VPK (qualification) 8000 VPK Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM = 2545 VPK, tm = 10 s ≤5 Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM = 3394 VPK, tm = 10 s ≤5 Method b1: At routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1 s; Vpd(m) = 1.875 × VIORM = 3977 VPK, tm = 1 s ≤5 VIO = 0.4 × sin (2 πft), f = 1 MHz ~1.5 Apparent charge(3) qpd CIO Barrier capacitance, input to output(4) RIO Insulation resistance, input to output(4) VIO = 500 V, TA = 25°C > 1012 VIO = 500 V, 100°C ≤ TA ≤ 125°C > 1011 VIO = 500 V at TS = 150°C > 109 Pollution degree 2 Climatic category 55/125/21 pC pF Ω UL 1577 VISO (1) (2) (3) (4) 6 Withstand isolation voltage VTEST = VISO = 5000 VRMS, t = 60 s (qualification), VTEST = 1.2 × VISO = 6000 VRMS, t = 1 s (100% production) 5000 VRMS Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care must be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed-circuit board are used to help increase these specifications. This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits. Apparent charge is electrical discharge caused by a partial discharge (pd). All pins on each side of the barrier tied together creating a two-pin device. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC1302 AMC1302 www.ti.com.cn ZHCSIF3D – JUNE 2018 – REVISED JUNE 2021 6.7 Safety-Related Certifications VDE UL Certified according to DIN VDE V 0884-11 (VDE V 0884-11): 2017-01, DIN EN 60950-1 (VDE 0805 Teil 1): 2014-08, and DIN EN 60065 (VDE 0860): 2005-11 Recognized under 1577 component recognition and CSA component acceptance NO 5 programs Reinforced insulation Single protection Certificate number: 40040142 Certificate number: E181974 6.8 Safety Limiting Values Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IS Safety input, output, or supply current RθJA = 85.4°C/W, VDDx = 5.5 V, TJ = 150°C, TA = 25°C 266 mA IS Safety input, output, or supply current RθJA = 85.4°C/W, VDDx = 3.6 V, TJ = 150°C, TA = 25°C 407 mA PS Safety input, output, or total power RθJA = 85.4°C/W, TJ = 150°C, TA = 25°C 1464 mW TS Maximum safety temperature 150 °C (1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These limits vary with the ambient temperature, TA. The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. Use these equations to calculate the value for each parameter: TJ = TA + RθJA × P, where P is the power dissipated in the device. TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature. PS = IS × VDDmax, where VDDmax is the maximum supply voltage for high-side and low-side. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC1302 7 AMC1302 www.ti.com.cn ZHCSIF3D – JUNE 2018 – REVISED JUNE 2021 6.9 Electrical Characteristics minimum and maximum specifications apply from TA = – 55°C to +125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, INP = – 50 mV to + 50 mV, and INN = GND1; typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 3.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT VCMov Common-mode overvoltage detection level (VINP + VINN) / 2 to GND1 V VDD1 – 2 Hysteresis of common-mode overvoltage detection level 60 VOS Input offset voltage(1) (2) TCVOS Input offset drift(1) (2) (3) CMRR Common-mode rejection ratio CIN Single-ended input capacitance INN = GND1, fIN = 300 kHz 4 CIND Differential input capacitance fIN = 300 kHz 2 RIN Single-ended input resistance INN = GND1 4.75 RIND Differential input resistance IIB Input bias current TCIIB Input bias current drift IIO Input offset current TA = 25°C, VINP = VINN = GND1 mV –50 ±2.5 50 µV –0.8 ±0.15 0.8 µV/°C fIN = 0 Hz, VCM min ≤ VCM ≤ VVCM max –100 fIN = 10 kHz, VCM min ≤ VCM ≤ VCM max –98 dB pF kΩ 4.9 INP = INN = GND1; IIB = (IIBP + IIBN) / 2 –48.5 IIO = IIBP – IIBN –36 –28.5 uA ±1.5 nA/°C ±10 nA ANALOG OUTPUT Nominal gain EG Gain TCEG 41 error(1) Gain error TA = 25°C drift(1) (4) Nonlinearity(1) –0.2% –35 ±3 –0.03% ±0.01% Nonlinearity drift THD SNR Total harmonic distortion fIN = 10 kHz Output noise INP = INN = GND1, fIN = 0 Hz, BW = 100 kHz brickwall filter Power-supply rejection fIN = 1 kHz, BW = 10 kHz 80 fIN = 10 kHz, BW = 100 kHz 8 35 ppm/°C 0.03% ratio(2) –85 dB 260 µVRMS 84 PSRR vs VDD1, at DC –113 PSRR vs VDD1, 100-mV and 10-kHz ripple –108 PSRR vs VDD2, at DC –116 VCMout Common-mode output voltage VCLIPout Clipping differential output voltage VFailsafe Failsafe differential output voltage BW Output bandwidth ROUT Output resistance On OUTP or OUTN Output short-circuit current On OUTP or OUTN, sourcing or sinking, INN = INP = GND1, outputs shorted to either GND2 or VDD2 Common-mode transient immunity |GND1 – GND2| = 1 kV ppm/°C dB 70 PSRR vs VDD2, 100-mV and 10-kHz ripple CMTI 0.2% 1 Signal-to-noise ratio PSRR ±0.04% dB –87 1.39 1.44 1.49 V VOUT = (VOUTP – VOUTN); |VIN| = |VINP – VINN| > |VClipping| –2.52 ±2.49 2.52 V VCM ≥ VCMov, or VDD1 missing –2.63 –2.57 –2.53 V 220 Submit Document Feedback 100 280 kHz < 0.2 Ω ±14 mA 150 kV/µs Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC1302 AMC1302 www.ti.com.cn ZHCSIF3D – JUNE 2018 – REVISED JUNE 2021 6.9 Electrical Characteristics (continued) minimum and maximum specifications apply from TA = – 55°C to +125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, INP = – 50 mV to + 50 mV, and INN = GND1; typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 3.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 2.4 2.6 2.8 3.0 V ≤ VDD1 ≤ 3.6 V 6.2 8.5 4.5 V ≤ VDD1 ≤ 5.5 V 7.2 9.8 3.0 V ≤ VDD2 ≤ 3.6 V 5.3 7.2 4.5 V ≤ VDD2 ≤ 5.5 V 5.9 8.1 UNIT POWER SUPPLY VDD1POR VDD1 power-on-reset threshold voltage IDD1 High-side supply current IDD2 (1) (2) (3) (4) VDD1 falling Low-side supply current V mA The typical value includes one standard deviation ("sigma") at nominal operating conditions. This parameter is input referred. Offset error temperature drift is calculated using the box method, as described by the following equation: TCVOS = (ValueMAX - ValueMIN) / TempRange Gain error temperature drift is calculated using the box method, as described by the following equation: TCEG (ppm) = (ValueMAX - ValueMIN) / (Value(T=25℃) x TempRange) x 106 6.10 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tr Output signal rise time 1.5 µs tf Output signal fall time 1.5 µs tAS VINx to VOUTx signal delay (50% – 10%) unfiltered output 1 1.5 µs VINx to VOUTx signal delay (50% – 50%) unfiltered output 1.6 2.1 µs VINx to VOUTx signal delay (50% – 90%) unfiltered output 2.5 3 µs Analog settling time VDD1 step to 3.0 V with VDD2 ≥ 3.0 V, to OUTP and OUTN valid, 0.1% settling 500 µs 6.11 Timing Diagram 50 mV INP - INN 0 – 50 mV tf tr OUTN VCMout OUTP 50% - 10% 50% - 50% 50% - 90% 图 6-1. Rise, Fall, and Delay Time Waveforms Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC1302 9 AMC1302 www.ti.com.cn ZHCSIF3D – JUNE 2018 – REVISED JUNE 2021 6.12 Insulation Characteristics Curves 450 1600 VDD1 = VDD2 = 3.6 V VDD1 = VDD2 = 5.5 V 400 1400 350 1200 PS (mW) IS (mA) 300 250 200 1000 800 600 150 400 100 200 50 0 0 0 25 50 75 TA (°C) 100 125 150 0 25 50 75 TA (°C) 100 125 D001 图 6-2. Thermal Derating Curve for Safety-Limiting Current per VDE 150 D002 图 6-3. Thermal Derating Curve for Safety-Limiting Power per VDE TA up to 150°C, stress-voltage frequency = 60 Hz, isolation working voltage = 1500 VRMS, operating lifetime = 135 years 图 6-4. Reinforced Isolation Capacitor Lifetime Projection 10 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC1302 AMC1302 www.ti.com.cn ZHCSIF3D – JUNE 2018 – REVISED JUNE 2021 6.13 Typical Characteristics at TA = 25°C, VDD1 = 5 V, VDD2 = 3.3 V, INP = –50 mV to 50 mV, INN = GND1, and fIN = 10 kHz (unless otherwise noted) 3.8 3.3 3.4 3.25 3.2 VCMov (V) VCMov (V) 3 2.6 2.2 3.1 3.05 1.8 3 1.4 2.95 2.9 -55 -40 -25 -10 1 3 3.25 3.5 3.75 4 4.25 4.5 VDD1 (V) 4.75 5 5.25 5.5 5 20 35 50 65 Temperature (qC) 80 95 110 125 D004 D003 图 6-6. Common-Mode Overvoltage Detection Level vs Temperature 图 6-5. Common-Mode Overvoltage Detection Level vs HighSide Supply Voltage 100 100 vs VDD1 vs VDD2 75 50 50 25 25 0 0 -25 -25 -50 -50 -75 -75 -100 3 3.25 3.5 3.75 4 4.25 4.5 VDDx (V) 4.75 5 5.25 Device 1 Device 2 Device 3 75 VOS (PV) VOS (PV) 3.15 -100 -55 -40 -25 -10 5.5 5 D007 图 6-7. Input Offset Voltage vs Supply Voltage 20 35 50 65 Temperature (°C) 80 95 110 125 D009 图 6-8. Input Offset Voltage vs Temperature -75 0 -80 -20 -85 CMRR (dB) CMRR (dB) -40 -60 -80 -90 -95 -100 -105 -100 -120 0.001 -110 0.01 0.1 1 fIN (kHz) 10 100 1000 -115 -55 -40 -25 -10 D012 图 6-9. Common-Mode Rejection Ratio vs Input Frequency 5 20 35 50 65 Temperature (°C) 80 95 110 125 D013 图 6-10. Common-Mode Rejection Ratio vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC1302 11 AMC1302 www.ti.com.cn ZHCSIF3D – JUNE 2018 – REVISED JUNE 2021 6.13 Typical Characteristics (continued) at TA = 25°C, VDD1 = 5 V, VDD2 = 3.3 V, INP = –50 mV to 50 mV, INN = GND1, and fIN = 10 kHz (unless otherwise noted) 60 -27 -29 40 -31 -33 0 IIB (PA) IIB (PA) 20 -20 -35 -37 -39 -40 -41 -60 -43 -80 -0.5 -45 0 0.5 1 1.5 VCM (V) 2 2.5 3 3.5 3 3.25 3.5 3.75 4 D014 图 6-11. Input Bias Current vs Common-Mode Input Voltage 4.25 4.5 VDD1 (V) 4.75 5 5.25 5.5 D015 图 6-12. Input Bias Current vs High-Side Supply Voltage 0.3 -27 -29 0.2 -31 0.1 EG (%) IIB (PA) -33 -35 -37 -39 0 -0.1 -41 -0.2 vs VDD1 vs VDD2 -43 -45 -55 -40 -25 -10 -0.3 5 20 35 50 65 Temperature (°C) 80 95 110 125 3 3.25 3.5 3.75 4 D016 图 6-13. Input Bias Current vs Temperature 4.25 4.5 VDDx (V) 4.75 5 5.25 5.5 D019 图 6-14. Gain Error vs Supply Voltage 0.3 5 0 Normalized Gain (dB) 0.2 EG (%) 0.1 0 -0.1 -0.3 -55 -40 -25 -10 5 20 35 50 65 Temperature (°C) 80 12 -20 -25 -35 95 110 125 图 6-15. Gain Error vs Temperature -15 -30 Device 1 Device 2 Device 3 -0.2 -5 -10 -40 0.01 0.1 1 10 100 fIN (kHz) D020 1000 D023 图 6-16. Normalized Gain vs Input Frequency Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC1302 AMC1302 www.ti.com.cn ZHCSIF3D – JUNE 2018 – REVISED JUNE 2021 6.13 Typical Characteristics (continued) at TA = 25°C, VDD1 = 5 V, VDD2 = 3.3 V, INP = –50 mV to 50 mV, INN = GND1, and fIN = 10 kHz (unless otherwise noted) 0° 5 -45° 4.5 VOUTN VOUTP 4 -90° -135° VOUT (V) Output Phase 3.5 -180° -225° 3 2.5 2 1.5 -270° 1 -315° 0.5 -360° 0.01 0.1 1 10 100 0 -70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 Differential Input Voltage (mV) D025 1000 fIN (kHz) D024 图 6-18. Output Voltage vs Input Voltage 0.03 0.03 0.02 0.02 0.01 0.01 Nonlinearity (%) Nonlinearity (%) 图 6-17. Output Phase vs Input Frequency 0 -0.01 -0.02 -0.03 -50 vs VDD1 vs VDD2 0 -0.01 -0.02 -0.03 -40 -30 -20 -10 0 10 20 30 Differential Input Voltage (mV) 40 3 50 3.5 3.75 4 4.25 4.5 VDDx (V) 4.75 5 5.25 5.5 D027 图 6-20. Nonlinearity vs Supply Voltage 图 6-19. Nonlinearity vs Input Voltage 0.03 -70 0.02 -75 0.01 -80 THD (dB) Nonlinearity (%) 3.25 D026 0 -0.01 vs VDD1 vs VDD2 -85 -90 Device 1 Device 2 Device 3 -0.02 -0.03 -55 -40 -25 -10 5 20 35 50 65 Temperature (°C) 80 -95 95 110 125 -100 3 3.25 D028 图 6-21. Nonlinearity vs Temperature 3.5 3.75 4 4.25 4.5 VDDx (V) 4.75 5 5.25 5.5 D029 图 6-22. Total Harmonic Distortion vs Supply Voltage Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC1302 13 AMC1302 www.ti.com.cn ZHCSIF3D – JUNE 2018 – REVISED JUNE 2021 6.13 Typical Characteristics (continued) at TA = 25°C, VDD1 = 5 V, VDD2 = 3.3 V, INP = –50 mV to 50 mV, INN = GND1, and fIN = 10 kHz (unless otherwise noted) -70 10 Noise Density (PV/—Hz) -75 THD (dB) -80 -85 -90 1 Device 1 Device 2 Device 3 -95 -100 -55 -40 -25 -10 5 20 35 50 65 Temperature (°C) 80 0.1 0.1 95 110 125 图 6-23. Total Harmonic Distortion vs Temperature 10 Frequency (kHz) 100 1000 D031 图 6-24. Output Noise Density vs Frequency 75 75 70 74 65 73 vs VDD1 vs VDD2 72 SNR (dB) 60 SNR (dB) 1 D030 55 50 45 71 70 69 68 40 67 35 66 30 65 0 5 10 15 20 25 30 35 |VINP - VINN| (mV) 40 45 50 55 3 3.25 3.5 D032 图 6-25. Signal-to-Noise Ratio vs Input Voltage 3.75 4 4.25 4.5 VDDx (V) 4.75 5 5.25 5.5 D033 图 6-26. Signal-to-Noise Ratio vs Supply Voltage 75 20 74 vs VDD2 vs VDD1 0 73 -20 PSRR (dB) SNR (dB) 72 71 70 69 -60 -80 68 67 Device 1 Device 2 Device 3 66 65 -55 -40 -25 -10 5 20 35 50 65 Temperature (°C) 80 -100 95 110 125 -120 0.001 D034 图 6-27. Signal-to-Noise Ratio vs Temperature 14 -40 0.01 0.1 1 10 Ripple Frequency (kHz) 100 1000 D035 图 6-28. Power-Supply Rejection Ratio vs Ripple Frequency Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC1302 AMC1302 www.ti.com.cn ZHCSIF3D – JUNE 2018 – REVISED JUNE 2021 6.13 Typical Characteristics (continued) 1.49 1.49 1.48 1.48 1.47 1.47 1.46 1.46 1.45 1.45 VCMout (V) VCMout (V) at TA = 25°C, VDD1 = 5 V, VDD2 = 3.3 V, INP = –50 mV to 50 mV, INN = GND1, and fIN = 10 kHz (unless otherwise noted) 1.44 1.43 1.43 1.42 1.42 1.41 1.41 1.4 1.4 1.39 -55 -40 -25 -10 1.39 3 3.25 3.5 3.75 4 4.25 4.5 VDD2 (V) 4.75 5 5.25 5.5 310 310 300 300 290 290 BW (kHz) 320 280 270 250 250 240 -55 -40 -25 -10 240 3.75 4 4.25 4.5 VDD2 (V) 4.75 5 5.25 5.5 5 D038 图 6-31. Output Bandwidth vs Low-Side Supply Voltage D037 20 35 50 65 Temperature (°C) 80 95 110 125 D039 图 6-32. Output Bandwidth vs Temperature 8.5 8.5 8 8 7.5 7.5 7 7 6.5 6.5 IDDx (mA) IDDx (mA) 95 110 125 270 260 3.5 80 280 260 3.25 20 35 50 65 Temperature (°C) 图 6-30. Output Common-Mode Voltage vs Temperature 320 3 5 D036 图 6-29. Output Common-Mode Voltage vs Low-Side Supply Voltage BW (kHz) 1.44 6 5.5 6 5.5 5 5 4.5 4.5 IDD1 vs VDD1 IDD2 vs VDD2 4 4 3.5 3 3.25 3.5 3.75 4 4.25 4.5 VDDx (V) 4.75 5 5.25 IDD1 at VDD1 = 5 V IDD1 at VDD1 = 3.3 V IDD2 at VDD2 = 5 V IDD2 at VDD2 = 3.3 V 5.5 3.5 -55 -40 -25 -10 D040 图 6-33. Supply Current vs Supply Voltage 5 20 35 50 65 Temperature (°C) 80 95 110 125 D041 图 6-34. Supply Current vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC1302 15 AMC1302 www.ti.com.cn ZHCSIF3D – JUNE 2018 – REVISED JUNE 2021 6.13 Typical Characteristics (continued) 3.8 3.8 3.4 3.4 3 3 2.6 2.6 tr/tf (Ps) tr / tf (Ps) at TA = 25°C, VDD1 = 5 V, VDD2 = 3.3 V, INP = –50 mV to 50 mV, INN = GND1, and fIN = 10 kHz (unless otherwise noted) 2.2 1.8 1.4 1 1 0.6 0.6 3 3.25 3.5 3.75 4 4.25 4.5 VDD2 (V) 4.75 5 5.25 0.2 -55 -40 -25 -10 5.5 5 D042 图 6-35. Output Rise and Fall Time vs Low-Side Supply Voltage 20 35 50 65 Temperature (°C) 80 95 110 125 D043 图 6-36. Output Rise and Fall Time vs Temperature 3.8 3.8 50% - 90% 50% - 50% 50% - 10% 3.4 3 2.6 2.2 1.8 1.4 2.6 2.2 1.8 1.4 1 1 0.6 0.6 0.2 3 3.25 3.5 3.75 4 4.25 4.5 VDD2 (V) 4.75 5 5.25 50% - 90% 50% - 50% 50% - 10% 3.4 Signal Delay (Ps) 3 Signal Delay (Ps) 1.8 1.4 0.2 5.5 0.2 -55 -40 -25 -10 D044 图 6-37. VIN to VOUT Signal Delay vs Low-Side Supply Voltage 16 2.2 5 20 35 50 65 Temperature (°C) 80 95 110 125 D045 图 6-38. VIN to VOUT Signal Delay vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC1302 AMC1302 www.ti.com.cn ZHCSIF3D – JUNE 2018 – REVISED JUNE 2021 7 Detailed Description 7.1 Overview The AMC1302 is a fully differential, precision, isolated amplifier. The input stage of the device consists of a fully differential amplifier that drives a second-order, delta-sigma (ΔΣ) modulator. The modulator converts the analog input signal into a digital bitstream that is transferred across the isolation barrier that separates the high-side from the low-side. On the low-side, the received bitstream is processed by a fourth-order analog filter that outputs a differential signal at the OUTP and OUTN pins that is proportional to the input signal. The SiO2-based, capacitive isolation barrier supports a high level of magnetic field immunity, as described in the ISO72x Digital Isolator Magnetic-Field Immunity application report. The digital modulation used in the AMC1302 to transmit data across the isolation barrier, and the isolation barrier characteristics itself, result in high reliability and common-mode transient immunity. 7.2 Functional Block Diagram AMC1302 VDD2 Barrier VDD1 Diagnostics Analog Filter Isolation INN RX / TX ΔΣ Modulator TX / RX INP GND1 OUTP OUTN GND2 7.3 Feature Description 7.3.1 Analog Input The differential amplifier input stage of the AMC1302 feeds a second-order, switched-capacitor, feed-forward ΔΣ modulator. The gain of the differential amplifier is set by internal precision resistors with a differential input impedance of RIND. The modulator converts the analog input signal into a bitstream that is transferred across the isolation barrier, as described in the Isolation Channel Signal Transmission section. There are two restrictions on the analog input signals INP and INN. First, if the input voltages VINP or VINN exceed the range specified in the Absolute Maximum Ratings table, the input currents must be limited to the absolute maximum value, because the electrostatic discharge (ESD) protection turns on. In addition, the linearity and parametric performance of the device are ensured only when the analog input voltage remains within the linear full-scale range (VFSR) and within the common-mode input voltage range (VCM) as specified in the Recommended Operating Conditions table. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC1302 17 AMC1302 www.ti.com.cn ZHCSIF3D – JUNE 2018 – REVISED JUNE 2021 7.3.2 Isolation Channel Signal Transmission The AMC1302 uses an on-off keying (OOK) modulation scheme, as shown in 图 7-1, to transmit the modulator output bitstream across the SiO2-based isolation barrier. The transmit driver (TX) shown in the Functional Block Diagram transmits an internally-generated, high-frequency carrier across the isolation barrier to represent a digital one and does not send a signal to represent a digital zero. The nominal frequency of the carrier used inside the AMC1302 is 480 MHz. The receiver (RX) on the other side of the isolation barrier recovers and demodulates the signal and provides the input to the 4th-order analog filter. The AMC1302 transmission channel is optimized to achieve the highest level of common-mode transient immunity (CMTI) and lowest level of radiated emissions caused by the highfrequency carrier and RX/TX buffer switching. Internal Clock Modulator Bitstream on High-side Signal Across Isolation Barrier Recovered Sigal on Low-side 图 7-1. OOK-Based Modulation Scheme 18 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC1302 AMC1302 www.ti.com.cn ZHCSIF3D – JUNE 2018 – REVISED JUNE 2021 7.3.3 Analog Output The AMC1302 offers a differential analog output comprised of the OUTP and OUTN pins. For differential input voltages (VINP – VINN) in the range from –50 mV to 50 mV, the device provides a linear response with a nominal gain of 41. For example, for a differential input voltage of 50 mV, the differential output voltage (VOUTP – VOUTN) is 2.05 V. At zero input (INP shorted to INN), both pins output the same common-mode output voltage VCMout, as specified in the Electrical Characteristics table. For absolute differential input voltages greater than 50 mV but less than 64 mV, the differential output voltage continues to increase in magnitude but with reduced linearity performance. The outputs saturate at a differential output voltage of VCLIPout, as shown in 图 7-2, if the differential input voltage exceeds the VClipping value. Maximum input range before clipping (VClipping) Linear input range (VFSR) VOUTN VFAILSAFE VCLIPout VCMout VOUTP
64 mV 50 mV 0 64 mV 50 mV Differential Input Voltage (VINP – VINN) 图 7-2. Output Behavior of the AMC1302 The AMC1302 offers a fail-safe feature that simplifies diagnostics on system level. 图 7-2 shows the fail-safe mode, in which the AMC1302 outputs a negative differential output voltage that does not occur under normal operating conditions. The fail-safe output is active in two cases: • When the high-side supply is missing or below the VDD1UV threshold • When the common-mode input voltage, that is VCM = (VINP + VINN) / 2, exceeds the common-mode overvoltage detection level VCMov Use the maximum VFAILSAFE voltage specified in the Electrical Characteristics table as a reference value for failsafe detection on system level. 7.4 Device Functional Modes The AMC1302 is operational when the power supplies VDD1 and VDD2 are applied, as specified in the Recommended Operating Conditions table. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC1302 19 AMC1302 www.ti.com.cn ZHCSIF3D – JUNE 2018 – REVISED JUNE 2021 8 Application and Implementation Note 以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定 器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。 8.1 Application Information The low analog input voltage range, excellent accuracy, and low temperature drift make the a high-performance solution for industrial applications where shunt-based current sensing in the presence of high common-mode voltage levels is required. 8.2 Typical Application The AMC1302 is ideally suited for shunt-based current sensing applications where accurate current monitoring is required in the presence of high common-mode voltages. 图 8-1 shows the AMC1302 in a typical application. The load current flowing through an external shunt resistor RSHUNT produces a voltage drop that is sensed by the AMC1302. The AMC1302 digitizes the analog input signal on the high-side, transfers the data across the isolation barrier to the low-side, reconstructs the analog signal, and presents that signal as a differential voltage on the output pins. The differential input, differential output, and the high common-mode transient immunity (CMTI) of the AMC1302 ensure reliable and accurate operation even in high-noise environments. Floating Gate Driver Supply + DC Link Low-side supply (3.3 V or 5 V) 1 uF 100 nF AMC1302 10
10 nF VDD1 VDD2 INP OUTP INN OUTN GND1 GND2 1 uF 100 nF ADC RSHUNT Load 10 – DC Link 图 8-1. Using the AMC1302 for Current Sensing in a Typical Application 20 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC1302 AMC1302 www.ti.com.cn ZHCSIF3D – JUNE 2018 – REVISED JUNE 2021 8.2.1 Design Requirements 表 8-1 lists the parameters for this typical application. 表 8-1. Design Requirements PARAMETER VALUE High-side supply voltage 3.3 V or 5 V Low-side supply voltage 3.3 V or 5 V Voltage drop across RSHUNT for a linear response ±50 mV (maximum) Signal delay (50% VIN to 90% OUTP, OUTN) 3 µs (maximum) 8.2.2 Detailed Design Procedure In 图 8-1, the high-side power supply (VDD1) for the AMC1302 is derived from the floating power supply of the upper gate driver. The floating ground reference (GND1) is derived from the end of the shunt resistor that is connected to the negative input of the AMC1302 (INN). If a four-pin shunt is used, the inputs of the AMC1302 are connected to the inner leads and GND1 is connected to the outer lead on the INN-side of the shunt. To minimize offset and improve accuracy, route the ground connection as a separate trace that connects directly to the shunt resistor rather than shorting GND1 to INN directly at the input to the device. See the Layout section for more details. 8.2.2.1 Shunt Resistor Sizing Use Ohm's Law to calculate the voltage drop across the shunt resistor (VSHUNT) for the desired measured current: VSHUNT = I × RSHUNT. Consider the following two restrictions when selecting the value of the shunt resistor, RSHUNT: • The voltage drop caused by the nominal current range must not exceed the recommended differential input voltage range for a linear response: |VSHUNT| ≤ |VFSR| • The voltage drop caused by the maximum allowed overcurrent must not exceed the input voltage that causes a clipping output: |VSHUNT| ≤ |VClipping| 8.2.2.2 Input Filter Design TI recommends placing an RC-filter in front of the isolated amplifier to improve signal-to-noise performance of the signal path. Design the input filter such that: • The cutoff frequency of the filter is at least one order of magnitude lower than the sampling frequency (20 MHz) of the ΔΣ modulator • The input bias current does not generate significant voltage drop across the DC impedance of the input filter • The impedances measured from the analog inputs are equal For most applications, the structure shown in 图 8-2 achieves excellent performance. RSHUNT AMC1302 10
VDD1 VDD2 INP OUTP INN OUTN GND1 GND2 10 nF 10 图 8-2. Differential Input Filter Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC1302 21 AMC1302 www.ti.com.cn ZHCSIF3D – JUNE 2018 – REVISED JUNE 2021 8.2.2.3 Differential to Single-Ended Output Conversion 图 8-3 shows an example of a TLV6001-based signal conversion and filter circuit for systems using singleended-input ADCs to convert the analog output voltage into digital. With R1 = R2 = R3 = R4, the output voltage equals (VOUTP – VOUTN) + VREF. Tailor the bandwidth of this filter stage to the bandwidth requirement of the system. For most applications, R1 = R2 = R3 = R4 = 3.3 kΩ and C1 = C2 = 330 pF yields good performance. C1 AMC1302 VDD1 VDD2 INP OUTP R2 R1 – ADC R3 INN OUTN GND1 GND2 To MCU + TLV6001 C2 R4 VREF 图 8-3. Connecting the AMC1302 Output to a Single-Ended Input ADC For more information on the general procedure to design the filtering and driving stages of SAR ADCs, see the 18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise and 18-Bit Data Acquisition Block (DAQ) Optimized for Lowest Power reference guides, available for download at www.ti.com. 8.2.3 Application Curve One important aspect of power-stage design is the effective detection of an overcurrent condition to protect the switching devices and passive components from damage. To power off the system quickly in the event of an overcurrent condition, a low delay caused by the isolated amplifier is required. 图 8-4 shows the typical full-scale step response of the AMC1302. VOUTN VIN VOUTP 图 8-4. Step Response of the AMC1302 8.3 What to Do and What Not to Do Do not leave the inputs of the AMC1302 unconnected (floating) when the device is powered up. If the device inputs are left floating, the input bias current may drive the inputs to a positive value that exceeds the operating common-mode input voltage and the device outputs the fail-safe voltage as described in the Analog Output section. Connect the high-side ground (GND1) to INN, either by a hard short or through a resistive path. A DC current path between INN and GND1 is required to define the input common-mode voltage. Do not exceed the input common-mode range as specified in the Recommended Operating Conditions table. For best accuracy, route the ground connection as a separate trace that connects directly to the shunt resistor rather than shorting GND1 to INN directly at the input to the device. See the Layout section for more details. 22 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC1302 AMC1302 www.ti.com.cn ZHCSIF3D – JUNE 2018 – REVISED JUNE 2021 9 Power Supply Recommendations The AMC1302 does not require any specific power up sequencing. The high-side power-supply (VDD1) is decoupled with a low-ESR 100-nF capacitor (C1) parallel to a low-ESR 1-µF capacitor (C2). The low-side power supply (VDD2) is equally decoupled with a low-ESR 100-nF capacitor (C3) parallel to a low-ESR 1-µF capacitor (C4). Place all four capacitors (C1, C2, C3, and C4) as close to the device as possible. The ground reference for the high-side (GND1) is derived from the end of the shunt resistor, which is connected to the negative input (INN) of the device. For best DC accuracy, use a separate trace (as shown in 图 9-1) to make this connection instead of shorting GND1 to INN directly at the device input. If a four-terminal shunt is used, the device inputs are connected to the inner leads and GND1 is connected to the outer lead on the INNside of the shunt. INP VDD1 VDD2 C2 1 µF C4 1 µF AMC1302 I RSHUNT C1 100 nF C3 100 nF R2 10
R1 10 C5 10 nF VDD1 VDD2 INP OUTP to RC filter / ADC INN OUTN to RC filter / ADC GND1 GND2 图 9-1. Decoupling of the AMC1302 Capacitors must provide adequate effective capacitance under the applicable DC bias conditions they experience in the application. Multilayer ceramic capacitors (MLCCs) typically exhibit only a fraction of their nominal capacitance under real-world conditions and this factor must be taken into consideration when selecting these capacitors. This problem is especially acute in low-profile capacitors, in which the dielectric field strength is higher than in taller components. Reputable capacitor manufacturers provide capacitance versus DC bias curves that greatly simplify component selection. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC1302 23 AMC1302 www.ti.com.cn ZHCSIF3D – JUNE 2018 – REVISED JUNE 2021 10 Layout 10.1 Layout Guidelines 图 10-1 shows a layout recommendation with the critical placement of the decoupling capacitors (as close as possible to the AMC1302 supply pins) and placement of the other components required by the device. For best performance, place the shunt resistor close to the INP and INN inputs of the AMC1302 and keep the layout of both connections symmetrical. Clearance area, to be kept free of any conductive materials. C2 C4 R2 INN R1 C5 RSHUNT C1 INP VDD2 VDD1 10.2 Layout Example C3 AMC1302 OUTP to RC filter / ADC OUTN to RC filter / ADC GND2 GND1 Top Metal Inner or Bottom Layer Metal Via 图 10-1. Recommended Layout of the AMC1302 24 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC1302 AMC1302 www.ti.com.cn ZHCSIF3D – JUNE 2018 – REVISED JUNE 2021 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation, see the following: Texas Instruments, Isolation Glossary application report Texas Instruments, Semiconductor and IC Package Thermal Metrics application report Texas Instruments, ISO72x Digital Isolator Magnetic-Field Immunity application report Texas Instruments, TLV600x Low-Power, Rail-to-Rail In/Out, 1-MHz Operational Amplifier for Cost-Sensitive Systems data sheet • Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise reference guide • Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Power reference guide • Texas Instruments, Isolated Amplifier Voltage Sensing Excel Calculator design tool • • • • 11.2 Trademarks 所有商标均为其各自所有者的财产。 11.3 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.4 术语表 TI 术语表 本术语表列出并解释了术语、首字母缩略词和定义。 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC1302 25 重要声明和免责声明 TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没 有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。 这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验 证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可 将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知 识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。 TI 提供的产品受 TI 的销售条款 (https:www.ti.com/legal/termsofsale.html) 或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。重要声明 邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2021，德州仪器 (TI) 公司 PACKAGE OPTION ADDENDUM www.ti.com 27-Jan-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) AMC1302DWV ACTIVE SOIC DWV 8 64 RoHS & Green NIPDAU Level-3-260C-168 HR -55 to 125 AMC1302 AMC1302DWVR ACTIVE SOIC DWV 8 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -55 to 125 AMC1302 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of