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AMC1305L25, AMC1305M05, AMC1305M25
SBAS654G – JUNE 2014 – REVISED JANUARY 2020
AMC1305x
High-Precision, Reinforced Isolated Delta-Sigma Modulators
1 Features
3 Description
•
The AMC1305 is a precision, delta-sigma (ΔΣ)
modulator with the output separated from the input
circuitry by a capacitive double isolation barrier that is
highly resistant to magnetic interference. This barrier
is certified to provide reinforced isolation of up to
7000 VPEAK according to the DIN VDE V 0884-11,
UL1577, and CSA standards. Used in conjunction
with isolated power supplies, the device prevents
noise currents on a high common-mode voltage line
from entering the local system ground and interfering
with or damaging low voltage circuitry.
1
•
•
•
•
•
•
Pin-compatible family optimized for shunt-resistorbased current measurements:
– ±50-mV or ±250-mV input voltage ranges
– CMOS or LVDS digital interface options
Excellent DC performance supporting highprecision sensing on system level:
– Offset error: ±50 µV or ±150 µV (max)
– Offset drift: 1.3 µV/°C (max)
– Gain error: ±0.3% (max)
– Gain drift: ±40 ppm/°C (max)
Safety-related certifications:
– 7000-VPK reinforced isolation per
DIN VDE V 0884-11: 2017-01
– 5000-VRMS isolation for 1 minute per UL1577
– CAN/CSA no. 5A-component acceptance
service notice and IEC 62368-1 end equipment
standard
Transient immunity: 15 kV/µs (min)
High electromagnetic field immunity
(see application note SLLA181A)
External 5-MHz to 20-MHz clock input for
easier system-level synchronization
Fully specified over the extended industrial
temperature range
The AMC1305 is optimized for direct connection to
shunt resistors or other low voltage level signal
sources and supports excellent dc and ac
performance. Shunt resistors are typically used to
sense currents in motor drives, green energy
generation systems, or other industrial applications.
By using an appropriate digital filter (that is, as
integrated on the TMS320F2837x) to decimate the bit
stream, the device can achieve 16 bits of resolution
with a dynamic range of 85 dB (13.8 ENOB) at a data
rate of 78 kSPS.
On the high-side, the modulator is supplied with a
nominal voltage of 5 V (AVDD), whereas the isolated
digital interface operates from a 3.3-V or 5-V power
supply (DVDD).
The AMC1305 is available in a wide-body SOIC-16
(DW) package and is specified from –40°C to
+125°C.
2 Applications
•
•
Device Information(1)
Shunt-resistor-based current sensing in:
– Industrial motor drives
– Photovoltaic inverters
– Uninterruptible power supplies
Isolated voltage sensing
PART NUMBER
AMC1305x
PACKAGE
SOIC (16)
BODY SIZE (NOM)
10.30 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
Floating
Power Supply
HV+
AMC1305
5.0 V
AVDD
AGND
RSHUNT
AINN
To Load
AINP
Gate Driver
Reinforced Isolation
Gate Driver
DVDD
3.3 V, or 5.0 V
DGND
DOUT
SD-Dx
CLKIN
SD-Cx
PWMx
TMS320F2837x
HV1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AMC1305L25, AMC1305M05, AMC1305M25
SBAS654G – JUNE 2014 – REVISED JANUARY 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
8
1
1
1
2
4
4
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Power Ratings........................................................... 5
Insulation Specifications............................................ 6
Safety-Related Certifications..................................... 7
Safety Limiting Values .............................................. 7
Electrical Characteristics: AMC1305M05.................. 8
Electrical Characteristics: AMC1305x25 ............... 10
Switching Characteristics ...................................... 12
Insulation Characteristics Curves ......................... 13
Typical Characteristics .......................................... 14
Detailed Description ............................................ 21
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
21
21
22
24
Application and Implementation ........................ 25
9.1 Application Information............................................ 25
9.2 Typical Applications ................................................ 26
10 Power Supply Recommendations ..................... 30
11 Layout................................................................... 31
11.1 Layout Guidelines ................................................. 31
11.2 Layout Examples................................................... 31
12 Device and Documentation Support ................. 33
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
33
33
33
33
33
33
33
13 Mechanical, Packaging, and Orderable
Information ........................................................... 34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (March 2017) to Revision G
Page
•
Changed VDE certificate revision from DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 to DIN VDE V 0884-11:
2017-01 in Safety-related certifications Features bullet ......................................................................................................... 1
•
Changed IEC standard revision from IEC 60950-1, and IEC 60065 to IEC 62368-1 in CAN/CSA no. 5A-component
acceptance service notice Features bullet ............................................................................................................................. 1
•
Changed DIN V VDE V 0884-10 to DIN VDE V 0884-11 in Description section ................................................................... 1
•
Changed DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 header row to DIN VDE V 0884-11: 2017-01 in
Insulation Specifications table ................................................................................................................................................ 6
•
VDE certificate details in Safety-Related Certifications table ................................................................................................. 7
•
Changed Safety Limiting Values table as per ISO standard: deleted last sentence from condition statement,
changed footnotes, deleted paragraph below table ............................................................................................................... 7
Changes from Revision E (January 2017) to Revision F
•
Page
Changed minimum specification from DGND – 0.3 to DGND – 0.5 and maximum specification from DVDD + 0.3 to
DVDD + 0.5 in Digital input voltage parameter row of Absolute Maximum Ratings table...................................................... 5
Changes from Revision D (August 2016) to Revision E
•
2
Page
Changed V(ESD) for Human-body model (HBM) from ±1000 V to ±2500 V............................................................................. 5
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SBAS654G – JUNE 2014 – REVISED JANUARY 2020
Changes from Revision C (December 2014) to Revision D
Page
•
Added last two Features bullets ............................................................................................................................................. 1
•
Changed Simplified Schematic figure..................................................................................................................................... 1
•
Moved Power Rating, Insulation Specifications, Regulatory Information, and Safety Limiting Values tables ....................... 5
•
Changed Insulation Specifications table as per ISO standard .............................................................................................. 6
•
Added Insulation Characteristics Curves section ................................................................................................................ 13
•
Changed Figure 54 .............................................................................................................................................................. 26
•
Changed Figure 58 .............................................................................................................................................................. 30
Changes from Revision B (October 2014) to Revision C
Page
•
Changed device status of AMC1305M05 to Production Data ................................................................................................ 1
•
Changed document status from Mixed Status to Production Data ........................................................................................ 1
•
Updated ESD Ratings table to latest standard ...................................................................................................................... 5
Changes from Revision A (November 2014) to Revision B
Page
•
Changed device status of AMC1305M25 to Production Data ................................................................................................ 1
•
Changed Features bullet from "Safety and Regulatory Approvals" to "Safety-Related Certifications" .................................. 1
Changes from Original (June 2014) to Revision A
•
Page
Made changes to product preview data sheet........................................................................................................................ 1
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SBAS654G – JUNE 2014 – REVISED JANUARY 2020
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5 Device Comparison Table
PART NUMBER
INPUT VOLTAGE
RANGE
DIFFERENTIAL INPUT
RESISTANCE
SNR (sinc3 Filter,
78 kSPS)
OUTPUT INTERFACE
AMC1305L25
±250 mV
25 kΩ
82 dB
LVDS
AMC1305M05
±50 mV
5 kΩ
76 dB
CMOS
AMC1305M25
±250 mV
25 kΩ
82 dB
CMOS
6 Pin Configuration and Functions
DW Package
16-Pin SOIC
Top View
DW Package
16-Pin SOIC
Top View
NC
1
16 DGND
15 NC
AINP
2
15 NC
3
14 DVDD
AINN
3
14 DVDD
AGND
4
13 CLKIN
AGND
4
13 CLKIN
NC
5
12 CLKIN_N
NC
5
12 NC
NC
6
11 DOUT
NC
6
11 DOUT
AVDD
7
10 DOUT_N
AVDD
7
10 NC
AGND
8
9
AGND
8
9
NC
1
16 DGND
AINP
2
AINN
DGND
LVDS Versions (AMC1305L25)
DGND
CMOS Versions (AMC1305Mx)
Pin Functions
PIN
NAME
I/O
DESCRIPTION
4
—
This pin is internally connected to pin 8 and can be left unconnected or tied to high-side
ground
8
—
High-side ground reference
AINN
3
I
Inverting analog input
AINP
2
I
Noninverting analog input
AVDD
7
—
AGND
High-side power supply, 4.5 V to 5.5 V.
See the Power-Supply Recommendations section for decoupling recommendations.
CLKIN
13
I
Modulator clock input, 5 MHz to 20.1 MHz
CLKIN_N
12
I
AMC1305L25 only: inverted modulator clock input
DGND
9, 16
—
Controller-side ground reference
DOUT
11
O
Modulator data output
DOUT_N
10
O
AMC1305L25 only: inverted modulator data output
DVDD
14
—
Controller-side power supply, 3.0 to 5.5 V
1
—
This pin can be connected to AVDD or can be left unconnected
5
—
This pin can be left unconnected or tied to AGND only
6, 10, 12
—
These pins have no internal connection (pins 10 and 12 on the AMC1305Mx only).
15
—
This pin can be left unconnected or tied to DVDD only
NC
4
NO.
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SBAS654G – JUNE 2014 – REVISED JANUARY 2020
7 Specifications
7.1 Absolute Maximum Ratings
over the operating ambient temperature range (unless otherwise noted) (1)
Supply voltage, AVDD to AGND or DVDD to DGND
Analog input voltage at AINP, AINN
Digital input voltage at CLKIN, CLKIN_N
MIN
MAX
UNIT
–0.3
6.5
V
V
AGND – 6
AVDD + 0.5
DGND – 0.5
DVDD + 0.5
V
–10
10
mA
150
°C
150
°C
Input current to any pin except supply pins
Maximum virtual junction temperature, TJ
Storage temperature, Tstg
(1)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
AVDD
High-side (analog) supply voltage
4.5
5.0
5.5
DVDD
Controller-side (digital) supply voltage
3.0
3.3
5.5
V
V
TA
Operating ambient temperature range
–40
125
°C
7.4 Thermal Information
AMC1305x
THERMAL METRIC (1)
DW (SOIC)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
80.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
40.5
°C/W
RθJB
Junction-to-board thermal resistance
45.1
°C/W
ψJT
Junction-to-top characterization parameter
11.9
°C/W
ψJB
Junction-to-board characterization parameter
44.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
7.5 Power Ratings
PARAMETER
VALUE
UNIT
AVDD = 5.5 V, DVDD = 5.5 V, LVDS, RLOAD = 100 Ω
89.1
mW
Maximum power dissipation
(high-side supply)
AVDD = 5.5 V
45.1
mW
Maximum power dissipation
(low-side supply)
DVDD = 5.5 V, LVDS, RLOAD = 100 Ω
44
mW
PD
Maximum power dissipation
(both sides)
PD1
PD2
TEST CONDITIONS
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7.6 Insulation Specifications
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
Minimum air gap (clearance) (1)
Shortest pin-to-pin distance through air
≥8
mm
CPG
Minimum external tracking (creepage) (1)
Shortest pin-to-pin distance across the package
surface
≥8
mm
DTI
Distance through insulation
Minimum internal gap (internal clearance) of the
double insulation (2 × 0.0135 mm)
0.027
mm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
≥ 600
V
Material group
According to IEC 60664-1
CLR
Overvoltage category per IEC 60664-1
I
Rated mains voltage ≤ 300 VRMS
I-IV
Rated mains voltage ≤ 600 VRMS
I-III
Rated mains voltage ≤ 1000 VRMS
I-II
At ac voltage (bipolar or unipolar)
1414
VPK
At ac voltage (sine wave)
1000
VRMS
At dc voltage
1500
VDC
VTEST = VIOTM, t = 60 s (qualification test)
7000
VTEST = 1.2 x VIOTM, t = 1 s (100% production
test)
8400
Test method per IEC 60065, 1.2/50-μs
waveform, VTEST = 1.6 x VIOSM = 10000 VPK
(qualification)
6250
VPK
Method a, after input/output safety test subgroup
2 / 3, Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 x VIORM
= 1697 VPK, tm = 10 s
≤5
pC
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.6 x VIORM =
2263 VPK, tm = 10 s
≤5
pC
Method b1, at routine test (100% production) and
preconditioning (type test), Vini = VIOTM, tini = 1 s,
Vpd(m) = 1.875 x VIORM = 2652 VPK, tm = 1 s
≤5
pC
1.2
pF
> 109
Ω
DIN VDE V 0884-11: 2017-01 (2)
VIORM
Maximum repetitive peak isolation
voltage
VIOWM
Maximum-rated isolation working
voltage
VIOTM
Maximum transient isolation voltage
VIOSM
Maximum surge isolation voltage (3)
Apparent charge (4)
qpd
CIO
Barrier capacitance, input to output (5)
VIO = 0.5 VPP at 1 MHz
RIO
Insulation resistance, input to output (5)
VIO = 500 V at TS = 150°C
Pollution degree
2
Climatic category
40/125/21
VPK
UL1577
VISO
(1)
(2)
(3)
(4)
(5)
6
Withstand isolation voltage
VTEST = VISO = 5000 VRMS or 7000 VDC, t = 60 s
(qualification test), VTEST = 1.2 x VISO = 6000
VRMS, t = 1 s (100% production test)
5000
VRMS
Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed
circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as
inserting grooves or ribs on the PCB are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier are tied together, creating a two-pin device.
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SBAS654G – JUNE 2014 – REVISED JANUARY 2020
7.7 Safety-Related Certifications
VDE
UL
Certified according to DIN VDE V 0884-11: 2017-01,
DIN EN 62368-1: 2016-05, EN 62368-1: 2014,
and IEC 62368-1: 2014
Recognized under UL1577 component recognition and CSA
component acceptance NO 5 programs
Reinforced insulation
Single protection
Certificate number: 40040142
File number: E181974
7.8 Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
IS
TEST CONDITIONS
Safety input, output, or supply current
PS
Safety input, output, or total power
TS
Maximum safety temperature
(1)
MAX
UNIT
RθJA = 80.2°C/W, AVDD = DVDD = 5.5 V, TJ =
150°C, TA = 25°C, see Figure 3
MIN
283
mA
RθJA = 80.2°C/W, AVDD = DVDD = 3.6 V, TJ =
150°C, TA = 25°C, see Figure 3
432
mA
1558 (1)
mW
RθJA = 80.2°C/W, TJ = 150°C, TA = 25°C, see
Figure 4
TYP
150
°C
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These
limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature.
PS = IS × AVDDmax + IS × DVDDmax, where AVDDmax is the maximum high-side voltage and DVDDmax is the maximum controller-side
supply voltage.
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7.9 Electrical Characteristics: AMC1305M05
All minimum and maximum specifications at TA = –40°C to +125°C, AVDD = 4.5 V to 5.5 V, DVDD = 3.0 V to 5.5 V, AINP =
–50 mV to 50 mV, AINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise noted. Typical values are at TA = 25°C,
CLKIN = 20 MHz, AVDD = 5.0 V, and DVDD = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
VClipping
Maximum differential voltage input range
(AINP-AINN)
FSR
Specified linear full-scale range
(AINP-AINN)
VCM
Operating common-mode input range
CID
Differential input capacitance
IIB
Input current
RID
Differential input resistance
IOS
Input offset current
CMTI
Common-mode transient immunity
CMRR
Common-mode rejection ratio
BW
±62.5
mV
–50
50
–0.032
AVDD – 2
2
Inputs shorted to AGND
–97
–72
V
pF
-57
5
μA
kΩ
±5
nA
15
fIN = 0 Hz,
VCM min ≤ VIN ≤ VCM max
mV
kV/μs
–104
dB
fIN from 0.1 Hz to 50 kHz,
VCM min ≤ VIN ≤ VCM max
–75
Input bandwidth
800
kHz
DC ACCURACY
DNL
Differential nonlinearity
Resolution: 16 bits
–0.99
0.99
LSB
INL
Integral nonlinearity (1)
Resolution: 16 bits
–4
±1.5
4
LSB
EO
Offset error
Initial, at 25°C
–50
±2.5
50
µV
TCEO
Offset error thermal drift (2)
1.3
μV/°C
EG
Gain error
TCEG
Gain error thermal drift (3)
PSRR
Power-supply rejection ratio
–1.3
Initial, at 25°C
–0.3%
–0.02%
0.3%
–40
±20
40
VAVDD from 4.5 to 5.5V, at dc
ppm/°C
105
dB
dB
AC ACCURACY
SNR
Signal-to-noise ratio
fIN = 1 kHz
76
81
SINAD
Signal-to-noise + distortion
fIN = 1 kHz
76
81
THD
Total harmonic distortion
fIN = 1 kHz
SFDR
Spurious-free dynamic range
fIN = 1 kHz
–90
83
dB
–83
92
dB
dB
DIGITAL INPUTS/OUTPUTS
External Clock
fCLKIN
Input clock frequency
DutyCLKIN
Duty cycle
5 MHz ≤ fCLKIN ≤ 20.1 MHz
5
20
20.1
40%
50%
60%
MHz
CMOS Logic Family, CMOS with Schmitt-Trigger
DGND ≤ VIN ≤ DVDD
IIN
Input current
CIN
Input capacitance
–1
1
VIH
High-level input voltage
0.7 × DVDD
DVDD + 0.3
VIL
Low-level input voltage
–0.3
0.3 × DVDD
CLOAD
Output load capacitance
VOH
High-level output voltage
VOL
Low-level output voltage
5
fCLKIN = 20 MHz
pF
30
IOH = –20 µA
DVDD – 0.1
IOH = –4 mA
DVDD – 0.4
μA
V
V
pF
V
IOL = 20 µA
0.1
IOL = 4 mA
0.4
V
(1)
Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.
(2)
Offset error drift is calculated using the box method as described by the following equation:
(3)
8
value MAX value MIN
TempRange
§ value MAX value MIN
TCE G ( ppm ) ¨¨
© value u TempRange
Gain error drift is calculated using the box method as described by the following equation:
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TCE O
·
¸¸ u 10 6
¹
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SBAS654G – JUNE 2014 – REVISED JANUARY 2020
Electrical Characteristics: AMC1305M05 (continued)
All minimum and maximum specifications at TA = –40°C to +125°C, AVDD = 4.5 V to 5.5 V, DVDD = 3.0 V to 5.5 V, AINP =
–50 mV to 50 mV, AINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise noted. Typical values are at TA = 25°C,
CLKIN = 20 MHz, AVDD = 5.0 V, and DVDD = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4.5
5.0
5.5
V
6.5
8.2
mA
32.5
45.1
mW
3.3
5.5
V
3.0 V ≤ DVDD ≤ 3.6 V
2.7
4.0
4.5 V ≤ DVDD ≤ 5.5 V
3.2
5.5
3.0 V ≤ DVDD ≤ 3.6 V
8.9
14.4
4.5 V ≤ DVDD ≤ 5.5 V
16.0
30.3
POWER SUPPLY
AVDD
High-side supply voltage
IAVDD
High-side supply current
PAVDD
High-side power dissipation
DVDD
Controller-side supply voltage
IDVDD
Controller-side supply current
PDVDD
Controller-side power dissipation
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7.10 Electrical Characteristics: AMC1305x25
All minimum and maximum specifications at TA = –40°C to 125°C, AVDD = 4.5 V to 5.5 V, DVDD = 3.0 V to 5.5 V, AINP =
–250 mV to 250 mV, AINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise noted. Typical values are at TA = 25°C,
CLKIN = 20 MHz, AVDD = 5.0 V, and DVDD = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
VClipping
Maximum differential voltage input range
(AINP-AINN)
FSR
Specified linear full-scale range
(AINP-AINN)
–250
VCM
Operating common-mode input range
–0.16
CID
Differential input capacitance
IIB
Input current
RID
Differential input resistance
IOS
Input offset current
CMTI
Common-mode transient immunity
CMRR
Common-mode rejection ratio
BW
±312.5
mV
250
AVDD – 2
1
Inputs shorted to AGND
–82
–60
mV
V
pF
–48
25
μA
kΩ
±5
nA
15
kV/μs
fIN = 0 Hz,
VCM min ≤ VIN ≤ VCM max
–95
fIN from 0.1 Hz to 50 kHz,
VCM min ≤ VIN ≤ VCM max
–76
dB
Input bandwidth
1000
kHz
DC ACCURACY
DNL
Differential nonlinearity
Resolution: 16 bits
–0.99
0.99
LSB
INL
Integral nonlinearity (1)
Resolution: 16 bits
–4
±1.5
4
LSB
EO
Offset error
Initial, at 25°C
–150
±40
150
µV
TCEO
Offset error thermal drift (2)
1.3
μV/°C
EG
Gain error
TCEG
Gain error thermal drift (3)
PSRR
Power-supply rejection ratio
–1.3
Initial, at 25°C
–0.3
–0.02
0.3
%FS
–40
±20
40
ppm/°C
VAVDD from 4.5 V to 5.5 V, at dc
90
dB
dB
AC ACCURACY
SNR
Signal-to-noise ratio
fIN = 1 kHz
82
85
SINAD
Signal-to-noise + distortion
fIN = 1 kHz
80
84
THD
Total harmonic distortion
fIN = 1 kHz
SFDR
Spurious-free dynamic range
fIN = 1 kHz
–90
83
dB
–83
92
dB
dB
DIGITAL INPUTS/OUTPUTS
External Clock
fCLKIN
Input clock frequency
DutyCLKIN
Duty cycle
5 MHz ≤ fCLKIN ≤ 20.1 MHz
5
20
20.1
40%
50%
60%
MHz
CMOS Logic Family (AMC1305M25), CMOS with Schmitt-Trigger
DGND ≤ VIN ≤ DVDD
IIN
Input current
CIN
Input capacitance
–1
1
VIH
High-level input voltage
0.7 × DVDD
DVDD + 0.3
VIL
Low-level input voltage
–0.3
0.3 × DVDD
CLOAD
Output load capacitance
VOH
High-level output voltage
VOL
Low-level output voltage
5
fCLKIN = 20 MHz
pF
30
IOH = –20 µA
DVDD – 0.1
IOH = –4 mA
DVDD – 0.4
μA
V
V
pF
V
IOL = 20 µA
0.1
IOL = 4 mA
0.4
V
(1)
Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as the number of LSBs or as a percent of the specified linear full-scale range FSR.
(2)
Offset error drift is calculated using the box method as described by the following equation:
(3)
10
value MAX value MIN
TempRange
§ value MAX value MIN
TCE G ( ppm ) ¨¨
© value u TempRange
Gain error drift is calculated using the box method as described by the following equation:
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TCE O
·
¸¸ u 10 6
¹
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SBAS654G – JUNE 2014 – REVISED JANUARY 2020
Electrical Characteristics: AMC1305x25 (continued)
All minimum and maximum specifications at TA = –40°C to 125°C, AVDD = 4.5 V to 5.5 V, DVDD = 3.0 V to 5.5 V, AINP =
–250 mV to 250 mV, AINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise noted. Typical values are at TA = 25°C,
CLKIN = 20 MHz, AVDD = 5.0 V, and DVDD = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mV
LVDS Logic Family (AMC1305L25)
VOD
Differential output voltage
VOCM
Output common-mode voltage
RLOAD = 100 Ω
IS
Output short-circuit current
VICM
Input common-mode voltage
VID
Differential input voltage
IIN
Input current
250
350
450
1.125
1.23
1.375
24
VID = 100 mV
V
mA
0.05
1.25
3.25
V
100
350
600
mV
–24
0
20
µA
4.5
5.0
5.5
V
6.5
8.2
mA
32.5
45.1
mW
3.3
5.5
V
AMC1305L25, RLOAD = 100 Ω
6.1
8.0
AMC1305M25, 3.0 ≤ DVDD ≤ 3.6 V,
CLOAD = 5 pF
2.7
4.0
AMC1305M25, 4.5 ≤ DVDD ≤ 5.5 V,
CLOAD = 5 pF
3.2
5.5
DGND ≤ VIN ≤ 3.3 V
POWER SUPPLY
AVDD
High-side supply voltage
IAVDD
High-side supply current
PAVDD
High-side power dissipation
DVDD
Controller-side supply voltage
IDVDD
Controller-side supply current
3.0
AMC1305L25, RLOAD = 100 Ω
PDVDD
Controller-side power dissipation
Copyright © 2014–2020, Texas Instruments Incorporated
20.1
44.0
AMC1305M25, 3.0 ≤ DVDD ≤ 3.6 V,
CLOAD = 5 pF
8.9
14.4
AMC1305M25, 4.5 ≤ DVDD ≤ 5.5 V,
CLOAD = 5 pF
16.0
30.3
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7.11 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
tCLK
CLKIN, CLKIN_N clock period
49.75
50
200
ns
tHIGH
CLKIN, CLKIN_N clock high time
19.9
25
120
ns
tLOW
CLKIN, CLKIN_N clock low time
19.9
25
120
ns
tD
Falling edge of CLKIN, CLKIN_N to DOUT, DOUT_N valid delay,
CLOAD = 5 pF
0
15
ns
tISTART
Interface startup time
(DVDD at 3.0 V min to DOUT, DOUT_N valid with AVDD ≥ 4.5 V)
32
32
CLKIN
cycles
tASTART
Analog startup time (AVDD step up to 4.5 V with DVDD ≥ 3.0 V)
1
tCLK
ms
tHIGH
CLKIN
CLKIN_N
tLOW
tD
DOUT
DOUT_N
Figure 1. Digital Interface Timing
DVDD
CLKIN
...
DOUT
Data not valid
Valid data
tISTART = 32 CLKIN cycles
Figure 2. Digital Interface Startup Timing
12
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SBAS654G – JUNE 2014 – REVISED JANUARY 2020
7.12 Insulation Characteristics Curves
500
1600
AVDD = DVDD = 3.6 V
AVDD = DVDD = 5.5 V
1400
400
300
PS (mW)
IS (mA)
1200
200
1000
800
600
400
100
200
0
0
0
50
100
TA (°C)
150
200
0
50
100
TA (°C)
D043
Figure 3. Thermal Derating Curve for Safety Limiting
Current per VDE
150
200
D044
Figure 4. Thermal Derating Curve for Safety Limiting Power
per VDE
TA up to 150°C, stress voltage frequency = 60 Hz
Figure 5. Reinforced Isolation Capacitor Lifetime Projection
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7.13 Typical Characteristics
At TA = 25°C, AVDD = 5.0 V, DVDD = 3.3 V, AINP = –250 mV to 250 mV, AINN = 0 V, fCLKIN = 20 MHz, and sinc3 filter with
OSR = 256, unless otherwise noted.
60
0
40
-20
-40
CMRR (dB)
IIB (PA)
20
0
-20
-60
-80
-40
-60
-100
1305x25
1305M05
-80
-0.5
0
0.5
1
1.5
VCM (V)
2
2.5
-120
0.001
3
3
3.5
2
3
1
2.5
INL (|LSB|)
INL (LSB)
4
0
-1
1
-3
0.5
0.15
0.2
50 100
D002
1.5
-2
0.1
2 3 5 710 20
2
0
-40
0.25
-25
-10
5
D003
Figure 8. Integral Nonlinearity vs Input Signal Amplitude
20 35 50 65
Temperature (°C)
80
95
110 125
D004
Figure 9. Integral Nonlinearity vs Temperature
150
50
125
40
100
30
75
20
50
25
EO (µV)
EO (µV)
0.1 0.2 0.5 1
fIN (kHz)
Figure 7. Common-Mode Rejection Ratio vs
Input Signal Frequency
4
-4
-0.25 -0.2 -0.15 -0.1 -0.05 0 0.05
VIN (mV)
0.01
D001
Figure 6. Input Current vs Input Common-Mode Voltage
0
-25
-50
10
0
-10
-20
-75
-30
-100
-125
-40
-150
4.5
-50
4.5
4.6
4.7
4.8
4.9
5
5.1
AVDD (V)
5.2
5.3
5.4
5.5
D005
AMC1305x25
Figure 10. Offset Error vs High-Side Supply Voltage
14
1305x25
1305M05
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4.6
4.7
4.8
4.9
5
5.1
AVDD (V)
5.2
5.3
5.4
5.5
D006
AMC1305M05
Figure 11. Offset Error vs High-Side Supply Voltage
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SBAS654G – JUNE 2014 – REVISED JANUARY 2020
Typical Characteristics (continued)
At TA = 25°C, AVDD = 5.0 V, DVDD = 3.3 V, AINP = –250 mV to 250 mV, AINN = 0 V, fCLKIN = 20 MHz, and sinc3 filter with
OSR = 256, unless otherwise noted.
150
50
125
40
100
30
75
20
25
EO (µV)
EO (µV)
50
0
-25
-50
10
0
-10
-20
-75
-30
-100
-40
-125
-150
-40
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
-50
-40
110 125
-25
-10
5
20 35 50 65
Temperature (qC)
D007
AMC1305x25
80
95
110 125
D008
AMC1305M05
Figure 12. Offset Error vs Temperature
Figure 13. Offset Error vs Temperature
150
0.3
1305x25
1305M05
125
100
0.2
75
0.1
EG (%FS)
EO (µV)
50
25
0
-25
-50
0
-0.1
-75
-100
-0.2
-125
-150
5
10
15
-0.3
4.5
20
fCLKIN (MHz)
4.7
4.8
4.9
5
5.1
AVDD (V)
5.2
5.3
5.4
5.5
D010
Figure 15. Gain Error vs High-Side Supply Voltage
0.3
0.2
0.2
0.1
0.1
EG (%FS)
EG (%FS)
Figure 14. Offset Error vs Clock Frequency
0.3
0
0
-0.1
-0.1
-0.2
-0.2
-0.3
-40
4.6
D009
-0.3
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
Figure 16. Gain Error vs Temperature
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D011
5
10
15
fCLKIN (MHz)
20
D012
Figure 17. Gain Error vs Clock Frequency
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Typical Characteristics (continued)
At TA = 25°C, AVDD = 5.0 V, DVDD = 3.3 V, AINP = –250 mV to 250 mV, AINN = 0 V, fCLKIN = 20 MHz, and sinc3 filter with
OSR = 256, unless otherwise noted.
0
100
1305x25
1305M05
SNR and SINAD (dB)
-20
PSRR (dB)
-40
-60
-80
-100
0.01
0.1
1
Ripple Frequency (kHz)
10
85
80
75
70
60
4.5
100
4.7
4.8
4.9
5
5.1
AVDD (V)
5.2
5.3
5.4
5.5
D014
Figure 19. SNR and SINAD vs High-Side Supply Voltage
100
100
SNR (x25)
SINAD (x25)
SNR (M05)
SINAD (M05)
90
SNR (x25)
SINAD (x25)
SNR (M05)
SINAD (M05)
95
SNR and SINAD (dB)
95
85
80
75
70
65
90
85
80
75
70
65
60
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
5
10
15
20
fCLKIN (MHz)
D015
Figure 20. SNR and SINAD vs Temperature
D016
Figure 21. SNR and SINAD vs Clock Frequency
100
100
SNR (x25)
SINAD (x25)
SNR (M05)
SINAD (M05)
90
SNR
SINAD
95
90
SNR and SINAD (dB)
95
SNR and SINAD (dB)
4.6
D013
Figure 18. Power-Supply Rejection Ratio vs
Ripple Frequency
SNR and SINAD (dB)
90
65
-120
0.001
60
-40
SNR (x25)
SINAD (x25)
SNR (M05)
SINAD (M05)
95
85
80
75
70
85
80
75
70
65
60
65
60
0.1
55
50
1
10
fIN (kHz)
100
D017
0
50
100
150
200 250 300
VIN (mVpp)
350
400
450
500
D018
AMC1305x25
Figure 22. SNR and SINAD vs Input Signal Frequency
16
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Figure 23. SNR and SINAD vs Input Signal Amplitude
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SBAS654G – JUNE 2014 – REVISED JANUARY 2020
Typical Characteristics (continued)
At TA = 25°C, AVDD = 5.0 V, DVDD = 3.3 V, AINP = –250 mV to 250 mV, AINN = 0 V, fCLKIN = 20 MHz, and sinc3 filter with
OSR = 256, unless otherwise noted.
100
-60
SNR
SINAD
-65
90
-70
85
-75
80
-80
THD (dB)
SNR and SINAD (dB)
95
75
70
-85
-90
65
-95
60
-100
55
-105
50
0
10
20
30
40
50
60
VIN (mVpp)
70
80
90
-110
4.5
100
4.6
4.7
4.8
4.9
5
5.1
AVDD (V)
D019
5.2
5.3
5.4
5.5
D020
AMC1305M05
Figure 25. Total Harmonic Distortion vs
High-Side Supply Voltage
-60
-60
-65
-65
-70
-70
-75
-75
-80
-80
THD (dB)
THD (dB)
Figure 24. SNR and SINAD vs Input Signal Amplitude
-85
-90
-90
-95
-95
-100
-100
-105
-105
-110
-40
-110
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
5
110 125
-65
-70
-70
-75
-75
-80
-80
THD (dB)
-60
-90
20
D022
Figure 27. Total Harmonic Distortion vs Clock Frequency
-65
-85
15
fCLKIN (MHz)
-60
-85
-90
-95
-95
-100
-100
-105
-105
-110
0.1
10
D021
Figure 26. Total Harmonic Distortion vs Temperature
THD (dB)
-85
-110
1
10
fIN (kHz)
100
D023
0
50
100
150
200 250 300
VIN (mVpp)
350
400
450
500
D024
AMC1305x25
Figure 28. Total Harmonic Distortion vs
Input Signal Frequency
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Figure 29. Total Harmonic Distortion vs
Input Signal Amplitude
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Typical Characteristics (continued)
-60
110
-65
105
-70
100
-75
95
SFDR (dB)
THD (dB)
At TA = 25°C, AVDD = 5.0 V, DVDD = 3.3 V, AINP = –250 mV to 250 mV, AINN = 0 V, fCLKIN = 20 MHz, and sinc3 filter with
OSR = 256, unless otherwise noted.
-80
-85
-90
90
85
80
-95
75
-100
70
-105
65
60
4.5
-110
0
50
100
150
VIN (mVpp)
4.6
4.7
4.8
D025
4.9
5
5.1
AVDD (V)
5.2
5.3
5.4
5.5
D026
AMC1305M05
Figure 31. Spurious-Free Dynamic Range vs
High-Side Supply Voltage
110
110
105
105
100
100
95
95
SFDR (dB)
SFDR (dB)
Figure 30. Total Harmonic Distortion vs
Input Signal Amplitude
90
85
80
90
85
80
75
75
70
70
65
65
60
-40
60
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
5
110 125
105
100
100
95
95
SFDR (dB)
SFDR (dB)
110
105
85
80
20
D028
Figure 33. Spurious-Free Dynamic Range vs
Clock Frequency
110
90
15
fCLKIN (MHz)
Figure 32. Spurious-Free Dynamic Range vs Temperature
90
85
80
75
75
70
70
65
65
60
0.1
10
D027
60
1
10
fIN (kHz)
100
D029
0
50
100
150
200 250 300
VIN (mVpp)
350
400
450
500
D030
AMC1305x25
Figure 34. Spurious-Free Dynamic Range vs
Input Signal Frequency
18
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Figure 35. Spurious-Free Dynamic Range vs
Input Signal Amplitude
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SBAS654G – JUNE 2014 – REVISED JANUARY 2020
Typical Characteristics (continued)
At TA = 25°C, AVDD = 5.0 V, DVDD = 3.3 V, AINP = –250 mV to 250 mV, AINN = 0 V, fCLKIN = 20 MHz, and sinc3 filter with
OSR = 256, unless otherwise noted.
110
0
105
-20
100
-40
Magnitude (dB)
SFDR (dB)
95
90
85
80
75
-60
-80
-100
70
-120
65
60
-140
0
50
100
150
VIN (mVpp)
0
AMC1305M05
15
20
25
Frequency (kHz)
30
35
40
D032
Figure 37. Frequency Spectrum with 1-kHz Input Signal
0
0
-20
-20
-40
-40
Magnitude (dB)
Magnitude (dB)
10
AMC1305x25, 4096-point FFT, VIN = 500 mVPP
Figure 36. Spurious-Free Dynamic Range vs
Input Signal Amplitude
-60
-80
-60
-80
-100
-100
-120
-120
-140
-140
0
5
10
15
20
25
Frequency (kHz)
30
35
40
0
-20
9
-40
8
IAVDD (mA)
10
-60
-80
-120
4
-140
30
35
35
40
D034
6
5
15
20
25
Frequency (kHz)
30
7
-100
10
15
20
25
Frequency (kHz)
Figure 39. Frequency Spectrum with 1-kHz Input Signal
0
5
10
AMC1305M05, 4096-point FFT, VIN = 500 mVPP
Figure 38. Frequency Spectrum with 5-kHz Input Signal
0
5
D033
AMC1305x25, 4096-point FFT, VIN = 500 mVPP
Magnitude (dB)
5
D031
40
D035
3
4.5
4.6
4.7
4.8
4.9
5
5.1
AVDD (V)
5.2
5.3
5.4
5.5
D036
AMC1305M05, 4096-point FFT, VIN = 500 mVPP
Figure 40. Frequency Spectrum with 5-kHz Input Signal
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Figure 41. High-Side Supply Current vs
High-Side Supply Voltage
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Typical Characteristics (continued)
10
10
9
9
8
8
IAVDD (mA)
IAVDD (mA)
At TA = 25°C, AVDD = 5.0 V, DVDD = 3.3 V, AINP = –250 mV to 250 mV, AINN = 0 V, fCLKIN = 20 MHz, and sinc3 filter with
OSR = 256, unless otherwise noted.
7
6
6
5
5
4
4
3
-40
3
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
5
110 125
20
D038
Figure 43. High-Side Supply Current vs Clock Frequency
12
LVDS
CMOS
11
LVDS
CMOS
11
10
9
9
8
8
IDVDD (mA)
10
7
6
5
7
6
5
4
4
3
3
2
2
1
1
4.5
3
3.1
3.2
3.3
DVDD (V)
3.4
3.5
3.6
D039
Figure 44. Controller-Side Supply Current vs
Controller-Side Supply Voltage (3.3 V, nom)
4.6
4.7
4.8
4.9
5
5.1
DVDD (V)
5.2
5.3
5.4
5.5
D040
Figure 45. Controller-Side Supply Current vs
Controller-Side Supply Voltage (5 V, nom)
12
12
LVDS 5 V
LVDS 3.3 V
CMOS 5 V
CMOS 3.3 V
11
10
9
10
9
8
7
6
5
8
7
6
5
4
4
3
3
2
2
1
-40
1
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
D041
Figure 46. Controller-Side Supply Current vs Temperature
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LVDS 5V
LVDS 3.3V
CMOS 5 V
CMOS 3.3 V
11
IDVDD (mA)
IDVDD (mA)
15
fCLKIN (MHz)
Figure 42. High-Side Supply Current vs Temperature
20
10
D037
12
IDVDD (mA)
7
5
10
15
Clock Frequency (MHz)
20
D042
Figure 47. Controller-Side Supply Current vs
Clock Frequency
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8 Detailed Description
8.1 Overview
The differential analog input (AINP and AINN) of the AMC1305 is a fully-differential amplifier feeding the
switched-capacitor input of a second-order delta-sigma (ΔΣ) modulator stage that digitizes the input signal into a
1-bit output stream. The isolated data output (DOUT) of the converter provides a stream of digital ones and zeros
synchronous to the externally-provided clock source at the CLKIN pin with a frequency in the range of 5 MHz to
20.1 MHz. The time average of this serial bit-stream output is proportional to the analog input voltage.
The Functional Block Diagram section shows a detailed block diagram of the AMC1305. The analog input range
is tailored to directly accommodate a voltage drop across a shunt resistor used for current sensing. The SiO2based capacitive isolation barrier supports a high level of magnetic field immunity as described in the application
report ISO72x Digital Isolator Magnetic-Field Immunity (SLLA181A), available for download at www.ti.com. The
external clock input simplifies the synchronization of multiple current-sense channels on the system level. The
extended frequency range of up to 20.1 MHz supports higher performance levels compared to other solutions
available on the market.
8.2 Functional Block Diagram
DVDD
AVDD
TX
BUF
1.25-V
Reference
Receiver
AINN
BUF
AMC1305
AGND
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Isolation Barrier
û -Modulator
+
DOUT
DOUT_N (AMC1305L25 only)
Interface
TX
-
Receiver
BUF
AINP
TX
CLKIN
CLKIN_N (AMC1305L25 only)
TX
DGND
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8.3 Feature Description
8.3.1 Analog Input
The AMC1305 incorporates front-end circuitry that contains a differential amplifier and sampling stage, followed
by a ΔΣ modulator. The gain of the differential amplifier is set by internal precision resistors to a factor of 4 for
devices with a specified input voltage range of ±250 mV (for the AMC1305x25), or to a factor of 20 for devices
with a ±50-mV input voltage range (for the AMC1305M05), resulting in a differential input impedance of 5 kΩ (for
the AMC1305M05) or 25 kΩ (for the AMC1305x25).
Consider the input impedance of the AMC1305 in designs with high-impedance signal sources that can cause
degradation of gain and offset specifications. The importance of this effect, however, depends on the desired
system performance. Additionally, the input bias current caused by the internal common-mode voltage at the
output of the differential amplifier causes an offset that depends on the actual amplitude of the input signal. See
the Isolated Voltage Sensing section for more details on reducing these effects.
There are two restrictions on the analog input signals (AINP and AINN). First, if the input voltage exceeds the
range of AGND – 6 V to AVDD + 0.5 V, the input current must be limited to 10 mA because the device input
electrostatic discharge (ESD) protection diodes turn on. In addition, the linearity and noise performance of the
device are ensured only when the differential analog input voltage remains within the specified linear full-scale
range (FSR), that is ±250 mV (for the AMC1305x25) or ±50 mV (for the AMC1305M05), and within the specified
input common-mode range.
8.3.2 Modulator
The modulator implemented in the AMC1305 is a second-order, switched-capacitor, feed-forward ΔΣ modulator,
such as the one conceptualized in Figure 48. The analog input voltage VIN and the output V5 of the 1-bit digitalto-analog converter (DAC) are differentiated, providing an analog voltage V1 at the input of the first integrator
stage. The output of the first integrator feeds the input of the second integrator stage, resulting in output voltage
V3 that is differentiated with the input signal VIN and the output of the first integrator V2. Depending on the polarity
of the resulting voltage V4, the output of the comparator is changed. In this case, the 1-bit DAC responds on the
next clock pulse by changing its analog output voltage V5, causing the integrators to progress in the opposite
direction while forcing the value of the integrator output to track the average value of the input.
fCLKIN
V1
V2
Integrator 1
VIN
V3
V4
Integrator 2
CMP
0V
V5
DAC
Figure 48. Block Diagram of a Second-Order Modulator
The modulator shifts the quantization noise to high frequencies; see Figure 49. Therefore, use a low-pass digital
filter at the output of the device to increase overall performance. This filter is also used to convert from the 1-bit
data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). TI's microcontroller
family TMS320F2837x offers a suitable programmable, hardwired filter structure termed a sigma-delta filter
module (SDFM) optimized for usage with the AMC1305 family. Also, SD24_B converters on the MSP430F677x
microcontrollers offer a path to directly access the integrated sinc-filters, thus offering a system-level solution for
multichannel isolated current sensing. An additional option is to use a suitable application-specific device (such
as the AMC1210, a four-channel digital sinc-filter). Alternatively, a field-programmable gate array (FPGA) can be
used to implement the digital filter.
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Feature Description (continued)
0
Magnitude (dB)
-20
-40
-60
-80
-100
-120
-140
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Figure 49. Quantization Noise Shaping
8.3.3 Digital Output
A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time. A
differential input of 250 mV (for the AMC1305x25) or 50 mV (for the AMC1305M05) produces a stream of ones
and zeros that are high 90% of the time. A differential input of –250 mV (–50 mV for the AMC1305M05)
produces a stream of ones and zeros that are high 10% of the time. These input voltages are also the specified
linear ranges of the different AMC1305 versions with performance as specified in this document. If the input
voltage value exceeds these ranges, the output of the modulator shows non-linear behavior while the
quantization noise increases. The output of the modulator would clip with a stream of only zeros with an input
less than or equal to –312.5 mV (–62.5 mV for the AMC1305M05) or with a stream of only ones with an input
greater than or equal to 312.5 mV (62.5 mV for the AMC1305M05). In this case, however, the AMC1305
generates a single 1 (if the input is at negative full-scale) or 0 every 128 clock cycles to indicate proper device
function (see the Fail-Safe Output section for more details). The input voltage versus the output modulator signal
is shown in Figure 50.
The density of ones in the output bit-stream for any input voltage value (with the exception of a full-scale input
signal as described in Output Behavior in Case of Full-Scale Input ) can be calculated using Equation 1:
V IN V Clipping
2 * V Clipping
(1)
The AMC1305 system clock is typically 20 MHz and is provided externally at the CLKIN pin. Data are
synchronously provided at 20 MHz at the DOUT pin. Data change at the CLKIN falling edge. For more details,
see the Switching Characteristics table.
Modulator Output
+FS (Analog Input)
-FS (Analog Input)
Analog Input
Figure 50. Analog Input versus AMC1305 Modulator Output
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8.4 Device Functional Modes
8.4.1 Fail-Safe Output
In the case of a missing high-side supply voltage (AVDD), the output of a ΔΣ modulator is not defined and could
cause a system malfunction. In systems with high safety requirements, this behavior is not acceptable.
Therefore, the AMC1305 implements a fail-safe output function that ensures the device maintains its output level
in case of a missing AVDD, as shown in Figure 51.
CLKIN
AVDD
AVDD GOOD
AVDD FAIL
DOUT
Case 1: DOUT = Z1[ ÁZ v s
( ]o•
DOUT
Case 2: DOUT = Z0[ ÁZ v s
( ]o•
Figure 51. Fail-Safe Output of the AMC1305
8.4.2 Output Behavior in Case of Full-Scale Input
If a full-scale input signal is applied to the AMC1305 (that is, VIN ≥ VClipping), the device generates a single one or
zero every 128 bits at DOUT, depending on the actual polarity of the signal being sensed, as shown in Figure 52.
In this way, differentiating between a missing AVDD and a full-scale input signal is possible on the system level.
CLKIN
...
DOUT
DOUT
...
VIN ” 312.5 mV (AMC1305M05: 61.5 mV)
...
...
...
...
VIN • 312.5 mV (AMC1305M05: 61.5 mV)
127 CLKIN cycles
127 CLKIN cycles
Figure 52. Overrange Output of the AMC1305
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Digital Filter Usage
The modulator generates a bit stream that is processed by a digital filter to obtain a digital word similar to a
conversion result of a conventional analog-to-digital converter (ADC). A very simple filter, built with minimal effort
and hardware, is a sinc3-type filter, as shown in Equation 2:
§ 1 z OSR ·
¸
H ( z ) ¨¨
1 ¸
© 1 z ¹
3
(2)
This filter provides the best output performance at the lowest hardware size (count of digital gates) for a secondorder modulator. All the characterization in this document is also done with a sinc3 filter with an over-sampling
ratio (OSR) of 256 and an output word width of 16 bits.
SNR 1.76dB 6.02dB * ENOB
(3)
16
14
ENOB (bits)
12
10
8
6
4
sinc1
sinc2
sinc3
2
0
1
10
100
OSR
1000
D053
Figure 53. Measured Effective Number of Bits versus Oversampling Ratio
An example code for an implementation of a sinc3 filter in an FPGA, see the application note Combining
ADS1202 with FPGA Digital Filter for Current Measurement in Motor Control Applications (SBAA094), available
for download at www.ti.com.
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9.2 Typical Applications
9.2.1 Frequency Inverter Application
Because to their high ac and dc performance, isolated ΔΣ modulators are being widely used in new generation
frequency inverter designs. Frequency inverters are critical parts of industrial motor drives, photovoltaic inverters
(string and central inverters), uninterruptible power supplies (UPS), electrical and hybrid electrical vehicles, and
other industrial applications. The input structure of the AMC1305 is optimized for use with low-impedance shunt
resistors and is therefore tailored for isolated current sensing using shunts.
DC link
Gate Driver
Gate Driver
Gate Driver
RSHUNT
RSHUNT
RSHUNT
Gate Driver
Gate Driver
Gate Driver
AMC1305
5.0 V
3.3 V
TMS320F2837x
AVDD
DVDD
AINP
DOUT
SD-D1
AINN
CLKIN
SD-C1
AGND
DGND
AMC1305
5.0 V
AMC1305
5.0 V
3.3 V
AVDD
DVDD
AINP
DOUT
SD-D2
AINN
CLKIN
SD-C3
AGND
DGND
AMC1305
3.3 V
5.0 V
3.3 V
AVDD
DVDD
AVDD
DVDD
AINP
DOUT
AINP
DOUT
SD-D4
AINN
CLKIN
AINN
CLKIN
SD-C4
AGND
DGND
AGND
DGND
PWMx
SD-D5
SD-C5
Figure 54. The AMC1305 in a Frequency Inverter Application
9.2.1.1 Design Requirements
A typical operation of the device in a frequency inverter application is shown in Figure 54. When the inverter
stage is part of a motor drive system, measurement of the motor phase current is done via the shunt resistors
(RSHUNT). Depending on the system design, either all three or only two phase currents are sensed.
In this example, an additional fourth AMC1305 is used to support isolated voltage sensing of the dc link. This
high voltage is reduced using a high-impedance resistive divider before being sensed by the device across a
smaller resistor. The value of this resistor can degrade the performance of the measurement, as described in the
Isolated Voltage Sensing section.
9.2.1.2 Detailed Design Procedure
The usually recommended RC filter in front of a ΔΣ modulator to improve signal-to-noise performance of the
signal path, is not required for the AMC1305. By design, the input bandwidth of the analog front-end of the
device is limited to 1 MHz.
For modulator output bit-stream filtering, a device from TI's TMS320F2837x family of dual-core MCUs is
recommended. This family supports up to eight channels of dedicated hardwired filter structures that significantly
simplify system level design by offering two filtering paths per channel: one providing high accuracy results for
the control loop and one fast response path for overcurrent detection.
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Typical Applications (continued)
9.2.1.3 Application Curve
In motor control applications, a very fast response time for overcurrent detection is required. The time for fully
settling the filter in case of a step-signal at the input of the modulator depends on its order; that is, a sinc3 filter
requires three data updates for full settling (with fDATA = fCLK / OSR). Therefore, for overcurrent protection, filter
types other than sinc3 can be a better choice; an alternative is the sinc2 filter. Figure 55 compares the settling
times of different filter orders.
16
14
ENOB (bits)
12
10
8
6
4
sinc1
sinc2
sinc3
2
0
0
2
4
6
8
10
12
settling time (µs)
14
16
18
20
D054
Figure 55. Measured Effective Number of Bits versus Settling Time
The delay time of the sinc filter with a continuous signal is half of its settling time.
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Typical Applications (continued)
9.2.2 Isolated Voltage Sensing
The AMC1305 is optimized for usage in current-sensing applications using low-impedance shunts. However, the
device can also be used in isolated voltage-sensing applications if the impact of the (usually higher) impedance
of the resistor used in this case is considered.
High voltage
potential
5V
R1
AMC1305
AVDD
R2
AINP
R4
IIB
RID
R3
R5
û -Modulator
+
AINN
R3'
R4'
R5'
AGND
VCM = 2 V
GND
Figure 56. Using AMC1305 for Isolated Voltage Sensing
9.2.2.1
Design Requirements
Figure 56 shows a simplified circuit typically used in high-voltage sensing applications. The high impedance
resistors (R1 and R2) are used as voltage dividers and dominate the current value definition. The resistance of
the sensing resistor R3 is chosen to meet the input voltage range of the AMC1305. This resistor and the
differential input impedance of the device (the AMC1305x25 is 25 kΩ, the AMC1305M05 is 5 kΩ) also create a
voltage divider that results in an additional gain error. With the assumption of R1, R2, and RIN having a
considerably higher value than R3, the resulting total gain error can be estimated using Equation 4, with EG
being the gain error of the AMC1305.
R3
E Gtot
EG
R IN
(4)
This gain error can be easily minimized during the initial system level gain calibration procedure.
9.2.2.2 Detailed Design Procedure
As indicated in Figure 56, the output of the integrated differential amplifier is internally biased to a common-mode
voltage of 2 V. This voltage results in a bias current IIB through the resistive network R4 and R5 (or R4' and R5')
used for setting the gain of the amplifier. The value range of this current is specified in the Electrical
Characteristics table. This bias current generates additional offset error that depends on the value of the resistor
R3. Because the value of this bias current depends on the actual common-mode amplitude of the input signal (as
shown in Figure 57), the initial system offset calibration does not minimize its effect. Therefore, in systems with
high accuracy requirements TI recommends using a series resistor at the negative input (AINN) of the AMC1305
with a value equal to the shunt resistor R3 (that is R3' = R3 in Figure 56) to eliminate the effect of the bias
current.
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Typical Applications (continued)
This additional series resistor (R3') influences the gain error of the circuit. The effect can be calculated using
Equation 5 with R5 = R5' = 50 kΩ and R4 = R4' = 2.5 kΩ (for the AMC1305M05) or 12.5 kΩ (for the
AMC1305x25).
R4 ·
§
EG (%) ¨1
¸ * 100 %
R 4' R 3' ¹
©
(5)
9.2.2.3 Application Curve
Figure 57 shows the dependency of the input bias current on the common-mode voltage at the input of the
AMC1305.
60
40
IIB (PA)
20
0
-20
-40
-60
-80
-0.5
1305x25
1305M05
0
0.5
1
1.5
VCM (V)
2
2.5
3
D001
Figure 57. Input Current vs Input Common-Mode Voltage
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10 Power Supply Recommendations
In a typical frequency inverter application, the high-side power supply (AVDD) for the device is derived from the
floating power supply of the upper gate driver. For lowest cost, a Zener diode can be used to limit the voltage to
5 V ±10%. Alternatively a low-cost low-drop regulator (LDO), for example the LM317-N, can be used to minimize
noise on the power supply. A low-ESR decoupling capacitor of 0.1 µF is recommended for filtering this powersupply path. Place this capacitor (C2 in Figure 58) as close as possible to the AVDD pin of the AMC1305 for best
performance. If better filtering is required, an additional 10-µF capacitor can be used. The floating ground
reference (AGND) is derived from the end of the shunt resistor, which is connected to the negative input (AINN)
of the device. If a four-pin shunt is used, the device inputs are connected to the inner leads, while AGND is
connected to one of the outer leads of the shunt.
For decoupling of the digital power supply on controller side, TI recommends using a 0.1-µF capacitor assembled
as close to the DVDD pin of the AMC1305 as possible, followed by an additional capacitor in the range of 1 µF to
10 µF.
HV+
Floating
Power Supply
20 V
R1
800
Gate Driver
Z1
1N751A
C1
10 F
AMC1305
5.1 V
AVDD
DVDD
3.3 V, or 5.0 V
C4
0.1 F
C2
0.1 F
C5
2.2 F
AGND
DGND
AINN
DOUT
SD-Dx
AINP
CLKIN
SD-Cx
RSHUNT
to load
TMS320F2837x
PWMx
Gate Driver
HV-
Figure 58. Zener-Diode-Based High-Side Power Supply
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11 Layout
11.1 Layout Guidelines
A layout recommendation showing the critical placement of the decoupling capacitors (as close as possible to the
AMC1305) and placement of the other components required by the device is shown in Figure 59.
For the AMC1305L25 version, place the 100-Ω termination resistor as close as possible to the CLKIN, CLKIN_N
inputs of the device to achieve highest signal integrity. If not integrated, an additional termination resistor is
required as close as possible to the LVDS data inputs of the MCU or filter device; see Figure 60.
11.2 Layout Examples
Top View
Clearance area
to be kept free of any
conductive materials
NC
1
16
DGND
0.1 µF
AINP
NC
AINN
DVDD
AGND
CLKIN
From shunt
resistor
SMD
0603
AMC1305Mxx
LEGEND
NC
NC
NC
DOUT
AVDD
NC
AGND
DGND
to/from
MCU
(filter)
TOP layer:
copper pour & traces
0.1 µF
high-side area
controller-side area
SMD
0603
via to ground plane
via to supply plane
Figure 59. Recommended Layout of the AMC1305Mx
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Layout Examples (continued)
Top View
Clearance area
to be kept free of any
conductive materials
NC
1
16
DGND
0.1 µF
AINP
NC
AINN
DVDD
AGND
CLKIN
From shunt
resistor
AMC1305L25
NC
CLKIN_N
SMD
0603
100 :
SMD
0603
to/from
MCU
(filter)
LEGEND
NC
DOUT
AVDD
DOUT_N
AGND
DGND
TOP layer:
copper pour & traces
high-side area
controller-side area
0.1 µF
SMD
0603
100 :
SMD
0603
via to ground plane
via to supply plane
Figure 60. Recommended Layout of the AMC1305L25
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Isolation Glossary application report
• Texas Instruments, ISO72x Digital Isolator Magnetic-Field Immunity application report
• Texas Instruments, Combining ADS1202 with FPGA Digital Filter for Current Measurement in Motor Control
Applications application report
• Texas Instruments, LM117, LM317-N Wide Temperature Three-Pin Adjustable Regulator data sheet
• Texas Instruments, TMS320F2837xD Dual-Core Delfino™ Microcontrollers data sheet
• Texas Instruments, MSP430F677x Polyphase Metering SoCs data sheet
• Texas Instruments, AMC1210 Quad Digital Filter for 2nd-Order Delta-Sigma Modulator data sheet
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 1. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
AMC1305L25
Click here
Click here
Click here
Click here
Click here
AMC1305M05
Click here
Click here
Click here
Click here
Click here
AMC1305M25
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12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2014–2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AMC1305L25 AMC1305M05 AMC1305M25
33
AMC1305L25, AMC1305M05, AMC1305M25
SBAS654G – JUNE 2014 – REVISED JANUARY 2020
www.ti.com
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
34
Submit Documentation Feedback
Copyright © 2014–2020, Texas Instruments Incorporated
Product Folder Links: AMC1305L25 AMC1305M05 AMC1305M25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
AMC1305L25DW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
AMC1305L25
AMC1305L25DWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
AMC1305L25
AMC1305M05DW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
AMC1305M05
AMC1305M05DWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
AMC1305M05
AMC1305M25DW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
AMC1305M25
AMC1305M25DWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
AMC1305M25
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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