AMC1350-Q1
SBASAB0 – DECEMBER 2021
AMC1350-Q1 Automotive, Precision, ±5-V Input, Reinforced Isolated Amplifier
1 Features
3 Description
•
The AMC1350-Q1 is a precision, isolated amplifier
with an output separated from the input circuitry
by an isolation barrier that is highly resistant to
magnetic interference. This barrier is certified to
provide reinforced galvanic isolation of up to 5 kVRMS
according to VDE V 0884-11 and UL1577, and
supports a working voltage of up to 1.5 kVRMS.
•
•
•
•
•
•
•
•
•
AEC-Q100 qualified for automotive applications:
– Temperature grade 1: –40°C to +125°C, TA
Functional Safety-Capable
– Documentation available to aid functional safety
system design
Linear input voltage range: ±5 V
High input impedance: 1.25 MΩ (typ)
Fixed gain: 0.4 V/V
Low DC errors:
– Offset error ±1.5 mV (max)
– Offset drift: ±15 μV/°C (max)
– Gain error: ±0.2% (max)
– Gain drift: ±35 ppm/°C (max)
– Nonlinearity ±0.02% (max)
Operation on high-side and low-side: 3.3 V or 5 V
High CMTI: 100 kV/μs (min)
Fail-safe output
Safety-related certifications:
– 7070-VPK reinforced isolation per DIN VDE V
0884-11: 2017-01
– 5000-VRMS isolation for 1 minute per UL1577
2 Applications
•
Isolated voltage sensing in:
– Traction inverters
– Onboard chargers
– DC/DC converters
– HEV/EV DC chargers
The isolation barrier separates parts of the system
that operate on different common-mode voltage levels
and protects the low-voltage side from potentially
harmful voltages and damage.
The high-impedance input of the AMC1350-Q1 is
optimized for connection to high-impedance resistive
dividers or other voltage signal sources with high
output resistance. The excellent accuracy and low
temperature drift supports accurate AC and DC
voltage sensing in onboard chargers (OBC), DC/DC
converters, traction inverters, or other applications
that must support high common-mode voltages.
The AMC1350-Q1 is offered in a wide-body 8pin SOIC package and is AEC-Q100 qualified for
automotive applications and supports the temperature
range from –40°C to +125°C
Device Information(1)
PART NUMBER
AMC1350-Q1
(1)
High-side supply
(3.3 V or 5 V)
PACKAGE
SOIC (8)
BODY SIZE (NOM)
5.85 mm × 7.50 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Low-side supply
(3.3 V or 5 V)
VAC
INP
+5.0 V
0V
–5.0 V
INN
GND1
AMC1350-Q1
Reinforced Isolation
VDD1
VDD2
OUTP
VCMout
±2 V
ADC
OUTN
GND2
Typical Application
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AMC1350-Q1
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Power Ratings.............................................................5
6.6 Insulation Specifications............................................. 6
6.7 Safety-Related Certifications...................................... 7
6.8 Safety Limiting Values.................................................7
6.9 Electrical Characteristics.............................................8
6.10 Switching Characteristics........................................10
6.11 Timing Diagram....................................................... 10
6.12 Insulation Characteristics Curves............................11
6.13 Typical Characteristics............................................ 12
7 Detailed Description......................................................19
7.1 Overview................................................................... 19
7.2 Functional Block Diagram......................................... 19
7.3 Feature Description...................................................19
7.4 Device Functional Modes..........................................21
8 Application and Implementation.................................. 22
8.1 Application Information............................................. 22
8.2 Typical Application.................................................... 22
8.3 What To Do and What Not To Do..............................27
9 Power Supply Recommendations................................27
10 Layout...........................................................................28
10.1 Layout Guidelines................................................... 28
10.2 Layout Example...................................................... 28
11 Device and Documentation Support..........................29
11.1 Documentation Support.......................................... 29
11.2 Receiving Notification of Documentation Updates.. 29
11.3 Support Resources................................................. 29
11.4 Trademarks............................................................. 29
11.5 Electrostatic Discharge Caution.............................. 29
11.6 Glossary.................................................................. 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
December 2021
2
REVISION
*
NOTES
Initial Release
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5 Pin Configuration and Functions
VDD1
1
8
VDD2
INP
2
7
OUTP
INN
3
6
OUTN
GND1
4
5
GND2
Not to scale
Figure 5-1. DWV Package, 8-Pin SOIC, Top View
Table 5-1. Pin Functions
PIN
NO.
NAME
TYPE
DESCRIPTION
High-side power supply(1)
1
VDD1
High-side power
2
INP
Analog input
Noninverting analog input. Either INP or INN must have a DC current path to GND1
to define the common-mode input voltage.(2)
3
INN
Analog input
Inverting analog input. Either INP or INN must have a DC current path to GND1 to
define the common-mode input voltage.(2)
4
GND1
High-side ground
High-side analog ground
5
GND2
Low-side ground
Low-side analog ground
6
OUTN
Analog output
Inverting analog output
7
OUTP
Analog output
Noninverting analog output
8
VDD2
Low-side power
(1)
(2)
Low-side power supply(1)
See the Power Supply Recommendations section for power-supply decoupling recommendations.
See the Layout section for details.
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6 Specifications
6.1 Absolute Maximum Ratings
see(1)
Power-supply voltage
MIN
MAX
High-side VDD1 to GND1
–0.3
6.5
Low-side VDD2 to GND2
–0.3
6.5
Analog input voltage
INP, INN
Analog output voltage
OUTP, OUTN
Input current
Continuous, any pin except power-supply pins
Temperature
(1)
V
–15
15
V
GND2 – 0.5
VDD2 + 0.5
V
–10
10
Junction, TJ
150
Storage, Tstg
UNIT
–65
150
mA
°C
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC
HBM ESD classification level 2
Q100-002(1),
UNIT
±2000
V
Charged-device model (CDM), per AEC Q100-011,
CDM ESD classification level C6
±1000
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
VDD1
High-side power-supply
VDD1 to GND1
3
5
5.5
V
VDD2
Low-side power-supply
VDD2 to GND2
3
3.3
5.5
V
ANALOG INPUT
VClipping
Input voltage before clipping output
VIN = VINP – VINN
VFSR
Specified linear full-scale voltage
VIN = VINP – VINN
VCM
Operating common-mode input voltage
±6.25
V
–5
5
V
–4
4
V
ANALOG OUTPUT
CLOAD
Capacitive load
RLOAD
Resistive load
On OUTP or OUTN to GND2
500
OUTP to OUTN
250
On OUTP or OUTN to GND2
10
pF
1
kΩ
125
°C
TEMPERATURE RANGE
TA
4
Specified ambient temperature
–40
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6.4 Thermal Information
AMC1350-Q1
THERMAL
METRIC(1)
DWV (SOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
84.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
28.3
°C/W
RθJB
Junction-to-board thermal resistance
41.1
°C/W
ψJT
Junction-to-top characterization parameter
4.9
°C/W
ψJB
Junction-to-board characterization parameter
39.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
PD
Maximum power dissipation (both sides)
PD1
Maximum power dissipation (high-side)
PD2
Maximum power dissipation (low-side)
VALUE
UNIT
VDD1 = VDD2 = 5.5 V
TEST CONDITIONS
96
mW
VDD1 = 3.6 V
29
VDD1 = 5.5 V
51
VDD2 = 3.6 V
26
VDD2 = 5.5 V
45
mW
mW
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6.6 Insulation Specifications
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
CLR
External clearance(1)
Shortest pin-to-pin distance through air
≥ 8.5
mm
CPG
External creepage(1)
Shortest pin-to-pin distance across the package surface
≥ 8.5
mm
DTI
Distance through insulation
Minimum internal gap (internal clearance) of the double
insulation
≥ 0.021
mm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
≥ 600
V
Material group
According to IEC 60664-1
Overvoltage category
per IEC 60664-1
Rated mains voltage ≤ 600 VRMS
I-IV
Rated mains voltage ≤ 1000 VRMS
I-III
I
DIN VDE V 0884-11 (VDE V 0884-11): 2017-01
VIORM
Maximum repetitive peak
isolation voltage
VIOWM
At AC voltage
2120
VPK
Maximum-rated isolation
working voltage
At AC voltage (sine wave)
1500
VRMS
At DC voltage
2120
VDC
VIOTM
Maximum transient
isolation voltage
VTEST = VIOTM, t = 60 s (qualification test)
7070
VTEST = 1.2 × VIOTM, t = 1 s (100% production test)
8480
VIOSM
Maximum surge
isolation voltage(2)
Test method per IEC 60065, 1.2/50-µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
8000
Apparent charge(3)
qpd
CIO
Barrier capacitance,
input to output(4)
RIO
Insulation resistance,
input to output(4)
Method a, after input/output safety test subgroups 2 and 3,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 × VIORM, tm = 10 s
≤5
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.6 × VIORM, tm = 10 s
≤5
Method b1, at routine test (100% production) and
preconditioning (type test), Vini = VIOTM, tini = 1 s, Vpd(m) = 1.875
× VIORM, tm = 1 s
≤5
VIO = 0.5 VPP at 1 MHz
~1.5
VIO = 500 V at TA = 25°C
> 1012
VIO = 500 V at 100°C ≤ TA ≤ 125°C
> 1011
VIO = 500 V at TS = 150°C
>
VPK
VPK
pC
pF
Ω
109
Pollution degree
2
Climatic category
55/125/21
UL1577
VISO
(1)
(2)
(3)
(4)
6
Withstand isolation voltage
VTEST = VISO = 5000 VRMS or 7071 VDC, t = 60 s (qualification),
VTEST = 1.2 × VISO = 6000 VRMS, t = 1 s (100% production test)
5000
VRMS
Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the
printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques
such as inserting grooves, ribs, or both on a PCB are used to help increase these specifications.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier are tied together, creating a two-pin device.
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6.7 Safety-Related Certifications
VDE
UL
Certified according to DIN VDE V 0884-11 (VDE V 0884-11):
2017-01,
DIN EN 60950-1 (VDE 0805 Teil 1): 2014-08, and
DIN EN 60065 (VDE 0860): 2005-11
Recognized under 1577 component recognition
Reinforced insulation
Single protection
Certificate number: pending
File number: E181974
6.8 Safety Limiting Values
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A
failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to
over-heat the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
IS
Safety input, output, or supply current
PS
Safety input, output, or total power
TS
Maximum safety temperature
(1)
TEST CONDITIONS
MIN
TYP
MAX
RθJA = 84.6°C/W, VDDx = 5.5 V,
TJ = 150°C, TA = 25°C
270
RθJA = 84.6°C/W, VDDx = 3.6 V,
TJ = 150°C, TA = 25°C
410
RθJA = 84.6°C/W, TJ = 150°C, TA = 25°C
UNIT
mA
1480
mW
150
°C
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These
limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature.
PS = IS × VDDmax, where VDDmax is the maximum supply voltage for high-side and low-side.
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6.9 Electrical Characteristics
minimum and maximum specifications apply from TA = –40°C to +125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, INP
= –5 V to +5 V, and INN = GND1 (unless otherwise noted); typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 =
3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
TA = 25°C, INN = INP = GND1,
4.5 V ≤ VDD1 ≤ 5.5 V(1)
–1.5
±0.3
1.5
TA = 25°C, INN = INP = GND1,
3.0 V ≤ VDD1 ≤ 5.5 V(3)
–2.5
–0.8
2.5
UNIT
ANALOG INPUT
Offset voltage(2)
VOS
ΔVOS
Offset voltage long-term stability
drift(5)
TCVOS
Offset voltage thermal
ΔTCVOS
Offset voltage thermal drift
long-term stability
0(7)
10 years at TA = 55℃
INN = INP = GND1
–15
10 years at TA = 55℃,
INN = INP = GND1
Input resistance, differential
RIN
mV
±3
mV
15
0(7)
µV/°C
mV/°C
2
2.5
3
1
1.25
1.5
MΩ
Input resistance, single ended
INN = GND1
ΔRIN
Input resistance long-term stability
10 years at TA = 55℃
TCRIN
Input resistance thermal drift
–40℃ ≤ TA ≤ 85℃
5
ppm/°C
CIN
Single-ended input capacitance
INN = HGND, fIN = 275 kHz
4
pF
CIND
Differential input capacitance
fIN = 275 kHz
2
pF
0.40
V/V
0(7)
ppm
ANALOG OUTPUT
Nominal gain
error(1)
EG
Gain
ΔEG
Gain error long-term stability
TA = 25℃
TCEG
Gain error thermal drift(1) (6)
ΔTCEG
Gain error thermal drift
long-term stability
–0.2%
–35
10 years at TA = 55℃
Nonlineartity(1)
–0.02%
Nonlinearity thermal drift
Total harmonic distortion(4)
THD
SNR
Signal-to-noise ratio
PSRR
VCMout
8
Common-mode rejection ratio
Power-supply rejection
81
ratio(2)
±10
35 ppm/°C
0(7)
ppm/°C
±0.003%
ppm/°C
–87
dB
85
75
250
DC, INN = INP, VCM min ≤ VCM ≤ VCM max
–72
fIN = 10 kHz, INN = INP = 10 VPP
–71
PSRR vs VDD1, DC
–67
PSRR vs VDD2, DC
–80
PSRR vs VDD1 with 10-kHz,
100-mV ripple
–65
PSRR vs VDD2 with 10-kHz,
100-mV ripple
–64
1.39
VCLIPout
Clipping differential output voltage
VOUT = (VOUTP – VOUTN),
VIN > VClipping
VFail-safe
Fail-safe differential output voltage
VDD1 undervoltage or VDD1 missing
BW
Output bandwidth
ROUT
Output resistance
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1.44
µVrms
dB
dB
1.49
2.49
–2.57
275
On OUTP or OUTN
0.02%
0.2
INN = INP = GND1, BW = 100 kHz
Output common-mode voltage
0.2%
dB
VIN = 10 VPP, fIN = 10 kHz,
BW = 100 kHz
Output noise
CMRR
VIN = 10 VPP, fIN = 10 kHz,
BW = 100 kHz
VIN = 10 VPP, fIN = 1 kHz,
BW = 10 kHz
±0.05%
0(7)
10 years at TA = 55℃
V
V
–2.5
V
300
kHz
< 0.2
Ω
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6.9 Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, INP
= –5 V to +5 V, and INN = GND1 (unless otherwise noted); typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 =
3.3 V
PARAMETER
Output short-circuit current
CMTI
TEST CONDITIONS
MIN
On OUTP or OUTN, sourcing or sinking,
INN = INP = GND1, outputs shorted to
either GND or VDD2
Common-mode transient immunity
TYP
MAX
UNIT
14
mA
100
150
kV/µs
POWER SUPPLY
VDD1UV
VDD1 undervoltage detection
threshold
VDD1 rising
2.5
2.7
2.9
VDD1 falling
2.4
2.6
2.8
VDD2UV
VDD2 undervoltage detection
threshold
VDD2 rising
2.2
2.45
2.65
VDD2 falling
1.85
2.0
2.2
IDD1
High-side supply current
3.0 V < VDD1 < 3.6 V
6.0
8.1
4.5 V < VDD1 < 5.5 V
7.0
9.3
IDD2
Low-side supply current
3.0 V < VDD2 < 3.6 V
5.3
7.2
4.5 V < VDD2 < 5.5 V
5.9
8.1
(1)
(2)
(3)
(4)
(5)
(6)
(7)
V
V
mA
mA
The typical value includes one standard deviation (sigma) at nominal operating conditions.
This parameter is input referred.
The typical value is at VDD1 = 3.3 V.
THD is the ratio of the rms sum of the amplitues of first five higher harmonics to the amplitude of the fundamental.
Offset error temperature drift is calculated using the box method, as described by the following equation:
TCVOS = (VOS,MAX - VOS,MIN) / TempRange where VOS,MAX and VOS,MIN refer to the maximum and minimum VOS values measured
within the temperature range (–40 to 125℃).
Gain error temperature drift is calculated using the box method, as described by the following equation:
TCEG (ppm) = ((EG,MAX - EG,MIN) / TempRange) x 104 where EG,MAX and EG,MIN refer to the maximum and minimum EG values (in %)
measured within the temperature range (–40 to 125℃).
Value is below measurement capability.
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6.10 Switching Characteristics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
tr
Output signal rise time
tf
Output signal fall time
tAS
TEST CONDITIONS
MIN
TYP
MAX
1.3
UNIT
µs
1.3
µs
IN to OUTx signal delay (50% – 10%)
Unfiltered output
1
1.5
µs
IN to OUTx signal delay (50% – 50%)
Unfiltered output
1.6
2.1
µs
IN to OUTx signal delay (50% – 90%)
Unfiltered output
2.5
3
µs
Analog settling time
VDD1 step to 3.0 V with VDD2 ≥ 3.0 V, to
VOUTP and VOUTN valid, 0.1% settling
500
800
µs
6.11 Timing Diagram
5V
INP - INN
0
–5V
tf
tr
OUTN
VCMout
OUTP
50% - 10%
50% - 50%
50% - 90%
Figure 6-1. Rise, Fall, and Delay Time Definition
10
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6.12 Insulation Characteristics Curves
600
1800
VDD1 = VDD2 = 3.6 V
VDD1 = VDD2 = 5.5 V
500
1600
1400
1200
PS (mW)
IS (mA)
400
300
1000
800
600
200
400
100
200
0
0
0
25
50
75
TA (°C)
100
125
150
0
25
50
D069
Figure 6-2. Thermal Derating Curve for Safety-Limiting Current
per VDE
75
TA (°C)
100
125
150
D070
Figure 6-3. Thermal Derating Curve for Safety-Limiting Power
per VDE
TA up to 150°C, stress-voltage frequency = 60 Hz, isolation working voltage = 1500 VRMS, operating lifetime = 135 years
Figure 6-4. Reinforced Isolation Capacitor Lifetime Projection
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6.13 Typical Characteristics
at VDD1 = 5 V, VDD2 = 3.3 V, INN = GND1, INP = –5 V to 5 V, and fIN = 10 kHz (unless otherwise noted)
3
Total Uncalibrated Output Error (%)
0.1
2.5
VOUTx(V)
2
VOUTP
VOUTN
1.5
1
0.5
0
-7
-6
-5
-4
-3
-2 -1 0
1
2
(VINP - VINN) (V)
3
4
5
6
D006
0.02
0
-0.02
-0.04
-0.06
-0.08
-6
-4
-2
0
2
(VINP - VINN) (V)
4
6
8
D074
Figure 6-6. Total Uncalibrated Output Error vs Input Voltage
2.5
Device 1
Device 2
Device 3
2
1.5
1.5
1
1
0.5
0.5
0
-0.5
0
-0.5
-1
-1
-1.5
-1.5
-2
-2
-2.5
-2.5
3
3.5
4
4.5
VDD1 (V)
5
3
5.5
3.5
4
D027
Figure 6-7. Input Offset Voltage vs High-Side Supply Voltage
4.5
VDD2 (V)
5
5.5
D027b
Figure 6-8. Input Offset Voltage vs Low-Side Supply Voltage
2.5
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-25
-10
5
20
35
50
65
Temperature (°C)
80
95
110 125
Differential Input Impedance (M)
2.5
Device 1
Device 2
Device 3
2
-2.5
-40
Device 1
Device 2
Device 3
2
VOS (mV)
VOS (mV)
0.04
Total uncalibrated output error is defined as:
(VOUT – VIN × G) / (VClipping × G) where VIN = (VINP – VINN),
G is the nominal gain of the device (0.4 V/V),
and VClipping is 6.25 V
2.5
VOS (mV)
0.06
TA = -40 C
TA = 25 C
TA = 125 C
-0.1
-8
7
Figure 6-5. Output Voltage vs Input Voltage
2.48
2.46
2.44
2.42
2.4
-40
-25
D026
Figure 6-9. Input Offset Voltage vs Temperature
12
0.08
-10
5
20
35
50
65
Temperature (°C)
80
95
110 125
D072
Figure 6-10. Differential Input Impedance vs Temperature
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, INN = GND1, INP = –5 V to 5 V, and fIN = 10 kHz (unless otherwise noted)
0.3
0.1
1.23
1.22
0
-0.1
1.21
-0.2
1.2
-40
-25
-10
5
20
35
50
65
Temperature (°C)
80
95
-0.3
110 125
3
3.5
4.5
VDD1 (V)
5
5.5
D020
Figure 6-12. Gain Error vs High-Side Supply Voltage
0.3
0.3
Device 1
Device 2
Device 3
0.2
Device 1
Device 2
Device 3
0.2
0.1
EG (%)
0.1
0
0
-0.1
-0.1
-0.2
-0.2
-0.3
3
3.5
4
4.5
VDD2 (V)
5
-0.3
-40
5.5
-10
5
20
35
50
65
Temperature (°C)
80
95
110 125
D021
Figure 6-14. Gain Error vs Temperature
0.02
0.015
0.015
0.01
0.01
Nonlinearity (%)
0.02
0.005
0
-0.005
Device 1
Device 2
Device 3
0.005
0
-0.005
-0.01
-0.01
-0.015
-0.015
-0.02
-5
-25
D020b
Figure 6-13. Gain Error vs Low-Side Supply Voltage
Nonlinearity (%)
4
D073
Figure 6-11. Single-Ended Input Impedance vs Temperature
EG (%)
Device 1
Device 2
Device 3
0.2
1.24
EG (%)
Single-Ended Input Impedance (M)
1.25
-0.02
-4
-3
-2
-1
0
1
(VINP - VINN) (V)
2
3
4
5
3
D028
Figure 6-15. Nonlinearity vs Input Voltage
3.5
4
4.5
VDD1 (V)
5
5.5
D029
Figure 6-16. Nonlinearity vs High-Side Supply Voltage
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, INN = GND1, INP = –5 V to 5 V, and fIN = 10 kHz (unless otherwise noted)
0.02
Device 1
Device 2
Device 3
0.015
Nonlinearity (%)
0.01
0.005
0
-0.005
-0.01
-0.015
-0.02
3
3.5
4
4.5
VDD2 (V)
5
5.5
D029b
Figure 6-17. Nonlinearity vs Low-Side Supply Voltage
Figure 6-18. Nonlinearity vs Temperature
-70
-70
Device 1
Device 2
Device 3
-75
-80
-80
THD (dB)
THD (dB)
Device 1
Device 2
Device 3
-75
-85
-85
-90
-90
-95
-95
-100
-100
0
0.5
1
1.5
2
2.5 3 3.5 4
|VINP - VINN| (V)
4.5
5
5.5
6
6.5
3
D049
Figure 6-19. Total Harmonic Distortion vs Input Voltage
3.5
4
4.5
VDD1 (V)
5
5.5
D056
Figure 6-20. Total Harmonic Distortion vs High-Side Supply
Voltage
-70
Device 1
Device 2
Device 3
-75
THD (dB)
-80
-85
-90
-95
-100
3
3.5
4
4.5
VDD2 (V)
5
5.5
D056b
Figure 6-21. Total Harmonic Distortion vs Low-Side Supply
Voltage
14
Figure 6-22. Total Harmonic Distortion vs Temperature
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, INN = GND1, INP = –5 V to 5 V, and fIN = 10 kHz (unless otherwise noted)
80
Device 1
Device 2
Device 3
75
SNR (dB)
70
65
60
55
50
45
40
0
0.5
1
1.5
2
2.5 3 3.5 4
|VINP - VINN| (V)
4.5
5
5.5
6
6.5
D032
Figure 6-24. Signal-to-Noise Ratio vs High-Side Supply Voltage
Figure 6-23. Signal-to-Noise Ratio vs Input Voltage
80
80
Device 1
Device 2
Device 3
79
78
77
77
76
76
SNR (dB)
SNR (dB)
78
75
74
74
73
72
72
71
71
70
3.5
4
4.5
VDD2 (V)
5
70
-40
5.5
-25
-10
D034b
Figure 6-25. Signal-to-Noise Ratio vs Low-Side Supply Voltage
5
20
35
50
65
Temperature (°C)
80
95
110 125
D035
Figure 6-26. Signal-to-Noise Ratio vs Temperature
-66
1000
Device 1
Device 2
Device 3
-68
100
CMRR (dB)
Noise Density (V/Hz)
75
73
3
Device 1
Device 2
Device 3
79
10
-70
-72
1
-74
0.1
0.1
1
10
Frequency (kHz)
100
1000
D017
Figure 6-27. Input-Referred Noise Density vs Frequency
-76
3
3.5
4
4.5
VDD1 (V)
5
5.5
D037
Figure 6-28. Common-Mode Rejection Ratio vs Supply Voltage
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, INN = GND1, INP = –5 V to 5 V, and fIN = 10 kHz (unless otherwise noted)
-66
0
Device 1
Device 2
Device 3
-40
-68
CMRR (dB)
CMRR (dB)
-20
-60
Device 1
Device 2
Device 3
-80
-70
-72
-74
-100
0.01
0.1
1
10
100
fIN (kHz)
-76
-40
1000
-25
-10
5
D038
20 35 50 65
Temperature (°C)
80
95
110 125
D039
fIN = 10 kHz
Figure 6-29. Common-Mode Rejection Ratio vs Input Frequency
Figure 6-30. Common-Mode Rejection Ratio vs Temperature
0
0
-20
-20
-40
-40
PSRR (dB)
PSRR (dB)
VDD1
VDD2
-60
-80
-60
-80
VDD1
VDD2
-100
0.01
0.1
1
10
Ripple Frequency (kHz)
100
-100
-40
1000
-25
-10
5
D041
20
35
50
65
Temperature (°C)
80
95
110 125
D042
fRipple = 10 kHz
1.49
1.48
1.48
1.47
1.47
1.46
1.46
1.45
1.45
1.44
1.43
1.44
1.43
1.42
1.42
1.41
1.41
1.4
1.4
1.39
3
3.5
4
4.5
VDD2 (V)
5
5.5
1.39
-40
-25
D009
Figure 6-33. Common-Mode Output Voltage vs Supply Voltage
16
Figure 6-32. Power-Supply Rejection Ratio vs Temperature
1.49
VCMout (V)
VCMout (V)
Figure 6-31. Power-Supply Rejection Ratio vs Ripple Frequency
-10
5
20
35
50
65
Temperature (°C)
80
95
110 125
D010
Figure 6-34. Common-Mode Output Voltage vs Temperature
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6.13 Typical Characteristics (continued)
5
0°
0
-45°
-5
-90°
-10
Output Phase
Normalized Gain (dB)
at VDD1 = 5 V, VDD2 = 3.3 V, INN = GND1, INP = –5 V to 5 V, and fIN = 10 kHz (unless otherwise noted)
-15
-20
-25
-135°
-180°
-225°
-270°
-30
-315°
-35
-360°
-40
1
10
100
1
1000
fIN (kHz)
10
100
1000
fIN (kHz)
D008
D007
Figure 6-36. Output Phase vs Input Frequency
Figure 6-35. Normalized Gain vs Input Frequency
320
320
Device 1
Device 2
Device 3
Device 1
Device 2
Device 3
310
BW (kHz)
BW (kHz)
310
300
300
290
290
280
-40
280
3
3.5
4
4.5
VDD1 (V)
5
5.5
Figure 6-37. Bandwidth vs Supply Voltage
-10
5
20 35 50
65
Temperature (°C)
80
95
110 125
D012
Figure 6-38. Bandwidth vs Temperature
8
8
7.5
7.5
7
7
6.5
6.5
IDDx (mA)
IDDx (mA)
-25
D011
6
5.5
5
6
5.5
5
4.5
IDD1 vs VDD1
IDD2 vs VDD2
4
3
3.5
4
4.5
VDDx (V)
5
5.5
4.5
4
-40
IDD1
IDD2
-25
D043
Figure 6-39. Supply Current vs Supply Voltage
-10
5
20
35
50
65
Temperature (°C)
80
95
110 125
D044
Figure 6-40. Supply Current vs Temperature
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6.13 Typical Characteristics (continued)
3
3
2.5
2.5
2
2
tr/tf (s)
tr / tf (s)
at VDD1 = 5 V, VDD2 = 3.3 V, INN = GND1, INP = –5 V to 5 V, and fIN = 10 kHz (unless otherwise noted)
1.5
1
1
0.5
0.5
0
3
3.5
4
4.5
VDD2 (V)
5
0
-40
5.5
-10
5
20
35
50
65
Temperature (°C)
80
95
110 125
D066
Figure 6-42. Output Rise and Fall Time vs Temperature
3.8
3.8
50% - 90%
50% - 50%
50% - 10%
3.4
2.6
2.2
1.8
1.4
3
2.6
2.2
1.8
1.4
1
1
0.6
0.6
0.2
3
3.5
4
4.5
VDD2 (V)
5
5.5
50% - 90%
50% - 50%
50% - 10%
3.4
Signal Delay (s)
3
Signal Delay (s)
-25
D065
Figure 6-41. Output Rise and Fall Time vs Supply Voltage
0.2
-40
-25
D067
Figure 6-43. Input to Output Signal Delay vs Supply Voltage
18
1.5
-10
5
20
35
50
65
Temperature (°C)
80
95
110 125
D068
Figure 6-44. Input to Output Signal Delay vs Temperature
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7 Detailed Description
7.1 Overview
The AMC1350-Q1 is a fully differential, precision, isolated amplifier with high input impedance. The input stage
of the device consists of a fully differential amplifier that drives a second-order, delta-sigma (ΔΣ) modulator.
The modulator converts the analog input signal into a digital bitstream that is transferred across the isolation
barrier that separates the high-side from the low-side. On the low-side, the received bitstream is processed by a
fourth-order analog filter that outputs a differential signal at the OUTP and OUTN pins proportional to the input
signal.
The SiO2-based, capacitive isolation barrier supports a high level of magnetic field immunity, as described
in the ISO72x Digital Isolator Magnetic-Field Immunity application report. The digital modulation used in the
AMC1350-Q1 to transmit data across the isolation barrier, and the isolation barrier characteristics itself, result in
high reliability and common-mode transient immunity.
7.2 Functional Block Diagram
VDD2
Barrier
VDD1
Diagnostics
Analog Filter
RX / TX
Modulator
OUTN
AMC1350-Q1
Isolation
INN
GND1
OUTP
TX / RX
INP
GND2
7.3 Feature Description
7.3.1 Analog Input
The single-ended, high-impedance input stage of the AMC1350-Q1 feeds a second-order, switched-capacitor,
feed-forward ΔΣ modulator. The modulator converts the analog signal into a bitstream that is transferred across
the isolation barrier, as described in the Isolation Channel Signal Transmission section.
There are two restrictions on the analog input signals INP and INN. First, if the input voltages VINP or VINN
exceed the range specified in the Absolute Maximum Ratings table, the input currents must be limited to the
absolute maximum value because the electrostatic discharge (ESD) protection turns on. In addition, the linearity
and parametric performance of the device are ensured only when the analog input voltage remains within
the linear full-scale range (VFSR) and within the common-mode input voltage range (VCM) as specified in the
Recommended Operating Conditions table.
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7.3.2 Isolation Channel Signal Transmission
The AMC1350-Q1 uses an on-off keying (OOK) modulation scheme, as shown in Figure 7-1, to transmit the
modulator output bitstream across the SiO2-based isolation barrier. The transmit driver (TX) shown in the
Functional Block Diagram transmits an internally-generated, high-frequency carrier across the isolation barrier
to represent a digital one and does not send a signal to represent a digital zero. The nominal frequency of the
carrier used inside the AMC1350-Q1 is 480 MHz.
The receiver (RX) on the other side of the isolation barrier recovers and demodulates the signal and provides
the input to the fourth-order analog filter. The AMC1350-Q1 transmission channel is optimized to achieve the
highest level of common-mode transient immunity (CMTI) and lowest level of radiated emissions caused by the
high-frequency carrier and RX/TX buffer switching.
Internal Clock
Modulator Bitstream
on High-side
Signal Across Isolation Barrier
Recovered Sigal
on Low-side
Figure 7-1. OOK-Based Modulation Scheme
20
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7.3.3 Analog Output
The AMC1350-Q1 offers a differential analog output on the OUTP and OUTN pins. For differential input voltages
(VINP – VINN) in the range from –5 V to +5 V, the device provides a linear response with a nominal gain of 0.4
V/V. For example, for a differential input voltage of 5 V, the differential output voltage (VOUTP – VOUTN) is 2 V. At
zero input (INP shorted to INN), both pins output the same common-mode output voltage VCMout, as specified in
the Electrical Characteristics table. For absolute differential input voltages greater than 5 V but less than 5.75 V,
the differential output voltage continues to increase in magnitude but with reduced linearity performance. The
outputs saturate at a differential output voltage of VCLIPout, as shown in Figure 7-2, if the differential input voltage
exceeds the VClipping value.
Maximum input range before clipping (VClipping)
Linear input range (VFSR)
VOUTN
VFail-safe
VCLIPout
VCMout
VOUTP
6.25 V
5V
0
6.25 V
5V
Differential Input Voltage (VINP – VINN)
Figure 7-2. Output Behavior of the AMC1350-Q1
The AMC1350-Q1 output offers a fail-safe feature that simplifies diagnostics on a system level. Figure 7-2 shows
the fail-safe condition, in which the AMC1350-Q1 outputs a negative differential output voltage that does not
occur under normal operating conditions. The fail-safe output is active in two cases:
• When the high-side supply VDD1 of the AMC1350-Q1 device is missing
• When the high-side supply VDD1 falls below the undervoltage threshold VDD1UV
Use the maximum VFail-safe voltage specified in the Electrical Characteristics table as a reference value for
fail-safe detection on a system level.
7.4 Device Functional Modes
The AMC1350-Q1 is operational when the power supplies VDD1 and VDD2 are applied as specified in the
Recommended Operating Conditions table.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The high input impedance, low input bias current, bipolar input voltage range, excellent accuracy, and low
temperature drift make the AMC1350-Q1 a high-performance solution for automotive applications where isolated
AC or DC voltage sensing is required.
8.2 Typical Application
Isolated amplifiers are widely used for voltage measurements in high-voltage applications that must be isolated
from a low-voltage domain. Typical applications are AC line voltage measurements, either line-to-neutral or
line-to-line in grid-connected equipment.
Figure 8-1 illustrates a simplified schematic of an onboard charger (OBC) application that uses three AMC1350Q1 devices to measure the AC line voltage on each phase of a three-phase system. The AC line voltage is
divided down to an approximate ±5-V level across the bottom resistor (RSNS) of a high-impedance resistive
divider that is sensed by the AMC1350-Q1. The output of the AMC1350-Q1 is a differential analog output
voltage proportional to the input voltage but is galvanically isolated from the high-side by a reinforced isolation
barrier. A common high-side power supply (VDD1) for all three AMC1350-Q1 devices is generated from the
low-side supply (VDD2) of the system by an isolated DC/DC converter circuit. A low-cost solution is based on the
push-pull driver SN6501-Q1 and a transformer that supports the desired isolation voltage ratings.
The high-impedance input, high input voltage range, and the high common-mode transient immunity (CMTI) of
the AMC1350-Q1 ensure reliable and accurate operation even in high-noise environments.
22
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EMI
Filter
Contactor
SW
L1
PFC
DC-Link
+ DC-Bus
DC/DC
SW
L2
HV Battery
SW
L3
R1
Number of unit resistors
depends on
design requirements.
R2
RSNS
SW
N
DC-Bus
N
Low-side supply
(3.3 V or 5 V)
AMC1350-Q1
VDD1
100 nF
1 uF
VDD2
INP
OUTP
INN
OUTN
GND1
GND2
ADC
1 μF
100 nF
AMC1350-Q1
VDD1
VDD2
INP
OUTP
INN
OUTN
GND1
GND2
100 nF
1 uF
ADC
1 μF
100 nF
AMC1350-Q1
VDD1
VDD2
INP
OUTP
INN
OUTN
GND1
GND2
100 nF
1 uF
ADC
1 μF
100 nF
TPS76350-Q1
NC
SN6501-Q1
EN
D1
IN
D2
100 nF 4.7 μF
10 μF
GND
100 nF
Barrier
10 μF
OUT
Isoation
VOUT = 5 V
GND
VCC
GND
Figure 8-1. Using the AMC1350-Q1 for AC Line-Voltage Sensing in an OBC Application
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8.2.1 Design Requirements
Table 8-1 lists the parameters for this typical application.
Table 8-1. Design Requirements
PARAMETER
120-VRMS LINE VOLTAGE
230-VRMS LINE VOLTAGE
120 V ±10%, 60 Hz
230 V ±10%, 50 Hz
High-side supply voltage
3.3 V or 5 V
3.3 V or 5 V
Low-side supply voltage
3.3 V or 5 V
3.3 V or 5 V
System input voltage
Maximum resistor operating voltage
Voltage drop across the sense resistor (RSNS) for a linear response
Current through the resistive divider, ICROSS
75 V
75 V
±5 V (maximum)
±5 V (maximum)
100 μA
100 μA
8.2.2 Detailed Design Procedure
This discussion covers the 230-VRMS example. The procedure for calculating the resistive divider for the 120VRMS use case is identical.
The 100-μA, cross-current requirement at peak input voltage (360 V) determines that the total impedance of
the resistive divider is 3.6 MΩ. The impedance of the resistive divider is dominated by the top resistors (shown
exemplary as R1 and R2 in Figure 8-1) and the voltage drop across RSNS can be neglected for a short time.
The maximum allowed voltage drop per unit resistor is specified as 75 V; therefore, the total minimum number of
unit resistors in the top portion of the resistive divider is 360 V / 75 V = 5. The calculated unit value is 3.6 MΩ / 5
= 720 kΩ and the next closest value from the E96 series is 715 kΩ.
The effective sense resistor value RSNSEFF is the parallel combination of the external resistor RSNS and the
input impedance of the AMC1350-Q1, RIN. RSNSEFF is sized such that the voltage drop across the impedance
at maximum input voltage (360 V) equals the linear full-scale input voltage (VFSR) of the AMC1350-Q1 (that is,
+5 V). RSNSEFF is calculated as RSNSEFF = VFSR / (VPeak – VFSR) × RTOP where RTOP is the total value of the
top resistor string (5 × 715 kΩ = 3575 kΩ). The resulting value for RSNSEFF is 9.96 kΩ. In a final step, RSNS is
calculated as RSNS = RIN × RSNSEFF / (RIN – RSNSEFF). With RIN = 1.25 MΩ (typical), RSNS equals 52.47 kΩ
and the next closest value from the E96 series is 52.3 kΩ.
Table 8-2 summarizes the design of the resistive divider.
Table 8-2. Resistor Value Examples
120-VRMS LINE VOLTAGE
230-VRMS LINE VOLTAGE
Peak voltage
PARAMETER
190 V
360 V
Unit resistor value, RTOP
634 kΩ
715 kΩ
3
5
Number of unit resistors in RTOP
Sense resistor value, RSNS
53.6 kΩ
52.3 kΩ
1953.4 kΩ
3625.2 kΩ
Resulting current through resistive divider, ICROSS
97.3 μA
99.3 μA
Resulting full-scale voltage drop across sense resistor RSNS
4.993 V
4.982 V
6 mW
7.1 mW
18.5 mW
35.7 mW
Total resistance value (RTOP + RSNS)
Peak power dissipated in RTOP unit resistor
Total peak power dissipated in resistive divider
24
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8.2.2.1 Input Filter Design
Placing an RC filter in front of the isolated amplifier improves signal-to-noise performance of the signal path. In
practice, however, the impedance of the resistor divider is so high that adding a filter capacitor on the INN or INP
pin limits the signal bandwidth to an unacceptable low limit, such that the filter capacitor is omitted. When used,
design the input filter such that:
•
•
The cutoff frequency of the filter is at least one order of magnitude lower than the sampling frequency
(20 MHz) of the internal ΔΣ modulator
The input bias current does not generate significant voltage drop across the DC impedance of the input filter
Most voltage-sensing applications use high-impedance resistor dividers in front of the isolated amplifier to scale
down the input voltage. In that case, no additional resistor is needed and a single capacitor (as shown in Figure
8-2) is sufficient to filter the input signal.
AMC1350-Q1
VDD1
VDD2
INP
OUTP
INN
OUTN
GND1
GND2
RSNS
1 nF
Figure 8-2. Input Filter
8.2.2.2 Differential to Single-Ended Output Conversion
Figure 8-3 shows an example of a TLVx313-Q1-based signal conversion and filter circuit for systems using
single-ended input ADCs to convert the analog output voltage into digital. With R1 = R2 = R3 = R4, the output
voltage equals (VOUTP – VOUTN) + VREF. Tailor the bandwidth of this filter stage to the bandwidth requirement of
the system and use NP0-type capacitors for best performance. For most applications, R1 = R2 = R3 = R4 = 3.3
kΩ and C1 = C2 = 330 pF yields good performance.
C1
AMC1350-Q1
VDD1
VDD2
INP
OUTP
R2
R1
–
ADC
R3
INN
OUTN
GND1
GND2
To MCU
+
TLV313-Q1
C2
R4
VREF
Figure 8-3. Connecting the AMC1350-Q1 Output to a Single-Ended Input ADC
For more information on the general procedure to design the filtering and driving stages of SAR ADCs, see
the 18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise and 18-Bit Data
Acquisition Block (DAQ) Optimized for Lowest Power reference guides, available for download at www.ti.com.
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8.2.3 Application Curve
One important aspect of system design is the effective detection of an overvoltage condition to protect switching
devices and passive components from damage. To power off the system quickly in the event of an overvoltage
condition, a low delay caused by the isolated amplifier is required. Figure 8-4 shows the typical full-scale step
response of the AMC1350-Q1.
VOUTP
VOUTN
VIN
Figure 8-4. Step Response of the AMC1350-Q1
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8.3 What To Do and What Not To Do
Do not leave the inputs of the AMC1350-Q1 unconnected (floating) when the device is powered up. If the device
inputs are left floating, the input bias current may drive the inputs to a positive or negative value that exceeds the
operating common-mode input voltage and the device output is undetermined.
Connect the high-side ground (GND1) to INN, either by a hard short or through a resistive path. A DC current
path between INN and GND1 is required to define the input common-mode voltage. Take care not to exceed
the input common-mode range as specified in the Recommended Operating Conditions table. For best accuracy,
route the ground connection as a separate trace that connects directly to the sense resistor rather than shorting
GND1 to INN directly at the input to the device. See the Layout section for more details.
Do not connect protection diodes to the inputs (INP or INN) of the AMC1350-Q1. Diode leakage current can
introduce significant measurement error especially at high temperatures. The input pin is protected against high
voltages by its ESD protection circuit and the high impedance of the external restive divider.
9 Power Supply Recommendations
In a typical application, the high-side power supply (VDD1) for the AMC1350-Q1 is generated from the low-side
supply (VDD2) by an isolated DC/DC converter. A low-cost solution is based on the push-pull driver SN6501 and
a transformer that supports the desired isolation voltage ratings.
The AMC1350-Q1 does not require any specific power-up sequencing. The high-side power supply (VDD1)
is decoupled with a low-ESR, 100-nF capacitor (C1) parallel to a low-ESR, 1-μF capacitor (C2). The low-side
power supply (VDD2) is equally decoupled with a low-ESR, 100-nF capacitor (C3) parallel to a low-ESR, 1-μF
capacitor (C4). Place all four capacitors (C1, C2, C3, and C4) as close to the device as possible. Figure 9-1
shows a decoupling diagram for the AMC1350-Q1.
VAC
R1
VDD1
VDD2
C2 1 µF
C4 1 µF
AMC1350-Q1
R2
C1 100 nF
C3 100 nF
VDD1
VDD2
INP
OUTP
to RC filter / ADC
INN
OUTN
to RC filter / ADC
GND1
GND2
RSNS
Figure 9-1. Decoupling of the AMC1350-Q1
Capacitors must provide adequate effective capacitance under the applicable DC bias conditions they
experience in the application. Multilayer ceramic capacitors (MLCC) typically exhibit only a fraction of their
nominal capacitance under real-world conditions and this factor must be taken into consideration when selecting
these capacitors. This problem is especially acute in low-profile capacitors, in which the dielectric field strength is
higher than in taller components. Reputable capacitor manufacturers provide capacitance versus DC bias curves
that greatly simplify component selection.
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10 Layout
10.1 Layout Guidelines
Figure 10-1 shows a layout recommendation with the critical placement of the decoupling capacitors (as close as
possible to the AMC1350-Q1 supply pins) and placement of the other components required by the device. For
best performance, place the sense resistor close to the device input pin (IN).
R2
C2
C4
C1
C3
INP
RSNS
Clearance area, to be
kept free of any
conductive materials.
VDD2
VDD1
R1
VAC
10.2 Layout Example
INN
AMC1350-Q1
OUTP
to RC filter / ADC
OUTN
to RC filter / ADC
GND1
GND2
Top Metal
Inner or Bottom Layer Metal
Via
Figure 10-1. Recommended Layout of the AMC1350-Q1
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
•
•
•
•
•
•
•
•
•
•
Texas Instruments, Isolation Glossary application report
Texas Instruments, Semiconductor and IC Package Thermal Metrics application report
Texas Instruments, ISO72x Digital Isolator Magnetic-Field Immunity application report
Texas Instruments, TLVx313-Q1 Low-Power, Rail-to-Rail In/Out, 750-μV Typical Offset, 1-MHz Operational
Amplifier for Cost-Sensitive Systems data sheet
Texas Instruments, TPS763xx-Q1 Low-Power, 150-mA, Low-Dropout Linear Regulators data sheet
Texas Instrument, SN6501-Q1 Transformer Driver for Isolated Power Supplies data sheet
Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise
reference guide
Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Power reference
guide
Texas Instruments, Isolated Amplifier Voltage Sensing Excel Calculator design tool
Texas Instruments, Best in Class Radiated Emissions EMI Performance with the AMC1300B-Q1 Isolated
Amplifier technical white paper
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
AMC1350QDWVRQ1
ACTIVE
SOIC
DWV
8
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
AMC1350Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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