AMC22C12DR

AMC22C12 SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 AMC22C12 Fast Response, Basic Isolated Window Comparator With Adjustable Threshold and Latch Function 1 Features 3 Description • • • The AMC22C12 is an isolated window comparator with a short response time. The open-drain output is separated from the input circuitry by an isolation barrier that is highly resistant to magnetic interference. This barrier is certified to provide galvanic isolation of up to 3 kVRMS according to DIN EN IEC 60747-17 (VDE 0884-17) and UL1577, and supports a working voltage of up to 560 VRMS. • 2 Applications Overcurrent or overvoltage detection in: – Motor drives – Frequency inverters – Solar inverters – DC/DC converters The open-drain output on the device supports transparent mode (LATCH input tied to GND2) where the output follows the input state, or latch mode, where the output is cleared on the falling edge of the latch input signal. The AMC22C12 is available in a 8-pin SOIC package and is specified over the extended industrial temperature range of –40°C to +125°C. Package Information(1) PART NUMBER AMC22C12 (1) VDD1 4.90 mm × 3.90 mm VDD2 LDO IN + 100
A REF SOIC (8) BODY SIZE (NOM) Low-side supply (2.7..5.5 V) AMC22C12 I PACKAGE For all available packages, see the orderable addendum at the end of the data sheet. High-side supply (3..27 V) RSHUNT • The comparison window is centered around 0 V, meaning that the comparator trips if the absolute value of the input voltage exceeds the trip threshold value. The trip threshold is adjustable from 20 mV to 300 mV through a single external resistor and, therefore, the comparison window ranges from ±20 mV to ±300 mV. When the voltage on the REF pin is greater than 550 mV, the negative comparator is disabled and only the positive comparator is functional. The reference voltage in this mode can be as high as 2.7 V. This mode is particularly useful for monitoring voltage supplies. – Galvanic Isolation Barrier • • • • • • Wide high-side supply range: 3 V to 27 V Low-side supply range: 2.7 V to 5.5 V Adjustable threshold: – Window-comparator mode: ±20 mV to ±300 mV – Positive-comparator mode: 600 mV to 2.7 V Reference for threshold adjustment: 100 μA, ±1% Trip threshold error: ±1% (max) at 250 mV Open-drain output with optional latch mode Propagation delay: 280 ns (typ) High CMTI: 55 V/ns (min) Safety-related certifications: – 4250-VPK basic isolation per DIN EN IEC 60747-17 (VDE 0884-17) – 3000-VRMS isolation for 1 minute per UL1577 Fully specified over the extended industrial temperature range: –40°C to +125°C GND1 LATCH OUT from MCU to MCU GND2 Typical Application An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions.........................5 6.4 Thermal Information ...................................................5 6.5 Power Ratings.............................................................5 6.6 Insulation Specifications ............................................ 6 6.7 Safety-Related Certifications ..................................... 7 6.8 Safety Limiting Values ................................................7 6.9 Electrical Characteristics ............................................8 6.10 Switching Characteristics .......................................10 6.11 Timing Diagrams..................................................... 10 6.12 Insulation Characteristics Curves............................11 6.13 Typical Characteristics............................................ 12 7 Detailed Description......................................................19 7.1 Overview................................................................... 19 7.2 Functional Block Diagram......................................... 19 7.3 Feature Description...................................................20 7.4 Device Functional Modes..........................................27 8 Application and Implementation.................................. 28 8.1 Application Information............................................. 28 8.2 Typical Applications ................................................. 28 8.3 Best Design Practices...............................................33 8.4 Power Supply Recommendations.............................34 8.5 Layout....................................................................... 34 9 Device and Documentation Support............................35 9.1 Documentation Support............................................ 35 9.2 Receiving Notification of Documentation Updates....35 9.3 Support Resources................................................... 35 9.4 Trademarks............................................................... 35 9.5 Electrostatic Discharge Caution................................35 9.6 Glossary....................................................................35 10 Mechanical, Packaging, and Orderable Information.................................................................... 35 10.1 Mechanical Data..................................................... 36 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (June 2022) to Revision A (August 2022) Page • Changed document status from advanced information to production data ....................................................... 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 5 Pin Configuration and Functions VDD1 1 8 VDD2 IN 2 7 LATCH REF 3 6 OUT GND1 4 5 GND2 Not to scale Figure 5-1. D Package, 8-Pin SOIC (Top View) Table 5-1. Pin Functions PIN NO. NAME TYPE DESCRIPTION High-side power supply.(1) 1 VDD1 High-side power 2 IN Analog input Analog input pin to the window comparator. Reference pin that defines the trip threshold. The voltage on this pin also affects the hysteresis of comparator Cmp0, as explained in the Reference Input section. This pin is internally connected to a 100-μA current source. Connect a resistor from REF to GND1 to define the trip threshold, and a capacitor from REF to GND1 to filter the reference voltage. For best transient noise immunity, place the capacitor as closely to the pin as possible. This pin can also be driven by an external voltage source. 3 REF Analog input 4 GND1 High-side ground High-side ground. 5 GND2 Low-side ground Low-side ground. 6 OUT Digital output Open-drain output of the window comparator. Connect to an external pullup resistor. 7 LATCH Digital input Digital input to select latch mode (high) or transparent mode (low) of the open-drain output. Do not leave the input pin unconnected (floating). Connect to GND2 when not used. 8 VDD2 Low-side power (1) Low-side power supply.(1) See the Power Supply Recommendations section for power-supply decoupling recommendations. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 3 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 6 Specifications 6.1 Absolute Maximum Ratings see(1) MIN Power-supply voltage Analog input voltage MAX VDD1 to GND1 –0.3 30 VDD2 to GND2 –0.3 6.5 REF to GND1 –0.5 6.5 –6 5.5 IN to GND1 UNIT V V Digital input voltage LATCH to GND1 –0.5 VDD2 + 0.5 V Digital output voltage OUT to GND2 –0.5 VDD2 + 0.5 V Input current Continuous, any pin except power-supply pins –10 Temperature (1) Junction, TJ 10 150 Storage, Tstg –65 150 mA °C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. 6.2 ESD Ratings VALUE V(ESD) (1) (2) 4 Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±2000 ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 6.3 Recommended Operating Conditions over operating ambient temperature range (unless otherwise noted) MIN NOM MAX UNIT POWER SUPPLY VVDD1 High-side power-supply voltage VDD1 to GND1 3.0 5 27 V VVDD2 Low-side power supply voltage VDD2 to GND2 2.7 3.3 5.5 V ANALOG INPUT VIN Input voltage Reference voltage, window comparator mode VREF IN to GND1, VDD1 ≤ 4.3 V –0.4 VDD1 – 0.3 IN to GND1, VDD1 > 4.3 V –0.4 4 REF to GND1 20 300 Low hysteresis mode 20 450 Reference voltage, positive-comparator mode High hysteresis mode (Cmp0 only) 600 2700(1) Reference voltage headroom VDD1 – VREF 1.4 Filter capacitance on REF pin V mV V 20 100 nF DIGITAL I/O Digital input voltage LATCH pin GND2 VDD2 V Digital output voltage OUT to GND2 GND2 VDD2 V Sink current OUT 0 4 mA 125 °C TEMPERATURE RANGE TA (1) Specified ambient temperature –40 25 Reference voltages (VREF) >1.6 V require VVDD1 > VVDD1,MIN to maintain minimum headroom (VVDD1 – VREF) of 1.4 V. 6.4 Thermal Information D (SOIC) THERMAL METRIC(1) 8 PINS UNIT RθJA Junction-to-ambient thermal resistance 116.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 52.8 °C/W RθJB Junction-to-board thermal resistance 58.9 °C/W ΨJT Junction-to-top characterization parameter 19.4 °C/W ΨJB Junction-to-board characterization parameter 58.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Power Ratings PARAMETER PD PD1 PD2 Maximum power dissipation (both sides) Maximum power dissipation (high-side) Maximum power dissipation (low-side) TEST CONDITIONS VALUE VDD1 = 25 V, VDD2 = 5.5 V 102 VDD1 = VDD2 = 5.5 V 32 VDD1 = VDD2 = 3.6 V 21 VDD1 = 25 V 90 VDD1 = 5.5 V 20 VDD1 = 3.6 V 13 VDD2 = 5.5 V 12 VDD2 = 3.6 V 8 UNIT mW mW mW Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 5 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 6.6 Insulation Specifications over operating ambient temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VALUE UNIT GENERAL CLR External clearance(1) Shortest pin-to-pin distance through air ≥4 mm CPG External creepage(1) Shortest pin-to-pin distance across the package surface ≥4 mm DTI Distance through insulation Minimum internal gap (internal clearance) of the insulation ≥ 15.4 µm CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 ≥ 400 V Material group According to IEC 60664-1 Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 150 VRMS I-IV Rated mains voltage ≤ 300 VRMS I-III At AC voltage 790 VPK II DIN EN IEC 60747-17 (VDE 0884-17)(2) VIORM Maximum repetitive peak isolation voltage VIOWM Maximum-rated isolation working voltage At AC voltage (sine wave) 560 VRMS At DC voltage 790 VDC VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60 s (qualification test) 4250 VTEST = 1.2 × VIOTM, t = 1 s (100% production test) 5100 VIMP Maximum impulse voltage(3) Tested in air, 1.2/50-µs waveform per IEC 62368-1 5000 VPK VIOSM Maximum surge isolation voltage(4) Tested in oil (qualification test), 1.2/50-µs waveform per IEC 62368-1 6500 VPK Apparent charge(5) qpd CIO Barrier capacitance, input to output(6) RIO Insulation resistance, input to output(6) Method a, after input/output safety test subgroups 2 and 3, Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 × VIORM, tm = 10 s ≤5 Method a, after environmental tests subgroup 1, Vini = VIOTM, tini = 60 s, Vpd(m) = 1.3 × VIORM, tm = 10 s ≤5 Method b2, at routine test (100% production), Vini = VIOTM = Vpd(m); tini = tm = 1 s ≤5 VIO = 0.5 VPP at 1 MHz ~1.5 VIO = 500 V at TA = 25°C > 1012 VIO = 500 V at 100°C ≤ TA ≤ 125°C > 1011 VIO = 500 V at TS = 150°C > 109 Pollution degree 2 Climatic category 55/125/21 VPK pC pF Ω UL1577 VISO (1) (2) (3) (4) (5) (6) 6 Withstand isolation voltage VTEST = VISO = 3000 VRMS or 4250 VDC, t = 60 s (qualification), VTEST = 1.2 × VISO = 3600 VRMS, t = 1 s (100% production test) 3000 VRMS Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a PCB are used to help increase these specifications. This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits. Testing is carried out in air to determine the surge immunity of the package. Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier. Apparent charge is electrical discharge caused by a partial discharge (pd). All pins on each side of the barrier are tied together, creating a two-pin device. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 6.7 Safety-Related Certifications VDE UL DIN EN IEC 60747-17 (VDE 0884-17), EN IEC 60747-17, DIN EN 61010-1 (VDE 0411-1) Clause : 6.4.3 ; 6.7.1.3 ; 6.7.2.1 ; 6.7.2.2 ; 6.7.3.4.2 ; 6.8.3.1 Recognized under 1577 component recognition Basic insulation Single protection Certificate number: pending File number: E181974 6.8 Safety Limiting Values Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures. PARAMETER IS Safety input, output, or supply current PS Safety input, output, or total power TS Maximum safety temperature (1) TEST CONDITIONS MIN TYP MAX UNIT RθJA = 116.5°C/W, VDD1 = VDD2 = 5.5 V, TJ = 150°C, TA = 25°C 195 RθJA = 116.5°C/W, VDD1 = VDD2 = 3.6 V, TJ = 150°C, TA = 25°C 300 RθJA = 116.5°C/W, TJ = 150°C, TA = 25°C 1070 mW 150 °C mA The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These limits vary with the ambient temperature, TA. The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. Use these equations to calculate the value for each parameter: TJ = TA + RθJA × P, where P is the power dissipated in the device. TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature. PS = IS × AVDDmax + IS × DVDDmax, where AVDDmax is the maximum high-side voltage and DVDDmax is the maximum controller-side supply voltage. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 7 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 6.9 Electrical Characteristics minimum and maximum specifications apply from TA = –40°C to 125°C, VDD1 = 3.0 V to 27 V, VDD2 = 2.7 V to 5.5 V, VREF = 20 mV to 2.7 V(1), and VIN = –400 mV to 4 V(3); typical specifications are at TA = 25°C, VDD1 = 5 V, VDD2 = 3.3 V, and VREF = 250 mV (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT RIN Input resistance IBIAS Input bias current CIN Input capacitance IN pin, 0 ≤ VIN ≤ 4 V IN pin, 0 ≤ VIN ≤ 4 1 V(4) IN pin, –400 mV ≤ VIN ≤ 0 V(5) 0.1 –310 GΩ 25 –0.5 IN pin 4 nA pF REFERENCE PIN IREF Reference current VMSEL Mode selection threshold(2) REF to GND1, 20 mV < VREF ≤ 2.7 V 99 100 101 VREF rising 500 550 600 VREF falling 450 500 550 Mode selection threshold hysteresis 50 μA mV mV COMPARATORS VIT+ EIT+ Positive-going trip threshold Positive-going trip threshold error VIT– Negative-going trip threshold EIT– Negative-going trip threshold error Cmp0 EIT– VIT+ Negative-going trip threshold Negative-going trip threshold error Positive-going trip threshold EIT+ Positive-going trip threshold error VHYS Trip threshold hysteresis mV –2 2 Cmp0, (VIT+ – VREF – VHYS), VREF = 250 mV, VHYS = 4 mV –2 2 Cmp0, (VIT+ – VREF – VHYS), VREF = 2 V, VHYS = 25 mV –5 5 Cmp0 VREF –2.5 2.5 Cmp0, (VIT– – VREF), VREF = 250 mV –2.5 2.5 –5 5 Cmp1 mV mV Cmp0, (VIT– – VREF), VREF = 20 mV Cmp0, (VIT– – VREF), VREF = 2 V VIT– VREF + VHYS Cmp0, (VIT+ – VREF – VHYS), VREF = 20 mV, VHYS = 4 mV –VREF – VHYS mV mV Cmp1, (VIT– + VREF + VHYS), VREF = 20 mV, VHYS = 4 mV –3 3 Cmp1, (VIT– + VREF + VHYS), VREF = 250 mV, VHYS = 4 mV –3 3 mV Cmp1 –VREF mV Cmp1, (VIT+ + VREF), VREF = 20 mV –3.5 3.5 Cmp1, (VIT+ + VREF), VREF = 250 mV –3.5 3.5 Cmp0 and Cmp1, (VIT+ – VIT–), VREF ≤ 450 mV 4 Cmp0 only, (VIT+ – VIT–), VREF ≥ 600 mV mV mV 25 DIGITAL I/O 8 VIH High-level input voltage LATCH pin 0.7 x VDD2 VDD2 + 0.3 V VIL Low-level input voltage LATCH pin –0.3 0.3 x VDD2 V CIN Input capacitance LATCH pin VOL Low-level output voltage ISINK = 4 mA ILKG Open-drain output leakage current VDD2 = 5 V, VOUT = 5 V CMTI Common-mode transient immunity |VIN – VREF| ≥ 4 mV, RPULLUP = 10 kΩ Submit Document Feedback 4 55 pF 80 250 5 100 110 mV nA V/ns Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 6.9 Electrical Characteristics (continued) minimum and maximum specifications apply from TA = –40°C to 125°C, VDD1 = 3.0 V to 27 V, VDD2 = 2.7 V to 5.5 V, VREF = 20 mV to 2.7 V(1), and VIN = –400 mV to 4 V(3); typical specifications are at TA = 25°C, VDD1 = 5 V, VDD2 = 3.3 V, and VREF = 250 mV (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY VDD1UV VDD1 undervoltage detection threshold VDD1POR VDD1 power-on reset threshold VDD1 rising 3 VDD1 falling 2.9 VDD1 falling 2.3 VDD2 rising 2.7 VDD2 falling 2.1 V V VDD2UV VDD2 undervoltage detection threshold IDD1 High-side supply current 3.2 4.3 mA IDD2 Low-side supply current 1.8 2.2 mA (1) (2) (3) (4) (5) V Reference voltages >1.6 V require VDD1 > VDD1MIN. See the Recommended Operating Conditions table for details. The voltage level VREF determines if the device operates as window-comparator with positive and negative thresholds or as simple comparator with positive thresholds only. See the Reference Input section for more details. But not exceeding the maximum input voltage specified in the Recommended Operating Conditions table. The typical value is measured at VIN = 0.4 V. The typical value is measured at VIN = –400 mV. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 9 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 6.10 Switching Characteristics over operating ambient temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LATCH INPUT Deglitch time Falling edge 1.8 3.2 µs OPEN-DRAIN OUTPUT tpH Propagation delay time, |VIN| rising tpL Propagation delay time, |VIN| falling tf Output signal fall time VDD2 = 3.3 V, VREF = 250 mV, VOVERDRIVE = 10 mV, CL = 15 pF 280 410 VDD2 = 3.3 V, VREF = 2 V, VOVERDRIVE = 50 mV, CL = 15 pF 240 370 VDD2 = 3.3 V, VREF = 250 mV, VOVERDRIVE = 10 mV, CL = 15 pF 280 410 VDD2 = 3.3 V, VREF = 2 V, VOVERDRIVE = 50 mV, CL = 15 pF 240 370 ns ns RPULLUP = 4.7 kΩ, CL = 15 pF 2 ns MODE SELECTION tHSEL Comparator hysteresis selection deglitch time Cmp0, VREF rising or falling 10 µs tDIS13 Comparator disable deglitch time Cmp1, VREF rising 10 µs tEN13 Comparator enable deglitch time Cmp1, VREF falling 100 µs START-UP TIMING tLS ,STA Low-side start-up time VDD2 step to 2.7 V, VDD1 ≥ 3.0 V 40 µs tHS ,STA High-side start-up time VDD1 step to 3.0 V, VDD2 ≥ 2.7 V 45 µs tHS,BLK High-side blanking time 200 µs tHS,FLT High-side-fault detection delay time 100 µs 6.11 Timing Diagrams VREF + VOVERDRIVE VOVERDRIVE VREF VOVERDRIVE IN VREF – VOVERDRIVE tpH tpL OUT 90% 50% 10% 10% tf Figure 6-1. Rise, Fall, and Delay Time Definition (LATCH = Low) VREF VIN –VREF OUT LATCH latch mode transparent mode Figure 6-2. Functional Timing Diagram 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 6.12 Insulation Characteristics Curves 350 1200 VDD1 = VDD2 = 3.6 V VDD1 = VDD2 = 5.5 V 300 1000 800 PS (mW) IS (mA) 250 200 150 600 400 100 200 50 0 0 0 25 50 75 TA (°C) 100 125 150 0 D069 Figure 6-3. Thermal Derating Curve for Safety-Limiting Current per VDE 25 50 75 TA (°C) 100 125 150 D070 Figure 6-4. Thermal Derating Curve for Safety-Limiting Power per VDE Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 11 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 6.13 Typical Characteristics 26 26 25 25 24 24 23 23 22 22 VIT (mV) VIT (mV) at VDD1 = 5 V, VDD2 = 3.3 V (unless otherwise noted) 21 20 19 21 20 19 18 Device 1, VIT+ Device 2, VIT+ Device 3, VIT+ 17 16 0 5 10 15 VDD1 (V) 18 Device 1, VIT− Device 2, VIT− Device 3, VIT− 20 25 Device 1, VIT+ Device 2, VIT+ Device 3, VIT+ 17 16 -40 30 -25 -10 5 D020a VREF = 20 mV 80 95 110 125 D021a VREF = 20 mV Figure 6-5. Cmp0 Trip Threshold vs Supply Voltage Figure 6-6. Cmp0 Trip Threshold vs Temperature 1.5 1.5 Device 1, EIT+ Device 2, EIT+ Device 3, EIT+ 1 Device 1, EIT− Device 2, EIT− Device 3, EIT− 1 0.5 EIT (mV) 0.5 EIT (mV) 20 35 50 65 Temperature (C) Device 1, VIT− Device 2, VIT− Device 3, VIT− 0 0 -0.5 -0.5 -1 -1 -1.5 0 5 10 15 VDD1 (V) 20 25 -1.5 -40 30 Device 1, EIT+ Device 2, EIT+ Device 3, EIT+ -25 -10 5 D020d VREF = 20 mV 20 35 50 65 Temperature (C) Device 1, EIT− Device 2, EIT− Device 3, EIT− 80 95 110 125 D021d VREF = 20 mV Figure 6-7. Cmp0 Trip Threshold Error vs Supply Voltage Figure 6-8. Cmp0 Trip Threshold Error vs Temperature 6 5 VHYS (mV) 4 3 2 Device 1 Device 2 Device 3 1 0 -40 -25 5 20 35 50 65 Temperature (C) 80 95 110 125 D025a VREF = 20 mV VREF = 20 mV Figure 6-9. Cmp0 Trip Threshold Hysteresis vs Supply Voltage 12 -10 Figure 6-10. Cmp0 Trip Threshold Hysteresis vs Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 6.13 Typical Characteristics (continued) 256 256 255 255 254 254 253 253 252 252 VIT (mV) VIT (mV) at VDD1 = 5 V, VDD2 = 3.3 V (unless otherwise noted) 251 250 249 251 250 249 248 Device 1, VIT+ Device 2, VIT+ Device 3, VIT+ 247 246 0 5 10 248 Device 1, VIT− Device 2, VIT− Device 3, VIT− 15 VDD1 (V) 20 25 Device 1, VIT+ Device 2, VIT+ Device 3, VIT+ 247 246 -40 30 -25 -10 5 D020b VREF = 250 mV 95 110 125 D021b Figure 6-12. Cmp0 Trip Threshold vs Temperature 2.5 2.5 Device 1, EIT+ Device 2, EIT+ Device 3, EIT+ 2 1.5 Device 1, EIT− Device 2, EIT− Device 3, EIT− 2 1.5 1 1 0.5 0.5 EIT (mV) EIT (mV) 80 VREF = 250 mV Figure 6-11. Cmp0 Trip Threshold vs Supply Voltage 0 -0.5 0 -0.5 -1 -1 -1.5 -1.5 -2 -2 -2.5 -40 -2.5 0 5 10 15 VDD1 (V) 20 25 30 Device 1, EIT+ Device 2, EIT+ Device 3, EIT+ -25 -10 5 D020e VREF = 250 mV 20 35 50 65 Temperature (C) Device 1, EIT− Device 2, EIT− Device 3, EIT− 80 95 110 125 D021e VREF = 250 mV Figure 6-13. Cmp0 Trip Threshold Error vs Supply Voltage Figure 6-14. Cmp0 Trip Threshold Error vs Temperature 6 6 5 5 4 4 VHYS (mV) VHYS (mV) 20 35 50 65 Temperature (C) Device 1, VIT− Device 2, VIT− Device 3, VIT− 3 2 3 2 Device 1 Device 2 Device 3 1 0 0 5 10 15 VDD1 (V) 20 25 30 Device 1 Device 2 Device 3 1 0 -40 -25 D024b VREF = 250 mV -10 5 20 35 50 65 Temperature (C) 80 95 110 125 D025b VREF = 250 mV Figure 6-15. Cmp0 Trip Threshold Hysteresis vs Supply Voltage Figure 6-16. Cmp0 Trip Threshold Hysteresis vs Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 13 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 6.13 Typical Characteristics (continued) 2.030 2.030 2.025 2.025 2.020 2.020 2.015 2.015 2.010 2.010 VIT (V) VIT (V) at VDD1 = 5 V, VDD2 = 3.3 V (unless otherwise noted) 2.005 2.000 1.995 2.005 2.000 1.995 1.990 Device 1, VIT+ Device 2, VIT+ Device 3, VIT+ 1.985 1.980 0 5 10 15 VDD1 (V) 1.990 Device 1, VIT− Device 2, VIT− Device 3, VIT− 20 25 Device 1, VIT+ Device 2, VIT+ Device 3, VIT+ 1.985 1.980 -40 30 -25 -10 5 D020c VREF = 2 V 110 125 D021c 5 Device 1, EIT+ Device 2, EIT+ Device 3, EIT+ 4 3 Device 1, EIT− Device 2, EIT− Device 3, EIT− 4 3 2 2 1 1 EIT (mV) EIT (mV) 95 Figure 6-18. Cmp0 Trip Threshold vs Temperature 5 0 -1 0 -1 -2 -2 -3 -3 -4 -4 -5 0 5 10 15 VDD1 (V) 20 25 -5 -40 30 Device 1, EIT+ Device 2, EIT+ Device 3, EIT+ -25 -10 5 D020f VREF = 2 V 20 35 50 65 Temperature (C) Device 1, EIT− Device 2, EIT− Device 3, EIT− 80 95 110 125 D021f VREF = 2 V Figure 6-19. Cmp0 Trip Threshold Error vs Supply Voltage Figure 6-20. Cmp0 Trip Threshold Error vs Temperature 30 30 25 25 20 20 VHYS (mV) VHYS (mV) 80 VREF = 2 V Figure 6-17. Cmp0 Trip Threshold vs Supply Voltage 15 10 15 10 Device 1 Device 2 Device 3 5 0 0 5 10 15 VDD1 (V) 20 25 30 Device 1 Device 2 Device 3 5 0 -40 -25 D024c VREF = 2 V -10 5 20 35 50 65 Temperature (C) 80 95 110 125 D025c VREF = 2 V Figure 6-21. Cmp0 Trip Threshold Hysteresis vs Supply Voltage 14 20 35 50 65 Temperature (C) Device 1, VIT− Device 2, VIT− Device 3, VIT− Figure 6-22. Cmp0 Trip Threshold Hysteresis vs Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 6.13 Typical Characteristics (continued) at VDD1 = 5 V, VDD2 = 3.3 V (unless otherwise noted) -16 -16 Device 1, VIT− Device 2, VIT− Device 3, VIT− -17 -18 -19 -19 -20 -20 -21 -22 -22 -23 -24 -24 -25 -25 -26 5 10 15 VDD1 (V) 20 25 -26 -40 30 Device 1, VIT+ Device 2, VIT+ Device 3, VIT+ -21 -23 0 Device 1, VIT− Device 2, VIT− Device 3, VIT− -17 VIT (mV) VIT (mV) -18 Device 1, VIT+ Device 2, VIT+ Device 3, VIT+ -25 -10 5 D026a VREF = 20 mV 20 35 50 65 Temperature (C) 80 95 110 125 D027a VREF = 20 mV Figure 6-23. Cmp1 Trip Threshold vs Supply Voltage Figure 6-24. Cmp1 Trip Threshold vs Temperature 1.5 1 EIT (mV) 0.5 0 -0.5 Device 1, EIT− Device 2, EIT− Device 3, EIT− -1 -1.5 0 5 10 15 VDD1 (V) Device 1, EIT+ Device 2, EIT+ Device 3, EIT+ 20 25 30 D026c VREF = 20 mV VREF = 20 mV Figure 6-26. Cmp1 Trip Threshold Error vs Temperature 6 6 5 5 4 4 VHYS (mV) VHYS (mV) Figure 6-25. Cmp1 Trip Threshold Error vs Supply Voltage 3 2 3 2 Device 1 Device 2 Device 3 1 0 0 5 10 15 VDD1 (V) 20 25 30 Device 1 Device 2 Device 3 1 0 -40 -25 D030a VREF = 20 mV -10 5 20 35 50 65 Temperature (C) 80 95 110 125 D031a VREF = 20 mV Figure 6-27. Cmp1 Trip Threshold Hysteresis vs Supply Voltage Figure 6-28. Cmp1 Trip Threshold Hysteresis vs Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 15 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 6.13 Typical Characteristics (continued) at VDD1 = 5 V, VDD2 = 3.3 V (unless otherwise noted) -246 -246 Device 1, VIT− Device 2, VIT− Device 3, VIT− -247 -248 -249 -249 -250 -250 -251 -252 -252 -253 -254 -254 -255 -255 -256 5 10 15 VDD1 (V) 20 25 -256 -40 30 -25 -10 5 D026b VREF = 250 mV Figure 6-29. Cmp1 Trip Threshold vs Supply Voltage Device 1, EIT− Device 2, EIT− Device 3, EIT− 1.5 95 110 125 D027b Figure 6-30. Cmp1 Trip Threshold vs Temperature Device 1, EIT+ Device 2, EIT+ Device 3, EIT+ Device 1, EIT− Device 2, EIT− Device 3, EIT− 2 1.5 1 1 0.5 0.5 EIT (mV) EIT (mV) 80 2.5 2 0 -0.5 Device 1, EIT+ Device 2, EIT+ Device 3, EIT+ 0 -0.5 -1 -1 -1.5 -1.5 -2 -2 -2.5 0 5 10 15 VDD1 (V) 20 25 -2.5 -40 30 -25 -10 5 D026d VREF = 250 mV 20 35 50 65 Temperature (C) 80 95 110 125 D027d VREF = 250 mV Figure 6-31. Cmp1 Trip Threshold Error vs Supply Voltage Figure 6-32. Cmp1 Trip Threshold Error vs Temperature 6 6 5 5 4 4 VHYS (mV) VHYS (mV) 20 35 50 65 Temperature (C) VREF = 250 mV 2.5 3 2 3 2 Device 1 Device 2 Device 3 1 0 0 5 10 15 VDD1 (V) 20 25 30 Device 1 Device 2 Device 3 1 0 -40 -25 D030b VREF = 250 mV -10 5 20 35 50 65 Temperature (C) 80 95 110 125 D031b VREF = 250 mV Figure 6-33. Cmp1 Trip Threshold Hysteresis vs Supply Voltage 16 Device 1, VIT+ Device 2, VIT+ Device 3, VIT+ -251 -253 0 Device 1, VIT− Device 2, VIT− Device 3, VIT− -247 VIT (mV) VIT (mV) -248 Device 1, VIT+ Device 2, VIT+ Device 3, VIT+ Figure 6-34. Cmp1 Trip Threshold Hysteresis vs Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 6.13 Typical Characteristics (continued) at VDD1 = 5 V, VDD2 = 3.3 V (unless otherwise noted) 310 310 VINP rising VINP falling 300 290 Propagation delay time (ns) Propagation delay time (ns) 300 280 270 260 250 240 230 290 280 270 260 250 240 230 220 220 210 210 -40 0 10 20 30 40 50 60 Overdrive (mV) 70 80 90 100 VINP rising VINP falling -25 -10 5 D046a 20 35 50 65 Temperature (C) 80 95 110 125 D057 VOVERDRIVE = 10 mV Figure 6-35. Cmp0 Propagation Delay vs Overdrive Figure 6-36. Cmp0 Propagation Delay vs Temperature 310 310 VINP falling VINP rising 300 290 Propagation delay time (ns) Propagation delay time (ns) 300 280 270 260 250 240 230 290 280 270 260 250 240 230 VINP rising VINP falling 220 220 210 0 10 20 30 40 50 60 Overdrive (mV) 70 80 90 100 210 -40 -25 D050 -10 5 20 35 50 65 Temperature (C) 80 95 110 125 D058 VOVERDRIVE = 10 mV Figure 6-38. Cmp1 Propagation Delay vs Temperature Figure 6-37. Cmp1 Propagation Delay vs Overdrive 7 VDD1 = 3.3 V VDD1 = 5 V 6 IIB (nA) 5 4 3 2 1 0 -0.5 0 0.5 1 1.5 2 2.5 VIN (V) 3 3.5 4 4.5 5 D001 VIN = 2 V Figure 6-39. Input Bias Current vs Input Voltage Figure 6-40. Input Bias Current vs Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 17 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 6.13 Typical Characteristics (continued) at VDD1 = 5 V, VDD2 = 3.3 V (unless otherwise noted) 102 102 101.5 101 100.5 IREF (A) IREF (A) 101 100 99.5 99 99 Device 1 Device 2 Device 3 98.5 98 10 100 1000 Device 1 Device 2 Device 3 98 -40 5000 VREF (mV) 100 -25 -10 5 D007 Figure 6-41. Reference Current vs Reference Voltage 20 35 50 65 Temperature (C) D007b VREF = 250 mV VREF = 2 V 4 4 3 3 IVDD1 (mA) IVDD1 (mA) 110 125 5 VREF = 250 mV VREF = 2 V 2 1 2 1 0 0 3 6 9 12 15 18 VDD1 (V) 21 24 27 0 -40 30 -10 5 20 35 50 65 Temperature (C) 2 2 1.8 1.8 IVDD2 (mA) 2.2 1.6 1.4 80 95 110 125 D033a Figure 6-44. High-Side Supply Current vs Temperature 2.2 1.2 2.5 -25 D038a Figure 6-43. High-Side Supply Current vs Supply Voltage IVDD2 (mA) 95 Figure 6-42. Reference Current vs Temperature 5 1.6 1.4 3 3.5 4 4.5 VDD2 (V) 5 5.5 6 1.2 -40 -25 D040 Figure 6-45. Low-Side Supply Current vs Supply Voltage 18 80 -10 5 20 35 50 65 Temperature (C) 80 95 110 125 D041 Figure 6-46. Low-Side Supply Current vs Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 7 Detailed Description 7.1 Overview The AMC22C12 is an isolated window comparator with an open-drain output and optional latch function. The window comparator is comprised of comparator Cmp0 and Cmp1. Cmp0 compares the input voltage (VIN) against the positive threshold (VIT+) and Cmp1 compares the input voltage (VIN) against the negative threshold (VIT–). VIT+ and VIT– are of equal magnitude but opposite signs, therefore the comparison window is centered around 0 V. The comparison threshold is adjustable from ±20 mV to ±300 mV through an internally generated 100-μA reference current and a single external resistor. The open-drain output is actively pulled low when the input voltage (VIN) is outside the comparison window. The behavior when VIN drops back inside the window is determined by the LATCH pin, as described in the Open-Drain Digital Output section. When the voltage on the REF pin is greater than VMSEL, the device operates in positive-comparator mode. This mode is particularly useful for monitoring positive voltages. The negative comparator (Cmp1) is disabled and only the positive comparator (Cmp0) is functional. The reference voltage in this mode can be as high as 2.7 V. Galvanic isolation between the high- and low-voltage side of the device is achieved by transmitting the comparator states across a SiO2-based, capacitive isolation barrier. This isolation barrier supports a high level of magnetic field immunity, as described in the ISO72x Digital Isolator Magnetic-Field Immunity application note. The digital modulation scheme used in the AMC22C12 to transmit data across the isolation barrier, and the isolation barrier characteristics, result in high reliability and common-mode transient immunity. 7.2 Functional Block Diagram AMC22C12 VDD2 LDO Barrier VDD1 LATCH IN TX RX VREF Cmp1 OUT –VREF Isolation REF Logic Cmp0 100 μA GND1 GND2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 19 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 7.3 Feature Description 7.3.1 Analog Input The positive comparator trips when the input voltage (VIN) rises above the VIT+ threshold that is defined as the reference value plus the internal hysteresis voltage. The positive comparator releases when VIN drops below the VIT– threshold that equals the reference value. The negative comparator trips when VIN drops below the VIT– threshold that is defined as the negative reference value minus the internal hysteresis voltage. The negative comparator releases when VIN rises above the VIT+ threshold that equals the negative reference value. The difference between VIT+ and VIT– is referred to as the comparator hysteresis and is 4 mV for reference voltages below 450 mV. The integrated hysteresis makes the AMC22C12 less sensitive to input noise and provides stable operation in noisy environments without having to add external positive feedback to create hysteresis. The hysteresis of Cmp0 increases to 25 mV for reference values (VREF) greater than 600 mV. See the Reference Input description for more details. Figure 7-1 shows a timing diagram of the relationship between hysteresis and switching thresholds. VIT+ VHYS VIT– (VREF) 0V VIN VIT+ (–VREF) VIT– VHYS OUT LATCH Figure 7-1. Switching Thresholds and Hysteresis 20 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 7.3.2 Reference Input The voltage on the REF pin determines the trip threshold of the window comparator. The internal precision current source forces a 100-μA current through an external resistor connected from the REF pin to GND1. The resulting voltage across the resistor (VREF) equals the magnitude of the positive and negative trip thresholds, see Figure 7-1. Place a 100-nF capacitor parallel to the resistor to filter the reference voltage. This capacitor must be charged by the 100-μA current source during power-up and the charging time may exceed the high-side blanking time (tHS,BLK). In this case, as shown in Figure 7-2, the comparator may output an incorrect state after the high-side blanking time has expired until VREF reaches the final value. See the Power-Up and Power-Down Behavior section for more details on power-up behavior. VDD1 VDD2 ON tHS,STA + tHS,BLK VDD2 (low-side) VDD2UV (Hi-Z) 90% normal operation OUT normal (open-drain) operation VDD2UV (Hi-Z) tLS,STA Figure 7-9. VDD1 Turns On, Followed by VDD2 (Long Delay) Figure 7-10. VDD2 Turns Off, Followed by VDD1 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 25 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 7.3.6 VDD1 Brownout and Power-Loss Behavior Brownout is a condition where the VDD1 supply droops below the specified operating voltage range but the device remains functional. Power-loss is a condition where the VDD1 supply drops below a level where the device stops being functional. Depending on the duration and the voltage level, a brownout condition may or may not be noticeable at the output of the device. A power-loss condition is always signaled on the output of the isolated comparator. Figure 7-11 through Figure 7-13 show typical brownout and power-loss scenarios. In Figure 7-11, VDD1 droops below the undervoltage detection threshold (VDD1UV) but recovers before the high-side-fault detection delay time (tHS,FLT) expires. The brownout event has no effect on the comparator output. In Figure 7-12, VDD1 droops below the undervoltage detection threshold (VDD1UV) for more than the high-sidefault detection delay time (tHS,FLT). The brownout condition is detected as a fault and the output is pulled low after a delay equal to tHS,FLT. The device resumes normal operation as soon as VDD1 recovers above the VDD1UV threshold. VDD1 (high-side) VDD1UV VDD1 (high-side) VDD1UV < tHS, FLT tHS, FLT VDD2 (low-side) OUT (open-drain) VDD2 (low-side) ON ON OUT normal (open-drain) operation no change on output 90% fault normal operation Figure 7-11. Output Response to a Short Brownout Figure 7-12. Output Response to a Long Brownout Event on VDD1 Event on VDD1 In Figure 7-13, VDD1 droops below the power-on-reset (POR) threshold (VDD1POR). The power-loss condition is detected as a fault and the output is pulled low after a delay equal to tHS,FLT. The device resumes normal operation after a delay equal to tHS,STA + tHS,BLK after VDD1 recovers above the VDD1UV threshold. VDD1 (high-side) VDD1UV VDD1POR tHS, STA+ tHS, BLK VDD2 (low-side) ON tHS, FLT OUT normal (open-drain) operation 90% fault normal operation Figure 7-13. Output Response to a Power-Loss Event on VDD1 26 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 7.4 Device Functional Modes The AMC22C12 is operational when the power supplies VDD1 and VDD2 are applied, as specified in the Recommended Operating Conditions table. Both comparators on the high-side function together as one window comparator when the voltage on the REF pin is below the VMSEL threshold. If the voltage on the REF pin exceeds the VMSEL threshold, the negative comparator (Cmp0) is disabled and Cmp1 functions as a single positive comparator with increased hysteresis, as described in the Reference Input section. The device has two output operating modes that are selected based on the LATCH input pin setting: transparent mode and latch mode. These modes affect how the OUT pin responds to the changing input signal conditions. See the Open-Drain Digital Output section for details. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 27 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 8 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 8.1 Application Information With the device low response time, high common-mode transient immunity (CMTI), and basic-certified isolation barrier, the AMC22C12 is designed to provide fast and reliable overcurrent and overvoltage detection for highvoltage applications in harsh and noisy environments. 8.2 Typical Applications 8.2.1 Overcurrent Detection Fast overcurrent detection is a common requirement in DC/DC converter and motor-control applications, and can be implemented with an AMC22C12 isolated window comparator as shown in Figure 8-1. DC-link Low-side supply (3..5.5 V) R2 4.7 k HS Gate Driver Supply (3..27 V) R4 10  AMC22C12 VDD1 VDD2 IN R5 10  LATCH C1 100 nF C6 1 nF R1 1.96 k to MCU GND2 GND1 C2 1 µF from MCU OUT REF C5 100 nF C3 100 nF C4 1 µF Low-side supply (3..5.5 V) AMC1200 VDD1 VOUTP VINN VOUTN ADC GND1 GND2 LS Gate Driver Supply Barrier RSHUNT 10 m
Isoation M 3~ VDD2 VINP Figure 8-1. Using the AMC22C12 for Overcurrent Detection The load current flowing through an external shunt resistor RSHUNT produces a voltage drop that is sensed by the AMC1200 for control purposes. The same voltage is monitored by the AMC22C12 that is connected in parallel to the current-sensing amplifier and provides a fast sensing path for positive and negative fault-current detection. The overcurrent detection threshold is set by the external resistor R1 and the overcurrent event is signaled on the open-drain output OUT. As depicted in Figure 8-1, the integrated low-dropout (LDO) regulator on the high-side allows direct connection of the VDD1 input to a commonly used floating gate-driver supply. Alternatively, the AMC22C12 can share a regulated supply with the AMC1200. In that case, the VDD1 pin of the AMC22C12 connects directly to the VDD1 pin of the AMC1200 and R4 is not needed. The fast response time and high common-mode transient immunity (CMTI) of the AMC22C12 ensure reliable and accurate operation even in high-noise environments. 28 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 8.2.1.1 Design Requirements Table 8-1 lists the parameters for the application example in Figure 8-1. Table 8-1. Design Requirements PARAMETER VALUE High-side supply voltage 3 V to 27 V Low-side supply voltage 2.7 V to 5.5 V Shunt-resistor value 10 mΩ Linear input voltage range of the AMC1200 ±250 mV Maximum peak motor current ±25 A Overcurrent detection threshold ±20 A 8.2.1.2 Detailed Design Procedure The value of the shunt resistor in this example is 10 mΩ, determined by the linear input voltage range of the AMC1200 current-sensing amplifier (±250 mV) and the full-scale current of ±25 A. At the desired 20-A overcurrent detection level, the voltage drop across the shunt resistor is 10 mΩ × 20 A = 200 mV. The positive-going trip threshold of the window comparator is VREF + VHYS, where VHYS is 4 mV as specified in the Electrical Characteristics table and VREF is the voltage across R1 that is connected between the REF and GND1 pins. R1 is calculated as (VTRIP – VHYS) / IREF = (200 mV – 4 mV) / 100 μA = 1.96 kΩ and matches a value from the E96 series (1% accuracy). A 10-Ω, 1-nF RC filter (R5, C6) is placed at the input of the comparator to filter the input signal and reduce noise sensitivity. This filter adds 10 Ω × 1 nF = 10 ns of propagation delay that must be considered when calculating the overall response time of the protection circuit. Larger filter constants are preferable to increase noise immunity if the system can tolerate the additional delay. Table 8-2 summarizes the key parameters of the design. Table 8-2. Overcurrent Detection Design Example PARAMETER VALUE Reference resistor value (R1) 1.96 kΩ Reference capacitor value (C5) 100 nF Reference voltage 196 mV Reference voltage settling time (to 90% of final value) 470 μs Overcurrent trip threshold (rising) 200 mV / 20.0 A Overcurrent trip threshold (falling) 196 mV / 19.6 A Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 29 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 8.2.2 Overvoltage Detection Industrial motor drive systems commonly deploy an active or passive rectifier stage to generate a high-voltage, DC link potential from a single- or three-phase AC line input. The DC link voltage is sensed by an isolated amplifier such as the AMC1311B for control purposes. Power stages connected to the DC link rail may be sensitive to overvoltage conditions that can occur (for example, during a braking operation). The isolated amplifier may not be able to alert the system controller fast enough to take appropriate action to reduce the DC link voltage (for example, by turning on the break resistor) in case of an overvoltage condition. Therefore, a fast, isolated comparator is required to detect overvoltage conditions. Figure 8-2 shows an active rectifier stage where the DC link voltage is sensed by an AMC1311B isolated amplifier. The AMC22C12 is connected parallel to the AMC1311B and monitors the voltage across RSNS for overvoltage conditions. The overvoltage trip-threshold is set by the R1 resistor connected to the REF pin of the AMC22C12. The open-drain OUT pin of the AMC22C12 is connected to a GPIO or interrupt pin of the MCU and is actively pulled low whenever the input voltage (VIN) exceeds the reference voltage (VREF). DC-link Break Resistor R1 Number of unit resistors depends on design requirements. See design examples for details. L1 Low-side supply (3..5.5 V) Gate driver supply (3..27 V) L2 R2 R2 4.7 k R4 10  L3 AMC22C12 VDD2 VDD1 N LATCH IN N from MCU OUT REF to MCU RSNS GND2 GND1 C2 1 µF C1 100 nF C6 1nF C5 R1 21.0 k
100 nF C3 100 nF C4 1 µF Low-side supply (3..5.5 V) AMC1311B VDD1 VDD2 IN OUTP SHTDN OUTN GND1 GND2 Barrier Isoation ADC Figure 8-2. Using the AMC22C12 for Overvoltage Detection 30 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 8.2.2.1 Design Requirements Table 8-3 lists the parameters for the application example in Figure 8-2. Table 8-3. Design Requirements PARAMETER VALUE High-side supply voltage 3 V to 27 V Low-side supply voltage 3 V to 5.5 V Nominal DC link voltage 400 V Linear full-scale input voltage of the AMC1311B 2V DC link voltage range for linear sensing 0 V to 450 V DC link overvoltage detection threshold 480 V 8.2.2.2 Detailed Design Procedure The voltage divider consisting of R1, R2, and RSNS is sized such that the voltage drop across RSNS equals the linear full-scale input voltage (2 V) of the AMC1311B at the maximum DC-link voltage that is of interest for linear sensing (450 V). Therefore, the voltage drop across RSNS at the overvoltage condition is 480 V / 450 V × 2 V = 2.133 V. This value is the target value for the reference voltage (VREF) of the AMC22C12. VREF is determined by the external resistor R1 and the internal 100-μA current source of the AMC22C12. R1 is calculated as (VTRIP – VHYS) / IREF = (2133 mV – 25 mV) / 100 μA = 21.08 kΩ. The closest value in the E192 series is 21.0 kΩ. The comparator hysteresis voltage (VHYS) is subtracted from VTRIP because the comparator trips at VREF + VHYS, see Figure 7-1. The hysteresis value is 25 mV because the reference voltage is greater than 550 mV, as explained in the Reference Input section. Table 8-4 summarizes the key parameters of the design. Table 8-4. Overvoltage and Undervoltage Detection Design Example PARAMETER VALUE Reference resistor value (R1) 21.0 kΩ Reference capacitor value (C5) 100 nF Reference voltage 2100 mV Reference voltage settling time (to 90% of final value) 4.85 ms Overvoltage trip threshold (rising) 478 V Overvoltage trip threshold (falling) 472 V Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 31 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 8.2.3 Application Curves Figure 8-3 shows the typical response of the AMC22C12 to a bipolar, triangular input waveform with an amplitude of 720 mVPP. The output (OUT) switches when VIN crosses the ±250-mV level determined by the REF pin voltage that is biased to 250 mV in this example. Figure 8-3. Output Response of the AMC22C12 to a Triangular Input Waveform The integrated LDO of the AMC22C12 greatly relaxes the power-supply requirements on the high-voltage side and allows powering the device from non-regulated transformer, charge pump, and bootstrap supplies. As given by the following images, the internal LDO provides a stable operating voltage to the internal circuitry, allowing the trip thresholds to remain mostly undisturbed even at ripple voltages of 2 VPP and higher. 1.4 VDD1 = 5 V VDD1 = 10 V 1.2 Trip Threshold Uncertainty (mV) Trip Threshold Uncertainty (mV) 1.4 1 0.8 0.6 0.4 0.2 1 0.8 0.6 0.4 0.2 0 0 0 1 VDD1 2 3 Ripple Voltage (VPP) 4 5 0 D063a Figure 8-4. Trip Threshold Sensitivity to VDD1 Ripple Voltage (Cmp0, fRIPPLE = 10 kHz) 32 VDD1 = 5 V VDD1 = 10 V 1.2 1 2 3 VDD1 Ripple Voltage (VPP) 4 5 D063b Figure 8-5. Trip Threshold Sensitivity to VDD1 Ripple Voltage (Cmp1, fRIPPLE = 10 kHz) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 8.3 Best Design Practices Keep the connection between the low-side of the sense resistor and the GND1 pin of the AMC22C12 short and low impedance. Any voltage drop in the ground line adds error to the voltage sensed at the input of the comparator and leads to inaccuracies in the trip thresholds. For best common-mode transient immunity, place the filter capacitor C5 as closely to the REF pin as possible as illustrated in Figure 8-7. Use a low value pullup resistor (5.5 V) place a 10-Ω resistor (R4) is series with the VDD1 power supply for additional filtering. Low-side supply (2.7..5.5 V) High-side supply (3..27V) R2 4.7 k R4 10  AMC22C12 R5 10 Ω I VDD1 RSHUNT IN LATCH REF GND1 C2 1 µF VDD2 from MCU OUT to MCU GND2 C1 C6 C5 R1 100 nF 1 nF 1.96 k
100 nF C3 100 nF C4 1 µF Figure 8-6. Decoupling of the AMC22C12 Capacitors must provide adequate effective capacitance under the applicable DC bias conditions they experience in the application. Multilayer ceramic capacitors (MLCCs) typically exhibit only a fraction of their nominal capacitance under real-world conditions and this factor must be taken into consideration when selecting these capacitors. This problem is especially acute in low-profile capacitors, in which the dielectric field strength is higher than in taller components. Reputable capacitor manufacturers provide capacitance versus DC bias curves that greatly simplify component selection. 8.5 Layout 8.5.1 Layout Guidelines Figure 8-7 shows a layout recommendation with the critical placement of the decoupling capacitors (as close as possible to the AMC22C12 supply pins) and placement of the other components required by the device. 8.5.2 Layout Example High-side supply R5 C4 C3 C6 IN Low-side supply VDD2 C1 AMC22C12 C5 REF R1 RSHUNT C2 VDD1 R4 Clearance area, to be kept free of any conductive materials. LATCH from MCU OUT to MCU GND2 GND1 Top Metal Inner or Bottom Layer Metal Via Figure 8-7. Recommended Layout of the AMC22C12 34 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 9 Device and Documentation Support 9.1 Documentation Support 9.1.1 Related Documentation For related documentation, see the following: • • • • • • Texas Instruments, Isolation Glossary application note Texas Instruments, Semiconductor and IC Package Thermal Metrics application note Texas Instruments, ISO72x Digital Isolator Magnetic-Field Immunity application note Texas Instruments, AMC1200/B Fully-Differential Isolation Amplifier data sheet Texas Instruments, AMC1311x High-Impedance, 2-V Input, Reinforced Isolated Amplifiers data sheet Texas Instruments, Isolated Amplifier Voltage Sensing Excel Calculator design tool 9.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 9.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 9.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 9.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 9.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 10 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 35 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 10.1 Mechanical Data PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 ) 4 5 B 8X .012-.020 [0.31-0.51] .010 [0.25] C A B .150-.157 [3.81-3.98] NOTE 4 .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A (.041) [1.04] TYPICAL 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com 36 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK OPENING METAL EXPOSED METAL .0028 MAX [0.07] ALL AROUND SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 37 AMC22C12 www.ti.com SBASAJ8A – JUNE 2022 – REVISED AUGUST 2022 EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com 38 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AMC22C12 PACKAGE OPTION ADDENDUM www.ti.com 14-Mar-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) AMC22C12DR ACTIVE SOIC D 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 22C12 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of